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Subthreshold Schottky-barrier thin-film transistors with ultralow power and high intrinsic gain Sungsik Lee and Arokia Nathan* The quest for low power becomes highly compelling in newly emerging application areas related to wearable devices in the Internet of Things. Here, we report on a Schottky-barrier indium-gallium-zinc-oxide thin-film transistor operating in the deep subthreshold regime (i.e., near the OFF state) at low supply voltages (<1 volt) and ultralow power (<1 nanowatt). By using a Schottky-barrier at the source and drain contacts, the current-voltage characteristics of the transistor were virtually channel-length independent with an infinite output resistance. It exhibited high intrinsic gain (>400) that was both bias and geometry independent. The transistor reported here is useful for sensor interface circuits in wearable devices where high current sensitivity and ultralow power are vital for battery-less operation.
T
hin-film transistors (TFTs) based on amorphous oxide semiconductors (AOSs), such as indium-gallium-zinc-oxide (i.e., In-Ga-ZnO or IGZO), have been shown to be a highly promising candidate for large-area electronics because of their high mobility, low-temperature processability, and wide band gap, hence high transparency and low OFF current, compared with the ubiquitous silicon thin-film technology and more recently the organic family (1–8). For deployment of TFTs in mobile devices, such as wearables, low voltage and low power are crucial because the operation of the wearable device is challenged by the limited battery lifetime even if it is augmented with energy harvesting (9–12). Other TFT technologies are unlikely to meet these requirements because of their higher quiescent power (table S2) (1–8, 13–16). The approach used here to achieve ultralow power is to operate the transistor in the deep subthreshold regime, i.e., near the OFF state. Within this regime, the saturation drain current (IDS) of the Schottky barrier (SB) TFT is independent of drain voltage (VDS), yielding an infinite output resistance (i.e., ro = @VDS/@IDS → ∞). Indeed, the magnitude of the current is scaled geometrically only by the channel width (W) as opposed to the channel width-to-length ratio (W/L) as in conventional transistors (see inset of Fig. 1B). The insulated gate provides an effective means of modulating the SB height at the source contact and hence the thermionic emission (TE) and thermionic field emission (TFE) properties. Thus, the emission current into the channel is determined by the reverse saturation current of the Schottky diode at the source, which in turn is Electrical Engineering Division, Department of Engineering, University of Cambridge, 9 JJ Thomson Avenue, Cambridge CB3 0FA, UK. *Corresponding author. Email: an299@cam.ac.uk
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modulated by the gate voltage. As a result, the SB-TFT yields a large intrinsic gain that is independent of both geometry and bias. This bias independence of intrinsic gain and zero input current by virtue of the insulated gate makes the SB-TFT capture the best of the bipolar junction transistor (BJT) and metal-oxide-semiconductor field-effect transistor (MOSFET) technology families (table S4) (16–18). To form a Schottky contact at the source/drain contact of the IGZO TFT, we decreased the electron concentration of the IGZO film by using a high oxygen-gas partial pressure relative to argon, i.e., Pox = O2/(O2 + Ar), during the radio frequency (RF) sputtering process, with subsequent thermal annealing for a more reliable contact (Fig. 1A and fig. S1). Here, a high Pox serves to compensate oxygen vacancies (Vox), which act as electron donors (7, 19, 20). Indeed, in the measured output characteristics, the MC-IGZO TFT (at Pox = 15%) provided Schottky characteristics at low VDS, whereas the LC-IGZO TFT (at Pox = 4%) showed the usual ohmic behavior (fig. S2). At higher VDS, both devices show current saturation (Fig. 1B). More important, the SB-TFT (i.e., MC-IGZO TFT) has a much flatter output curvature compared to the ohmic device, yielding a much higher ro. In particular, the output characteristics of the ohmic device had a L dependence (fig. S2). In contrast, the output characteristics of the SB-TFT were almost independent of L (Fig. 1B). This can be explained with the saturation drain-current (Isat) relation as (21–23) ϕ VDS Isat ¼ AJ Jsat ðVGSÞexp − B0 1 − exp − vth nvth ð1Þ where n is the ideality factor (~1.7 of the examined device); AJ is the contact area, where electrons are emitted through TE-TFE rather than the drift-diffusion process; vth is the thermal
voltage (i.e., kBT/q, where kB is Boltzmann’s constant, T is the absolute temperature, and q is the elementary charge); and Jsat is the saturation current density as a function of gate voltage (VGS). Isat is linearly proportional to AJ, and scales with W. In addition, the term (1 – exp(–VDS/nvth)) is almost unity in the saturation regime because VDS >> nvth at 300 K, and thus is independent of VDS. These are consistent with the results in Fig. 1B. Besides, Fig. 1, C to E, show input characteristics, in which a conceptual color-bar of output power consumption (Pout) for a 1-V supply, normalized with W, is shown, clearly indicating each operational regime (Fig. 1F). In particular, as seen in Fig. 1E, the SB-TFT has a higher transconductance (gm). This can be explained with its smaller subthreshold slope (SS) ~ 0.28 V/decade compared to the ohmic device (Fig. 1D, fig. S2, and table S1). Because the intrinsic gain (Ai) of a transistor is defined as gmro, the SB-TFT provides a higher Ai associated with its higher ro and gm compared to the ohmic device (table S3). To theoretically explain the results of the SBTFT, we describe its operating principle in Fig. 2. At a given VGS, the nonlinear response of the drain current at VDS < Vtran (the transition voltage) suggests a forward-biased Schottky diode at the drain junction (Fig. 2A). Here, the electron collection is modulated with VGS through an effective SB lowering at the drain side (DϕBD) (Fig. 2B). When VDS > Vtran, IDS becomes firmly saturated because of the reverse-biased Schottky diode at the source (Fig. 2C). This regime satisfies the condition of L >> WD, suggesting a negligible image-charge effect from the drain to source, where WD is the depletion width at the drain (Fig. 2C and fig. S5A). Thus, the SB lowering at the source (DϕBS) is mainly a function of VGS modulating the current density expressed as DϕBS ðVGS Þ Jsat ðVGS Þ ¼ J0 exp vth
ð2Þ
Here, J0 is a reference current density. As seen in Fig. 2D, the intercept (Dϕ0) ~ 0.165 V can be considered as an initial SB lowering corresponding to the reference current at VGS = Vref (the reference voltage). An effective SB-lowering (e.g., DϕBS) approximation is used to account for changes in the SB width (WS) and, hence, the degree of the quantum mechanical tunneling (fig. S5C) (23). Based on the theory discussed along with Fig. 2, the output characteristics of the SB device for different VGS (ranging from 0 to 1 V, in steps of 0.1 V) were measured (movie S1) and modeled (Fig. 3A). The results show good agreement with each other. Figure 3B shows the transfer characteristics for VDS of 0.5 and 1 V. They are nearly identical, implying current saturation for VDS > Vtran ~ 0.48 V. Also, it shows an exponential dependency on VGS, which can be explained with Eq. 2 where DϕBS(VGS) = z0(VGS − Vref) + Dϕ0. z0 is a coefficient that describes the sensitivity of barrier lowering to VGS. The retrieved ro and gm for VDS = 1 V are shown as a function of VGS (Fig. 3C). Both follow an exponential law with an opposite proportionality on VGS, as described in Eqs. 3 and 4. Their sciencemag.org SCIENCE
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R ES E A RC H
RE S EAR CH | R E P O R T S
ro ¼ n
vth −z0 ðVGS −Vref Þ−Dϕ0 vsat exp exp AJ JB0 vth nvth ð3Þ
gm ¼ z 0
AJ JB0 z ðVGS −Vref Þ þ Dϕ0 ð4Þ exp 0 vth vth
Ai ¼ z0 nexp
vsat nvth
ð5Þ
where JB0 = J0 exp(–ϕB0/vth) (eqs. S17 to S21). As seen in Eq. 5, Ai is not a function of either bias (e.g., VGS, VDS) or geometry (e.g., W and L), but rather is a function of intrinsic parameters (e.g., z0, n, vth, and a saturation voltage vsat). So, it is just a constant, unlike the ohmic device. With Eq. 5, Ai is calculated as ~450 with the retrieved values of intrinsic parameters (fig. S6), which is
consistent with measurements (Fig. 3D). Here, Ai of the SB-TFT is at least an order of magnitude higher compared to the ohmic IGZO TFT (table S3) or a typical Si-MOSFET (17, 18). Because the SB-TFT operates at low voltage and low current, it is also electrically stable over time (fig. S7). The low power and high-gain performance of the SBTFTs were applied to a common source amplifier as demonstrated in Fig. 4 (movie S2). As seen in Fig. 4, A and B, the TFT-2 (load), whose Vref (and VT) was shifted to negative because of light stress,
Fig. 1. Device structure and basic electrical characteristics. (A) Schematic cross-section of the examined device [inset: Illustration of atomic structures for less compensated (LC) and more compensated (MC) IGZO films, respectively]. (B) Measured IDS/W versus VDS for MC and LC devices (inset: IDS/W versus L). Measured input characteristics: (C) in linear scale, indicating VT (the threshold voltage), and (D) in logarithmic scale, indicating Vref, respectively (IG is a gate leakage current). (E) Measured g m/W of each device along with the ratio between them. (F) Conceptual color bar of Pout normalized with W for 1-V supply. Here, the sub-T and above-T denote the subthreshold and above-threshold, respectively. Fig. 2. Operating principle of the deep subthreshold SB-TFT. (A) Band diagram along L when VDS < Vtran. (B) Retrieved DϕBD at drain contact as a function of VGS calibrated with Vref, i.e., VGS − Vref. (C) Band diagram along L when VDS > Vtran. (D) Extracted DϕBS at source contact as a function of VGS – Vref. Here, EC and EF denote the conduction band minima and Fermi level, respectively. [Insets in (A) and (C) are equivalent circuit representations, and those of (B) and (D) are schematic diagrams to describe the bias-dependent SB lowering, respectively.]
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product gives a signal amplification factor, i.e., intrinsic gain (Ai):
Fig. 3. Modulation characteristics and small-signal parameters of the SB-TFT in the deep subthreshold regime. (A) Measured IDS versus VDS for a different VGS along with theoretical prediction. Here, V0 is a threshold at which the source-side Schottky diode starts dominating. (B) Transfer characteristics for VDS = 0.5 and 1 V. (C) Experimental values of ro and gm as a function of VGS along with theoretical prediction (dashed lines). (D) Measured Ai of the SB-TFT as a function of VGS.
Fig. 4. Circuit-level demonstrations with the SB-TFTs. (A) Transfer characteristics of TFT-1 (driver) and TFT-2 (depletion load due to light stress), where IB and VB are determined as ~90 pA and ~0.5 V, respectively. (B) Common-source circuit and its three-dimensional view. (C) Measured output voltage (Vout) as a function of input voltage (Vin) while using 2-V supply (VDD), (D) AV, (E) output current (Iout), and (F) Pout versus Vin, respectively.
was used as a depletion load (fig. S8) (24). Alternatively, a TFT with a larger W as a design parameter can also be employed (fig. S9A). As shown in Fig. 4D, the circuit exhibits a high voltage gain (AV) >220, and its output-power consumption (Pout) is very low, <150 pW (Fig. 4F). Thus, it can even be driven by a nanowatt power source. Our deep subthreshold operating SB-TFT is fundamentally an ultralow-power and high-gain device, which opens up possibilities for innovative system design in many applications, including wearables and implantable devices, where lowpower and low-current analog signal processing are essential requirements. In addition, the operating principle of the SB-TFT in the deep subthreshold regime (i.e., near-OFF-state) brings together the best of two transistor families: the bias independence of gain of the BJT and the zero input current of the MOSFET (table S4). Thus, the SBTFT will bring about a new design paradigm for near-OFF-state sensor interfaces and analog frontend circuits (figs. S10 to S12). RE FE RENCES AND N OT ES
1. K. Nomura et al., Science 300, 1269–1272 (2003). 2. J. F. Wager, Science 300, 1245–1246 (2003).
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3. K. Nomura et al., Nature 432, 488–492 (2004). 4. R. Martins et al., Adv. Mater. 23, 4491–4496 (2011). 5. S. Lee, S. Jeon, R. Chaji, A. Nathan, Proc. IEEE 103, 644–664 (2015). 6. E. Fortunato, P. Barquinha, R. Martins, Adv. Mater. 24, 2945–2986 (2012). 7. Y. J. Tak et al., Sci. Rep. 6, 21869 (2016). 8. J. F. Wager, B. Yeh, R. L. Hoffman, D. A. Keszler, Curr. Opin. Solid State Mater. Sci. 18, 53–61 (2014). 9. H. Nishide, K. Oyaizu, Science 319, 737–738 (2008). 10. P. D. Mitcheson, E. M. Yeatman, G. K. Rao, A. S. Holmes, T. C. Green, Proc. IEEE 96, 1457–1486 (2008). 11. J. M. Donelan et al., Science 319, 807–810 (2008). 12. R. J. M. Vullers, R. van Schaijk, I. Doms, C. Van Hoof, R. Mertens, Solid-State Electron. 53, 684–693 (2009). 13. T. Kodaira et al., J. Soc. Inf. Disp. 16, 107–111 (2008). 14. H. Gleskova, S. Wagner, W. Soboyejo, Z. Suo, J. Appl. Phys. 92, 6224 (2002). 15. T. Sekitani, U. Zschieschang, H. Klauk, T. Someya, Nat. Mater. 9, 1015–1022 (2010). 16. R. Chaji, A. Nathan, Thin Film Transistor Circuits and Systems (Cambridge Univ. Press, 2013). 17. B. Razavi, Design of Analog CMOS Integrated Circuits (McGrawHill, New York, 2001). 18. A. S. Sedra, K. C. Smith, Microelectronic Circuits (Oxford Univ. Press, New York, 2007). 19. A. Janotti, C. G. Van de Walle, Appl. Phys. Lett. 87, 122102 (2005).
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S.L and A.N. contributed equally to this work. We thank the Engineering and Physical Sciences Research Council under Project EP/M013650/1; European Union (EU) under Projects DOMINO 645760, ORAMA 246334, 1D-NEON 685758-2, BET-EU 692373; and Danbond under Project 69191 for their generous support. We also thank X. Cheng and J. Li (Cambridge University) for stimulating discussions. All data are available in the main text, supplementary materials, and the Cambridge University's repository. SUPPLEMENTARY MATERIALS
www.sciencemag.org/content/354/6310/302/suppl/DC1 Materials and Methods Supplementary Text Figs. S1 to S12 Tables S1 to S4 Movies S1 and S2 References (25–38) 6 July 2016; accepted 20 September 2016 10.1126/science.aah5035
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R ES E A RC H | R E PO R TS
Subthreshold Schottky-barrier thin-film transistors with ultralow power and high intrinsic gain Sungsik Lee and Arokia Nathan (October 20, 2016) Science 354 (6310), 302-304. [doi: 10.1126/science.aah5035]
Almost-off transistors Wearable devices and environmental sensors ideally should consume very little power to avoid the need for batteries that would have to be replaced. Lee and Nathan developed a thin-film transistor (TFT) from In-Ga-Zn-O thin films. To make the material less conductive, the films were fabricated to avoid oxygen vacancies. The TFT operated at ultralow power (less than 1 nW) and at switching voltages of less than 1 V with very high intrinsic gain. The devices work by changing the height of the so-called Schottky barrier formed between the semiconductor gate material and the metal drain contact. Science, this issue p. 302
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