THE OPPORTUNITY
The National Institute of Standards and Technology (NIST), of the United States Department of Commerce, intends to fund a new CHIPS Manufacturing USA Institute up to approximately $285 million for a first-of-its kind institute focused on the development, validation, and use of digital twins for semiconductor manufacturing, advanced packaging, assembly, and test processes.
OBJECTIVES
Convene stakeholders across the industry to address shared challenges relevant to digital twins in a collaborative environment.
� Improve the state of the art for both unit-level and the combination of multiple manufacturing-relevant digital twins
� Significantly reduce U.S. chip development and manufacturing costs by improving efficiencies using digital twins
� Improve development cycle times and accelerate the development and adoption of relevant innovative technologies
� Advance digital twin-enabled curricula, best practices, and hands-on opportunities for training the next generation of the domestic semiconductor workforce
� Create a digital twin marketplace for industry to access digital models and manufacturing process flows and to de-risk digital twin development and implementation.
THE VISION
To enable rapid development and seamless integration of digital twin models into the U.S. semiconductor manufacturing, advanced packaging, assembly and test industry, enabling rapid development and adoption of innovations and enhancing domestic competitiveness for decades
THE MISSION
� Foster a collaborative environment within the domestic semiconductor industry, enabled by shared facilities and institute expertise,
� Support industry-led solutions through funded research projects,
� Accelerate technology towards commercialization through significant co-investment, and
� Enable digital-twin-enhanced workforce training
TECHNICAL THRUSTS
� Advanced Sensing and Metrology
� Verification, Validation & Uncertainty Quantification
� Digital Twin Backbone
� End-to-End Digital Twin Framework & Hierarchy
� Co-Optimization
� AI-Driven Applications
LIVE MEMBER BENEFITS
� Networking opportunities among the institute consortium members including top universities and industry partners in semiconductor manufacturing digital twins
� Opportunities to participate in funded Institute-led and Member-led projects
� Access to expertise through a distributed network of complementary centers of excellence
� Access to a baseline set of world-class facilities at the launch of the Institute
� Access to a digital marketplace with licenses for digital twins and related technologies
� Digital twin-equipped workforce training that is inclusive and accessible
� Access to a network of the top university nanofabrication laboratories in the nation that will provide a data-centric research and education ecosystem
JULY 24 + 25
TEAM WORKSHOP AT CARNEGIE MELLON
CORE COMPETENCIES AND AREAS OF EXPERTISE
KEY ACTIVITIES
� Collaboration with a broad and diverse institute membership
� Digital twin development and innovation
� Formation of the Digital Twin Backbone, enabling digital twin interoperability and flows
� Supporting a Digital Marketplace, to accelerate digital twin development and integration
� Pilot line and data access, for development, verification and validation
� Education and workforce development, scaled and enhanced by digital twin technologies
� Coordination with other CHIPS-related programs, e.g. NSTC, NAPMP, ME Commons, Manufacturing USA
AUGUST 8 + 9
TEAM WORKSHOP AT UT AUSTIN
AUGUST 19 LETTERS OF COMMITMENT DUE SEPTEMBER 9 FINAL PROPOSAL DUE
Agnihil et, autet fugia lorem
FOUNDING INSTITUTIONS
� Carnegie Mellon University,
� Arizona State University,
� Intel Corp.,
� Massachusetts Institute of Technology,
� Micron Technologies,
� PDF Solutions,
� Stanford University,
� Texas A&M University,
� University of California at Berkeley,
� University of Texas at Austin
SAMPLING OF PARTICIPANTS
INDUSTRY
Analog Devices, Amazon Web Services, Ansys, ASML, Analog Inference, Applied Materials, CI&T, Cadence, Dassault Systemes, GLX Power, IBM, IMEC, Lam Research, Microsoft, Multiscale Technologies, NVIDIA, Plato, Seagate, Siemens, Synopsys
UNIVERSITIES / COLLEGES
Alabama, A&M, Cornell, Howard, Indiana, Lehigh, Morehouse College, Morgan State, Notre Dame, Ohio State, Purdue, Rensselaer Polytechnic Institute, SUNY Erie
NATIONAL LABORATORIES (NL) / FFRDCs
Lawrence Berkeley NL, Lawrence Livermore NL, MIT Lincoln Laboratory, Princeton Plasma Physics Laboratory, Sandia NL, Software Engineering Institute
MANUFACTURING USA / MICROELECTRONICS COMMONS / MEPs / NPOs
AFFOA, AIM Photonics, ARM, Catalyst Connection, CMTC, CESMII, MAGNET, MMEC, NEMC, RAND, SEMI, SME
� Chief Executive Officer: Gary Fedder (CMU)
� Chief Technical Officer: Dragan Djurdjanovic (UTA)
� Chief Workforce Officer: Julie Diop (MIT)