Semiconductor 2014
End to End development of a Wireless LAN Router Base station chip How we work with our clients to help overcome challenges for a better tomorrow
Semiconductor
Business Case
Delivered 126 percent of the targeted die size reduction
The client, a multi-billion dollar enterprise, is one of the world’s largest fabless communications semiconductor company catering to the high profile consumer device companies like Apple Computer, HP, Motorola, IBM, Dell, Lenovo among many others. The client wanted Cyient to provide a solution to decrease the development cost of the Wireless LAN Router Basestation chip (with 65 nm technology, 8 million gates and 533 MHz frequency specification)
Semiconductor
Expertise
Cyient, an expert in “Concept to Prototype” development across the chip design cycle, delivered the project under an aggressive time schedule
Time to market is the key to succeed in the fast moving Semiconductor market space and Cyient’s Global Engineering model is particularly designed to address this need by bringing in better Client coordination. With delivery teams based out of both U.S. and India, Cyient setup a global team to take up complete ownership of the derivative chip and delivered the project under an aggressive time schedule to help our client achieve a faster time to market with considerable cost savings. Cyient’s expertise in “Concept to Prototype” development across the chip design cycle all the way from RTL design, verification, synthesis, DFT, physical design, timing closure and post silicon bring up were leveraged to provide end to end solution.
Semiconductor
Benefits
Helping the client achieve a faster time to market with significant cost savings
Delivered 126 percent of the targeted die size reduction, thereby reducing manufacturing costs. First-pass silicon achievement. Achieved two seconds tester time resulting in lower production costs. Achieved package pin compatibility with previous generation.
Semiconductor
Project Details
Tools and Technologies ModelSim, DC-Ultra, RTL Compiler, Conformal, Logic Vision, SOC Encounter, ATOP, Star- RC, Primetime, Calibre.
The major challenge the team faced in implementation was reduction of die size so the manufacturing cost per chip would come down. Area reduction and optimal optimization techniques using our proprietary “Library of Flows� were used to reduce the die size. Because of the small geometries involved, reduction in die sizes caused the utilizations to go up and which resulted in unexpected signal integrity issues. The team leveraged its expertise gained over 200+ ASIC tapeouts and fixed the issues in a timely manner and met aggressive customer schedules.
About Cyient
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Š 2014 Cyient. Cyient believes the information in this publication is accurate as of its publication date; such information is subject to change without notice. Cyient acknowledges the proprietary rights of the trademarks and product names of other companies mentioned in this document.