CONCORDIA UNIVERSITY
COMP 228
DEPARTMENT OF COMPUTER SCIENCE AND SOFTWARE ENGINEERING
Fall 2000
ASSIGNMENT 5
Due: December 8, 2009 ___________________________________________________________________________________ 1.
[50%] A cache is incorporated into a MARIE computer with the following system details. Main memory: capacity = 4K words (word size is 2 bytes) Memory cycle time = 6 clock cycles Cache: capacity = 256 words Block/line size = 8 words Cache access time = 1 clock cycle Cache miss penalty = 20 cycles Direct mapping The following MARIE program is executed: S0
S1
P C One T X (a) (b)
Load P AddI X Skipcond 400 Jump S1 Load C Add One Store C Load X Add One Store X Load T Subt One Store T Skipcond 400 Jump S0 Halt Dec -100 Dec 0 Dec 1 Dec 100 Dec 512
Determine the memory address format by specifying the size of (i) the tag, (ii) the line, and (iii) the word fields. Suppose the program is loaded into the main memory starting from location 0. Determine which memory blocks (numbers) are used to store the program code and the program data. Hence determine which cache lines are used to buffer the program code and data.
COMP 228 (System Hardware), Fall 2008 ⎯ Assignment 5
(c) (d) (e) (f)
2.
(a) (b) (c) (d) (e) (f) (g)
3.
(a) (b) (c)
Page 2
Trace the execution and identify the best case and worst case cache misses that occur in the first iteration of the program loop (repeating the instruction at S0). Assuming the best case, determine the total number of instruction misses (in fetching instructions) in executing the entire program. Repeat the same for data misses (for accessing data). Determine the best case hit ratio arising from your results in (d). Hence compute the memory speedup provided by the cache. Consider an alternative cache design with a line size of 16 words and cache miss penalty of 26 cycles. How much cache hit ratio increase should result in order that the alternative design achieves a better performance (speedup) than the original design with a line size of 8? [35%] Consider the following input/output devices connected to a computer: (i) laser printer, (ii) monitor, (iii) keyboard, (iv) mouse, (v) modem, (vi) disk. All three types of input/output interfaces (programmed I/O, interrupt and DMA) can be used to support these devices. Explain under what situations it would be justified to use DMA to support an I/O device. Repeat the same for using interrupt. For each of the listed input/output devices, explain which input/output interface you would use to support it. Can the CPU acknowledge an interrupt while DMA operation is taking place? Can the CPU be executing an instruction while DMA operation is taking place? While the CPU is executing a program, it is interrupted and spends 20% of its time to serve interrupts. How is the program execution time being affected? While the CPU is executing a program, other DMA activities consume 20% of the system bus time. How is the program execution time being affected? Explain why a computer system can support multiple concurrent processes (CPU running a program, input/output devices performing different I/O functions) using a single system bus. [15%] The following characteristics of a moving-arm disk are known: • 4 recording surfaces • 1024 tracks per surface • 256 sectors per track • 1K bytes/sector • Average seek time of 2 ms • Rotational speed of 9000 rpm Determine the total capacity of the disk drive. Determine the average access time of the disk drive. Assuming that disk (address) accesses are totally random and are served in FCFS (first come first served) order, the average number of tracks traversed in an access is not equal to ½ (total number of tracks/surface), i.e. 1024/2. Explain why this is so.