Ipad mini 2 full schematic diagram by yun zhang

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TOP SIDE ASSEMBLY

TITLE

APPLE

X200 MLB (C1)

THIS IS THE PROPERTY OF APPLE AND IT MUST BE RETURNED

ORIG DIV

PCBF,

DESIGNER

DATE

SCALE

HURLEY

01/08/13

1:1

DRAWING NUMBER

820-4124-A NOTICE OF PROPRIETARY PROPERTY

NOTES: ARTWORK VIEWED FROM COMPONENT SIDE. PCB SHALL CONFORM

THE INFORMATION CONTAINED HEREIN IS THE

TO STANDARDS AS DEFINED IN APPLE SPECIFICATION

PROPRIETARY PROPERTY OF APPLE

062-0031 (DOUBLE-SIDED BOARDS) OR 062-0073 (MULTI-

THE POSSESSOR AGREES TO THE FOLLOWING

LAYER BOARDS) AS APPLICABLE.

(I) TO MAINTAIN THIS DOCUMENT IN CONFIDENCE (II) NOT TO REPRODUCE OR COPY IT (III) NOT TO REVEAL OR PUBLISH IT

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

X200

SCH AND BOARD PART NUMBERS

MLB-C1

REV

ECN

DESCRIPTION OF REVISION

0002535199

CK APPD DATE

PRODUCTION RELEASED

2014-01-13

LAST_MODIFIED=Tue Oct 29 15:52:27 2013

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION

PDF CSA CONTENTS SYNC MASTER DATE 21 27 SENSOR: ACCEL, COMPASS, GYRO N/A N/A 22 28 SENSOR: PROX J85 MLB_C 12/05/12 23 29 CAMERA: REAR CONN & FILTERS N/A N/A 24 30 CELL:AP INTERFACE & DEBUG CONNECTORS RADIO_MLB_87 10/29/2013 25 32 CELL: BASEBAND PMU (1 0F 2) RADIO_MLB_87 10/29/2013 26 33 CELL: BASEBAND PMU (2 OF 2) RADIO_MLB_87 10/29/2013 27 34 CELL: BASEBAND (1 OF 2) RADIO_MLB_87 10/29/2013 28 35 CELL: BASEBAND (2 OF 2) RADIO_MLB_87 10/29/2013 29 36 CELL: RF TRANSCEIVER (1 0F 2) RADIO_MLB_87 10/29/2013 30 37 CELL: RF TRANSCEIVER (2 OF 2) RADIO_MLB_87 10/29/2013 31 38 CELL: RX MATCHING RADIO_MLB_87 10/29/2013 32 39 CELL: RF TRANSCEIVER (3 OF 4) RADIO_MLB_87 10/29/2013 33 40 CELL: PENTABAND PA RADIO_MLB_87 10/29/2013 34 41 CELL: BAND 2/3 PAD RADIO_MLB_87 10/29/2013 35 42 CELL: BAND 7/20 PAD RADIO_MLB_87 10/29/2013 36 43 CELL: BAND 5/8 PAD RADIO_MLB_87 10/29/2013 37 44 CELL: 2G PA RADIO_MLB_87 10/29/2013 38 45 CELL: PA DCDC CONVERTER RADIO_MLB_87 10/29/2013 39 46 CELL: ASM AND HB LTE FRONT-END RADIO_MLB_87 10/29/2013 40 47 CELL: RX DIVERSITY RADIO_MLB_87 10/29/2013 41 48 CELL: GPS RADIO_MLB_87 10/29/2013 42 49 CELL: ANTENNA FEEDS RADIO_MLB_87 10/29/2013 43 57 IO: FILTERS & HOTBAR CONN N/A 04/18/2011 44 58 WIFI/BT: MODULE WIFI_DEV05/20/2013 45 75 POWER: BATTERY CONNECTOR N/A N/A 46 81 PMU: ANYA PAGE 1 J72_MLB_C 11/26/2012 47 82 PMU: ANYA PAGE 2 J85 MLB_C 12/03/2012 48 83 PMU: ANYA PAGE 3 J72_MLB_C 11/26/2012 49 84 PMU: ANYA PAGE 4 J72_MLB_C 11/26/2012 50 85 POWER: PP1V8_SW J85 MLB_C 11/26/2012 51 90 SEP: EEPROM & SOC DEBUG J72_MLB_C 11/26/2012 52 93 TEST: TP/HOLES/FIDUCIALS J85 MLB_C 12/03/12 53 94 TEST: EE TP/PP J72_MLB_C 11/26/2012 54 121 POWER: ALIASES J72_MLB_C 11/26/2012

TABLE_5_ITEM

051-0886

SCH,MLB-C1,X200

SCH1

820-4124

PCBF,MLB-C1,X200

PCB1

TABLE_5_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

PDF CSA CONTENTS

SYNC MASTER

DATE

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE OF CONTENTS

N/A

BLOCK DIAGRAM: SYSTEM

J85_MLB_B 04/02/2013

BOM TABLES

J72_MLB_C 11/26/2012

SOC: MAIN

N/A

04/18/2011

SOC: I/OS

N/A

05/05/2011

SOC: NAND

N/A

04/18/2011

SOC: DP,MIPI

MLB

05/04/2012

SOC: SRAM, IO PWRS

N/A

04/18/2011

SOC: VDD, SRAM, CPU, GPU PWRS

N/A

04/18/2011

SOC: MISC & ALIASES

N/A

04/11/2011

IO:

TRISTAR

N/A

NAND STORAGE

MLB

05/04/2012

TOUCH:

SUPPORT CKT & CONN

N/A

06/21/2010

AUDIO:

HP FLEX CONN

N/A

03/31/2011

AUDIO: L81 CODEC

N/A

TABLE_TABLEOFCONTENTS_ITEM

6 TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

10 TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

KAVITHA 01/18/2012

TABLE_TABLEOFCONTENTS_ITEM

AUDIO: CS35L19A AMPS

KAVITHA 01/18/2012

BUTTON:

N/A

VIDEO: EDP SUPPORT & CONN

J85 MLB_C 12/05/2012

SENSOR: OSCAR

J72_MLB_C 11/26/2012

TABLE_TABLEOFCONTENTS_ITEM

CONN

N/A

TABLE_TABLEOFCONTENTS_ITEM

18 TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

CAMERA: FF-ALS CONN & FILTERS

J85 MLB_C 12/03/2012

TABLE_TABLEOFCONTENTS_ITEM

A DRAWING TITLE

SCH,MLB-C1,X200 DRAWING NUMBER

Apple Inc.

051-0886 REVISION

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

DRAWING

A.0.0 BRANCH

PAGE

1 OF 121 SHEET

1 OF 54

SIZE

GRAPE CUMULUS

ISP1_I2C MIPI1C ISP0_I2C MIPI0C

SPI1

CUMULUS

FRONT CAMERA REAR CAMERA D

HSIC2 UART1

MIMO

WIFI/BT ANT

WIFI/BT

UART2 I2S3

WIFI/BT ANT

BT_I2S CSA 58

ALCATRAZ DISPLAY/ TOUCH PANEL

CELLULAR/ GPS HSIC1

HSIC1

EDP

I2S4 UART3

JTAG USART USB

CSA 31-46

BACKLIGHT

NOT ON WIFI-ONLY CONFIG PRIMARY CELLULAR ANT DIVERSITY CELLULAR ANT GPS ANT

SIM CARD

UART5

PMU ANYA

BUTTON FLEX

BATTERY TRISTAR USB2.0 UART0 UART6

CSA 75

DWI I2C0

HOME BUTTON

CSA 81-84

I2C0 OSCAR

UART4 I2C1

HALL EFF 1-3

I2C2 I2S1

CSA 24

CSA 17

RIGHT I2C3

SPI BUS

COMPASS

CSA 13

ACCELEROMETER

AMP SPI2 I2S0 I2S2

GYRO

FMI0 FMI1

SPEAKER

CSA 20

SPI ASP XSP

MBUS

AMP LEFT CSA 20

CSA 27

SPEAKER

CSA 27

L81

AUDIO CODEC

SYNC_MASTER=J85_MLB_B

SYNC_DATE=04/02/2013

PAGE TITLE

NAND FLASH

PROX SENSOR

BLOCK DIAGRAM: SYSTEM

DRAWING NUMBER

CSA 19

Apple Inc.

ALS

NOTICE OF PROPRIETARY PROPERTY:

CSA 28 MIC1

CSA 14

051-0886 REVISION

MIC2

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

A.0.0 BRANCH

PAGE

2 OF 121 SHEET

2 OF 54

SIZE

SOC TABLE_5_HEAD

Page Notes

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

U0652

CRITICAL

BOM OPTION TABLE_5_ITEM

339S0207

H6P + 1GB ELPIDA

Power aliases required by this page: (NONE)

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR PART NUMBER

339S0208

339S0207

Signal aliases required by this page:

BOM OPTION

REF DES

COMMENTS: TABLE_ALT_ITEM

(NONE)

U0652

HYNIX DDR

BOM options provided by this page:

D BOM OPTIONS COMMON ALTERNATE 16GB_PROD 32GB_PROD 64GB_PROD 128GB_PROD DEVELOPMENT_JTAG_TAP JTAG_DAP MLB (WDOG TO PMU)

PMU TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

U8100

CRITICAL

BOM OPTION TABLE_5_ITEM

343S0656

WIFI BOM OPTIONS

IC,PMU,ANYA,D2089A1,OTPXX,FCCSP342

FLASH CONFIGURATIONS

ANDGATE_TI FERRITE_TY FERRITE_TDK

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION TABLE_5_ITEM

335S0921

TOS,19NM,PPN1.5,C,DDP,16GB

U1400

16GB

335S0922

TOS,19NM,PPN1.5,C,QDP,32GB

U1400

32GB

335S0923

TOS,19NM,PPN1.5,C,ODP,64GB

U1400

64GB

335S0929

TOS,19NM,PPN1.5,C,12DP,64GB

U1400

96GB

335S0924

TOS,19NM,PPN1.5,C,16DP,128GB

U1400

128GB

TABLE_5_ITEM

TABLE_ALT_HEAD

TABLE_BOMGROUP_HEAD

BOM GROUP

BOM OPTIONS

BASIC

COMMON,ALTERNATE

PART NUMBER

ALTERNATE FOR PART NUMBER

BOM OPTION

REF DES

COMMENTS:

335S0930

335S0921

16GB

U1400

HYNIX 20NM PPN1.5 16GB

335S0931

335S0922

32GB

U1400

HYNIX 20NM PPN1.5 32GB

335S0932

335S0923

64GB

U1400

HYNIX 20NM PPN1.5 64GB

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

U2200 TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION TABLE_5_ITEM

353S4272 NOTE:

WIFI

U2200

IC,SLG5AP1423V,PWR SW,GREENFET3,4A,TDFN8

FOLLOWING J72, U2200 USES 353S3672 FOOTPRINT (353S4272 HAS SMALLER PADS DUE TO NEW DFM RULES)

4.3UF CAP TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR PART NUMBER

BOM OPTION

REF DES

TABLE_ALT_HEAD

COMMENTS:

PART NUMBER

ALTERNATE FOR PART NUMBER

138S0702

138S0657

BOM OPTION

REF DES

COMMENTS:

C1009,C1015,...

RDAR #13988471

TABLE_ALT_ITEM

339S0223

339S0213

TABLE_ALT_ITEM

U5800

MECHANICAL PARTS TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

TABLE_5_ITEM

806-6207

FENCE,TALL,MLB,X221

PD_FENCE_MLB

CRITICAL

806-7613

FENCE,RADIO,MLB,C BRD,X221

PD_CAN_RADIO

CRITICAL

TABLE_5_ITEM

GYRO TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION TABLE_5_ITEM

338S1192

GYRO, ST MICRO

U2720

CRITICAL

GYRO_STMICRO

338S1218

GYRO, INVENSENSE

U2720

CRITICAL

GYRO_INVENSENSE

132S0391

CAP 0.01UF 25V 0201

C2726

CRITICAL

GYRO_STMICRO

132S0288

CAP 0.1UF 16V 0201

C2726

CRITICAL

GYRO_INVENSENSE

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

338S1158 OLD GYRO - ST MICRO TABLE_5_ITEM

BARCODE LABEL/EEEE CODES

OLDER INVENSENSE P/N 338S1135 OLD INVENSENSE P/N 338S1200 (3/22/13) TABLE_5_ITEM

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

CRITICAL

EEEE_X200C_GOOD

TABLE_5_ITEM

825-7639

EEEE FOR 639-5393 (X200C1 GOOD)

FNJD

TABLE_5_ITEM

825-7639

EEEE FOR 639-5394 (X200C1 BETTER)

FNJ5

CRITICAL

EEEE_X200C_BETTER

825-7639

EEEE FOR 639-5385 (X200C1 BEST)

FNJ9

CRITICAL

EEEE_X200C_BEST

825-7639

EEEE FOR 639-5386 (X200C1 BEST+)

FNJH

CRITICAL

EEEE_X200C_BEST+

825-7639

EEEE FOR 639-5387 (X200C1 ULTIMATE)

FNJ6

CRITICAL

EEEE_X200C_ULTIMATE

825-7639

EEEE FOR 639-5388 (X200C1 GOOD IVS)

FNJ8

CRITICAL

EEEE_X200C_GOOD_IVS

825-7639

EEEE FOR 639-5389 (X200C1 BETTER IVS)

FNJF

CRITICAL

EEEE_X200C_BETTER_IVS

825-7639

EEEE FOR 639-5390 (X200C1 BEST IVS)

FNJC

CRITICAL

EEEE_X200C_BEST_IVS

825-7639

EEEE FOR 639-5391 (X200C1 BEST+ IVS)

FNJ7

CRITICAL

EEEE_X200C_BEST+_IVS

TABLE_5_ITEM

ACCEL

TABLE_5_ITEM

QTY

DESCRIPTION

TABLE_5_ITEM

825-7639

EEEE FOR 639-5392 (X200C1 ULTIMATE IVS)

FNJG

CRITICAL

SYNC_MASTER=J72_MLB_C

TABLE_5_HEAD

PART# 338S1163

EEEE_X200C_ULTIMATE_IVS

U2700

IC,ACCEL,3-AXIS,DIG,BMA282,LGA14

SYNC_DATE=11/26/2012

PAGE TITLE

BOM TABLES

TABLE_5_ITEM

CRITICAL

DRAWING NUMBER TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR PART NUMBER

BOM OPTION

REF DES

Apple Inc.

COMMENTS:

051-0886 REVISION

NOTICE OF PROPRIETARY PROPERTY: 338S1233 ST MICRO - DISQUALâ&#x20AC;&#x2122;ED 338S1114 OLD ACCEL - ST MICRO 338S1191 OLD ACCEL - ST MICRO

A.0.0 BRANCH

PAGE

4 OF 121 SHEET

3 OF 54

SIZE

H6P: JTAG, USB, PLL, HSIC, XTAL D

NOTE: CANDIDATE FOR COST-SAVINGS (REPLACE WITH XW LATER?)

R06222

0.01UF

10% 6.3V 2 X5R 01005

C0608 0.01UF

10% 6.3V 2 X5R 01005

C0691 1

0.22UF

HSIC_VDD120 G22 HSIC_VDD121 G23 HSIC_VDD122 AM31 (3X 13MA)

C0690 1

20% 6.3V X5R 2 0201

OMIT

=PP1V8_SOC 1

R0647 R0646 100K

100K

1% 1/32W MF 2 01005 52 4

JTAG_SOC_TDI

52 11 4

JTAG_SOC_TMS

1% 1/32W MF 2 01005

U0652

R0645

NC_HSIC0_DATA

100K

NC_HSIC0_STB

1% 1/32W MF 2 01005

53 27 24

JTAG_SOC_TCK

53 44

HSIC2_BB_DATA HSIC2_BB_STB

MAKE_BASE=TRUE

HSIC1_BB_DATA HSIC1_BB_STB

HSIC1_WLAN_DATA HSIC1_WLAN_STB

MAKE_BASE=TRUE

52 10

HSIC2_WLAN_DATA HSIC2_WLAN_STB

JTAG_SOC_SEL

JTAG_SOC_TRST_L 52

=PP1V8_SOC 1

R0617

RESET_SOC_L 1

52 4

52 11 4

100K

52 48 24 11 10 8

TP_JTAG_SOC_TDO

JTAG_SOC_TDI JTAG_SOC_TMS JTAG_SOC_TCK

0.1UF

C0607

FCMSP SYM 1 OF 13

A27 HSIC1_DATA B27 HSIC1_STB

HSIC_VDD121

AM33 HSIC2_DATA AM34 HSIC2_STB

HSIC_VDD122

ANALOGMUXOUT E26

Y0602 1.60X1.20MM-SM

1% 1/32W MF 01005 2

24.000MHZ-30PPM-9.5PF-60OHM

R0655

XTAL_SOC_24M_I XTAL_SOC_24M_O

XI0 F25 XO0 E25

VDDIO18_GRP4

12PF

TBD: XTAL PASSIVES WILL CHANGE ON H6P WITH FIRST HW BUILD

1.00M

R0640

5% 16V CERM 01005

C0613 12PF

1.33K2

1 1% 1/32W

SOC_24M_O

MF 01005

5% 16V CERM 01005

D28 D27 E28 E27 F27 F28 C28

JTAG_SEL JTAG_TRTCK JTAG_TRST* JTAG_TDO JTAG_TDI JTAG_TMS JTAG_TCK

NC_ANALOGMUXOUT

USB_DP B29 USB_DM A29

USB_SOC_P USB_SOC_N

11 52

USBHS ON/OFF TOLERANCE 5V/1.98V USB_ANALOGTEST D26 USB_VBUS D23 VDDIO18_GRP3

USB_ID E24

NC_USB_ANALOGTEST

R0651 68.1K

USB_VBUS_DETECT_R

USB_VBUS_DETECT

1% 1/32W MF 01005

NC_USB_ID

F29 RESET* 1.8V TOLERANT

C0618

USB_REXT E23

E29 CFSB 10

SOC_HOLD_RESET

1000PF

C0630

20% 6.3V 2 X5R-CERM 01005

H6P POP-1GB-DDR

MAKE_BASE=TRUE

NC_JTAG_SOC_TRTCK

1% 1/32W MF 2 01005

HSIC_VDD120

MAKE_BASE=TRUE

52 10

54 18 10 7 5 4

A26 HSIC0_DATA B26 HSIC0_STB

=PP3V3_USB_SOC 54

10% 6.3V 2 X5R-CERM 01005

D29 HOLD_RESET

WDOG AD4

H16 FUSE1_FSRC

TST_CLKOUT AC3

USB_REXT WDOG_SOC OUT

VDDIO18_GRP1

H21 HSIC_VSS121 AM32 HSIC_VSS122 H20 HSIC_VSS120

R0642

TP0600

SOC_TEST_CLKOUT

TP-P55

FAST_SCAN_CLK AD3

SOC_FAST_SCAN_CLK

TESTMODE AB3

SOC_TESTMODE

10 52

200

1% 1/32W MF 2 01005

NOTE: NEW USB_REXT VALUE FOR H6 = 200 OHM OLD (H5) VALUE: 44.2 OHM

H23 USB_VSSA0

C0627 0.01UF

=PP1V2_HSIC_SOC

20% 6.3V X5R 2 0201

52 11 4

C0648

0.1UF

C0651

20% 6.3V 2 X5R-CERM 01005

54 18 10 7 5 4

=PP1V0_USB_SOC 54

PP1V8_PLL_SOC_F

01005

0.00

(6X 1MA) VDD_ANA_PLL U16 VDD_ANA_PLL_CCC AE20 (1MA) (5.4MA) USB_DVDD F24 USB_VDD330 F23 (25MA) (25MA)

=PP1V8_PLL_SOC 54

SYNC_MASTER=N/A

SYNC_DATE=04/18/2011

PAGE TITLE

SOC: MAIN DRAWING NUMBER

Apple Inc.

051-0886 REVISION

A.0.0 BRANCH

PAGE

6 OF 121 SHEET

4 OF 54

SIZE

SOC I/OS R0720

OMIT

R0721

33.2 1%

53 16

OUT

I2S1_SPKAMP_MCK

1/32W MF 01005

OUT

2 53 16

OUT

53 16

OUT

53 16

OUT

I2S0_CODEC_ASP_MCK_R I2S0_CODEC_ASP_BCLK I2S0_CODEC_ASP_LRCK I2S0_CODEC_ASP_DIN I2S0_CODEC_ASP_DOUT I2S1_SPKAMP_MCK_R I2S1_SPKAMP_BCLK I2S1_SPKAMP_LRCK I2S1_SPKAMP_DIN I2S1_SPKAMP_DOUT

15 53 15

OUT IN OUT

GPIO_SPKAMP_RIGHT_IRQ_L

OUT

52 27 24

I2S2_CODEC_XSP_BCLK I2S2_CODEC_XSP_LRCK I2S2_CODEC_XSP_DIN I2S2_CODEC_XSP_DOUT

OUT

I2S3_SOC2BT_BCLK I2S3_SOC2BT_LRCK I2S3_BT2SOC_DATA I2S3_SOC2BT_DATA

OUT

52 27 24

OUT

BB_JTAG_TMS BB_JTAG_TDI

52 27 24

BB_JTAG_TDO

52 27 24

OUT

FCMSP SYM 3 OF 13

CRITICAL

AL33 I2S1_MCK AL34 I2S1_BCLK AK33 I2S1_LRCK AJ32 I2S1_DIN AK34 I2S1_DOUT E30 AJ33 AJ34 AH31 AH34

I2S2_MCK I2S2_BCLK I2S2_LRCK I2S2_DIN I2S2_DOUT

VDDIO18_GRP2

AG31 I2S3_MCK AG32 I2S3_BCLK AH33 I2S3_LRCK AF31 I2S3_DIN AG34 I2S3_DOUT AE31 I2S4_MCK AF33 I2S4_BCLK AE32 I2S4_LRCK AD31 I2S4_DIN AE33 I2S4_DOUT

BB_JTAG_TCK

52 27 24

H6P POP-1GB-DDR

BB_JTAG_TRST_L

GPIO_BOARD_ID2 GPIO_BOARD_ID1 GPIO_BOARD_ID0 NC_SPI0_SSIN

OUT

I2C3_SCL W30 I2C3_SDA W32

I2C3_SCL_1V8 I2C3_SDA_1V8

OUT

DWI_AP_CLK

SEP_7816UART0_RST SEP_7816UART0_SCL SEP_7816UART0_SDA SEP_7816UART1_RST SEP_7816UART1_SCL SEP_7816UART1_SDA SIO_7816UART0_RST SIO_7816UART0_SCL SIO_7816UART0_SDA SIO_7816UART1_RST SIO_7816UART1_SCL SIO_7816UART1_SDA

52 13

OUT

52 13

OUT

53 15

OUT

53 15

OUT

AU5 AV4 AU4 AR5

SPI1_MISO SPI1_MOSI SPI1_SCLK SPI1_SSIN

SPI2_CODEC_MISO SPI2_CODEC_MOSI SPI2_CODEC_SCLK SPI2_CODEC_CS_L

AU6 AR6 AP7 AN8

SPI2_MISO SPI2_MOSI SPI2_SCLK SPI2_SSIN

AV10 AN12 AT10 AP11

SPI3_MISO SPI3_MOSI SPI3_SCLK SPI3_SSIN

NC_SPI1_NAVAJO_MOSI NC_SPI1_NAVAJO_SCLK NC_GPIO_NAVAJO2SOC_INT

54 51 5

OUT

48 17 5

5 19

OUT

5 19

SPK AMPS

5 20 22

ALS PROX

5 20 22

OUT

52 15

52 28

OUT

52 13

48 53

OUT

NC_SEP_7816UART0_RST

SEP_I2C0_SCL SEP_I2C0_SDA

OUT

48 52

TP_SOC_TST_CPUSWITCH_OUT

DWI_AP_DO

5 16 52

5 51

OUT

28 24

5 51

NC_SEP_7816UART1_RST NC_SEP_7816UART1_SCL

48 5

OUT

NC_SEP_7816UART1_SDA

52 13

OUT

HSIC1_WLAN2SOC_REMOTE_WAKE HSIC1_WLAN2SOC_DEVICE_RDY HSIC1_SOC2WLAN_HOST_RDY

HSIC2_SOC2BB_HOST_RDY

52 26 24

44 53 44 53

5 44 53

HSIC2_BB2SOC_REMOTE_WAKE HSIC2_BB2SOC_DEVICE_RDY

52 5

24 28

SOCHOT0 AP18 SOCHOT1 AP17

SOCHOT0_L

AN17

DISPLAY_SYNC

OUT

52 26 24

OUT

5 49 52

SOCHOT1_L OUT OUT

5 48

SPI0_MISO SPI0_MOSI SPI0_SCLK SPI0_SSIN

SPI1_GRAPE_MISO SPI1_GRAPE_MOSI SPI1_GRAPE_SCLK SPI1_GRAPE_CS_L

NC_SPI1_NAVAJO_MISO

AB33 AA31 AB31 AA33 AA32 AA34

5 16 52

16 5

OUT

53 44

OUT

48 11

OUT

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38

U0652 H6P POP-1GB-DDR FCMSP SYM 2 OF 13

CRITICAL

TMR32_PWM0 AC31 TMR32_PWM1 AD34 TMR32_PWM2 AC32 UART0_RXD AR19 UART0_TXD AR18

OSCAR_TIME_SYNC_HOST_INT GPIO_SPKAMP_KEEPALIVE

OUT

5 16 52

CLK_32K_SOC2CUMULUS

OUT

13 52

UART0_SOC_RXD UART0_SOC_TXD

11 52

OUT

11 52

UART1_CTSN UART1_RTSN UART1_RXD UART1_TXD

AL2 AL4 AK4 AK3

UART1_BT2SOC_RTS_L UART1_SOC2BT_RTS_L UART1_BT2SOC_TX UART1_SOC2BT_TX

UART2_CTSN UART2_RTSN UART2_RXD UART2_TXD

AL5 AM3 AM2 AM1

NC_UART2_CTS

UART2_WLAN2SOC_TX UART2_SOC2WLAN_TX

UART3_CTSN UART3_RTSN UART3_RXD UART3_TXD

AN3 AN4 AP1 AN1

UART3_BB2SOC_RTS_L UART3_SOC2BB_RTS_L UART3_BB2SOC_TX UART3_SOC2BB_TX

UART4_CTSN UART4_RTSN UART4_RXD UART4_TXD

AV3 AU3 AT3 AT2

OUT

44 53

OUT

44 53

NC_UART2_RTS

PMU_GPIO_OSCAR2PMU_HOST_WAKE GPIO_OSCAR_RESET_L UART4_OSCAR2SOC_RXD UART4_SOC2OSCAR_TXD

UART5_RTXD AM5

UART5_BATT_RTXD

UART6_RXD W31 UART6_TXD Y31

OUT

44 53

24 28

OUT

24 28

11 24 28 52

OUT

11 24 28 52

IN OUT

19 19 53

OUT

19 53

UART6_TS_ACC_RXD UART6_TS_ACC_TXD

19 48

45 48

11 52

OUT

11 52

VDDIO18_GRP1

52 13

I2C1_SOC2OSCAR_SWDCLK_1V8 I2C1_SOC2OSCAR_SWDIO_1V8

48 17 5

TRISTAR PMU

5 11 48 52

I2C2_SCL_1V8 I2C2_SDA_1V8

AR1 AP3 AP2 AR4 AR2 AP4

5 11 48 52

OUT

I2C2_SCL AT11 I2C2_SDA AR11

DISP_VSYNC

AN6 AP5 AT5 AV5

I2C0_SCL_1V8 I2C0_SDA_1V8

I2C1_SCL AP8 I2C1_SDA AU7

DWI_CLK AP19 DWI_DI AT18 DWI_DO AT19

VDDIO18_GRP1

I2C0_SCL AV6 I2C0_SDA AR7

AC5 AB1 AB2 AD1 AD5 AE4 GPIO_SOC2BEACON_EN AF1 GPIO_SOC2AJ_HS4_SHUNT_EN AE2 GPIO_SOC2AJ_HS3_SHUNT_EN AE5 GPIO_BOARD_REV0 AF3 GPIO_BOARD_REV1 AF4 GPIO_BOARD_REV2 AF2 GPIO_CODEC_IRQ_L AG1 GPIO_SOC2BB_WAKE_MODEM AG3 GPIO_GRAPE_IRQ_L AG4 BB_IPC_GPIO AH3 GPIO_ALS_IRQ_L AH2 GPIO_BOARD_ID3 AH4 GPIO_BB2SOC_RESET_DET_L AG5 GPIO_BOOT_CONFIG0 AJ5 GPIO_PMU2SOC_IRQ_L GPIO_SOC2PMU_KEEPACT AJ4 AK2 GPIO_GRAPE_RST_L GPIO_BB2SOC_GPS_SYNC AP13 AP12 GPIO_SOC2BB_RADIO_ON_L AR13 NC_GPIO_BB_HSIC_DEV_RDY AN14 GPIO_BOOT_CONFIG1 AT12 GPIO_FORCE_DFU AT13 TP_GPIO_DFU_STATUS AV13 GPIO_BOOT_CONFIG2 AP14 GPIO_BOOT_CONFIG3 AU13 GPIO_SOC2OSCAR_DBGEN GPIO_SOC2BB_RST_L AP15 AR14 GPIO_PROX_IRQ_L AT14 GPIO_BB2SOC_GSM_TXBURST AT15 GPIO_SPKAMP_RST_L AP16 GPIO_BT_WAKE GPIO_TS2SOC2PMU_INT AR16 AT16 GPIO_SPKAMP_LEFT_IRQ_L AT17 GPIO_SOC2LCD_PWREN

GPIO_BTN_HOME_L GPIO_BTN_ONOFF_L GPIO_BTN_VOL_UP_L GPIO_BTN_VOL_DOWN_L GPIO_BTN_SRL_L

VDDIO18_GRP1

53 15

OUT

U0652

I2S0_MCK I2S0_BCLK I2S0_LRCK I2S0_DIN I2S0_DOUT

VDDIO18_GRP2

NC_GPIO_GYRO_IRQ1

C30 AL32 AL31 AJ31 AK31

VDDIO18_GRP2

48 13 5

VDDIO18_GRP1

I2S0_CODEC_ASP_MCK

VDDIO18_GRP1

OUT

OMIT

VDDIO18_GRP2

53 15

1/32W MF 01005

VDDIO18_GRP2

33.2 1%

=PP1V8_S2R_MISC

R0771 1

220K 2

GPIO_BTN_HOME_L

5 13 48

54 18 10 7 5 4

=PP1V8_SOC NOSTUFF

5% 1/32W MF 01005 54

=PP1V8_ALWAYS

R0700

2.2K 5% 1/32W MF 2 01005

R0770 1

220K 2

GPIO_BTN_ONOFF_L

5 17 48 52 48 11 5

5% 1/32W MF 01005

52 48 11 5

52 16 5 54 51 5

=PP1V8_S2R_MISC

52 16 5

R0765 1

220K 2

22 20 5

5 17 48

22 20 5

(SCREEN ROTATION LOCK)

51 5 51 5

19 5 19 5

=PP1V8_SOC

R0701

2.2K 5% 1/32W MF 2 01005

R0702

1.8K 5% 1/32W MF 2 01005

R0703

1.8K 5% 1/32W MF 2 01005

R0704

2.2K 5% 1/32W MF 2 01005

R0705

2.2K 5% 1/32W MF 2 01005

R0750

2.2K 5% 1/32W MF 2 01005

R0751

2.2K 5% 1/32W MF 2 01005

R0752

2.2K 5% 1/32W MF 2 01005

NOSTUFF

GPIO_SPKAMP_RST_L 5 16 GPIO_SOC2PMU_KEEPACT 5 48 HSIC1_SOC2WLAN_HOST_RDY 5 44 GPIO_FORCE_DFU 5 52 GPIO_SPKAMP_KEEPALIVE 5 16 52

R0753

2.2K 5% 1/32W MF 2 01005

I2C0_SDA_1V8 I2C0_SCL_1V8 I2C2_SDA_1V8 I2C2_SCL_1V8

R0739

100K GPIO_BTN_SRL_L

5% 1/32W MF 01005

54 18 10 7 5 4

1% 1/32W MF 2 01005

I2C3_SDA_1V8 I2C3_SCL_1V8

100K 1% 1/32W MF 2 01005

R0736

100K 1% 1/32W MF 2 01005

R0737

R0738

100K

1% 1/32W MF 2 01005

SEP_I2C0_SDA SEP_I2C0_SCL I2C1_SOC2OSCAR_SWDIO_1V8 I2C1_SOC2OSCAR_SWDCLK_1V8

100K 2

SOCHOT0_L

5 49 52

5% 1/32W MF 01005 54 51 5

R0735

R0754 1

=PP1V8_S2R_MISC

SYNC_MASTER=N/A

SYNC_DATE=05/05/2011

PAGE TITLE

R0755 1

100K 2

SOCHOT1_L

SOC: I/OS

5 48

DRAWING NUMBER

5% 1/32W MF 01005

Apple Inc.

051-0886 REVISION

A.0.0 BRANCH

PAGE

7 OF 121 SHEET

5 OF 54

SIZE

U0652 H6P POP-1GB-DDR FCMSP SYM 12 OF 13

CRITICAL

VSS

OMIT

OMIT AN32 AN33 AN34 AP6 AP20 AP21 AP24 AP25 AP26 AP27 AP28 AP29 AP30 AP31 AP32 AR3 AR8 AR12 AR15 AR17 AR20 AR21 AR22 AR23 AR24 AR25 AR28 AR29 AR32 AT1 AT4 AT6 AT20 AT21 AT22 AT23 AT24 AT25 AT26 AT27 AT28 AT29 AT30 AT31 AT32 AU1 AU2 AU11 AU16 AU18 AU21 AU33 AU34 AV1 AV2 AV9 AV11 AV14 AV16 AV18 AV20 AV33 AV34 B1 B2 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B15 B16 B17 B18 B19 B25 B28 B30 B33 B34 C1 C2 C3 C5 C6 C7 C9

VSS

A1 A2 A3 A4 A5 A7 A9 A11 A13 A14 A16 A18 A25 A28 A30 A33 A34 AA1 AA2 AA3 AA4 AA8 AA10 AA12 AA14 AA16 AA18 AA22 AA24 AA26 AA28 AA30 AB5 AB7 AB9 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB25 AB27 AB29 AB32 AC4 AC8 AC10 AC12 AC14 AC16 AC18 AC20 AC22 AC24 AC26 AC28 AC30 AC34 AD2 AD7 AD9 AD11 AD13 AD15 AD17 AD19 AD21 AD23 AD25 AD29 AD32 AE3 AE8 AE10 AE12 AE14 AE16 AE18 AE22 AE24 AE26 AE28 AF5 AF7 AF9 AF11 AF13 AF15 AF17 AF19

C10 C11 C12 C13 C15 C16 C17 C18 C19 C22 C23 C24 C26 C27 C29 C31 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D15 D16 D17 D18 D19 D20 D21 D22 D32 E1 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E18 E19 E20 E21 E22 E31 E32 E34 F2 F3 F4 F5 F6 F7 F8 F9 F10 F12 F13 F14 F15 F26 F30 F31 G1 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G26 G28

U0652 H6P POP-1GB-DDR FCMSP SYM 11 OF 13

CRITICAL

VSS VSS

AF21 AF23 AF29 AF32 AG2 AG8 AG10 AG12 AG14 AG16 AG18 AG20 AG22 AG24 AG26 AG28 AG30 AH5 AH7 AH9 AH11 AH13 AH15 AH17 AH19 AH21 AH23 AH25 AH27 AH29 AH32 AJ1 AJ3 AJ8 AJ10 AJ12 AJ14 AJ16 AJ18 AJ22 AJ24 AJ26 AJ28 AJ30 AK5 AK7 AK9 AK11 AK13 AK15 AK17 AK19 AK21 AK23 AK27 AK29 AK32 AL3 AL6 AL8 AL10 AL12 AL14 AL16 AL18 AL20 AL22 AL24 AL26 AL28 AL30 AM4 AM7 AM18 AM30 AN2 AN5 AN7 AB6 AM9 AM11 AM13 AN16 AM15 AN19 AN20 AN21 AN22 AN23 AN24 AN31

54 6

=PP1V8_NAND_SOC R0831

R0832

100K

1% 1/32W MF 2 01005 52 12

OUT

FMI0_CE0_L NC_PPN0_CEN1

1% 1/32W MF 2 01005

OMIT G32 PPN0_CEN0 H31 PPN0_CEN1

U0652 H6P POP-1GB-DDR

PPN1_CEN0 R32 PPN1_CEN1 P32

FMI1_CE0_L

12 52

OUT

NC_PPN1_CEN1

FCMSP SYM 4 OF 13

CRITICAL

53 12

OUT

53 12

FMI0_AD<0> FMI0_AD<1> FMI0_AD<2> FMI0_AD<3> FMI0_AD<4> FMI0_AD<5> FMI0_AD<6> FMI0_AD<7>

B32 C32 C33 C34 F32 F33 F34 G34

PPN0_IO0 PPN0_IO1 PPN0_IO2 PPN0_IO3 PPN0_IO4 PPN0_IO5 PPN0_IO6 PPN0_IO7

FMI0_ALE FMI0_CLE FMI0_WE_L FMI0_RE_L FMI0_DQS

A31 B31 A32 D33 D34 E33

PPN0_ALE PPN0_CLE PPN0_WEN PPN0_REN PPN0_DQS PPN0_ZQ

FMI0_ZQ

VDDIO18_GRP3

PPN1_IO0 PPN1_IO1 PPN1_IO2 PPN1_IO3 PPN1_IO4 PPN1_IO5 PPN1_IO6 PPN1_IO7

M34 M33 L32 M32 K32 J32 H33 H34

FMI1_AD<0> FMI1_AD<1> FMI1_AD<2> FMI1_AD<3> FMI1_AD<4> FMI1_AD<5> FMI1_AD<6> FMI1_AD<7>

PPN1_ALE PPN1_CLE PPN1_WEN PPN1_REN PPN1_DQS PPN1_ZQ

N34 P31 N32 L31 L34 K33

FMI1_ALE FMI1_CLE FMI1_WE_L FMI1_RE_L FMI1_DQS

R0871

1% 1/32W MF 01005

D31 PPN0_VREF

OUT

FMI1_ZQ

R0870 240

240

1% 1/32W MF 01005

PPN1_VREF N31

=PP1V8_NAND_SOC 6 1

R0860 50K

1% 1/32W MF 2 01005

B 54

C0860 0.01UF

10% 6.3V 2 X5R 01005

PPVREF_FMI_SOC

R0861

50K

1% 1/32W MF 2 01005

C0861 0.01UF

10% 2 6.3V X5R 01005

SYNC_MASTER=N/A

SYNC_DATE=04/18/2011

PAGE TITLE

SOC: NAND DRAWING NUMBER

Apple Inc.

051-0886 REVISION

A.0.0 BRANCH

PAGE

8 OF 121 SHEET

6 OF 54

SIZE

=PP1V8_MIPI_SOC 1

C0962 0.1UF

20% 6.3V 2 X5R-CERM 01005

D NC_MIPI0D_VREG

1UF

20% 2 4V X6S 0204

NC_SENSOR0_XSHUTDOWN NC_SENSOR1_ISTRB NC_SENSOR1_XSHUTDOWN

53 23

MIPI0C_CAM_REAR_DATA_P<0> MIPI0C_CAM_REAR_DATA_N<0>

AN10 AR9

SENSOR0_ISTRB SENSOR0_XSHUTDOWN

AR10 AP10

SENSOR1_ISTRB SENSOR1_XSHUTDOWN

AU27 MIPI0C_DPDATA0 AV27 MIPI0C_DNDATA0

VDDIO18_GRP1

NC_SENSOR0_ISTRB

MIPI_VDD10 (55MA)

OMIT

U0652

MIPI0D_VREG_0P4V AR27 MIPI1D_VREG_0P4V AR30

C0930

(2MA) MIPI0D_VDD18 AR26 (2MA) MIPI1D_VDD18 AR31

NC_MIPI1D_VREG

AN25 AN26 AN27 AN28 AN29

=PP1V0_MIPI_SOC

=PP1V8_SOC 1

R0931 R0930

2.2K

R0933

2.2K

5% 1/32W MF 2 01005

2.2K 5% 1/32W MF 2 01005

4 5 10 18 54

R0932

2.2K 5% 1/32W MF 2 01005

H6P POP-1GB-DDR

FCMSP SYM 5 OF 13

ISP0_SCL AT7 ISP0_SDA AV7

ISP0_CAM_REAR_SCL ISP0_CAM_REAR_SDA

OUT

ISP1_CAM_FRONT_SCL ISP1_CAM_FRONT_SDA

OUT

20 52

OUT

23 52

OUT

23 52

ISP1_CAM_FRONT_CLK ISP1_CAM_FRONT_SHUTDOWN_L

OUT

20 52

OUT

20 52

MIPI1C_CAM_FRONT_DATA_P<0> MIPI1C_CAM_FRONT_DATA_N<0>

20 53

OUT

20 53

OUT

20 53

23 52 23 52

CRITICAL IN

53 23

DISPLAYPORT

MIPI0C_CAM_REAR_DATA_P<1> MIPI0C_CAM_REAR_DATA_N<1> NC_MIPI0C_CAM_REAR_DATA_P2 NC_MIPI0C_CAM_REAR_DATA_N2

NC_MIPI0C_CAM_REAR_DATA_P3

NC_MIPI0C_CAM_REAR_DATA_N3

R0901 54

=PP1V8_EDP_SOC 1

C0951 56PF

0.00 2 0% 1/32W MF 01005

5% 16V 2 NP0-C0G 01005

PP1V8_EDP_AVDD_AUX 1

C0952

8.2PF

+/-0.5PF 16V 2 NP0-C0G-CERM 01005

C0953

56PF

C0954

0.22UF

5% 16V 2 NP0-C0G 01005

C0955 1.0UF

20% 6.3V 2 X5R 0201

20% 6.3V 2 X5R 0201-1

C0956

53 23

OUT

53 23

OUT

MIPI0C_CAM_REAR_CLK_P MIPI0C_CAM_REAR_CLK_N

1.0UF

20% 6.3V 2 X5R 0201-1

NC_MIPI0D_DPDATA0 NC_MIPI0D_DNDATA0 NC_MIPI0D_DPDATA1 NC_MIPI0D_DNDATA1 NC_MIPI0D_DPDATA2

=PP1V0_EDP_PAD_DVDD_SOC 1

NC_MIPI0D_DNDATA2

C0957 1.0UF

20% 6.3V 2 X5R 0201-1

C0958

NC_MIPI0D_DPDATA3

8.2PF

NC_MIPI0D_DNDATA3

+/-0.5PF 16V 2 NP0-C0G-CERM 01005

NC_MIPI0D_DPCLK

AU24 MIPI0C_DPDATA2 AV24 MIPI0C_DNDATA2 AU23 MIPI0C_DPDATA3 AV23 MIPI0C_DNDATA3

ISP1_SCL AU8 ISP1_SDA AP9 100 01005

SENSOR0_CLK AV8 SENSOR0_RST AT8

ISP0_CAM_REAR_CLK_R

2 49.9 01005

SENSOR1_CLK AU9 SENSOR1_RST AT9

AU25 MIPI0C_DPCLK AV25 MIPI0C_DNCLK

ISP1_CAM_FRONT_CLK_R

R0941

ISP0_CAM_REAR_CLK ISP0_CAM_REAR_SHUTDOWN_L

R0940

20 52

AU32 MIPI0D_DPDATA0 AV32 MIPI0D_DNDATA0 AU31 MIPI0D_DPDATA1 AV31 MIPI0D_DNDATA1

MIPI_VDD10

AU29 MIPI0D_DPDATA2 AV29 MIPI0D_DNDATA2 MIPI1C_DPDATA0 AT33 MIPI1C_DNDATA0 AT34

AU28 MIPI0D_DPDATA3 AV28 MIPI0D_DNDATA3

MIPI1C_DPDATA1 AP33 MIPI1C_DNDATA1 AP34

AU30 MIPI0D_DPCLK AV30 MIPI0D_DNCLK

NC_MIPI1C_CAM_FRONT_DATA_P1 NC_MIPI1C_CAM_FRONT_DATA_N1

MIPI1C_DPCLK AR33 MIPI1C_DNCLK AR34

(50MA) DP_PAD_AVDD3 F22 (50MA) DP_PAD_AVDD2 F21

H6P POP-1GB-DDR

MIPI1C_CAM_FRONT_CLK_P MIPI1C_CAM_FRONT_CLK_N

MIPI_VSS AM25 AM26 AM27 AM28 AM29 AL25

(1MA) DP_PAD_AVDD_AUX F18

DP_PAD_AVDDP0 G18 (14MA)

OMIT

U0652

(50MA) DP_PAD_AVDD1 F20 (50MA) DP_PAD_AVDD0 F19

DP_PAD_AVDDX F17 (14MA)

DP_PAD_DVDD F16 (10MA)

NC_MIPI0D_DNCLK

AU26 MIPI0C_DPDATA1 AV26 MIPI0C_DNDATA1

VDDIO18_GRP1

53 23

FCMSP

TP_EDP_PAD_DC_TP

EDP_HPD D30

EDP_HPD

DP_PAD_AUXP A20 DP_PAD_AUXN B20

EDP_AUX_P EDP_AUX_N

DP_PAD_TX0P A21 DP_PAD_TX0N B21

EDP_DATA_P<0> EDP_DATA_N<0>

OUT OUT

18 53

DP_PAD_TX1P A22 DP_PAD_TX1N B22

EDP_DATA_P<1> EDP_DATA_N<1>

OUT

18 53

OUT

18 53

DP_PAD_TX2P A23 DP_PAD_TX2N B23

EDP_DATA_P<2> EDP_DATA_N<2>

OUT

18 53

OUT

18 53

DP_PAD_TX3P A24 DP_PAD_TX3N B24

EDP_DATA_P<3> EDP_DATA_N<3>

OUT

18 53

OUT

18 53

VDDIO18_GRP3

R0900

4.99K

DP_PAD_AVSS_AUX

18 53

SYNC_MASTER=MLB

SYNC_DATE=05/04/2012

PAGE TITLE

SOC: DP,MIPI DRAWING NUMBER

Apple Inc.

G17

DP_PAD_AVSSP0

DP_PAD_AVSS1 DP_PAD_AVSS0 G19 H19

G20 G21

H18

DP_PAD_AVSS2 DP_PAD_AVSS3

1% 1/32W MF 2 01005

DP_PAD_DVSS

0.01UF

10% 6.3V 2 X5R 01005

CRITICAL

DP_PAD_AVSSX

C0950

H17

SYM 6 OF 13

G16

NOSTUFF

E16 DP_PAD_DC_TP E17 DP_PAD_R_BIAS

SOC_EDP_R_BIAS

051-0886 REVISION

A.0.0 BRANCH

PAGE

9 OF 121 SHEET

7 OF 54

SIZE

OMIT 54

=PP1V2_VDDIOD_SOC

CAPS FOR VDDIOD ARE SHARED WITH VDDQ

AM20 AM21 AM22 AM23 AM24 R29 T29 U29 V29

AA6 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 M6 N6 P6 R6 T6 U6 V6 W6 Y6

U0652 VDDIOD_DDR0CA

H6P POP-1GB-DDR FCMSP

CRITICAL

VDDIOD_DDR1CA

SYM 9 OF 13

VDDIOD_DDRDQ (1000MA)

C VSS

CAPS FOR VDDIO18_X ARE SHARED WITH VDDIODX

=PP1V8_VDDIO18_SOC 54 9

C1070 4.7UF

20% 2 6.3V X5R 402

C1071 1UF

20% 4V 2 X6S 0204

C1072 1UF

VDDIO18_GRP1 (65MA) (GPIO,UART,SPI,I2C) (SENSOR,SOCHOT,PMU)

C1073 0.47UF

20% 4V 2 X7S 0204

20% 4V 2 X6S 0204

AD6 AH6 AM8 AM10 AM12 AM14 AM16 AM19

AD30 AH30

FL1000

1KOHM-25%-0.2A 1

G25 G27 H30 K30 M30 P30 G29

VDDIO18_GRP2 (20MA)

VDDIO18_GRP3 (31MA)

0201 52

PP1V8_XTAL

G24

C1042 1.0UF

20% 10V 2 X5R-CERM 0201-1

VDDIO18_GRP4 (2MA)

R33 T1 T2 T3 T5 T7 T9 T11 T13 T15 T17 T19 T21 T23 T25 T27 T30 T31 T32 T33 T34 U3 U5 U8 U10 U12 U14 U18 U20 U22 U24 U26 U28 U30 U34 V2 V3 V4 V5 V7 V9 V11 V13 V15 V17 V19 V21 V23 V25 V27 V30 V32 V34 W1 W2 W3 W4 W5 W8 W10 W12 W14 W16 W18 W20 W22 W24 W26 W28 W33 Y2 Y3 Y4 Y5 Y7 Y9 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y27 Y29 Y32 AM17 Y30 AC6 AE6 AG6 AJ6 AE30

52 48 24 11 10 4 RESET_SOC_L NOTE: CKEIN CONFIRMED 1.8V TOLERANT ON 5/6/12, BY MANU G

=PP1V2_S2R_DDR_SOC

C1000

DDR0_CA_ZQ DDR1_CA_ZQ DDR0_DQ_ZQ DDR1_DQ_ZQ

0.1UF

54 8

20% 6.3V X5R-CERM 2 01005

=PP1V2_S2R_DDR

R1001 1R1000

R1005

2.21K 1% 1/32W MF 2 01005

PPVREF_DDR0_CA NOSTUFF

R1006

2.21K

10% 6.3V 2 X5R 01005

R1030

R1031

240

1% 1/32W MF 2 01005

8 8

MIN_NECK_WIDTH=0.15 MM MIN_LINE_WIDTH=0.3MM

NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM

C1009

4.3UF 20% 4V 2 X5R-CERM 0610

=PP1V2_VDDQ_DDR 8

C1006

C1007

1UF

20% 2 4V X6S 0204

R1053

1.00K

1% 1/32W MF 2 01005

0.47UF

R1054

1.00K

NOSTUFF

VOLTAGE=0.6V

C1054

0.01UF

1% 1/32W MF 2 01005

10% 6.3V 2 X5R 01005

MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM

NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM

=PP1V8_S2R_DDR 1

54 8

C1004

20% 4V 2 X7S 0204

20% 2 4V X5R-CERM 0610 1

R1051

2.21K 1% 1/32W MF 2 01005

PPVREF_DDR1_CA 1

R1052

2.21K

NOSTUFF

0.01UF

1% 1/32W MF 2 01005

10% 6.3V 2 X5R 01005

VOLTAGE=0.6V

C1052

MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM

NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM

54 8

=PP1V2_VDDQ_DDR 1

C1027 4.3UF

20% 2 4V X5R-CERM 0610

54 8

=PP1V2_VDDQ_DDR 1

C1028 1UF

1.00K 1% 1/32W MF 2 01005 1

NOSTUFF

R1056

1.00K 1% 1/32W MF 2 01005

C1056

0.01UF 10% 6.3V 2 X5R 01005

C1031 0.47UF

PPVREF_DDR1_DQ8

20% 2 4V X7S 0204

VOLTAGE=0.6V MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM

NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM

C1029 1UF

20% 2 4V X6S 0204

R1055

20% 2 4V X6S 0204

AC2 AD33 C20 G2 J33 L3 P33 U2 U33 Y34 AG33 AJ2 AU10 AU14 AU20 AU22 AV17 C4 C8 C14 D24 AE34 AK1 B3 B14 D25 E2 J34 P34 U1 V33 AU12 AU19 AV22

C1015 4.3UF

=PP1V2_S2R_DDR

DDR0_VDD_CKE (<1MA) DDR1_VDD_CKE (<1MA) DDR0_RREF_CA OMIT DDR1_RREF_CA DDR0_RREF_DQ U0652 DDR1_RREF_DQ H6P DDR0_VREF_CA POP-1GB-DDR FCMSP DDR1_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

CRITICAL

(CURRENT CONSUMPTION SHARED WITH VDDIOD)

SYM 7 OF 13

VDDCA

=PP1V2_S2R_DDR 1

PPVREF_DDR0_DQ

AP23 U31 AU15 AC33 F11 T4 AU17 Y33 D14 U4 AB34 AF34 AV12 AV15 AV19 AV21 R34 W34

(DDR IMPEDANCE CONTROL)

54 8

PPVREF_DDR0_CA PPVREF_DDR1_CA PPVREF_DDR0_DQ PPVREF_DDR1_DQ

240

VOLTAGE=0.6V

C1002

0.01UF

1% 1/32W MF 2 01005

240

AP22 DDR0_CKEIN U32 DDR1_CKEIN

C1026 0.47UF

20% 2 4V X7S 0204

A6 A8 C21 C25 F1 J1 L1 N1 R1 V1 A10 A12 A15 A17 A19 AC1 AE1 AH1 AL1 Y1

VSS (500MA) VDD2

(CURRENT CONSUMPTION SHARED WITH VDDIOD)

VDDQ

SYNC_MASTER=N/A

SYNC_DATE=04/18/2011

PAGE TITLE

SOC: SRAM, IO PWRS DRAWING NUMBER

Apple Inc.

051-0886

SIZE

REVISION

(45MA) VDD1

NOTICE OF PROPRIETARY PROPERTY:

G30 G31 G33 H1 H2 H3 H4 H5 H25 H27 H29 H32 J2 J3 J4 J5 J6 J8 J10 J12 J14 J16 J18 J20 J22 J24 J26 J28 J30 J31 K1 K2 K3 K4 K5 K7 K9 K11 K13 K15 K17 K19 K21 K23 K25 K27 K29 K31 K34 L2

A.0.0 BRANCH

PAGE

10 OF 121 SHEET

8 OF 54

4 54

=PPVDD_GPU CRITICAL

=PPVDD_SOC 54

CRITICAL 1

C1100 4.3UF

20% 4V 2 X5R-CERM 0610

CRITICAL 1

C1101 4.3UF

20% 4V 2 X5R-CERM 0610

CRITICAL 1

C1102 4.3UF

20% 4V 2 X5R-CERM 0610

C1103

20% 4V 2 X5R 0402

OMIT

4.3UF

20% 4V 2 X5R-CERM 0610

U0652 H6P POP-1GB-DDR FCMSP SYM 8 OF 13

CRITICAL 1

C1104 1UF

20% 2 4V X6S 0204

CRITICAL

C1110

0.47UF

20% 2 4V X7S 0204

PPVDD_SOC_SOC_SENSE

CRITICAL 1

C1105 1UF

20% 2 4V X6S 0204

CRITICAL

0.47UF

20% 2 4V X7S 0204

1UF

20% 2 4V X6S 0204

CRITICAL

C1111

C1106

CRITICAL 1

1UF

20% 2 4V X6S 0204

C1112 0.22UF

20% 2 6.3V X5R 0201

C1107

CRITICAL 1

C1108

20% 2 4V X6S 0204

C1113 0.22UF

20% 2 6.3V X5R 0201

1UF

C1109 1UF

20% 2 4V X6S 0204

C1114 8.2PF

+/-0.5PF 2 16V NP0-C0G-CERM 01005

OMIT AA7 U0652 AA17 H6P AA19 POP-1GB-DDR FCMSP L29 M28 SYM 10 OF 13 N27 CRITICAL P26 R25 U15 V22 AB30 AH20 H26 J25 K20 K22 K24 K26 K28 L7 L9 L11 L13 L15 L17 L19 L21 L23 L25 L27 (VDD BALLS = VDD_SOC PWR DOMAIN) M8 M10 VDD VDD 2,500MA FOR VDD_SOC M12 @125C M14 @1.0V (THERMAL VIRUS) M16 M18 M20 M22 M24 M26 N7 N9 N11 N13 N15 N17 N19 N21 N23 N25 N29 P8 P10 P12 P14 P16 P18 P20 P22 P24 P28 R7 R9 R11 R13 R15 R17 R19 R21 V31 VDD_SENSE

CRITICAL

CRITICAL 1

R23 R27 T14 T16 T18 T20 T22 T24 T26 T28 U7 U17 U19 U21 U23 U25 U27 V14 V16 V18 V20 V24 V26 V28 W7 W17 W19 Y16 Y18 Y20 AN11 AB14 AB20 AN13 AD20 AN15 AE21 AF6 AF20 AF30 AN18 AK6 AK20 AK30 AL23 AN9 H24 H28 J7 J9 J11 J13 J15 J17 J19 J21 J23 J27 J29 K6 K8 K10 K12 K14 K16 K18

C1170

C1171

15UF

CRITICAL 1

=PPVDD_SRAM_SOC 54 1

C1148 4.3UF

20% 4V 2 X5R-CERM 0610

C1150 1UF

C1151 1UF

20% 4V 2 X6S 0204

C1152 0.47UF

20% 4V 2 X7S 0204

C1153 0.47UF

20% 4V 2 X7S 0204

=PP1V8_VDDIO18_SOC

54 8

C1160

AD24 AD26 AD28 AE23 AE25 AE27 AF24 AF26 AF28 AK25 Y25 AA9 AA11 AA13 AA15 AB8 T8 T10 T12 U9 U11 U13 V8 V10 V12 W9 W11 W13 W15 Y8 Y10 Y12 Y14

AJ20 AA20 AB4 H22

VDD_SRAM_CPU 1,500MA FOR CYCLONE + M$ SRAM @125C @1.0V

VSS

(1500MA)

VDD_SRAM_SOC

VDD_ANA_TMPSADC0(2.5MA) VDD_ANA_TMPSADC1(2.5MA) VDD_ANA_TMPSADC2(2.5MA) VDD_ANA_TMPSADC3(2.5MA)

0.1UF

20% 6.3V 2 X5R-CERM 01005

L4 L5 L6 L8 L10 L12 L14 L16 L18 L20 L22 L24 L26 L28 L30 L33 M1 M2 M3 M4 M5 M7 M9 M11 M13 M15 M17 M19 M21 M23 M25 M27 M29 M31 N2 N3 N4 N5 N8 N10 N12 N14 N16 N18 N20 N22 N24 N26 N28 N30 N33 P1 P2 P3 P4 P5 P7 P9 P11 P13 P15 P17 P19 P21 P23 P25 P27 P29 R2 R3 R4 R5 R8 R10 R12 R14 R16 R18 R20 R22 R24 R26 R28 R30 R31

15UF 20% 4V 2 X5R 0402

CRITICAL

C1172

C1173

4.3UF

CRITICAL 1

4.3UF

20% 4V 2 X5R-CERM 0610

C1174

20% 4V 2 X5R-CERM 0610

CRITICAL

C1115

15UF 20% 4V 2 X5R 0402

CRITICAL

C1121 4.3UF

20% 4V 2 X5R-CERM 0610

20% 4V 2 X5R 0402

20% 2 6.3V X5R 0201

CRITICAL

C1139 0.47UF

20% 4V 2 X7S 0204

0.47UF

20% 4V 2 X7S 0204

C1122

CRITICAL

C1128

20% 2 4V X6S 0204

CRITICAL 1

20% 4V 2 X5R-CERM 0610

CRITICAL

C1123 1UF

C1134

C1189

CRITICAL

C1129

20% 2 4V X6S 0204

CRITICAL

C1135

0.47UF +/-0.5PF 20% 2 16V NP0-C0G-CERM 2 4V X7S 01005 0204

CRITICAL

C1141 0.47UF

20% 4V 2 X7S 0204

CRITICAL

C1142 0.47UF

20% 4V 2 X7S 0204

1UF

CRITICAL

C1130 1UF

20% 2 4V X6S 0204

CRITICAL

C1136

0.47UF

20% 2 4V X7S 0204

C1143 0.22UF

20% 6.3V 2 X5R 01005

C1119

20% 4V 2 X5R-CERM 0610

CRITICAL

20% 4V 2 X7S 0204

CRITICAL

C1125 1UF

20% 4V 2 X6S 0204

CRITICAL

C1131 1UF

20% 2 4V X6S 0204

CRITICAL

C1137

0.47UF

20% 2 4V X7S 0204

C1144 0.22UF

20% 6.3V 2 X5R 01005

CRITICAL 1

C1178

CRITICAL 1

CRITICAL

C1179

C1180

1UF

20% 4V 2 X6S 0204

CRITICAL

C1184

CRITICAL

C1185

0.47UF

20% 4V 2 X7S 0204

20% 6.3V 2 X5R 01005

C1120 4.3UF

20% 4V 2 X5R-CERM 0610

CRITICAL

C1126 1UF

20% 4V 2 X6S 0204

CRITICAL

C1132 1UF

20% 2 4V X6S 0204

CRITICAL

C1138

0.47UF

20% 2 4V X7S 0204

C1190

0.22UF

CRITICAL 1

4.3UF

C1124

20% 4V 2 X5R-CERM 0610

0.47UF

20% 4V 2 X6S 0204

0.47UF

CRITICAL 1

20% 4V 2 X6S 0204

1UF

8.2PF

C1118 4.3UF

20% 4V 2 X6S 0204

1UF

CRITICAL

C1140

CRITICAL

20% 2 4V X6S 0204

0.22UF

20% 4V 2 X5R-CERM 0610

C1127

C1117 4.3UF

4.3UF

CRITICAL

C1133

15UF

1UF

C1116

C1183

4.3UF

20% 4V 2 X5R-CERM 0610

1UF

=PPVDD_CPU

CRITICAL

C1177

4.3UF

CRITICAL

C1182

CRITICAL

C1176

CRITICAL

C1186

0.47UF

20% 4V 2 X7S 0204

C1187 0.47UF

20% 4V 2 X7S 0204

CRITICAL 1

0.47UF 20% 4V 2 X7S 0204

20% 4V 2 X5R-CERM 0610

20% 4V 2 X6S 0204

CRITICAL

CRITICAL 1

4.3UF

1UF

20% 4V 2 X6S 0204

C1188

C1175

CRITICAL

C1181 1UF

CRITICAL 1

4.3UF

CRITICAL 1

C1145 0.22UF

20% 6.3V 2 X5R 0201

PPVDD_CPU_SOC_SENSE

C1191

C1192

0.22UF 20% 6.3V 2 X5R 01005

AA21 AA23 AA25 AA27 AA29 AB22 AB24 AB26 AB28 AC21 AC23 AC25 AC27 AC29 AD22 AD27 AE29 AF22 AF25 AF27 AG21 AG23 AG25 AG27 AG29 AH22 AH24 AH26 AH28 AJ21 AJ23 AJ25 AJ27 AJ29 AK22 AK24 AK26 AK28 AL21 AL27 W21 W23 W25 W27 W29 Y22 Y24 Y26 Y28 AL29

0.22UF

C1193 0.22UF

20% 6.3V 2 X5R 01005

C1194 8.2PF

+/-0.5PF 16V 2 NP0-C0G-CERM 01005

OMIT

U0652 H6P POP-1GB-DDR FCMSP SYM 13 OF 13 CRITICAL

7,500MA FOR G3 GPU @125C @1.1V VDD_CPU VDD_GPU 10,800MA FOR CPU0+1 @125C @1.1V/1.2GHZ

AN30 VDD_SENSE_CPU

AB10 AB12 AB16 AB18 AC11 AC13 AC15 AC17 AC19 AC7 AC9 AD10 AD12 AD14 AD16 AD18 AD8 AE11 AE13 AE15 AE17 AE19 AE7 AE9 AF10 AF12 AF14 AF16 AF18 AF8 AG11 AG13 AG15 AG17 AG19 AG7 AG9 AH10 AH12 AH14 AH16 AH18 AH8 AJ11 AJ13 AJ15 AJ17 AJ19 AJ7 AJ9 AK10 AK12 AK14 AK16 AK18 AK8 AL11 AL13 AL15 AL17 AL19 AL7 AL9 AM6

VDD_GPU_SENSE AA5 PPVDD_GPU_SOC_SENSE

SYNC_MASTER=N/A

SYNC_DATE=04/18/2011

PAGE TITLE

SOC: VDD, SRAM, CPU, GPU PWRS DRAWING NUMBER

Apple Inc.

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

11 OF 121 SHEET

9 OF 54

BOOT CONFIG ID 54 18 10 7 5 4

=PP1V8_SOC NOSTUFF 1

R1200

2.2K

5% 1/32W MF 2 01005

BOOT_CONFIG[3] (GPIO29)

GPIO_BOOT_CONFIG3

BOOT_CONFIG[2] (GPIO28)

GPIO_BOOT_CONFIG2

BOOT_CONFIG[1] (GPIO25)

GPIO_BOOT_CONFIG1

BOOT_CONFIG[0] (GPIO18)

GPIO_BOOT_CONFIG0

NOSTUFF 1

R1201

2.2K

5% 1/32W MF 2 01005

NOSTUFF 1

NOSTUFF

R1203

2.2K

R1250

2.2K

5% 1/32W MF 2 01005

52 4

JTAG_SOC_TRST_L

0.00 2

RESET_SOC_L

4 8 11 24 48 52

0% 1/32W MF 01005

R1211 100

5% 1/32W MF 2 01005

BOOT_CONFIG[3-0] 0000 0001 0010 0011

JTAG

R1202

JTAG_SOC_SEL

S/W READ FLOW

SPI0 SPI0 TEST MODE NAND <-- SELECTED NAND TEST MODE

1. 2. 3.

SET GPIO AS INPUT DISABLE PU AND ENABLE PD READ

D OUT

4 52

R1210 100

5% 1/32W MF 2 01005

R1260 1

100

SOC_TESTMODE

4 52

5% 1/32W MF 01005

BOARD ID

54 18 10 7 5 4

=PP1V8_SOC 1

R1213

R1204

2.2K

BOARD_ID[3]

GPIO_BOARD_ID3

BOARD_ID[2]

GPIO_BOARD_ID2

BOARD_ID[1]

GPIO_BOARD_ID1

BOARD_ID[0]

GPIO_BOARD_ID0

ID_J86_J87

2.2K

5% 1/32W MF 2 01005

ID_J85_J87

R1205

2.2K

5% 1/32W MF 2 01005

ID_DEV

SOC_FAST_SCAN_CLK

SOC_HOLD_RESET

I2S3_SOC2BT_BCLK

I2S3_SOC2BT_LRCK

I2S4_SOC2BT_LRCK

I2S4_BT2SOC_DATA

I2S4_SOC2BT_DATA

MAKE_BASE=TRUE

2.2K

5% 1/32W MF 2 01005

I2S3_BT2SOC_DATA

I2S3_SOC2BT_DATA

MAKE_BASE=TRUE

ID[3-0]

I2S4_SOC2BT_BCLK MAKE_BASE=TRUE

R1206

WDOG_SOC

WDOG_SOC2PMU_RESET_IN

MAKE_BASE=TRUE

SYSTEM

MLB

1010 1011

J85 J85

AP DEV

MLB_B

1100 1101

J86 J86

AP DEV

MLB_C

1110 1111

J87 J87

AP DEV

S/W READ FLOW 1. 2. 3.

SET GPIO AS INPUT DISABLE PU AND ENABLE PD READ

BOARD REVISION

SIM CARD

GPIO_BOARD_REV2 GPIO_BOARD_REV1 5 GPIO_BOARD_REV0 5

NOSTUFF 1

R1207

PP_LDO6_RUIM_1V8

R1209

2.2K

5% 1/32W MF 2 01005

CELL

2.2K

5% 1/32W MF 2 01005

C3001 1.0UF

10% 2 16V X5R 0402

CELL

NC_J3000_5

R3000 15.00K

5% 1/32W MF 2 01005

52 27 25 24

R1208

2.2K

VCC

1% 1/32W MF 2 01005

NOSTUFF

CELL

VPP

J3000 SIM-CARD-X113-X223 F-ST-SM

S/W READ FLOW 52 28 24

EVT

1. 2. 3.

SET GPIO AS INPUT ENABLE PU AND DISABLE PD READ

52 28 24

SIMCRD_CLK_CONN

2 RESET 3 CLK

I/O 6

SIMCRD_IO_CONN

DETECT 7

SIM_TRAY_DETECT

BI OUT

24 28 52

CELL 1

8 9 10 11 12 4

101

SIMCRD_RST_CONN

DETGND GND GND GND GND GND

BRD_REV[2-0]

C3002

100PF

5% 6.3V 2 CERM 01005

SYNC_MASTER=N/A

SYNC_DATE=04/11/2011

PAGE TITLE

SOC: MISC & ALIASES DRAWING NUMBER

Apple Inc.

051-0886

NOTICE OF PROPRIETARY PROPERTY:

TABLE_DASHBOARD_INFO

CKPLUS RULE EXCEPTIONS SCHEMATIC DEFINED CONSTRAINTS (YES/NO)

REQUIRED

SIZE

REVISION

A.0.0 BRANCH

PAGE

12 OF 121 SHEET

10 OF 54

8 343S0658 998-5855 343S0639 343S0614

7 = = = =

TRISTAR TRISTAR TRISTAR TRISTAR

2, A1 2, TC 2, A0 1

D TRISTAR =PP3V0_S2R_TRISTAR 1

C1320

C1300

8.2PF

C1360

1.0UF 20% 10V 2 X5R-CERM 0201-1

=PP1V8_S2R_TRISTAR 1

C1321

8.2PF +/-0.5PF 2 16V NP0-C0G-CERM 01005

=PP3V3_ACC 54 1

C1301

0.1UF 20% 2 6.3V X5R-CERM 01005

ACC_PWR D5

0.1UF

+/-0.5PF 20% 6.3V 2 16V NP0-C0G-CERM 2 X5R-CERM 01005 01005

VDD_3V0 F4

VDD_1V8 F3

C1302

0.1UF CRITICAL

C1322

8.2PF

10% 2 6.3V CERM-X5R 0201

+/-0.5PF 2 16V NP0-C0G-CERM 01005

PPVBUS_PROT 46

U1300 52 15

53 52 24

TO USB BB MUX 53 52 24

AP USB

52 4 52 4

ACCESSORY UART

52 5 52 5

AP DEBUG UART

52 5 52 5

BB DEBUG UART (Tâ&#x20AC;&#x2122;S OFF TO H4A UART4)

52 28 24 5 52 28 24 5

52 4

C3 C4

USB_BB_P USB_BB_N

A1 B1

PMU_USB_BRICKID

USB_SOC_P USB_SOC_N

A3 B3

UART6_TS_ACC_TXD UART6_TS_ACC_RXD

E2 E1

UART0_TX UART0_RX POW_GATE_EN* D6

UART0_SOC_TXD UART0_SOC_RXD

F2 F1

UART1_TX UART1_RX

SWITCH_EN E4 HOST_RESET B6

UART3_BB2SOC_TX UART3_SOC2BB_TX

D2 D1

UART2_TX UART2_RX

JTAG_SOC_TCK JTAG_SOC_TMS

A5 B5

JTAG_CLK JTAG_DIO

SDA SCL INT BYPASS

P_IN F6 ACC1 C5 ACC2 E5

DIG_DN USB1_DP USB1_DN

PPOUT_E75_ACC_ID1 PPOUT_E75_ACC_ID2

DP1 A2 DN1 B2

E75_DPAIR1_P E75_DPAIR1_N

DP2 A4 DN2 B4

E75_DPAIR2_P E75_DPAIR2_N

CON_DET_L E3

TS_CON_DET_L

BRICK_ID USB0_DP USB0_DN

D3 D4 C6 E6

OVP_SW_EN_L

F5 C1 A6

10% 2 25V X5R 402 43 43

43 43

OUT

RESET_SOC_L TS2PMU_RESET_IN I2C0_SDA_1V8 I2C0_SCL_1V8 GPIO_TS2SOC2PMU_INT TRISTAR_BYPASS

4 8 10 24 48 52

OUT

5 48 52 5 48 52

OUT

5 48

VOLTAGE=3V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=0.5MM

DVSS DVSS DVSS

52 4

WLCSP

MIKEY_TS_P MIKEY_TS_N

DIG_DP

C1361

1UF

CBTL1610A1UK 52 15

CRITICAL 1

C1303

1.0UF 20%

2 10V X5R-CERM

TRISTAR BYPASS FOR 3V LDO

0201-1

R1370 15

OUT

L81_MBUS_REF

0.00 2 0% 1/32W MF 01005

SYNC_MASTER=N/A

SYNC_DATE=N/A

PAGE TITLE

IO:

TRISTAR DRAWING NUMBER

Apple Inc.

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

13 OF 121 SHEET

11 OF 54

=PP3V3_NAND 1

C1490

27PF

5% 16V 2 NP0-C0G 01005

C1491

27PF

5% 16V 2 NP0-C0G 01005

C1400

10UF

20% 6.3V 2 CERM-X5R 0402-2

C1401

10UF

20% 6.3V 2 CERM-X5R 0402-2

C1402

10UF

20% 6.3V 2 CERM-X5R 0402-2

C1480

10UF

20% 6.3V 2 CERM-X5R 0402-2

C1405

1UF

C1406

1UF

20% 4V 2 X6S 0204

20% 6.3V 2 X5R 0201

C1407

1UF

20% 6.3V 2 X5R 0201

C1404

=PP1V8_NAND

0.47UF

20% 4V 2 X7S 0204

C1410

15UF

C1411

15UF

20% 2 4V X5R 0402

C1412

15UF 20% 2 4V X5R 0402

C1413

2.2UF 20% 2 4V X5R-CERM 0201

C1493

27PF 5% 2 16V NP0-C0G 01005

12 48 54

C1494

27PF 5% 2 16V NP0-C0G 01005

PPVDDI_NAND

27PF

5% 2 16V NP0-C0G 01005

C1450

2.2UF

20% 2 4V X5R-CERM 0201

N1 N7 OC8 OD8 OE0 OF8 G0 OA8

C1492

B6 F2 M6

OB8

LAYOUT NOTE FOR U1400 VDDI: ENSURE TRACE INDUCTANCE < 2NH

VDDI VCC BI

53 6

FMI0_AD<0> FMI0_AD<1> FMI0_AD<2> FMI0_AD<3> FMI0_AD<4> FMI0_AD<5> FMI0_AD<6> FMI0_AD<7> FMI1_AD<0> FMI1_AD<1> FMI1_AD<2> FMI1_AD<3> FMI1_AD<4> FMI1_AD<5> FMI1_AD<6> FMI1_AD<7>

G3 H2 J3 K2 L5 K6 J5 H6 G1 J1 L1 N3 N5 L7 J7 G7

IO0-0 IO1-0 IO2-0 IO3-0 IO4-0 IO5-0 IO6-0 IO7-0

VCCQ CRITICAL OMIT

U1400 LGA-12X17

XXNM-XGBX8-MLC-PPN1.5-ODP

IO0-1 IO1-1 IO2-1 IO3-1 IO4-1 IO5-1 IO6-1 IO7-1

CE0* CLE0 ALE0 WE0*

A5 A3 C1 E3

RE0 B4 RE0* C7

FMI0_CE0_L FMI0_CLE FMI0_ALE FMI0_WE_L

6 52

FMI0_RE_L

FMI0_DQS

6 53

6 52

FMI1_RE_L

FMI1_DQS

NC_U1400_RE0

DQS0 H4 DQS0* F4

NC_U1400_DQS0

R/B0* E5

TP_U1400_RB0

CE1* CLE1 ALE1 WE1*

C5 C3 D2 E1

RE1 D4 RE1* D6

FMI1_CE0_L FMI1_CLE FMI1_ALE FMI1_WE_L

DQS1 M4 DQS1* K4

NC_U1400_DQS1

R/B1* E7

TP_U1400_RB1

53 53

TP_TMSC_U1400

OA0 TCKC OB0 TMSC

ZQ A1

R1460

50K

48 54

C1460 0.01UF

1% 1/32W MF 2 01005

10% 2 6.3V X5R 01005

PPVREF_FMI_NAND

VREF G5 TP_TCKC_U1400

=PP1V8_NAND 12

NC_U1400_RE1

FMI_ZQ_U1400

VSSQ

VSS

B2 F6 L3

A7 M2 OC0 OD0 OE8 OF0 G8

R1454

243

R1461 50K

1% 1/32W MF 2 01005

C1461 0.01UF

10% 6.3V 2 X5R 01005

SYNC_MASTER=MLB

SYNC_DATE=05/04/2012

PAGE TITLE

NAND STORAGE DRAWING NUMBER

Apple Inc.

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

14 OF 121 SHEET

12 OF 54

TOUCH SUBSYSTEM L1700

RCPT - MLB 998-4526 -> 516S1054 (PLUG - FLEX 998-4527)

240OHM-350MA

=PP5V25_GRAPE

PP5V25_GRAPE_FILT

13 52

0201 1

C1700

5% 16V 01005

2 X5R

27PF

2 NP0-C0G

C1701

10% 10V 402

2 X7R-CERM

1UF

CRITICAL

C1702

J1700

1000PF

503304-2010

10% 16V 0201

F-ST-SM-1 22

R1752

0.00 0% 1/32W MF 01005

5 5

DISPLAY_SYNC

SPI1_GRAPE_SCLK

52 13

1/32W MF 01005

=PP1V8_S2R_GRAPE

CRITICAL 54

=PPVCC_MAIN_GRAPE 1

C1750

01005

2 6.3V X5R

52 13

PP1V8_GRAPE_FILT

13 52

NC_PMU_GPIO_HALL_IRQ_4

PMU_GPIO_MB_HALL3_IRQ PMU_GPIO_MB_HALL2_IRQ PMU_GPIO_MB_HALL1_IRQ

PP5V25_GRAPE_FILT

48 48 48

13 52

TDFN

7 CAP

GPIO_BTN_HOME_FILT_L

PP1V8_GRAPE_SW

CRITICAL

1 C1753

GND

C1751

R1751

27PF

0201

2 ON

10UF

4700PF

20% 2 10V X5R-CERM 0402-2

10% 10V 201

1% 1/32W MF 2 01005

C1761

SLG5AP302

=PP1V8_GRAPE

100K

U1700

VCC_MAIN_GRAPE_RAMP

NOSTUFF

2 16V NP0-C0G

20%

CRITICAL

VDD

0.1UF

10% 16V 2 X5R-CERM 0201

C1752

1UF CRITICAL

DISPLAY_SYNC_R 52 SPI1_GRAPE_SCLK_R SPI1_GRAPE_MISO 5 5 SPI1_GRAPE_MOSI 5 SPI1_GRAPE_CS_L 5 CLK_32K_SOC2CUMULUS 5 GPIO_GRAPE_IRQ_L 5 GPIO_GRAPE_RST_L 52

R1753 0.00 0%

PP3V0_S2R_HALL_FILT

2 X7R

C L1760

LAYOUT NOTE: PUT THERMAL VIAS AROUND U2200 IN CASE OF SHORTED CONDITION

48 5

GPIO_BTN_HOME_L

R1790 2

GPIO_BTN_HOME_R_L

1.00K2

GPIO_BTN_HOME_FILT_L

01005 150OHM-25%-200MA-0.7DCR

13 52

1% 1/32W MF 01005

C1760 27PF 5%

2 16V NP0-C0G

01005

0.38 DCR

L1701 240OHM-350MA 1

PP1V8_GRAPE_FILT

13 52

0201 1

C1703

27PF 5% 16V 01005

2 NP0-C0G

C1704 1UF

20% 6.3V 0201

2 X5R

C1705 1000PF 10% 16V 0201

2 X7R-CERM

L1702 240-OHM-0.2A-0.8-OHM

=PP3V0_S2R_HALL 54

PP3V0_S2R_HALL_FILT

13 52

0201-2 1

C1706 27PF 5% 16V 01005

2 NP0-C0G

C1707 1UF

20% 6.3V 0201

2 X5R

C1708 1000PF 10% 16V 0201

2 X7R-CERM

SYNC_MASTER=N/A

SYNC_DATE=06/21/2010

PAGE TITLE

TOUCH:

SUPPORT CKT & CONN DRAWING NUMBER

Apple Inc.

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

17 OF 121 SHEET

13 OF 54

D R1850 15

DMIC1_FF_SCLK

0.00 2 0% 1/32W MF 01005

DMIC1_FF_SCLK_FILT NOSTUFF 1

C1850

P/N 510S0760 - MLB (P/N 510S0761 - FLEX)

27PF 5%

16V 2 NP0-C0G

CRITICAL

01005

J1800

AA07A-S016VA1 F-ST-SM-COMBO

18 17

L1800 54

=PP1V8_DMIC

DMIC1_FF_SD

PP1V8_DMIC_FILT

0201-2 240-OHM-0.2A-0.8-OHM

5 5 52 28

C1800 27PF

5% 16V 2 NP0-C0G 01005

40 39 33 32 25 52 28 24

GPIO_SOC2AJ_HS4_SHUNT_EN GPIO_SOC2AJ_HS3_SHUNT_EN LAT_SW2_CTL

PP_LDO14_2V65

VOLTAGE=2.65V

C1801 1 C1802

19 20

LAT_SW1_CTL

MIN_NECK_WIDTH=0.06 MM

C1820 56PF

5% 2 16V NP0-C0G 01005

C1830 56PF

5% 2 16V NP0-C0G 01005

C1821 56PF

5% 2 16V NP0-C0G 01005

C1822 56PF

5% 2 16V NP0-C0G 01005

0.1UF

27PF

2 6.3V CERM-X5R

2 16V NP0-C0G

10%

0201

CONN_HP_HS4_FILT 15 CONN_HP_HS4_REF_FILT 15 CONN_HP_HS3_REF_FILT 15 CONN_HP_HS3_FILT 15 CONN_HP_RIGHT_FILT 15 CONN_HP_LEFT_FILT 15 CONN_HP_HEADSET_DET_FILT 15

AUDIO_JACK_FLEX AUDIO_JACK_FLEX AUDIO_JACK_FLEX AUDIO_JACK_FLEX

RET2 MIC1 MIC2 RET1

PER DAVE BREECE

01005

SYNC_MASTER=N/A

SYNC_DATE=03/31/2011

PAGE TITLE

AUDIO:

HP FLEX CONN DRAWING NUMBER

Apple Inc.

051-0886

SIZE

REVISION

A.0.0 BRANCH

14 OF 54 PAGE

18 OF 121 SHEET

6 54 16

=PPVCC_MAIN_AUDIO CRITICAL

54 15

C1904

=PP1V8_AUDIO

0.1UF 1

C1902

C1915

0.1UF

20% 2 6.3V X5R-CERM 01005

C1909

NOTE:

4.7UF

10% 10V X5R-CERM 2 0201

20% 10V 2 X5R-CERM 0402

U1900 DECAPS CHANGED ON 5/24/12 PER RADAR #11485846

SIGNAL_MODEL=EMPTY

VOLTAGE=4.2V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.15MM

R1950

1.00

54 16

PP1V7_VCP

1 2 MF-LF 1% 0201 1/20W

=PP1V7_VA_VCP

CRITICAL 1

C1950

4.7UF

CRITICAL 1

C1901

4.7UF

52 15

GND_AUDIO_CODEC

20% 6.3V 2 X5R 402

CRITICAL 1

C1903

0.1UF

10% 10V 2 X5R-CERM 0201

52 15

0.1UF

C1951

10% 10V 2 X5R-CERM 0201

4.7UF

4.7UF 2

6.3V 20% 402 X5R

2.21K2 1% 1/20W

L81_MIC2_BIAS_IN

201

L81_MIC2_BIAS

CRITICAL

0.3MM 0.15MM

NC_MIC1_BIAS 15 AIN1P 15 AIN1N 15 MIC1_BIAS_FILT

R1901

1 MF

L81_FLYN H10 J10 K10 NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE

H2 E3 E4 H3

C1912

4.7UF 1

L81_MIC2_BIAS_FILT_IN

L81_MIC2_BIAS_FILT

20% 6.3V X5R 402 SHORT-8L-0.25MM-SM 2 1

NOSTUFF

2 15

6.3V 10% 0201 CERM-X5R

VOLTAGE=4.2V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.15MM

J3 G4 K3 F3 C1 D1

NC_MIC3_BIAS AIN3P AIN3N MIC3_BIAS_FILT

NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE

H4 C3 C2 G3

XW1903 NOSTUFF

6.3V 10% 0201 CERM-X5R

15 15 15

NC_MIC4_BIAS AIN4P AIN4N MIC4_BIAS_FILT

NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE

F4 D2 E2 F2

GND_AUDIO_CODEC

DP DN HPOUTA HPOUTB HS3 HS4 HS3_REF HS4_REF HPDETECT

J4 K4 J8 K8 J1 52 K1 52 K7 J7 H8

LINEOUTA K6 LINEOUTB J6 LINEOUT_REF H6

MIC4_BIAS AIN4+ AIN4MIC4_BIAS_FILT

L1920

C1908

CODEC_HP_DET

4.7UF 1

C1990

MIC3_BIAS_FILT

MIC4_BIAS_FILT

AIN1N

C1991

AIN3P

100PF

AIN3N

AIN4N

=PP1V8_AUDIO

MIN_LINE_WIDTH=0.20MM

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.50MM

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

MIN_NECK_WIDTH=0.20MM

IN IN

53 5

IN OUT OUT

R1940

53 5

1.00K

53 5

OUT

52 5

OUT

52 48

OUT

5% 1/32W MF 2 01005

5 53 5

CODEC_HP_DET

NO_TEST=TRUE

OUT

L1901

TO HEADPHONE JACK

CONN_HP_RIGHT_FILT MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

L1902

FERR-33-OHM-0.8A-0.09-OHM 2

NC_CODEC_LINE_OUT_L NC_CODEC_LINE_OUT_R

NO_TEST=TRUE

CONN_HP_LEFT_FILT

FERR-33-OHM-0.8A-0.09-OHM 0201

CONN_HP_HS3_FILT MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

0201

L1903

E1 L81_FILT F1 CRITICAL

GNDP GNDD GNDHS GNDHS GNDA 53 5

53 5

NOSTUFF

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

0201

MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.1MM

IN IN

L1904

120-OHM-210MA 1

CONN_HP_HS3_REF_FILT MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.1MM

L1905

VOLTAGE=0V 0.15MM 0.20MM

120-OHM-210MA 1

GND_AUDIO_CODEC15

2 01005

CONN_HP_HS4_REF_FILT

MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.1MM

TABLE_ALT_HEAD

DMIC1_FF_SD DMIC1_FF_SCLK

R1912 1/32W 5% R1913 1/32W 5%

22 MF

L81_DMIC1_FF_SD

01005

22 MF

L81_DMIC1_FF_SCLK

B1 B2

DMIC1_SD DMIC1_SCLK

01005

NO_TEST=TRUE

U1900 B7 DMIC2_SD CS42L81-CWZR-A1 WLCSP B6 DMIC2_SCLK

I2S0_CODEC_ASP_MCK

MCLK

I2S0_CODEC_ASP_BCLK I2S0_CODEC_ASP_LRCK I2S0_CODEC_ASP_DOUT I2S0_CODEC_ASP_DIN R1910

A3 B3 A2 A1

ASP_SCLK ASP_LRCK ASP_SDIN ASP_SDOUT

B4 B5 A5 A4 K5 C5 A6 B8 A7

XSP_SCLK XSP_LRCK_FSYNC XSP_SDIN_DAC2_MUTE XSP_SDOUT MBUS_REF CS* CCLK CDIN CDOUT

1/32W

I2S2_CODEC_XSP_BCLK I2S2_CODEC_XSP_LRCK I2S2_CODEC_XSP_DOUT I2S2_CODEC_XSP_DIN R1911 1/32W 5% L81_MBUS_REF SPI2_CODEC_CS_L SPI2_CODEC_SCLK SPI2_CODEC_MOSI SPI2_CODEC_MISO

22 MF

I2S0_CODEC_ASP_SDOUT

01005

I2S2_CODEC_XSP_SDOUT

01005

B9 B10 C9

GPIO_CODEC_IRQ_L PMU_GPIO_CODEC_HS_INT_L PMU_GPIO_CODEC_RST_L

CONN_HP_HS4_FILT MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

0201

CODEC_HP_HS3_REF

C1910

DIGITAL MIC

54 15

4700PF

MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.1MM

MAKE_BASE=TRUE

AIN4P

CONN_HP_HEADSET_DET_FILT

C1920

NC_DMIC2_SCLK

2 0201-2

01005

AIN1P

L1900

SYM 2 OF 2

CODEC_HP_DET_R NOSTUFF

CODEC_HP_HS4_REF

CODEC_AIN

PLACE L1900 TO 1905 CLOSE TO THE HP CONNECTOR

5% 16V 2 NP0-C0G 01005

3.3K 2

10% 10V 2 X7R 201

10UF

100PF

5% 1/32W MF 01005

20% 2 6.3V CERM-X5R 0402

MAKE_BASE=TRUE 1

240-OHM-0.2A-0.8-OHM

R1920 CRITICAL

20% 6.3V X5R 402

L81_MBUS_P L81_MBUS_N 52 CODEC_HP_LEFT 52 CODEC_HP_RIGHT 15 CODEC_HP_HS3 15 CODEC_HP_HS4

NOSTUFF XW1900

MIC1_BIAS_FILT

C1932

FERR-33-OHM-0.8A-0.09-OHM FILT+ FILT-

SHORT-8L-0.25MM-SM 1 2

CODEC_MIC_BIAS_FILT

SIGNAL_MODEL=EMPTY 1

FERR-33-OHM-0.8A-0.09-OHM

MIC3_BIAS AIN3+ AIN3MIC3_BIAS_FILT

SPEAKER_VQ

11 52

15 52

20% 6.3V X5R 402

E10 A10 K2 J2 G2

C10

11 52

C1907

NC_SPEAKER_VQ

4.7UF

MIKEY_TS_P MIKEY_TS_N

100PF

NO_TEST=TRUE

0.1UF 1

C1931

5% 25V 2 NP0-CERM 0201

R1931

5% 25V 2 NP0-CERM 0201

NO_TEST=TRUE

MIC2_BIAS_IN MIC2_BIAS MIC2_BIAS_FILT_IN MIC2_BIAS_FILT AIN2+ AIN2M

5% 1/20W MF 201

C1917

SHORT-8L-0.25MM-SM 2 1 HP_MIC_NEG

CODEC_HP_HS3

L81_AIN2_POS L81_AIN2_NEG

0.1UF HP_MIC_POS

52 15

PPVCC_VPROG_MB

1% 1/20W 201 MF

NOSTUFF

CRITICAL

AIN1MIC1_BIAS_FILT

C1916

XW1902 CODEC_HP_HS4

255K 2

D10 NC_RIGHT_CH_OUT_P AOUT2+ NO_TEST=TRUE NC_RIGHT_CH_OUT_N AOUT2- D9

20% 6.3V X5R 2 0201-1

L81_MBUS_P L81_MBUS_N

L81_PVCP 0.15MM 0.30MM +VCP_FILT H9 CS42L81-CWZR-A1 GNDCP J9 K9 WLCSP L81_NVCP -VCP_FILT 0.15MM 0.30MM SYM 1 OF 2 NC_LEFT_CH_OUT_P MIC1_BIAS AOUT1+ F10 NO_TEST=TRUE NC_LEFT_CH_OUT_N AIN1+ AOUT1_M F9

1.0UF

52 15

U1900

FLYP FLYC FLYN

C C1911

VPROG_MB H1

VPROG_CP G10

VP0 E8 VP1 E9

VL A8

0.3MM 0.15MM

L81_FLYC

VCP0 G8 VCP1 G9

C1906

L81_FLYP

6.3V 20% 402 X5R

C1913

0.1UF

C1905 1

5% 1/20W MF 2 201

5% 1/20W MF 201

R1952

PPVCC_VPROG_MB_F

R1953 0

VOLTAGE=4.2V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.15MM

GND_AUDIO_CODEC

R1930 1

1.0UF

20% 6.3V 2 X5R 0201-1

5% 25V 2 NP0-CERM 0201

PLACE R1930 & R1931 CLOSE TO U3600

1% 1/20W 0201 MF-LF

C1914

C1930 100PF

1.00 2 1

10% 10V 2 X5R-CERM 0201

CRITICAL

R1951

PPVCC_VPROG_CP

VOLTAGE=1.7V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.15MM

MIKEY BUS FILTER

INT* WAKE* RESET*

GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18

C6 D3 D5 D6 D7 D8 E5 E6 E7 F5 F6 F7 F8 G5 G6 G7 H5 H7 J5

PART NUMBER

ALTERNATE FOR PART NUMBER

BOM OPTION

REF DES

155S0773

155S0453

L1904,L1905

338S1213

338S1116

U1900

COMMENTS: TABLE_ALT_ITEM

RADAR:11100717 TABLE_ALT_ITEM

RADAR:13373870 SSMC FAB

SYNC_MASTER=KAVITHA

SYNC_DATE=01/18/2012

PAGE TITLE

AUDIO: L81 CODEC DRAWING NUMBER

Apple Inc.

051-0886

TSTI0 C4 TSTI1 C7 TSTI2 D4

SIZE

REVISION

A.0.0 BRANCH

15 OF 54 PAGE

19 OF 121 SHEET

RIGHT SPEAKER AMP I2C ADDRESS: 1000001X =PPVCC_MAIN_AUDIO

=PP1V7_VA_VCP 15 1 C2091 1 C2094 10UF 10UF 20% 20% 10V 10V 2 X5R-CERM 2 X5R-CERM 0402-1

0402-1

0.1UF

VBST

C2046

10% 6.3V 2 CERM-X5R 0201

CRITICAL

C2047

4.7UF

L2040

U2040

2.2UH-20%-3.3A-0.115OHM L19_R_SWITCH

52 16 5

16 5

52 16 5

54 52 47

CS35L19B-CWZR/C0

A2 B2

FILT+ F2 LDO_FILT C5

WLCSP VER1

I2C2_SDA_1V8

I2C2_SCL_1V8

GPIO_SPKAMP_RIGHT_IRQ_L

A7 INT*

GPIO_SPKAMP_RST_L

A6 RESET*

GPIO_SPKAMP_KEEPALIVE

D7 ALIVE

SDA SCL

ISENSE- F1 ISENSE+ E1 OUT+ D2 OUT- C2

I2S1_SPKAMP_MCK

E7 MCLK

53 16 5

I2S1_SPKAMP_BCLK

E6 SCLK

53 16 5

I2S1_SPKAMP_LRCK

F6 LRCK/FSYNC

2 X5R-CERM1 402

SPKR_R_SES_N SPKR_R_SES_P SPKR_R_P

F7 SDIN

I2S1_SPKAMP_DOUT

E5 SDOUT

I2S1_SPKAMP_DIN

53 16 5

1 20% 6.3V

IREF+ B7 L19_R_IREF

53 16 5

4.7UF

VSENSE- E3 VSENSE+ E2

C7 ADO

PP1V7_VA_VCP

C2048 L19_R_FILT L19_R_LDO_FILT

TFA302610A-SM

X5R-CERM1 402

CRITICAL

XW2040

R2041

CRITICAL

R2040 0.1002 1

SPKR_R_VSENSE_N

SPKR_R_VSENSE_P

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

SPKR_R_CONN_P

MIN_LINE_WIDTH=0.5 MM 1% MIN_NECK_WIDTH=0.2 MM 1/4W

MF 0402

44.2K

GNDA B5 B6 C6 E4 F3 F4

GNDP A3 B3 B4 C3 C4 D3 D4

20% 6.3V

CRITICAL

SIGNAL_MODEL=EMPTY

1 C2045 1 C2092 0.1UF 10UF 10% 20% 10V 10V 2 X5R-CERM 2 X5R 0201 603

0.1UF 10% 10V 2 X5R-CERM 0201

4.7UF 20% 10V 2 X5R-CERM 0402

XW2041

4.7UF 20% 2 10V X5R-CERM 0402

CRITICAL CRITICAL CRITICAL

1 C2044

SIGNAL_MODEL=EMPTY

4.7UF 20% 10V 2 X5R-CERM 0402

16 54

NET_SPACING_TYPE=PWR

L19_R_VBOOST

CRITICAL 1 C2043

CRITICAL 1 C2042

A4 A5

CRITICAL 1 C2041

A1 B1 C1 D1

54 16 15

SPEAKER CONNECTOR

1% 1/20W MF 2 201

C SPKR_R_CONN_P XW2074 SM 16

SPKR_R_CONN_N

SPKR_R_VSENSE_P

SIGNAL_MODEL=EMPTY

SPKR_R_CONN_N XW2075

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

SM 16

SPKR_R_VSENSE_N

16 43 5216 43 52

SIGNAL_MODEL=EMPTY

16 43 5216 43 52

SPKR_L_CONN_P

16 43 5216 43 52 16 43 5216 43 52

XW2076 SM 16

SPKR_L_VSENSE_P

LEFT SPEAKER AMP =PP1V7_VA_VCP 15 L19_L_VBOOST

SPKR_L_VSENSE_N

SIGNAL_MODEL=EMPTY

16 54

NET_SPACING_TYPE=PWR

1 C2090

10UF 20% 10V

2 X5R-CERM 0402-1

1 C2095

10UF 20% 10V 2 X5R-CERM 0402-1

C2056

0.1UF

VBST

10% 6.3V 2 CERM-X5R 0201

CRITICAL

1 20% 6.3V

U2050

L19_L_SWITCH

TFA302610A-SM 52 16 5

52 16 5

16 5

52 16 5

A2 B2

CS35L19B-CWZR/C0 WLCSP VER1

I2C2_SDA_1V8

D5 SDA

I2C2_SCL_1V8

D6 SCL

GPIO_SPKAMP_LEFT_IRQ_L

A7 INT*

GPIO_SPKAMP_RST_L

A6 RESET*

GPIO_SPKAMP_KEEPALIVE

D7 ALIVE

FILT+ F2 LDO_FILT C5

ISENSE- F1 ISENSE+ E1 OUT+ D2 OUT- C2

C7 ADO E7 MCLK

53 16 5

I2S1_SPKAMP_BCLK

E6 SCLK

53 16 5

I2S1_SPKAMP_LRCK

F6 LRCK/FSYNC

53 16 5

I2S1_SPKAMP_DOUT

F7 SDIN

I2S1_SPKAMP_DIN

E5 SDOUT

X5R-CERM1 402 16

SPKR_L_SES_N SPKR_L_SES_P SPKR_L_P

CRITICAL

R2050 0.1002 1

SPKR_L_VSENSE_N SPKR_L_VSENSE_P

MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.5 MM

SPKR_L_CONN_P

MIN_LINE_WIDTH=0.5 MM 1% R2051MIN_NECK_WIDTH=0.2 MM 1/4W

A3 B3 B4 C3 C4 D3 D4

GNDP

GNDA

44.2K

MF 0402

1% 1/20W MF 2 201

SYNC_MASTER=KAVITHA SPKR_L_CONN_N

SYNC_DATE=01/18/2012

PAGE TITLE

AUDIO: CS35L19A AMPS

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

DRAWING NUMBER

Apple Inc.

051-0886

SIZE

REVISION

2. THE CURRENT VERSION OF L19 IS B0 AND WILL CHANGE TO C0 BY MARCH 2013. C0 FIXES PROCESS ISSUES.

B5 B6 C6 E4 F3 F4

53 16 5

1 20% 6.3V

IREF+ B7 L19_L_IREF

I2S1_SPKAMP_MCK

1. ALL THE EMI/DESSENSE FILTER COMPONENTS HAVE BEEN REMOVED BASED ON PERFORMANCE ON J65

4.7UF

VSENSE- E3 VSENSE+ E2

53 16 5

X5R-CERM1 402

C2058 L19_L_FILT L19_L_LDO_FILT

XW2050

CRITICAL

SIGNAL_MODEL=EMPTY

L2050

2.2UH-20%-3.3A-0.115OHM

UPDATED: DEC 13

C2057

4.7UF

SIGNAL_MODEL=EMPTY

1 C2093 1 C2055 0.1UF 10UF 10% 20% 10V 2 X5R-CERM 2 10V X5R 0201 603

0.1UF 10% 2 10V X5R-CERM 0201

CRITICAL

4.7UF 20% 2 10V X5R-CERM 0402

CRITICAL

XW2051

CRITICAL

1 C2054

4.7UF 20% 2 10V X5R-CERM 0402

SM 1

CRITICAL 1 C2053

A4 A5

4.7UF 20% 2 10V X5R-CERM 0402

CRITICAL 1 C2052

A1 B1 C1 D1

CRITICAL

SIGNAL_MODEL=EMPTY

PLACE XWS CLOSE TO CONNECTOR

=PPVCC_MAIN_AUDIO 1 C2051

XW2077 16

I2C ADDRESS: 1000000X 54 16 15

SPKR_L_CONN_N

A.0.0 BRANCH

PAGE

20 OF 121 SHEET

16 4 OF 54 4

BUTTON CONNECTOR (MOVED HERE TO SUPPORT COST FORMAT) (REF DES PRESERVED FOR LAYOUT)

516S0828 CRITICAL

J2960

503548-1010 F-ST-SM 11

L2960 1

1.00K2

GPIO_BTN_VOL_DOWN_R_L

0201-2

GPIO_BTN_VOL_UP_L

1% 1/32W MF 01005

GPIO_BTN_VOL_UP_R_L

R2901 1.00K2 1 1% 1/32W MF 01005

L2962 48 5

GPIO_BTN_SRL_L

240-OHM-0.2A-0.8-OHM 1 2 0201-2

GPIO_BTN_VOL_DOWN_L_FILT 52 GPIO_BTN_VOL_UP_L_FILT 52 GPIO_BTN_SRL_L_FILT

L2961 240-OHM-0.2A-0.8-OHM 1 2 0201-2

GPIO_BTN_SRL_R_L

R2902 1.00K2

GPIO_BTN_ONOFF_L

240-OHM-0.2A-0.8-OHM 1 2 0201-2

3 5

4 6

7 9

8 10

1% 1/32W MF 01005

L2963 48 5

R2900

240-OHM-0.2A-0.8-OHM 5 GPIO_BTN_VOL_DOWN_L

GPIO_BTN_ONOFF_R_L

R2903 1.00K2

1% 1/32W MF 01005 1

C2960

82PF

5% 2 25V CERM 0201

DZ2960

201-1 12.8V-100PF

C2961

82PF

C2962

82PF

5% 2 25V CERM 0201

5% 25V 2 CERM 0201

DZ2961

C2963

82PF

5% 25V 2 CERM 0201

DZ2962

GPIO_BTN_ONOFF_L_FILT

201-1 12.8V-100PF

DZ2963 1

201-1 12.8V-100PF

SYNC_MASTER=N/A

SYNC_DATE=N/A

PAGE TITLE

BUTTON:

CONN DRAWING NUMBER

Apple Inc.

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

21 OF 121 SHEET

17 OF 54

EDP CONNECTOR SUPPORT 54

C2240

0.1UF

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR PART NUMBER

155S0667

155S0583

BOM OPTION

REF DES

COMMENTS: TABLE_ALT_ITEM

L2242,L2810,L2811,L2812,L2813,L2814,L2710,L2711,L2712,L6030,L6031

RDAR://PROBLEM/8616060,

RADAR://PROBLEM/9015335

C2239 0.1UF

10% 2 16V X5R-CERM 0201

OMIT VDD

U2200

CRITICAL

SLG5AP304V

TDFN

LCD_RAMP 7 CAP IN

=PPVCC_MAIN_LCD 1

18 5

GPIO_SOC2LCD_PWREN

CRITICAL ON

L2201

FERR-120-OHM-1.5A

PPVCC_MAIN_LCD_SW

PPVCC_MAIN_LCD_SW_CONN

18 52

0402A

R2205

GND 1

5% 1/32W MF 2 01005

100K

C2241 3900PF

C2203 0.1UF

10% 2 50V X7R 0402

CRITICAL

C2202 10UF

10% 2 16V X5R-CERM 0201

C2230

C2232 15PF

82PF

20% 2 6.3V CERM-X5R 0402

5% 2 16V NP0-C0G-CERM 01005

5% 2 25V CERM 0201

REVIEW: 4700PF 0201 132S0187 RDAR://PROBLEM/12579948

P/N 516S1056 CRITICAL

J2201

LAYOUT NOTE: PUT THERMAL VIAS AROUND U2200 IN CASE OF SHORTED CONDITION

AA07A-S032-VA1

LCM_PWR_EN_RES 18 5

OUT

F-ST-SM-1 34 33

R2291 2

GPIO_SOC2LCD_PWREN

0.00 0% 1/32W MF 01005

18 52 18

LCM_OFF_L EDP_HPD_EMI

PPVCC_MAIN_LCD_SW_CONN

BACK-UP DELAYED PWREN CKT 54 10 7 5 4

=PP1V8_SOC

CRITICAL

L2200

220-OHM-1A 54

=PPLED_REG_A

LCM_PWR_EN_OR_GATE

C2270

0.1UF

PPLED_BACK_REG_A

20% 2 6.3V X5R-CERM 01005

18 52

0402

C2233 8.2PF

+/-0.5PF 2 50V C0G-CERM 201

LCM_PWR_EN_OR_GATE CRITICAL 6

C2221

74LVC1G32

56PF

2% 2 50V NP0-C0G-CERM 0201

18 5

U2201

GPIO_SOC2LCD_PWREN

SOT891 4

R2290 2 1/32W MF 01005

IN IN

PPLED_BACK_REG_A

0.00 0%

LCM_PWR_EN_OR_GATE

GATE2LCD_PWREN

LED_IO_6_A LED_IO_5_A LED_IO_4_A LED_IO_3_A LED_IO_2_A LED_IO_1_A

52 18

EDP_DATA_EMI_CONN_N<3> EDP_DATA_EMI_CONN_P<3>

18 53

EDP_DATA_EMI_CONN_N<2> EDP_DATA_EMI_CONN_P<2>

18 53

EDP_DATA_EMI_CONN_N<1> EDP_DATA_EMI_CONN_P<1>

18 53

EDP_DATA_EMI_CONN_N<0> EDP_DATA_EMI_CONN_P<0>

18 53

EDP_AUX_EMI_CONN_N EDP_AUX_EMI_CONN_P

NC_U2201_5

REVIEW: CAN/SHOULD WE USE 132S0316, 0.1UF 20%, 01005 RDAR://PROBLEM/12579963

CRITICAL 7

EDP_AUX_P EDP_AUX_N

C2250 1 01005 6.3V

20.1UF EDP_AUX_EMI_P 20% X5R-CERM

C2251 1 01005 6.3V

2 EDP_AUX_EMI_N 20% X5R-CERM

L2242

0.1UF

R2243

100K

EDP_AUX_EMI_CONN_N

OUT

REVIEW: WILL THE DISPLAY INCLUDE A VOLTAGE DIVIDER TO REDUCE THE 2.5V FROM THE TCON TO 1.8V TO THE AP? RDAR://PROBLEM/12579981

L2240 18

100K

5% 1/32W MF 2 01005

R2250

240-OHM-25%-0.20A-1.0DCR

SYM_VER-2 TAM0605-4SM 3.25-OHM-0.1A-2.4GHZ

R2241

EDP_AUX_EMI_CONN_P

EDP_HPD_EMI

EDP_HPD_2P5

01005

5% 1/32W MF 2 01005

7.5K 2 5% 1/32W MF 01005

C2260 27PF

EDP_HPD

OUT

R2242 20.0K

5% 1/32W MF 2 01005

2 16V NP0-C0G

01005

CRITICAL 53 7

53 7

EDP_DATA_P<0>

C2242 1 01005 6.3V

2 0.1UF 53 EDP_DATA_EMI_P<0> 20% X5R-CERM

C2243 1

2 0.1UF 53 EDP_DATA_EMI_N<0> 20% X5R-CERM

EDP_DATA_N<0>

01005 6.3V

L2212 2

EDP_DATA_EMI_CONN_P<0>

OUT

18 53

EDP_DATA_EMI_CONN_N<0>

OUT

18 53

EDP_DATA_EMI_CONN_N<1>

OUT

18 53

EDP_DATA_EMI_CONN_P<1>

OUT

18 53

EDP_DATA_EMI_CONN_N<2>

OUT

18 53

EDP_DATA_EMI_CONN_P<2>

OUT

18 53

NOTE: PER GREG DE MERCEY, EDP_HPD PIN IS 2.5V TOLERANT HOWEVER TO BE CONSERVATIVE, DIVIDER CKT IS NOT REMOVED

SYM_VER-2 TAM0605-4SM 3.25-OHM-0.1A-2.4GHZ

CRITICAL 53 7

53 7

C2244 1 01005 6.3V

2 0.1UF 53 EDP_DATA_EMI_N<1> 20% X5R-CERM

C2245 1 01005 6.3V

2 0.1UF 53 EDP_DATA_EMI_P<1> 20% X5R-CERM

C2246 1 01005 6.3V

2 0.1UF 53 EDP_DATA_EMI_N<2> 20% X5R-CERM

C2247 1 01005 6.3V

2 0.1UF 53 EDP_DATA_EMI_P<2> 20% X5R-CERM

EDP_DATA_N<1> EDP_DATA_P<1>

L2222 2

SYM_VER-2 TAM0605-4SM 3.25-OHM-0.1A-2.4GHZ

CRITICAL 53 7

53 7

EDP_DATA_N<2> EDP_DATA_P<2>

L2232 2

SYM_VER-2 TAM0605-4SM 3.25-OHM-0.1A-2.4GHZ

SYNC_MASTER=J85 MLB_C

53 7

EDP_DATA_N<3> EDP_DATA_P<3>

C2248 1 01005 6.3V C2249

1 01005 6.3V

2 0.1UF 53 EDP_DATA_EMI_N<3> 20% X5R-CERM 2 0.1UF 53 EDP_DATA_EMI_P<3> 20% X5R-CERM

SYNC_DATE=12/05/2012

PAGE TITLE

CRITICAL

L2202

EDP_DATA_EMI_CONN_N<3>

EDP_DATA_EMI_CONN_P<3>

OUT

18 53

OUT

18 53

VIDEO: EDP SUPPORT & CONN DRAWING NUMBER

Apple Inc. R

SYM_VER-2 TAM0605-4SM 3.25-OHM-0.1A-2.4GHZ

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

22 OF 121 SHEET

18 OF 54

OSCAR OSCAR VDDIO = 1.8V HIBERNATE (NEED TO WAKE HOST) OSCAR CORE = 1.2V HIBERNATE (NEED TO RUN IN S2R)

=PP1V2_S2R_OSCAR

C2400

=PP1V8_S2R_OSCAR

C2401 VDDC C1 VDDC C6

1.0UF

20% 6.3V 2 X5R 0201-1

=PP1V8_S2R_OSCAR 1

R2400 100K

5% 1/32W MF 2 01005 5

19 54

1.0UF

20% 6.3V 2 X5R 0201-1

R2405

CRITICAL

REVIEW:NEED PU ON CS? RDAR://PROBLEM/12579997

54 19

APN 337S4416

VDDIO C2

U2400

OUT

48 5

OUT

SPI_OSCAR2ACCEL_CS_L SPI_OSCAR2GYRO_CS_L ACCEL2OSCAR_INT1 GYRO2OSCAR_INT2 GYRO2OSCAR_INT1 ACCEL2OSCAR_INT2 COMPASS2OSCAR_INT SPI_OSCAR2COMPASS_CS_L OSCAR_TIME_SYNC_HOST_INT PMU_GPIO_OSCAR2PMU_HOST_WAKE NC_ISP0_CAM_REAR_SDA

GPIO_OSCAR_RESET_L

LPC18A1UK-CPA1

E3 E5 E6 C5 D5 E2 D3 D4 E1 A3 A2

P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7 P0_8 P0_9 P0_10

RESET*

WLCSP

P0_11 P0_12 P0_13 P0_14 P0_15 P0_16 P0_17 P0_18 P0_19 P0_20 P0_21 P0_22

A1 B2 A4 B3 B4 A5 B5 C3 C4 B6 D1 A6

DBGEN D2

GPIO_SOC2OSCAR_DBGEN_R

VSS VSS

NC_ISP0_CAM_REAR_SCL SPI_OSCAR_SCLK_R SPI_OSCAR_MISO IN 21 SPI_OSCAR_MOSI_R UART4_OSCAR2SOC_RXD OUT 5 53 UART4_SOC2OSCAR_TXD IN 5 53 OSCAR2RADIO_CONTEXT_A OUT 28 44 OSCAR2RADIO_CONTEXT_B OUT 28 44 I2C1_SOC2OSCAR_SWDIO_1V8 BI 5 I2C1_SOC2OSCAR_SWDCLK_1V8 IN 5 PMU_GPIO_CLK_32K_OSCAR IN 48 52 TP_OSCAR_P0_22 R2450

0.00 2

SPI_OSCAR_SCLK

OUT

SPI_OSCAR_MOSI

5% 1/32W MF 01005

R2406 1

15.0 2

5% 1/32W MF 01005

52 52

NOTE: I2C1 IS ASSUMED TO USE PUSH-PULL INSTEAD OF OPEN-DRAIN

GPIO_SOC2OSCAR_DBGEN

0% 1/32W MF 01005

B1 D6

REVIEW: N51 HAS OSCAR I2C CONNECTED TO RF CAM I2C COMPARE SENSOR CONNECTIONS WITH N51, IDENTIFY AND UNDERSTAND DIFFERENCES RDAR://PROBLEM/12580012

15.0 2

SYNC_MASTER=J72_MLB_C

SYNC_DATE=11/26/2012

PAGE TITLE

SENSOR: OSCAR DRAWING NUMBER

Apple Inc.

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

24 OF 121 SHEET

19 OF 54

VGA FRONT CAMERA CONNECTOR D

L2600 240OHM-350MA

=PP2V9_CAM_FRONT

PP2V9_AVDD_CAM_FRONT_FILT

2 0201

56PF

XW2600 SM 1

C2600

1UF

5% 16V 01005

10% 6.3V 01005

2 X5R

VOLTAGE=2.9V MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm NET_SPACING_TYPE=PWR

C2602 1000PF

20% 6.3V 0201

2 NP0-C0G

C2601

MAX_NECK_LENGTH=3 MM

L2610

2 X5R-CERM

GND_AVDD_CAM_FRONT

VOLTAGE=0V MIN_LINE_WIDTH=0.15 MM MIN_NECK_WIDTH=0.15 MM NET_SPACING_TYPE=GND

53 20

MIPI1C_CAM_FRONT_CLK_FILT_P

53 20

MIPI1C_CAM_FRONT_CLK_FILT_N

MIPI1C_CAM_FRONT_CLK_P

MIPI1C_CAM_FRONT_CLK_N

MIPI1C_CAM_FRONT_DATA_P<0>

OUT

7 53

MIPI1C_CAM_FRONT_DATA_N<0>

OUT

7 53

OUT

7 53

OUT

SYM_VER-2

TCM0605-1 90-OHM-50MA

L2611 53 20

MIPI1C_CAM_FRONT_DATA_FILT_P<0>

53 20

MIPI1C_CAM_FRONT_DATA_FILT_N<0>

L2601 240OHM-350MA

=PP1V8_CAM_FRONT 54

PP1V8_CAM_FRONT_FILT

SYM_VER-2

TCM0605-1

0201 1

C2603 56PF

5% 16V 2 NP0-C0G 01005

C2604

1UF

90-OHM-50MA

C2605 1000PF

20% 6.3V 2 X5R 0201

L2660

10% 6.3V 01005

150OHM-25%-200MA-0.7DCR

2 X5R-CERM 20

ISP1_CAM_FRONT_CLK_F_R

ISP1_CAM_FRONT_CLK_F

01005

516S0869 PLUG FLEX

L2602 240-OHM-0.2A-0.8-OHM

=PP3V0_ALS

516S0876 RCPT MLB

PP3V0_ALS_FILT

CRITICAL

0201-2 1

C2606

5% 16V 01005

2 X5R

56PF

2 NP0-C0G

C2607

20% 6.3V 0201

2 X5R-CERM

1UF

J2601

C2608

503548-1820

1000PF

F-ST-SM

10% 6.3V 01005

20 2

PP3V0_ALS_FILT

53 20 53 20

53 20

U2600

53 20

400MHZ-0.1A-27PF 1208 52 7

52 7 22 5

IN BI

52 7

ISP1_CAM_FRONT_SDA ISP1_CAM_FRONT_SCL I2C3_SDA_1V8 ISP1_CAM_FRONT_CLK

IN1 IN2

OUT1 OUT2

IN3

OUT3

IN4

MIPI1C_CAM_FRONT_DATA_FILT_P<0> MIPI1C_CAM_FRONT_DATA_FILT_N<0> MIPI1C_CAM_FRONT_CLK_FILT_P MIPI1C_CAM_FRONT_CLK_FILT_N

ISP1_CAM_FRONT_SDA_F 20 ISP1_CAM_FRONT_SCL_F 20 I2C3_SDA_1V8_F 20 ISP1_CAM_FRONT_CLK_F 20

OUT4

I2C3_SCL_1V8_F GPIO_ALS_IRQ_L_F

I2C3_SDA_1V8_F ISP1_CAM_FRONT_CLK_F_R ISP1_CAM_FRONT_SHUTDOWN_L_F ISP1_CAM_FRONT_SDA_F ISP1_CAM_FRONT_SCL_F

20 20

20 20 20

PP2V9_AVDD_CAM_FRONT_FILT 20 GND_AVDD_CAM_FRONT 20 PP1V8_CAM_FRONT_FILT 20

GND

U2601 400MHZ-0.1A-27PF 1208

NC_U2601_1 22 5 5 52 7

IN OUT IN

I2C3_SCL_1V8 GPIO_ALS_IRQ_L ISP1_CAM_FRONT_SHUTDOWN_L

IN1

OUT1

IN2 IN3

OUT2 OUT3

IN4

NC_U2601_5

I2C3_SCL_1V8_F 20 GPIO_ALS_IRQ_L_F 20 ISP1_CAM_FRONT_SHUTDOWN_L_F 20

OUT4

GND 1

R2601

ISP1_CAM_FRONT_SHUTDOWN_L

100K

1% 1/32W MF 2 01005

LOW = SHUT DOWN CAMERA HIGH = TURN ON CAMERA

SYNC_MASTER=J85 MLB_C

SYNC_DATE=12/03/2012

PAGE TITLE

CAMERA: FF-ALS CONN & FILTERS DRAWING NUMBER

Apple Inc.

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

26 OF 121 SHEET

20 OF 54

GYRO L2702

120-OHM-25%-250MA-0.5DCR 54

=PP3V0_S2R_GYRO

PP3V0_GYRO

ACCELEROMETER

C2721 0.1UF

C2723

C2725

10UF

20% 6.3V 2 X5R-CERM 01005

L2700

=PP1V8_S2R_GYRO

01005 1

0.1UF

20% 6.3V 2 CERM-X5R 0402-2

20% 6.3V X5R-CERM 2 01005

120-OHM-25%-250MA-0.5DCR 54

=PP3V0_S2R_ACCEL

PP3V0_ACCEL

=PP1V8_S2R_ACCEL

01005

20% 6.3V CERM-X5R 2 0402-2

C2701

C2750

0.1UF 20% 6.3V X5R-CERM 2 01005

0.1UF

10UF

C2700

OMIT VDD VDD_IO

CRITICAL

20% 6.3V X5R-CERM 2 01005

CKPLUS_WAIVE=PWRTERM2GND

U2700

GYRO_RES_VDD

4 CS

SPI_OSCAR2ACCEL_CS_L

14 RES 13 RES 12 RES 19

OUT

SCL/SPC 1 SDA/SDI/SDO 2 SDO/SA0 3

6 INT1 5 INT2

ACCEL2OSCAR_INT1 ACCEL2OSCAR_INT2

SPI_OSCAR_SCLK IN 19 SPI_OSCAR_MOSI IN 19 SPI_OSCAR_MISO_ACCEL

15 VDD 16

LGA 21 21

R2757 1

0.00 2

RES/VDD

SPI_OSCAR_MISO

OMIT

VDD_IO

CRITICAL

U2720

19 21

0% 1/32W MF 01005

RES 10 RES 11

AP2DHAB26TR

AP3GDL20HAB18TR LGA 19

OUT

SPI_OSCAR2GYRO_CS_L GYRO2OSCAR_INT2 GYRO_DEN

5 6 8

GYRO2OSCAR_INT1

7 INT1

CS DRDY/ INT2 DEN

SCL/SPC 2 SDA/SDI/SDO 3 SDO/SA0 4

SPI_OSCAR_SCLK IN SPI_OSCAR_MOSI IN SPI_OSCAR_MISO_GYRO

19 21 19 21

13 GND

OUT

R2750 0.00

CAP 14

0.00 2

SPI_OSCAR_MISO 19

0% 1/32W MF 01005

RES0 9 RES1 10 RES2 11 12 GND

GND 19

R2727 1

GYRO_PUMP OMIT 1

11V CHARGE PUMP

C2726 0.1UF

10% 2 16V X5R-CERM 0201

0% 1/32W MF 2 01005

COMPASS

APN 338S1014

L2701

L2741

120-OHM-25%-250MA-0.5DCR

=PP3V0_S2R_COMP

PP3V0_COMP

PP1V8_COMP

=PP1V8_S2R_COMP

01005 1

1.0UF

U2710

20% 6.3V X5R-CERM 01005

AK8963C

GND_COMP

CRITICAL

GND_COMP

NC_COMPASS_TST1

NO_TEST=TRUE

C2 TST1

NC_COMPASS_RSV

NO_TEST=TRUE

B3 RSV

CSP D1 CAD0 D2 CAD1

NC_COMPASS_TRG

C2711 0.1UF

VDD VID

20% 6.3V 2 X5R 0201-1

C2710

01005

CSB* A2

SPI_OSCAR2COMPASS_CS_L

19 21

SO B4 SPI_OSCAR_MISO_COMP1

C3 TRG

NO_TEST=TRUE

SCL/SK A3 SPI_OSCAR_SCLK SDA/SI A4 SPI_OSCAR_MOSI

DRDY A1 COMPASS2OSCAR_INT

R2747 1

OUT

15.0 2

SPI_OSCAR_MISO

OUT

19 21

5% 1/32W MF 01005

D4 RST*

PP1V8_COMP

VSS

TO VID WHEN NOT USED 21

GND_COMP

XW2700

SYNC_MASTER=N/A

SHORT-10L-0.25MM-SM 1 2

SYNC_DATE=N/A

PAGE TITLE

TIE CSB* TO VID FOR I2C MODE

XW2701

SENSOR:

ACCEL, COMPASS, GYRO

SHORT-10L-0.25MM-SM

DRAWING NUMBER

Apple Inc.

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

27 OF 121 SHEET

21 OF 54

PROX SENSOR D

54 22

VDRIVE FOR: I2C AND GPIO

=PP1V8_PROX PROX

C2804

PROX 1

C2805

0.1UF

PROX

68PF

20% 6.3V X5R-CERM 2 01005

5% 6.3V NP0-C0G 2 01005

L2800

240-OHM-0.2A-0.8-OHM =PP3V0_PROX

PP3V0_SENSOR_PROX_FILT

1 0201-2

PROX

PROX 1

C2800

C2801

2.2UF

54 22

68PF

20% 6.3V X5R-CERM 2 01005

5% 6.3V NP0-C0G 2 01005

I2C ADDRESS: 0101100+R/W READ: 0X59, WRITE: 0X58

516S0872

PROX

CRITICAL

PROX

R2800

2.0K

SDA

I2C3_SCL_1V8

SCLK

ADD0

GPIO_PROX_IRQ_L PROX_GPIO

ADD1

INT*

GPIO

INT* IS OPEN DRAIN PU RAIL MATCH VDRIVE

C2802

10% 10V X5R-CERM 2 0201

PROX GPIO WILL NOT BE USED. THEREFORE,PROX GPIO IS NOT CONNECTED TO MLB INTERCONNECT.

PROX 1

0.01UF

C2807

27PF 1% 25V NP0-C0G 2 201

R2801

100K 1% 1/32W MF 01005 2

PROX

INT IS 1.8V LEVEL.

ACSHIELD

353S2964

CRITICAL

CIN0 CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 CIN8 CIN9 CIN10 CIN11 CIN12

D3 A3 B3 A4 C3 A5 B4 B5 C4 C5 D4 D5 E5

PROX_CIN1

F-ST-SM

L2801

CIN9

CIN9 SENSOR ELECTRODE PROX_CIN9_CONN CIN7 DUMMY PROX_CIN7_CONN

0603

0402

PROX_ACSHIELD_CONN

TP_PROX_CIN2

NC NC NC NC

PROX

CRITICAL

L2804

390NH-2%-170MA-4.0OHM 2

PROX_CIN7

NC_J2800_2 NC_J2800_4 NC_J2800_6

L2803

68NH-2%-320MA-1.0OHM

CIN7

0603

68NH-2%-320MA-1.0OHM

0402

PROX_CIN9

NC NC NC

PCB: ACSHIELD NEEDS TO BE A PLANE UNDER PROX_CIN NETS AND ALSO TIE TO CONNECTOR.

PROX

GND

BIAS

I2C3_SDA_1V8

C2803

0.5PF

+/-0.05PF 25V CERM 2 201

OUT

390NH-2%-170MA-4.0OHM

WLCSP

503548-0620

PROX

CRITICAL

L2802

AD7149

VDRIVE RAIL

PROX

CRITICAL

U2800 PROX_BIAS

20 5

J2800

VCC VDRIVE

1% 1/32W MF 01005 2

20 5

=PP1V8_PROX D2

C2806

0.1UF

10% 6.3V X5R 2 402

1.8 MA MAX

PROX 1

0.5 PF JUST IN CASE NEED EXTERNAL REF CAP TO MEASURE

CHOSE CIN NUMBERS FOR LAYOUT EASE PROX

PROX

CRITICAL

L2808

L2807

390NH-2%-170MA-4.0OHM 2

ACSHIELD_SB

1 0603

68NH-2%-320MA-1.0OHM ACSH_SB

1 0402

PCB: ENSURE ACSHIELD PLANE UNDER U3200, NO GND PLANE NEAR PROX_CIN NETS..

SYNC_MASTER=J85 MLB_C

SYNC_DATE=12/05/12

PAGE TITLE

SENSOR:

PROX DRAWING NUMBER

Apple Inc.

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

28 OF 121 SHEET

22 OF 54

REAR CAMERA CONNECTOR D

APN: 516S0973

L2902 240OHM-350MA

=PP1V8_CAM_REAR

ISP0_CAM_REAR_CLK_F

0201 1

L2950

150OHM-25%-200MA-0.7DCR

PLUG: 516S0974

PP1V8_CAM_REAR_FILT

ISP0_CAM_REAR_CLK

7 52

MIPI0C_CAM_REAR_DATA_P<0>

OUT

7 53

MIPI0C_CAM_REAR_DATA_N<0>

OUT

7 53

MIPI0C_CAM_REAR_CLK_P

OUT

7 53

MIPI0C_CAM_REAR_CLK_N

OUT

7 53

MIPI0C_CAM_REAR_DATA_P<1>

OUT

7 53

MIPI0C_CAM_REAR_DATA_N<1>

OUT

7 53

01005

C2972

C2906

56PF

2 NP0-C0G

5% 16V 01005

C2907

1UF

CRITICAL

1000PF

10% 10V 402

5% 16V 01005

C2908 10% 6.3V 01005

2 X5R

J2950

2 X5R-CERM

AA07-S022VA1

L2911

F-ST-SM 24

23 1

L2903 240OHM-350MA

=PP1V3_CAM_REAR

PP1V3_CAM_REAR_FILT

52 7

ISP0_CAM_REAR_SCL ISP0_CAM_REAR_SDA ISP0_CAM_REAR_SHUTDOWN_L

C2973

56PF

C2909

56PF

2 10V X5R

01005

C2911 1000PF

10%

2 16V NP0-C0G

01005

1UF

2 16V NP0-C0G

C2910

10%

CAM_REAR_VSYNC

01005

GND_CAM_AVDD GND_AF_AVDD

2 6.3V X5R-CERM

402

0201 1

SYM_VER-2

TCM0605-1 53

MIPI0C_CAM_REAR_DATA_FILT_P<0>

90-OHM-50MA

MIPI0C_CAM_REAR_DATA_FILT_N<0> 2

L2910

MIPI0C_CAM_REAR_CLK_FILT_P MIPI0C_CAM_REAR_CLK_FILT_N 1 SYM_VER-2

TCM0605-1 90-OHM-50MA

MIPI0C_CAM_REAR_DATA_FILT_P<1> MIPI0C_CAM_REAR_DATA_FILT_N<1>

L2912 2

R2950

L2900

100K 1% 1/32W MF 2 01005

240OHM-350MA

=PP2V9_CAM_REAR

PP2V9_AVDD_CAM_REAR_FILT

2 0201

C2970

56PF

C2900

56PF

5% 16V 01005

XW2950 SM

2 NP0-C0G

C2901

1UF 10% 10V 402

2 X5R

C2902 1000PF 10% 6.3V 01005

25 1

C2980

1000PF

10% 6.3V 01005

SYM_VER-2

TCM0605-1

2 X5R-CERM

90-OHM-50MA

VOLTAGE=2.9V MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM

2 X5R-CERM

VOLTAGE=0V MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.1 MM NET_SPACING_TYPE=GND MAX_NECK_LENGTH=5 MM

L2901 240OHM-350MA

=PP2V6_CAM_REAR_AF 54

PP2V6_CAM_REAR_AF_FILT

2 0201

C2971

56PF

5% 16V 2 NP0-C0G 01005

C2903 56PF

5% 16V 2 NP0-C0G 01005

XW2951 SM 1

C2904 1UF

10% 10V 2 X5R 402

C2905 1000PF

10% 6.3V 2 X5R-CERM 01005

VOLTAGE=2.6V MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM

VOLTAGE=0V MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.1 MM NET_SPACING_TYPE=GND MAX_NECK_LENGTH=5 MM

SYNC_MASTER=N/A

SYNC_DATE=N/A

PAGE TITLE

CAMERA:

REAR CONN & FILTERS DRAWING NUMBER

Apple Inc.

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

29 OF 121 SHEET

23 OF 54

AP INTERFACE & DEBUG CONNECTORS

DEBUG CONNECTOR =PPBATT_VCC_BB

25 33 34 35 36 37 38 54

NOSTUFF

J3003 AXE654124

52 26

OUT

52 26 5

OUT

52 48 26

OUT

XW3002 53 52 11

SHORT-10L-0.25MM-SM 2 USB_BB_N 1

27 26

NOSTUFF

PROBE POINTS 27

PP3000 P4MM SM

BB_ERROR_FLAG

BI BI

USB_BB_DEBUG_N USB_BB_DEBUG_P

52 27 5

OUT

52 27

OUT

DEBUG_RST_L BB_JTAG_TMS BB_JTAG_TRST_L BB_JTAG_TCK BB_JTAG_TDO BB_JTAG_TDI BB_JTAG_RTCLK

52 28 24 14

OUT

LAT_SW1_CTLGPIO48/BOOT_CONFIG_6

PP3008

40 39 28

OUT

P4MM

52 48 28

PP3001

XW3003

P4MM SM

SLEEP_CLK_32K

26 27

53 52 11

SHORT-10L-0.25MM-SM 1 2

USB_BB_P

NOSTUFF

PP3002 P4MM SM

PMIC_SSBI

52 27

OUT

52 27 5

OUT

52 27 5

OUT

52 27 5

OUT

26 27

PP3003 P4MM SM

PS_HOLD_PMIC GPIO_SOC2BB_RADIO_ON_L PMU_GPIO_PMU2BBPMU_RST_L PMIC_RESOUT_L

19P2M_MDM

26 27

WTR_SSBI_TX_GPS

28 29

40 39 33 28 24

OUT

PP3009

ANT_SEL_2 GPIO54/BOOT_CONFIG_0 PMU_GPIO_BB2PMU_HOST_WAKE ANT_SEL_1 GPIO_51

GPIO53/BOOT_CONFIG_1 GPIO51/BOOT_CONFIG_3

P4MM SM

WTR_SSBI_PRX_DRX

28 29

PP3010 P4MM SM

WTR_RX_ON

M-ST-SM

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53

GPIO_SOC2BB_RST_L OUT

5 26 52

PP_SMPS3_MSME_1V8IN

24 25 27 28 30 52

RESET_SOC_L

11 48 52 4 8 10

OUT

UART3_BB2SOC_TX GPIO_DEBUG_LED UART3_SOC2BB_TX UART3_BB2SOC_RTS_L UART3_SOC2BB_RTS_L

IN IN

OUT

PMU_GPIO_BB_VBUS_DET

HSIC2_BB2SOC_DEVICE_RDY GPIO_BB2SOC_RESET_DET_L HSIC2_SOC2BB_HOST_RDY

CKPLUS_WAIVE=SINGLE_NODENET

5 11 28 52

5 28

OUT

5 28

OUT

27 48 52

5 28

28 29

PP3011 P4MM SM

WTR_RF_ON

28 29

PP3012 P4MM SM

UART_WLAN2BB_LTE_COEX

28 44

PP_SMPS3_MSME_1V8

GPIO/BOOT_CONFIG CONFIGURATION

24 25 27 28 30 52

PP3013 P4MM SM

UART_BB2WLAN_LTE_COEX

NOSTUFFNOSTUFF

28 44

BOOT OPTIONS

R3002 R3003

10K

5% 1/32W MF 2 01005

LAT_SW1_CTL

GPIO48/BOOT_CONFIG_6 GPIO53/BOOT_CONFIG_1

52 28 24 14 40 39 33 28 24

ANT_SEL_1

BOOT_CONFIG SW REGISTER VALUE

49 50

BOOT_DEFAULT_OPTION

0X00

BOOT_NAND_OPTION

0X01

BOOT_HSIC_OPTION

0X02

BOOT_USB_OPTION

0X03

0X08

ENABLE SAHARA PROTOCOL

J3002 MM4829-2702 F-ST-SM

B PP_LDO6_RUIM_1V8

HSIC2_BB_DATA

4 27 53

NOSTUFF

SIM CARD ESD PROTECTION

10 25 27 52

CELL CELL

C3000

CELL

J3001

2 52 28 10

SIMCRD_IO_CONN

TSSLP-2-1

52 28 10

SIMCRD_RST_CONN

TSSLP-2-1

F-ST-SM

NOSTUFF

SIM_TRAY_DETECT

10 28 52

SIMCRD_CLK_CONN

10 28 52

TSSLP-2-1

CELL

U3001 ESD0P2RF-02LS

MM4829-2702

U3002 ESD0P2RF-02LS

HSIC2_BB_STB

4 27 53

U3000 ESD0P2RF-02LS

12V-33PF 01005-1

CELL

U3003 ESD0P2RF-02LS 2

TSSLP-2-1

A PAGE TITLE

CELL:AP INTERFACE & DEBUG CONNECTORS DRAWING NUMBER

Apple Inc.

051-0886

NOTICE OF PROPRIETARY PROPERTY:

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SIZE

REVISION

A.0.0 BRANCH

PAGE

30 OF 121 SHEET

24 OF 54

PMU (1 OF 2) PP_LVS1

OUT

PP_VREG INTERNAL USE ONLY 1

C3230 1.0UF

20% 6.3V 2 X5R 0201-1

L3200

2.2UH-20%-1.2A-0.15OHM 1

PP_SMPS1_MSMC_1V05

OUT

27 52

OUT

27 30

OUT

24 25 27 28 30 52

OUT

25 30 52

OUT

25 52

0806

CRITICAL

C3229 22UF

20% 6.3V 2 X5R-CERM-1 603

S1_GND 25

L3201

2.2UH-20%-1.2A-0.15OHM 1

PP_SMPS2_RF1_1V3

2 0806

CRITICAL

C3228 22UF

20% 6.3V 2 X5R-CERM-1 603

S2_GND

L3202

REF_BYP 1

C3209

XW3200 SHORT-10L-0.1MM-SM 1 2

20% 6.3V 2 X5R-CERM 01005

28 REF_BYP 34 REF_GND

54 38 37 36 35 34 33 24

0806

CRITICAL 1

VOUT_LVS1 53

VSW_S1 1

C3200 10UF

20% 2 6.3V CERM-X5R 0402-2

C3201 10UF

20% 2 6.3V CERM-X5R 0402-2

C3202 10UF

20% 2 6.3V CERM-X5R 0402-2

C3203

VREG_S1

56PF

95 VDD_S2

5% 2 16V NP0-C0G 01005

VSW_S2 VREG_S2 6 18 24

VDD_S3

VSW_S3 VSW_S5_2 VREG_S3

98 VDD_S4 VSW_S4 VREG_S4 89 101 1

C3204 4.7UF

20% 10V 2 X5R-CERM 0402 25 26

S1_GND

25 26

S2_GND

C3205 4.7UF

20% 10V 2 X5R-CERM 0402 25 26

S3_GND

C3206 4.7UF

20% 10V 2 X5R-CERM 0402 25 26

S4_GND

C3207 4.7UF

20% 10V 2 X5R-CERM 0402 25 26

S5_GND

VDD_S5

VREG_S5

C3208

52 30 28 27 25 24

52 25

PP_SMPS4_RF2_2V05 PP_SMPS3_MSME_1V8 PP_SMPS5_DSP_1V05

0.1UF

S3_GND

L3203

PP_VSW_S1

92 97 79 90 102 83 42 48 100 12 81 87 105 82 88 76

C3227

20% 4V 2 X5R 01005

20% 2 6.3V X5R-CERM-1 603

NOSTUFF

25 26

2.2UH-20%-1.2A-0.15OHM 1

PP_SMPS4_RF2_2V05

2 0806

PP_VSW_S2

CRITICAL 1

C3225 22UF

20% 6.3V 2 X5R-CERM-1 603

PP_VSW_S3

S4_GND

L3204

25 26

2.2UH-20%-2.34A-0.113OHM PP_VSW_S4

PP_SMPS5_DSP_1V05

2 2520-SM

CRITICAL 1

PP_VSW_S5

C3224 22UF

20% 6.3V 2 X5R-CERM-1 603

S5_GND

25 26

INTERNAL USE ONLY

8 VDD_XO 44 VDD_L2_L3

5 VDD_L5_L6_L13_L14

52 30 25

C3226

4.7UF 20% 10V 2 X5R-CERM 0402

78 VDD_L4

VSW_S5

22UF

VREG_RFCLK 13 104 VDD_S1

=PPBATT_VCC_BB

PP_SMPS3_MSME_1V8

CRITICAL

REF_GND

BGA VREG (SYM 5 OF 5)

0.1UF

25 26

2.2UH-20%-1.2A-0.15OHM

U3300

PM8018-0

75 58 70 59

VDD_L7 VDD_L8 VDD_L9 VDD_L10_L11

64 VDD_L12

VREG_XO VREG_L2 VREG_L3 VREG_L4 VREG_L5 VREG_L6 VREG_L13 VREG_L14 VREG_L7 VREG_L8 VREG_L9 VREG_L10 VREG_L11 VREG_L12

PP_LDO1 PP_LDO2_XO_HS_1V8 PP_LDO3_AMUX_1V8 PP_LDO4_VDDA_3V3 PP_LDO5_GPS_LNA_2V5 PP_LDO6_RUIM_1V8 PP_LDO13_VDDPX_2V95 PP_LDO14_2V65 PP_LDO7_DAC_1V8 PP_LDO8_VDDPX_1V2 PP_LDO9_PLL_1V05 PP_LDO10_ADSP_1V05 PP_LDO11_MDSP_FW_1V05 PP_LDO12_MDSP_SW_1V05

20 31 32 84 11 17 23 29 63 54 77 65 55 43 1

C3211

1.0UF

C3210 1.0UF

C3212

20% 6.3V 2 X5R 0201-1

C3215

1.0UF

20% 2 6.3V X5R 0201-1

1.0UF

20% 2 6.3V X5R 0201-1

1.0UF

20% 2 6.3V X5R 0201-1

C3213

C3214 1.0UF

20% 6.3V 2 X5R 0201-1

1.0UF

20% 2 6.3V X5R 0201-1

C3216

20% 2 6.3V X5R 0201-1

C3217 1.0UF

20% 6.3V 2 X5R 0201-1

C3218

C3220

C3222

10UF

20% 2 6.3V CERM-X5R 0402-2

C3219 1.0UF

20% 6.3V 2 X5R 0201-1

C3221 10UF

20% 6.3V 2 CERM-X5R 0402-2

OUT

26 27

OUT

10 24 27 52

OUT

14 32 33 39 40

OUT

C3231 1.0UF

20% 2 6.3V X5R 0201-1

C3223 10UF

20% 6.3V 2 CERM-X5R 0402-2

A PAGE TITLE

CELL: BASEBAND PMU (1 0F 2) DRAWING NUMBER

Apple Inc.

051-0886

NOTICE OF PROPRIETARY PROPERTY:

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SIZE

REVISION

A.0.0 BRANCH

PAGE

32 OF 121 SHEET

25 OF 54

PMU (2 OF 2)

PA_ID

27 26 25

PP_LDO3_AMUX_1V8

R3306

BOARD_ID 0.7V 0.9V 1.1V 1.3V 1.5V 1.7V

R3304

REVISION PROTO1 PROTO2 EVT1 EVT2 DVT PVT

100K

1% 1/32W MF 2 01005

1% 1/32W MF 2 01005 BOARD_ID

PA_ID

1.5V

PROTO2

MAV VER

0.1V

8.7

0.3V

8.6

0.5V

8.5

1.1V

7.7

1.3V

7.6

1.5V

7.5

R3307

R3305

499K

100K

1% 1/32W MF 2 01005

OUT

U3300 PM8018-0 85 67 66 72 73 80

VDDPX_BIAS

NC NC

BB GPIO_29 PRODUCT_ID 1 (1.8V) JXX 0 (NC, PD) NXX

VREF_DAC_BIAS

MPP_01 MPP_02 MPP_03 MPP_04 MPP_05 MPP_06

BGA MPP MISC (SYM 4 OF 5) CRITICAL

GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06

33 38 50 60 71 49

NC NC NC NC NC NC

R3300 52 24 5

GPIO_SOC2BB_RST_L

1.00K2

AP SECTION NEEDS ITS OWN THERMISTOR PLACED NEAR THE PAâ&#x20AC;&#x2122;S.

5% 1/32W MF 01005

U3300

PM8018-0 BGA CONTROL (SYM 1 OF 5)

R3301

PS_HOLD

20.0K2

52 24

PS_HOLD_PMIC

52 24 5

5% 1/32W MF 01005 GPIO_SOC2BB_RADIO_ON_L IN

52 48 24

47 PS_HOLD

LED_DRV_N 86 NC

69 KPD_PWR* PMU_GPIO_PMU2BBPMU_RST_L16 PM_RESIN_N

PON_RESET* 4

OUT

24 27

OUT

PON_TRIG 41 BAT_ID 35

68 SSBI

PMIC_SSBI

PMIC_RESOUT_L

PM_USR_INT_N 21 PM_USR_IRQ_L PM_MDM_INT_N 14 PM_MDM_IRQ_L

OPT_1 NC 74 OPT_2 NC

27 24

GND NEEDS TO BE CLEARED UNDER THIS CRYSTAL TO MINIMIZE THERMAL DRIFT

Y3300

19.200MHZ 2.0X1.6-SM 1 3 4

19P2M_XTAL_IN

U3300

PM8018-0

CRITICAL

BGA CLOCKS (SYM 2 OF 5) 1 XTAL_19M_IN 2 XTAL_19M_OUT

19P2M_XTAL_OUT

27 26 25

PP_LDO3_AMUX_1V8

XO_OUT_A0 19 XO_OUT_D0 25

19P2M_WTR 19P2M_MDM

OUT

24 27

XW3300 SM

U3300

PM8018-0

R3303

3 XTAL_32K_IN NC 15 XTAL_32K_OUT

100K

BGA INPUT PWR (SYM 3 OF 5)

1% 1/32W MF 2 01005

XW3301 SHORT-10L-0.25MM-SM 1 2

91 GND_S1 103 GND_S2 96 30 GND_S3 36 93 GND_S4 99 GND_S5 94

57 VCOIN NC GND

S2_GND

XW3302

XO_THERM_Y1

S3_GND

S4_GND

XW3303

C3300

27 GND0 10 XO_THERM 22 XOADC_GND

19P2M_CLK_EN

S5_GND

SLEEP_CLK 26

SLEEP_CLK_32K

OUT

24 27

RSVD 7

1000PF

39 51 61 56 46 52 40

XO_OUT_D0_EN 9

45 GND1

S1_GND

XO_OUT_A1 37 NC

10% 6.3V 2 X5R-CERM 01005

SHORT-10L-0.25MM-SM 1 2

XW3304 SM 1

XO_GND 2 2

XW3305 SHORT-10L-0.1MM-SM 1

A PAGE TITLE

CELL: BASEBAND PMU (2 OF 2) DRAWING NUMBER

Apple Inc.

051-0886

NOTICE OF PROPRIETARY PROPERTY:

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SIZE

REVISION

A.0.0 BRANCH

PAGE

33 OF 121 SHEET

26 OF 54

BASEBAND (1 OF 2) CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST. 52 27 25

PP_SMPS1_MSMC_1V05

27 25

C3400 1.0UF

20% 6.3V 2 X5R 0201-1

C3401 1.0UF

C3402

1.0UF

20% 6.3V 2 X5R 0201-1

C3403 1.0UF

20% 6.3V 2 X5R 0201-1

PP_LDO8_VDDPX_1V2

C3404

1.0UF

20% 6.3V 2 X5R 0201-1

C3431

1.0UF

27 25

C3432

0.22UF

20% 6.3V 2 X5R 0201-1

C3433

C3434

1.0UF

20% 6.3V 2 X5R 01005

A21 AA1 AA21 B2 B7 B11 B14 B15 C19 F6 F7 F10 F15 F16 F19 G2 G6 G10 G11 G15 G16 G17 G20 H6 H10 H11 H15 H16 J6 J7 J10 J11 J14 J15 K6 K7 K10 K11 K14 K15 K20 L2 L6 L7 L10 L11 L14 L15 M6 M7 M10 M11

0.22UF

20% 6.3V 2 X5R 0201-1

20% 6.3V 2 X5R 0201

D PP_LDO9_PLL_1V05

27 25

PP_LDO10_ADSP_1V05 1

C3405

C3406

1.0UF 20% 6.3V 2 X5R 0201-1

52 30 28 27 25 24

PP_SMPS3_MSME_1V8 1

C3409 1.0UF

20% 2 6.3V X5R 0201-1

1.0UF 20% 6.3V 2 X5R 0201-1

27 25 24 52 30 28

C3410

C3407

27 25

C3412

C3418

1.0UF

C3415

1.0UF

C3419 1.0UF

20% 6.3V 2 X5R 0201-1

C3416

20% 6.3V 2 X5R 0201-1

C3420 1.0UF

20% 6.3V 2 X5R 0201-1

C3417

1.0UF

20% 2 6.3V X5R 0201-1

C3414

PP_LDO12_MDSP_SW_1V05 1

1.0UF

20% 2 6.3V X5R 0201-1

PP_LDO11_MDSP_FW_1V05

20% 6.3V 2 X5R 0201-1

PP_SMPS3_MSME_1V8

C3411

C3413 1.0UF

20% 6.3V 2 X5R 0201-1

1.0UF

20% 2 6.3V X5R 0201-1

C3408 1.0UF

20% 6.3V 2 X5R 0201-1

1.0UF

27 25

1.0UF

20% 2 6.3V X5R 0201-1

U3400

MDM9615M 52 27 25

52 27 25

PP_SMPS1_MSMC_1V05 PP_SMPS1_MSMC_1V05

IN 1

C3421 1.0UF

20% 6.3V 2 X5R 0201-1

F8 F9 F12 F13 F14 G9 G12 H9 H12 J8 J9 J12 J13 K8 K9 K12 K13 L8 L9 L12 L13 M8 M9 M12 M13 N8 N9 N12 N13 P9 P12 R9 R12 T8 T9

BGA (5 OF 6) PWR VDD_DDR

VDD_ADSP

AA20 B19 F20 M20 C5 C6 E6 E7 F5

VDD_MDSP_FW

T15 T16 T17 U14 U15 U16 U17 U19 T19

VDD_MDSP_SW

N15 N16 N17 N19 P15 P16 P17 P19

VDD_CORE

PP_SMPS3_MSME_1V8

PP_LDO10_ADSP_1V05

PP_LDO9_PLL_1V05

C17 C18 E17 F17 G7 G8 G13 G14 H7 H8 H13 H14 P7 P8 P13 P14 R7 R8 R13 R14

PP_LDO11_MDSP_FW_1V05

PP_LDO12_MDSP_SW_1V05

24 25 27 28 30 52

25 27

PP_LVS1

BGA (6 OF 6) GND CRITICAL

GND

GND_ANA

PP_SMPS3_MSME_1V8

A14 A19 F21 M1 M21

U3400

MDM9615M BGA (2 OF 6) EBI1_EBI2

F11 J16 K16 L16 T6 T7 T11 U9 U12 W7 W14 Y7 Y11 Y15 Y18 U13 W13

D21 NC E19 NC D20 NC D19

EBI2_NAND_CS* EBI2_OE* EBI2_WE* EBI2_BUSY*

C20 EBI2_CLE* NC E20 EBI2_ALE* NC

EBI2_AD_0 EBI2_AD_1 EBI2_AD_2 EBI2_AD_3 EBI2_AD_4 EBI2_AD_5 EBI2_AD_6 EBI2_AD_7

J20 NC J19 NC G19 NC H20 NC J21 NC H19 NC H21 NC E21

240

1% 1/32W MF 01005

470K 5% 1/32W MF 2 01005

U3400

MDM9615M VDD_QFUSE_PRG B13 VDD_USB_1P8 E12 VDD_USB_3P3 E10

PP_LDO2_XO_HS_1V8 PP_LDO4_VDDA_3V3

VDDPX_BIAS IN

K17 PP_LDO9_PLL_1V05

1 IN

PP_LDO3_AMUX_1V8

C3422

20% 6.3V 2 X5R 0201-1

20% 2 4V X5R 01005

25 26

26 24

52 24

26 24

52 24 5

1.0UF

C3423 0.1UF

25 27

VDD_PLL1

L17 VDD_PLL2 W12

25 27

52 24 5

PMIC_RESOUT_L DEBUG_RST_L SLEEP_CLK_32K BB_JTAG_TCK BB_JTAG_TDI BB_JTAG_TMS BB_JTAG_TRST_L

Y20 RESIN* Y4 SRST* AA19 SLEEP_CLK Y3 AA2 W4 AA4

BGA (1 OF 6) DIGITAL

TCK TDI TMS TRST*

NOSTUFF

VDD_A2 VDD_A2 GND GND

U6 PP_LDO7_DAC_1V8 U7 AA11 AA18

PP_SMPS2_RF1_1V3

1.0UF 20% 6.3V 2 X5R 0201-1

VDD_A1 W9 VDD_A1 AA7 GND AA15

VDD_MEM

C3424

1.0UF

26 24 26

VDD_P3

PP_SMPS3_MSME_1V8

24 25 27 28 30 52

IN OUT

26 24

A15 G1 G21 L1 U1 W19

VDD_P4 VDD_P5 VDD_P6 VDD_P7

VDD_P1

A2 A3 A7 A11

19P2M_MDM 19P2M_CLK_EN PMIC_SSBI

TDO AA3 BB_JTAG_TDO RTCK Y2 BB_JTAG_RTCLK HSIC_CAL A8 HSIC_DATA C7 HSIC_STB B8

1.0UF

52 24 48

USB_HS_DP USB_HS_DM USB_HS_REXT USB_HS_ID USB_HS_SYSCLK USB_HS_VBUS

DNC

1 IN

10 24 25 52

24 25 27 28 30 52

25 27

24 25 27 28 30 52

50_HSIC_CAL HSIC2_BB_DATA HSIC2_BB_STB

OUT

5 24 52

OUT

24 52

R3402 1

4 24 53

240

1% 1/32W MF 01005

V20 CXO U21 CXO_EN Y21 SSBI_PMIC

C11 E11 A12 C12 NC B12 PMU_GPIO_BB_VBUS_DET C10

USB_BB_DEBUG_P USB_BB_DEBUG_N RREFEXT

C3426

20% 6.3V 2 X5R 0201-1

PP_LDO6_RUIM_1V8 PP_SMPS3_MSME_1V8 PP_LDO8_VDDPX_1V2 PP_SMPS3_MSME_1V8

25 30

C3425

20% 6.3V 2 X5R 0201-1

TP_BB_TEST_MODE_0 TP_BB_TEST_MODE_1

W20 MODE_0 Y19 MODE_1

RESOUT* U20

R3401

E8 C8 B9 A9

E9 C9 B10 A10

200

NC NC NC NC

PAGE TITLE

CELL: BASEBAND (1 OF 2) DRAWING NUMBER

1% 1/32W MF 2 01005

SDC1_CMD K19 SDC1_CLK L21 SDC1_DATA0 SDC1_DATA1 SDC1_DATA2 SDC1_DATA3

PP_LDO13_VDDPX_2V95 K21 VDD_P2

L19 L20 N20 N21

NC NC

Apple Inc.

051-0886

NOTICE OF PROPRIETARY PROPERTY:

NC NC NC NC

SIZE

REVISION

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

R3403 EBI1_CAL C21 EBI1_CAL

R3400

DNC 52 30 28 27 25 24

M14 M15 M16 M17 M19 N6 N7 N10 N11 N14 P6 P10 P11 R6 R10 R11 R15 R16 R17 R19 T10 T12 T13 T14 U2 V19

VDD_HVPAD_BIAS E16 27 25

U3400

MDM9615M

PP_LDO4_VDDA_3V3

A.0.0 BRANCH

PAGE

34 OF 121 SHEET

27 OF 54

BASEBAND (2 OF 2) D

U3400

MDM9615M BGA (4 OF 6) ANALOG

CRITICAL 29

U8 W8 Y8 AA8

PRX_BB_I_P PRX_BB_I_N PRX_BB_Q_P PRX_BB_Q_N DRX_BB_I_P DRX_BB_I_N DRX_BB_Q_P DRX_BB_Q_N

NC NC NC NC

BBRX_IP_CH0 BBRX_IM_CH0 BBRX_QP_CH0 BBRX_QM_CH0

Y10 AA10 Y9 AA9

BBRX_IP_CH1 BBRX_IM_CH1 BBRX_QP_CH1 BBRX_QM_CH1

W17 W18 W15 W16

BBRX_IP_CH2 BBRX_IM_CH2 BBRX_QP_CH2 BBRX_QM_CH2

W10 U10 W11 U11

GPS_BB_I_P GPS_BB_I_N GPS_BB_Q_P GPS_BB_Q_N

OUT

C3500

0.1UF

TX_DAC0_IP TX_DAC0_IM TX_DAC0_QP TX_DAC0_QM TX_DAC0_IREF

52 30 28 27 25 24

10K

Y6 AA6 Y5 AA5 W6

TX_BB_I_P BI TX_BB_I_N OUT TX_BB_Q_P OUT TX_BB_Q_N OUT WTR_BB_TX_DAC_IREF OUT

52 24 10

OUT

52 24 10

OUT

NC NC

28 28 28

V21 NC W21 NC Y12 NC Y16 NC Y17 NC AA12 NC AA16 NCNC AA17

28 24 5 24 5 52 24 11 5

OSCAR2RADIO_CONTEXT_A1

52 5

OUT

OSCAR_CONTEXT_A_MDM GPIO_SOC2BB_WAKE_MODEM GPIO_DEBUG_LED

NC NC NC NC NC NC NC NC NC 52 30 28 27 25 24

PP_SMPS3_MSME_1V8

RESERVED FOR FUTURE PRODUCT ID USE NC 37

OUT

GSM_PA_LB_EN GSM_PA_HB_EN PA_ON_B7_B20

PP_SMPS3_MSME_1V8_FILT

01005-1 1

SPI_CLK SPI_CS_L SPI_DATA_MISO SPI_DATA_MOSI UART3_BB2SOC_RTS_L UART3_SOC2BB_RTS_L UART3_SOC2BB_TX UART3_BB2SOC_TX

0.00 2 0% 1/32W MF 01005

L3520

IN OUT IN

R3531 52 44 19

OUT

52 24 11 5

70-OHM-300MA PP_SMPS3_MSME_1V8 1

SIM_TRAY_DETECT SIMCRD_RST_CONN SIMCRD_CLK_CONN SIMCRD_IO_CONN

NC NC NC NC

B IN

MDM9615M

52 24 10

DNC

U3400

5% 1/32W MF 2 01005

TX_DAC1_IP Y14 NC TX_DAC1_IM AA14 NC

GNSS_BB_IP GNSS_BB_IM GNSS_BB_QP GNSS_BB_QM

CRITICAL

R3502

GPIO_29 PRODUCT_ID 1 (1.8V) JXX 0 (NC, PD) NXX 52 30 28 27 25 24

WLAN_TX_BLANK NEEDS TO CONNECT TO AP

PP_SMPS3_MSME_1V8

20% 2 4V X5R 01005

TX_DAC1_QP Y13 NC TX_DAC1_QM AA13 NC

H17 J17 29

VREF_DAC_BIAS

DAC0_VREF W5

C3520 0.1UF

20% 4V 2 X5R 01005

OUT

33 32

OUT

PA_MB_CTL1 PA_ON_B2_B3 PA_ON_B5_B8 PA_MB_CTL0

NC 36 35 34 33

OUT OUT

29 24

OUT

29 24

PA_BS WTR_RX_ON WTR_RF_ON

B6 A6 A5 B5 C4 B3 B4 A4 A16 A13 E14 E13 C14 C13 E15 A18 C15 B16 B18 C16 A17 B21 B20 A20 B17 P21 R21 P20 R20 T20 T21 U5 V2 V1 U3 T3 T1 T5 R5 R3 T2 R2 P5 P1

BGA (3 OF 6) GPIO GPIO_0 GRFC_14 GPIO_44 GPIO_1 GRFC_15 GPIO_45 GPIO_2 GRFC_18 GPIO_46 GPIO_3 GRFC_19 GPIO_47 GPIO_4 GRFC_20 GPIO_48 GPIO_5 GRFC_21 GPIO_49 GPIO_6 GRFC_22 GPIO_50 GPIO_7 GRFC_23 GPIO_51 GPIO_8 GRFC_24 GPIO_52 GRFC_25 GPIO_53 GPIO_9 GRFC_26 GPIO_54 GPIO_10 GPIO_11 GRFC_27 GPIO_55 GPIO_12 GRFC_28 GPIO_56 GPIO_13 GRFC_29 GPIO_57 GPIO_14 GRFC_30 GPIO_58 GRFC_31 GPIO_59 GPIO_15 GPIO_16 GRFC_32 GPIO_60 GPIO_17 GRFC_33 GPIO_61 GPIO_18 GRFC_34 GPIO_62 GPIO_19 GRFC_35 GPIO_63 GRFC_36 GPIO_64 GPIO_20 GPIO_21 GRFC_37 GPIO_65 GPIO_22 GRFC_38 GPIO_66 GPIO_23 GRFC_39 GPIO_67 GPIO_24 GPIO_68 GPIO_25 GPIO_69 GPIO_26 GPIO_70 GPIO_27 GPIO_71 GPIO_28 GPIO_72 GPIO_29 GPIO_73 GPIO_30 GPIO_74 GPIO_31 GRFC_0 GPIO_75 GPIO_32 GRFC_1 GPIO_76 GPIO_33 GRFC_2 GPIO_77 GPIO_34 GRFC_3 GPIO_78 GPIO_35 GRFC_4 GPIO_79 GPIO_36 GRFC_5 GPIO_80 GPIO_37 GRFC_6 GPIO_81 GPIO_38 GRFC_7 GPIO_82 GPIO_39 GRFC_8 GPIO_83 GPIO_40 GRFC_9 GPIO_84 GPIO_41 GRFC_10 GPIO_85 GPIO_42 GRFC_11 GPIO_86 GPIO_43 GRFC_13 GPIO_87

P3 R1 N5 N3 P2 M2 N1 N2 M3 L3 M5 L5 K1 K5 K3 K2 J2 J5 J1 J3 H3 H5 G5 H1 H2 F3 F1 G3 V3 W3 W2 W1 Y1 F2 E2 E3 D1 E1 D2 D3 C1 B1 C2 C3

PA_R1 B40_FILT_SELECT

OUT

33 34 35 36 37

OUT

14 24 52

NC LAT_SW3_CTL NC

BOOT_CONFIG_6 LAT_SW1_CTL GPIO_BB2SOC_GSM_TXBURST

NC GPIO_51 ANT_SEL_0 ANT_SEL_1 ANT_SEL_2 ANT_SEL_3 ANT_SEL_4 3P4T_SEL_0 3P4T_SEL_1 LAT_SW2_CTL DCDC_EN DCDC_MODE

NC NC

BOOT_CONFIG_5

BOOT_CONFIG_4 BOOT_CONFIG_3 BOOT_CONFIG_2 BOOT_CONFIG_1 BOOT_CONFIG_0

BB_PDM UART_WLAN2BB_LTE_COEX UART_BB2WLAN_LTE_COEX

33 39 40

OUT

24 33 39 40

OUT

24 39 40

HSIC2_BB2SOC_REMOTE_WAKE BB_IPC_GPIO WTR_SSBI_PRX_DRX WTR_SSBI_TX_GPS BB_ERROR_FLAG WTR_GP_DATA0 GPH WTR_GP_DATA1 GPH WLAN_TX_BLANK OSCAR_CONTEXT_B_MDM

39 40

OUT

14 52

OUT

24 44

OUT

24 44

OUT

24 29

OUT

B R3530 44 52

HSIC2_BB2SOC_DEVICE_RDY HSIC2_SOC2BB_HOST_RDY PM_MDM_IRQ_L GPIO_BB2SOC_RESET_DET_L PS_HOLD

OUT

0.00

OUT

5 24

1/32W MF 01005

OUT

5 24

OUT

24 48 52

OUT

OSCAR2RADIO_CONTEXT_B 19 IN

44 52

NC GPIO_BB2SOC_GPS_SYNC PMU_GPIO_BB2PMU_HOST_WAKE PM_USR_IRQ_L

VCC

U3520

SERIAL-SPI-2MX8-1.8V WLCSP MX25U1635EBAI-10G D3 28

SPI_DATA_MOSI

SPI_CLK

D2 C2

SI/SIO0 SCLK

CRITICAL

CS*

SPI_CS_L

SO/SIO1

SPI_DATA_MISO

NC NC/SIO3

GND

F1 F4

NC NC NC

WP*/SIO2

PAGE TITLE

CELL: BASEBAND (2 OF 2) DRAWING NUMBER

Apple Inc.

051-0886

NOTICE OF PROPRIETARY PROPERTY:

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SIZE

REVISION

A.0.0 BRANCH

PAGE

35 OF 121 SHEET

28 OF 54

RF TRANSCEIVER (1 OF 2) PRX TRANSCEIVER RF AND IQ PORTS TRANSCEIVER PHASE CONTROL, TX RF & IQ PORTS

U3600

WTR1605

31 31

IN IN IN IN IN IN IN

31 31

IN IN IN

100_XCVR_B20_PRX_P 100_XCVR_B20_PRX_N

100_XCVR_B8_PRX_N 100_XCVR_B8_PRX_P

100_XCVR_B5_B18_PRX_P 100_XCVR_B5_B18_PRX_N

100_XCVR_B2_PRX_P 100_XCVR_B2_PRX_N

100_XCVR_B3_PRX_P 100_XCVR_B3_PRX_N

100_XCVR_B1_B34_B39_DCS_PRX_N 100_XCVR_B1_B34_B39_DCS_PRX_P 100_XCVR_B7_B38_B40_PRX_P 100_XCVR_B7_B38_B40_PRX_N

8 16 7 15

SM SYM 3 OF 5 PRX

WTR1605 SM PRX_BB_I_P

PRX_BB_IP 84 PRX_BB_IM 92

PRX_BB_I_N

PRX_LB2_INP PRX_LB2_INM

PRX_BB_QP 91 PRX_BB_QM 82

PRX_BB_Q_P PRX_BB_Q_N

PRX_LB3_INP PRX_LB3_INM

PRX_LB1_INP PRX_LB1_INM

CRITICAL

DNC

OUT OUT

OUT

NC 28

PRX_MB1_INP PRX_MB1_INM

28 28

PRX_MB3_INP PRX_MB3_INM 1

PRX_HB_INP PRX_HB_INM

4.75K

5 14

100_XCVR_B8_B20_DRX_P 100_XCVR_B8_B20_DRX_N

4 13

100_XCVR_B1_B2_B3_B34_B39_DRX_P 100_XCVR_B1_B2_B3_B34_B39_DRX_N

100_XCVR_B7_B38_B40_DRX_P 100_XCVR_B7_B38_B40_DRX_N

100_XCVR_GPS_RX_P 100_XCVR_GPS_RX_N

10 18

TX_BB_QP TX_BB_QM

WTR_BB_TX_DAC_IREF

109

DAC_REF

WTR_GP_DATA0 WTR_GP_DATA1

105 121 88 114 96

U3600

C3600

WTR1605

100PF

SM SYM 1 OF 5 DRX_GPS DRX_LB1_INP DRX_LB1_INM

GPH GPH

NC WTR_RBIAS

1% 1/32W MF 01005

DRX TRANSCEIVER RF AND IQ PORTS

100_XCVR_B5_B18_DRX_P 100_XCVR_B5_B18_DRX_N

131 139

CRITICAL

DRX_LB2_INP DRX_LB2_INM

DRX_BB_IP 63 DRX_BB_IM 72

DRX_BB_I_P DRX_BB_I_N

OUT

DRX_BB_QP 50 DRX_BB_QM 57

DRX_BB_Q_P DRX_BB_Q_N

OUT

GNSS_BB_IP 56 GNSS_BB_IM 62

GPS_BB_I_P GPS_BB_I_N

OUT

GNSS_BB_QP 70 GNSS_BB_QM 71

GPS_BB_Q_P GPS_BB_Q_N

OUT

19P2M_WTR

5% 16V NP0-C0G 01005

IN IN

28 24

WTR_RX_ON WTR_RF_ON WTR_SSBI_TX_GPS WTR_SSBI_PRX_DRX

R3604 19P2M_WTR_FILT_IN

TX_BB_IP TX_BB_IM

TX_BB_Q_P TX_BB_Q_N

R3600

28 24

130 138

NC NC NC

28 24

TX_BB_I_P TX_BB_I_N

PRX_MB2_INP PRX_MB2_INM

SYM 2 OF 5 TX

0.00

CRITICAL

GP_DATA0 GP_DATA1 GP_DATA2 DNC DNC

DNC

RBIAS

VTUNE_PRX

TX_LB1 TX_LB2 TX_LB3 TX_LB4

140 132 141 133

50_XCVR_B20_TX 50_XCVR_2G_LB_TX 50_XCVR_B8_TX 50_XCVR_B5_B18_TX

TX_MB1 TX_MB2 TX_MB3 TX_MB4

126 119 112 95

50_XCVR_B2_TX 50_XCVR_B1_B3_TX 50_XCVR_B34_B39_TX 50_XCVR_2G_HB_TX

TX_HB 103 DNC 93 PDET_IN 101

50_XCVR_B7_B38_B40_TX

NC 50_PDET_IN

OUT

C3602

R3602

56PF 1

50_PDET_PAD_OUT

RX_ON RF_ON SSBI_TX_GNSS SSBI_PRX_DRX

134

GND

120

XO_IN

1% 1/32W MF 01005

5% 16V NP0-C0G 01005 1

R3601

45 100 89 80

61.9 2 50_PDET_PAD_IN IN

R3603

105

1% 1/32W MF 2 01005

9.0 DB ATTENUATOR

19P2M_WTR_IN

0% 1/32W MF 01005

C3601 10PF

5% 16V 2 CERM 01005

NOSTUFF

DRX_MB_INP DRX_MB_INM DRX_HB_INP DRX_HB_INM GNSS_INP GNSS_INM

GND 1

TRANSCEIVER GROUND CONNECTIONS U3600

WTR1605 SM SYM 5 OF 5 GND 46 77 47 68 29 22 27 21 20 33 6 75 38 41 58 74 59 52 39 73 34

64 81

GND GND GND GND GND GND GND GND GND GND GND GND GND

GND 125 GND 124

CRITICAL

GND GND GND GND GND GND GND GND GND GND

GND

142

GND

GND GND GND GND GND GND GND

123

GND GND GND GND GND GND GND GND

137

110 102 99 129 94 115

122 107 106 135 128 104 113

GND 19 GND 32 GND 49

A PAGE TITLE

CELL: RF TRANSCEIVER (1 0F 2) DRAWING NUMBER

GND 9

Apple Inc.

051-0886

NOTICE OF PROPRIETARY PROPERTY:

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SIZE

REVISION

A.0.0 BRANCH

PAGE

36 OF 121 SHEET

29 OF 54

RF TRANSCEIVER (2 OF 2) RF1_1V3

R3700

22-OHM-25%-1800MA 25 27

1 PP_SMPS2_RF1_1V3

RF1_1V3

STAR ROUTING

STAR ROUTING ALIAS

PP_RF1_1V3_PRX_PLL

0201 1

C3701

20% 10V X5R-CERM 0402-1

R3702

STAR ROUTING

PP_SMPS2_RF1_1V3_FILT

ALIAS

C3702

0.1UF

10UF

RF2_2V05

STAR ROUTING

PP_SMPS2_RF1_1V3_FILT

PLACE NEAR U3.66

52 25

PP_SMPS4_RF2_2V05

20% 6.3V X5R-CERM 01005

ALIAS

PP_RF1_1V3_GPS_DIG

STAR ROUTING

PP_SMPS4_RF2_2V05_FILT

5% 1/20W MF 201

C3713 0.1UF

20% 6.3V X5R-CERM 01005

PP_RF1_1V3_GPS_LNA

C3715

PLACE NEAR U3.24 AND U3.31

PP_RF2_2V05_TX_DA

ALIAS

10UF 2

PP_RF2_2V05_DRX_BB

ALIAS

20% 10V X5R-CERM 0402-1

ALIAS

PP_RF1_1V3_GPS_VCO

C3716

100PF 5% 16V 2 NP0-C0G 01005 PLACE NEAR U3.111

STAR ROUTING

PP_RF1_1V3_SHDR_PLL

NOSTUFF 1 1

C3703

0.1UF

0.1UF 2

C3714

20% 6.3V X5R-CERM 01005

ALIAS

PP_RF1_1V3_GPS_PLL

STAR ROUTING

PLACE NEAR U3.37 AND U3.55 ALIAS

PP_RF1_1V3_PRX_VCO 1

0.1UF 2

20% 6.3V X5R-CERM 01005

52 28 27 25 24

PP_RF2_2V05_TX_BB

PP_RF2_2V05_PRX_VCO 30

ALIAS 1

PP_SMPS3_MSME_1V8

PP_RF1_1V8_DIG

ALIAS

PLACE NEAR U3.76

PP_RF1_1V3_SHDR_VCO

0.1UF

PLACE NEAR U3.67

20% 10V X5R-CERM 0201-1

PP_RF2_2V05_SHDR_VCO 30

ALIAS

C3705 1

0.1UF 2

20% 6.3V X5R-CERM 01005

PLACE NEAR U3.87 1

C3717

C3700 1.0UF

ALIAS

STAR ROUTING

RF1_1V8

C3704

ALIAS

PLACE NEAR U3.65

ALIAS

PP_RF2_2V05_PRX_BB

20% 6.3V X5R-CERM 01005

C3718 0.1UF 20% 6.3V X5R-CERM 01005

PLACE NEAR U3.40

PLACE NEAR U3.51

ALIAS

PP_RF1_1V3_TX_DA 1

C3706

0.1UF 2

PP_RF2_2V05_TX_VCO 30

ALIAS

C3721 56PF

20% 6.3V X5R-CERM 01005

PLACE NEAR U3.118

5% 2 16V NP0-C0G 01005

C3719 0.1UF 20% 6.3V X5R-CERM 01005

NOSTUFF STAR ROUTING

PLACE NEAR U3.136 ALIAS

PP_RF1_1V3_TX_SYNTH

ALIAS 1

PP_RF2_2V05_TX_PLL

C3707 0.1UF

20% 6.3V X5R-CERM 01005

ALIAS

PP_RF2_2V05_XO_FILT

PLACE NEAR U3.98

C3720 0.1UF

ALIAS

PP_RF1_1V3_TX_LO 1

20% 6.3V X5R-CERM 01005

PLACE NEAR U3.127

C3708 0.1UF

20% 6.3V X5R-CERM 01005

PLACE NEAR U3.116

ALIAS

PP_RF1_1V3_TX_UPCONVERTER 1

TRANSCEIVER POWER CONNECTIONS 30

U3600

C3709

WTR1605

100PF

5% 16V NP0-C0G 01005

PP_RF1_1V3_PRX_FELO1 PP_RF1_1V3_PRX_FELO2 PP_RF1_1V3_DRX_LBLO 30 30 PP_RF1_1V3_DRX_FE PP_RF1_1V3_DRX_MBLO 30 PP_RF1_1V3_JAM_DET 30 30 PP_RF2_2V05_PRX_BB PP_RF2_2V05_DRX_BB 30

PP_RF2_2V05_PRX_VCO PP_RF1_1V3_PRX_VCO 30 PP_RF1_1V3_PRX_PLL 30 30 PP_RF2_2V05_SHDR_VCO PP_RF1_1V3_SHDR_VCO 30 PP_RF1_1V3_SHDR_PLL 30

STAR ROUTING

PP_RF1_1V3_PRX_FELO1

C3710 0.1UF

PP_RF1_1V3_DRX_FE

20% 6.3V X5R-CERM 01005

ALIAS

PLACE NEAR U3.53 AND U3.26

PP_RF1_1V3_PRX_FELO2 1

C3711 0.1UF

28 26 25 85 83 44

ALIAS

ALIAS 1

SM SRM 4 OF 5 PWR

PLACE NEAR U3.117

20% 6.3V X5R-CERM 01005

76 66 51 40 65

VDD_RF1_P_FELO VDD_RF1_P_FELO VDD_RF1_D_LBLO VDD_RF1_D_FE VDD_RF1_D_MBLO VDD_RF1_JDET VDD_RF2_P_BB VDD_RF2_D_BB VDD_RF2_P_VCO VDD_RF1_P_VCO VDD_RF1_P_PLL VDD_RF2_S_VCO VDD_RF1_S_VCO VDD_RF1_S_PLL

CRITICAL

VDD_RF2_T_DA VDD_RF1_T_DA VDD_RF1_T_UPC VDD_RF1_T_LO VDD_RF2_T_BB

111

VDD_RF2_T_VCO VDD_RF2_XO VDD_RF1_T_SYN VDD_RF2_T_PLL

136

118 117 116 108

127 98 97 24

VDD_RF1_G_LNA VDD_RF1_G_VCO 37 VDD_RF1_G_PLL 55 VDD_RF1_G_BB 31

PLACE NEAR U3.42

VDD_DIO 87

STAR ROUTING

PP_RF1_1V3_DRX_LBLO

PP_RF1_1V3_DRX_MBLO

PP_RF2_2V05_TX_DA 30 PP_RF1_1V3_TX_DA 30 PP_RF1_1V3_TX_UPCONVERTER 30 PP_RF1_1V3_TX_LO 30 PP_RF2_2V05_TX_BB 30 PP_RF2_2V05_TX_VCO PP_RF2_2V05_XO_FILT PP_RF1_1V3_TX_SYNTH PP_RF2_2V05_TX_PLL PP_RF1_1V3_GPS_LNA PP_RF1_1V3_GPS_VCO PP_RF1_1V3_GPS_PLL PP_RF1_1V3_GPS_DIG PP_RF1_1V8_DIG

30 30 30 30

ALIAS

C3712 0.1UF

ALIAS

20% 6.3V X5R-CERM 01005

PLACE NEAR U3.25 AND U3.28

ALIAS

PP_RF1_1V3_JAM_DET

A PAGE TITLE 30

CELL: RF TRANSCEIVER (2 OF 2) DRAWING NUMBER

Apple Inc.

051-0886

NOTICE OF PROPRIETARY PROPERTY:

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SIZE

REVISION

A.0.0 BRANCH

PAGE

37 OF 121 SHEET

30 OF 54

RX MATCHING L3805

L3810

0.7NH-0.8A

D 33

100_RX_MODULE_OUT_P

100_XCVR_B1_B34_B39_DCS_PRX_P

OUT

100_B8_DUPLX_RX_N

0201

100_XCVR_B8_PRX_N

OUT

100_XCVR_B8_PRX_P

OUT

100_XCVR_B5_B18_PRX_N

OUT

01005

CRITICAL

10NH-3%-140MA

L3804

L3811

5.6NH-3%-0.35A

18NH-3%-140MA

0201

01005

CRITICAL 2

L3812

L3806

100_RX_MODULE_OUT_N

10NH-3%-140MA

0.7NH-0.8A 100_XCVR_B1_B34_B39_DCS_PRX_NOUT

100_B8_DUPLX_RX_P

2 01005

0201

CRITICAL

L3808

8.2NH+/-3%-0.25A-0.7OHM

C3800

0.6PF 34

50_B2_DUPLX_RX

100_XCVR_B2_PRX_NOUT

100_B5_DUPLX_RX_N

2 0201

1 +/-0.05PF 16V CERM 01005

L3800

6.8NH-5%-0.5A

0201DS

CRITICAL

C3801 1

22NH-5%-0.1A 01005

L3809

100_XCVR_B2_PRX_POUT

C3802

0.9PF

100_B5_DUPLX_RX_P

L3840

50_B7_B38_B40_PRX_BALUN_IN

C3803 1

1 100_B7_B38_B40_PRX_BALUN_OUT_N

100_XCVR_B3_PRX_NOUT

0201DS

CRITICAL

C3804

100_XCVR_B3_PRX_POUT

1.2PF

ACFM-2043-AP1 LGA

1 3

C3808

9.1NH-3%-220MA 0201

18NH-3%-140MA

B38 B40

CRITICAL

B 50_B38_B40_SPDT

ANT 6

GND

2 4 5 7 8 9

100_XCVR_B20_PRX_NOUT

01005

L3817 33

50_B40_FILTER

L3823

C3810

50_B40_FILTER_MATCH

5.6NH-3%-0.35A 0201

5% 1/20W MF 201

22NH-5%-0.1A 01005

CRITICAL

NOSTUFF

C3809

L3824

2 35

CRITICAL

100_B20_DUPLX_RX_P

FIL_DIPLEXER_B38_B40

L3822

100_XCVR_B7_B38_B40_PRX_P OUT

U3801

50_B38_FILTER BI

B 100_B20_DUPLX_RX_N

2 0201

5% 16V NP0-C0G 01005

100_B7_B38_B40_PRX_MATCH_P1

+/-0.05PF NO_XNET_CONNECTION=TRUE 2 16V NP0-C0G-CERM 01005

0.6NH+/-0.1NH-0.85A

27PF

5% 16V NP0-C0G 01005

C3805

L3815

C3807 1 100_B7_B38_B40_PRX_BALUN_OUT_P

GND

27PF

50_B3_RX_BALUN

0201

0201DS

CRITICAL

3.6NH+/-0.1NH-400MA

CRITICAL

5.6NH-5%-0.33A

100_XCVR_B7_B38_B40_PRX_N OUT

L3814

BAL_PORT1 3 BAL_PORT2 4

L3803

8.7NH-5%-0.29A

2 0201

2.3-2.69GHZ LLP

NO_XNET_CONNECTION=TRUE

L3802

100_B7_B38_B40_PRX_MATCH_N1

UNBAL_PORT 2

+/-0.05PF 16V NP0-C0G-CERM 01005

5% 16V NP0-C0G 01005

U3803

0.6NH+/-0.1NH-0.85A

27PF

+/-0.1PF 25V 2 C0G-CERM 201

1.2PF 50_B3_DUPLX_RX

L3813

C3806

L3825

0.4PF

CRITICAL

0201

CRITICAL

NO_XNET_CONNECTION=TRUE

50_3P4T_PRX_OUT

100_XCVR_B5_B18_PRX_P

0201

2.0NH+/-0.1NH-0.6A

5% 16V NP0-C0G 01005

+/-0.05PF 2 16V CERM 01005

8.2NH+/-3%-0.25A-0.7OHM

27PF

50_B2_RX_BALUN 1

L3807 L3801

13NH-5%-0.28A 2

NO_XNET_CONNECTION=TRUE

6.8NH-3%-0.3A

18NH-3%-140MA 1

0201

100_XCVR_B20_PRX_POUT

CRITICAL

01005

U3802

TX-BAND40-LTE

SAFEA2G35MB0F57

L3819

LGA

CRITICAL

2.7NH+/-0.1NH-200MA 50_FULL_B40_FILTER BI

2 01005

CRITICAL 1

4 UNB_PORT2

50_FULL_B40_FILTER_MATCH

C3811

L3821 UNB_PORT1 1

56PF

50_FULL_B40_SPDT_MATCH

5% 2 16V NP0-C0G 01005

50_FULL_B40_SPDT

5% 1/20W MF 201

GND 5 3 2

L3820

3.3NH+/-0.1NH-0.45A

NOSTUFF

0201

CRITICAL

2 PAGE TITLE

CELL: RX MATCHING DRAWING NUMBER

Apple Inc.

051-0886

NOTICE OF PROPRIETARY PROPERTY:

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SIZE

REVISION

A.0.0 BRANCH

PAGE

38 OF 121 SHEET

31 OF 54

TX INTERSTAGE FILTERS C3901

2.0NH+/-0.1NH-0.2A-1.35OHM 29

50_XCVR_B2_TX

50_B2_TX_SAW_IN

01005 1

CRITICAL

C3902

56PF

5% 2 16V NP0-C0G 01005

C3913

NOSTUFF 29

50_XCVR_B34_B39_TX

0.00 2 0% 1/32W MF 01005

C3903 29

50_XCVR_B5_B18_TX

0.00 2

50_B5_B18_TX_SAW_IN

50_B34_B39_TX_FILT_IN 1

FL3901 LGA 1 INPUT BAND2 CRITICALOUTPUT BAND2 11 50_B2_TX_SAW_OUT OUT

2.7NH+/-0.1NH-200MA 01005

CRITICAL

L3901

OUTPUT BAND5+18 9

50_B5_TX_SAW_OUT

OUT

OUTPUT BAND8 7

50_B8_TX_SAW_OUT

OUT

10NH-5%-140MA

1 IN B34/B39

LGA

CRITICAL

3 INPUT BAND5+18

FL3902 SAW-BAND-TX-B1-B3-B34-B39 AF48

L3905

SATGR832MBM0F57

0% 1/32W MF 01005

4 IN B1/B3

OUT B3 6

CRITICAL

33 33

R3901

1.5NH+/-0.1NH-220MA 50_B1_TX_SAW_MATCH

50_B1_TX_SAW_OUT OUT

01005

2 3 5 10

5 INPUT BAND8

50_B34_TX_SAW_OUTOUT 50_B39_TX_SAW_OUTOUT

OUT B1 7

GND

01005

OUT B34 9 OUT B39 8

GND

50_XCVR_B8_TX

0.00 2

50_XCVR_B1_B3_TX 29

2 4 6 8 10 12

C3904

C3914

THRM PAD

0.00 2 0% 1/32W MF 01005

50_B8_TX_SAW_IN

50_B1_B3_TX_SAW_IN

L3907

10NH-3%-140MA 01005

NOSTUFF 1 2

0% 1/32W MF 01005

L3909

L3906

1.5NH+/-0.1NH-220MA

2.0NH+/-0.1NH-0.2A-1.35OHM

50_B3_TX_SAW_MATCH

01005

L3902

01005

50_B3_TX_SAW_OUT OUT

01005

10NH-5%-140MA 1

CRITICAL

L3908

5.1NH-3%-0.16A 01005

NOSTUFF 2

C3905 29

50_XCVR_B20_TX

0.00 2 0% 1/32W MF 01005

50_B20_TX_SAW_IN

OUT

L3903

10NH-5%-140MA 01005

40 39 33 25 14

PP_LDO14_2V65

C3909

0.01UF

10% 6.3V 2 X5R 01005

VDD

C3906 29

50_XCVR_B7_B38_B40_TX

50_XCVR_B7_B38_B40_TX_MATCH

U3901 BGS12SL6 5 RFIN TSLP6-2

C3910 RF1

50_B7_TX_SPDT_OUT

CRITICAL

+/-0.1PF 16V NP0-C0G 01005

1 33 28

PA_MB_CTL0

6 CTRL

RF2

1.5NH+/-0.1NH-220MA 01005

C3908

0.00 2

50_B7_TX_FILT_IN OUT

B 35

0% 1/32W MF 01005

5% 16V 2 NP0-C0G 01005

56PF

5% 16V 2 NP0-C0G 01005

C3911

56PF

GND

C3907

3.3PF

NOSTUFF

C3912

100PF 50_B38_B40_TX_SPDT_OUT1

5% 16V NP0-C0G 01005

50_B38_B40_TX_SPDT_MATCH OUT

L3904

1.2NH+/-0.1NH-220MA 01005

NOSTUFF 2

A PAGE TITLE

CELL: RF TRANSCEIVER (3 OF 4) DRAWING NUMBER

Apple Inc.

051-0886

NOTICE OF PROPRIETARY PROPERTY:

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SIZE

REVISION

A.0.0 BRANCH

PAGE

39 OF 121 SHEET

32 OF 54

R4064

38 37 36 35 34

C4001

0.1UF

20% 2 6.3V X5R-CERM 01005

32 28

37 36 35 34 28

C4002

1.0UF

100PF

C4054

33 28

40 39 28 24

40 39 28

B1 C1 C2 A2

3P4T_SEL_0 3P4T_SEL_1 ANT_SEL_1 ANT_SEL_0 1

C4075

C4076

56PF

5% 16V 2 NP0-C0G 01005

C4008

56PF

5% 16V 2 NP0-C0G 01005

U4000

VC1 VC2

SKY13477 RF1 BGA

CRITICAL

VC4 VC3

C4012

56PF

5% 16V 2 NP0-C0G 01005

RF2 RF3 RF4 RF5 RF6 RF7

5% 16V 2 NP0-C0G 01005

C5 C4 C3 B5 A4 A5 A3

50_3P4T_PRX_OUT

C4041

56PF 5% 2 16V NP0-C0G 01005

C4042

56PF 5% 2 16V NP0-C0G 01005

C4052

56PF

5% 2 16V NP0-C0G 01005

C4060

0.00 2 50_B7_DUPLX_RX

0% 1/32W MF 01005

C4023

56PF 5% 16V 2 NP0-C0G 01005

NOSTUFF

56PF 5% 2 25V NP0-C0G 201

50_B1_PA_IN

C4048

0% 1/32W MF 01005

1.2PF

50_B38_PA_MATCH

NOSTUFF

0.00 2

C4038

5% 1/20W MF 201

C4053

L4029 50_B1_TX_SAW_OUT IN

L4012 1 50_B7_RX_SP3T_IN

OUT

50_B40_FILTER 50_FULL_B40_FILTER 50_B38_FILTER

C4058 50_B38_PA_OUT

C4072

56PF

5% 2 16V NP0-C0G 01005

PA_BS PA_MB_CTL1 PA_MB_CTL0 PA_R1

5% 16V 2 NP0-C0G 01005

100PF

20% 2 6.3V X5R 0201-1

5% 2 16V NP0-C0G 01005

PP_LDO14_3P4T

B2 B4 B3

C4043

0.00 2 0% 1/32W MF 01005

=PPBATT_VCC_BB PP_PA

D 36 35 34 28

PP_LDO14_2V65 1

DGND GND1 GND2

54 38 37 36 35 34 25 24

VDD A1

BAND 1/34/39/38/40 TX

40 39 33 32 25 14

50_B40_PA_OUT

C4061

NOSTUFF

3 7 8

+/-0.1PF 16V 2 NP0-C0G 01005

50_B40_PA_MATCH

5% 1/20W MF 201

12NH+/-3%-0.25A-0.7OHM

C4039

2 21

1.2PF +/-0.1PF 2 16V NP0-C0G 01005

NOSTUFF

L4044 32

50_B39_TX_SAW_OUT

0.00 2

50_B39_PA_IN

0% 1/32W MF 01005

5 4 19

RFIN_B34 RFIN_B39 RFOUT_B34/B39

6 17 15

RFIN_B38/B40 RFOUT_B38 RFOUT_B40 GND

C4040

U4025 ACPM-7900-AP1

CPL_IN 12 50_MBPA_CPL_IN IN CPL_OUT 24 50_B2_B3_CPL_INOUT

LLP

50_B34_B39_PA_OUT1

C4037

R4065 0.00 2 1 PP_LDO14_2V65

C4073

CRITICAL

C4063

C4074

10NH-3%-250MA

15NH+/-3%-0.25A-0.7OHM

OUT

0201

OUT

0201

100_RX_MODULE_OUT_P 100_RX_MODULE_OUT_N

0.00 2

50_DCS_RX_ASM 1

11 BAND1_34_39_DCSRXOUT0 12 BAND1_34_39_DCSRXOUT1

C4055

0.5PF

+/-0.05PF 16V 2 NP0-C0G 01005

L4071

BAND34_39_RXIN 18

4.0PF 1

50_RX_MOD_B34_B39_IN

50_B34_B39_RX_ASM

+/-0.1PF 25V COG-CERM 0201

20 19

NOSTUFF

DCSRXIN 1

PAD

56PF

5% 16V 2 NP0-C0G 01005

CRITICAL

VC1 8 VC2 7

CRITICAL

THRM

28 33

C4034

0% 1/32W MF 01005

LGA

17 BAND1ANT

C4046

28 33

L4070 50_RX_MOD_DCS_IN1

U4027

20% 2 6.3V X5R-CERM 01005

LMSWFKJM

15 BAND1_TX

C4064

C4033

5% 16V 2 NP0-C0G 01005

0.1UF

56PF

50_B1_PA_OUT_MATCH

CRITICAL

VDD

+/-0.05PF 25V C0G-CERM 0201

OUT

+/-0.05PF 25V 2 CERM 0201

56PF

C4047 50_B1_PA_OUT

50_B34_B39_TX_ASM

0.6PF

PP_LDO14_RX_MOD

3.0PF

01005

3P4T_SEL_0 3P4T_SEL_1

5% 16V 2 NP0-C0G 01005

7.5NH-3%-0.140A

2 0201

50_B38_B40_PA_IN

+/-0.1PF 16V NP0-C0G 01005

50_B34_B39_PA_FILT_OUT

5% 16V NP0-C0G 01005

4.0PF 50_B38_B40_TX_MATCH

0201

L4045

100PF

L4083

2.9NH+/-0.1NH-0.5A-0.2OHM

CRITICAL

0% 1/32W MF 01005

L4020 IN

THRM PAD

40 39 33 32 25 14

50_B34_B39_PA_FILT_IN1 IN/OUTLGAOUT/IN 3 CRITICAL GND

8.2NH+/-3%-0.25A-0.7OHM

C4071

01005

5% 1/20W MF 201

18NH-3%-140MA

50_B38_B40_TX_SPDT_MATCH

FL4012 1880-2025MHZ DEA162025LT-5046B1SJ

C4049

CRITICAL

1 9 13 14 16 18 20 22 23 25

RFIN_B1 RFOUT_B1

2 4

0% 1/32W MF 01005

VCC

50_B34_PA_IN

GND

CRITICAL

C4056

16 14 13 10 9 5 4 3 2

0.00 2

VBATT

27 28 29 30 31 32

50_B34_TX_SAW_OUT

VBS_0 VBS_1 VBS_2

VMODE

0201

L4030

5.6NH-3%-0.35A 0201

CRITICAL 2

BAND PA POWER MODE PA_BS PA_CTL1 PA_CTL0 PA_R1 ======================================================= OFF X X 0 0 0 B1 HPM X 1 0 0 B1 LPM X 1 0 1 B34 HPM 1 0 1 0 B34 LPM 1 0 1 1 B39 HPM 0 0 1 0 B39 LPM 0 0 1 1 B38 HPM 1 1 1 0 B38 LPM 1 1 1 1 B40 HPM 0 1 1 0 B40 LPM 0 1 1 1

L4072

100PF 50_B1_RX_MOD_ANT

50_B1_ANT

CRITICAL

L4097

7.5NH-0.30A 0201

CRITICAL 2

A PAGE TITLE

CELL: PENTABAND PA DRAWING NUMBER

Apple Inc.

051-0886

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

5% 25V NP0-CERM 0201

A.0.0 BRANCH

PAGE

40 OF 121 SHEET

33 OF 54

BAND 2/3 PAD D

38 37 36 35 33

54 38 37 36 35 33 25 24

PA_ON_B2_B3

PP_PA =PPBATT_VCC_BB

PA_BS 1

C4100

0.22UF

20% 6.3V 2 X5R 01005

C4146

0.1UF

L4122

L4182

9.1NH-3%-140MA

2.2NH+/-0.1NH-200MA

01005

NOSTUFF

NOSTUFF 50_B3_TX_PAD_IN 50_B2_TX_PAD_IN

26 RFIN_B3 28 RFIN_B2

U4123

TQM6M6224

C4104

0.5PF

+/-0.05PF 16V 2 C0G-CERM 01005

28 33 35 36 37

GND

C4103

100PF

5% 2 6.3V CERM 01005

OUT

L4136

3.0NH+/-0.1NH-0.45A CPL_IN 4 CPL_OUT 20

50_B3_ANT

0201

CRITICAL 1

ANT_B3 16 ANT_B2 8

50_B3_DPLX_ANT 50_B2_DPLX_ANT

C4154

C4150

0.5PF

+/-0.05PF 25V 2 COG-CERM 0201

+/-0.05PF 25V 2 CERM 201

CRITICAL

THRM_PAD

2 01005

50_B7_B20_CPL_IN

CRITICAL

1 3 5 6 7 9 12 15 17 18 19 21 22 23 27

50_B2_TX_SAW_OUT

C4102

5% 2 6.3V CERM 01005

LGA

11 RX_B2 10 GND

2.7NH+/-0.1NH-200MA

VMODE 24

L4123

100PF

13 RX_B3 14 GND

PA_R1

20% 6.3V 2 X5R 0201-1

50_B2_B3_CPL_IN

C4149

1.0UF

20% 6.3V 2 X5R-CERM 01005

0.00 2 0% 1/32W MF 01005

C4148

VEN_B2_B3 30 BS 29

20% 6.3V 2 X5R 01005

NOSTUFF

50_B3_TX_SAW_OUT

0.22UF

VCC 2

C4101

VBATT 25

28 33 35 36

C4147

0.5PF

+/-0.05PF 16V 2 C0G-CERM 01005

L4138

3.0NH+/-0.1NH-0.45A

NOSTUFF

R4139

50_B2_DPLX_ANT_MATCH

0201

CRITICAL 50_B2_DUPLX_RX 50_B3_DUPLX_RX

1 OUT OUT

C4155

0.6PF

0.00 2

50_B2_ANT

1% 1/20W MF 0201

0.5PF

+/-0.05PF 2 25V CERM 0201

C4151

+/-0.05PF 2 25V CERM 201

CRITICAL

NOSTUFF

BAND PA POWER MODE PA_BS PA_ON_B2_B3 PA_R1 ===================================================== OFF X X 0 X B3 HPM 0 1 0 B3 LPM 0 1 1 B2 HPM 1 1 0 B2 LPM 1 1 1

A PAGE TITLE

CELL: BAND 2/3 PAD DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY:

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

41 OF 121 SHEET

34 OF 54

BAND 20/7 PAD D

D PA_ON_B7_B20 PA_BS 1

C4239

C4233

100PF 5% 6.3V 2 CERM 01005

38 37 36 34 33

54 38 37 36 34 33 25 24

C4235

0.22UF

20% 6.3V 2 X5R 01005

C4231

C4229

0.1UF

20% 2 6.3V X5R-CERM 01005

C4230

1.0UF

1 INPUT_BAND20

OUTPUT_BAND7 6

1.2PF

OUTPUT_BAND20 9

NOSTUFF

L4254

2 3 5 7 8 10

50_B7_TX_FILT_OUT

50_B20_TX_SAW_MATCH

1.0PF IN

01005

5% 16V NP0-C0G 01005

CRITICAL 1

+/-0.1PF 16V 2 NP0-C0G 01005

L4200

6.2NH-0.30A CPL_IN 4 CPL_OUT 20

CRITICAL

50_B20_ANT

CRITICAL

CELL

1 1

C4208

3.9PF

ANT_B20 16 ANT_B7 8 GND

0201

50_B20_DPLX_ANT

+/-0.1PF 25V 2 C0G-CERM 0201

L4257

10NH-3%-250MA 0201

THRM_PAD

NOSTUFF

C4228

0.8PF

5% 2 16V NP0-C0G 01005

11 RX_B7 10 GND

OUT

+/-0.1PF 16V NP0-C0G 01005

CRITICAL CELL

LGA

12 RX_P_B20 13 RX_N_B20

CRITICAL

56PF

C4207

28 33 34 36 37

50_PDET_PAD_IN

U4215 AFEM-790720

50_B20_TX_PAD_IN 26 RFIN_B20 50_B7_TX_PAD_IN 28 RFIN_B7

3.3NH+/-0.1NH-180MA

56PF

C4219

VMODE 24

C4227

+/-0.1PF 16V 2 NP0-C0G 01005

GND

C4218 2

CRITICAL

VCC 2

VEN_B7_B20 30 BS 29

CRITICAL

PA_R1

31 32 33 34 35 36 37 38 39 40 41 42

LGA 4 INPUT_BAND7

NOSTUFF

50_B20_TX_SAW_IN

CELL

20% 2 6.3V X5R 0201-1

01005

SAWFD847MGA0F57

01005

20% 6.3V 2 X5R 01005

2.7NH+/-0.1NH-200MA 50_B20_TX_SAW_OUT

FL4211

2.2NH+/-0.1NH-200MA

0.22UF

L4253

C4216

100PF 5% 6.3V 2 CERM 01005

50_B7_TX_FILT_MATCH

5% 16V CERM 01005

C4232

VBATT 25

1 3 5 6 7 9 14 15 17 18 19 21 22 23 27

50_B7_TX_FILT_IN

28 33 34 36

C4234

50_B7_B20_CPL_IN

22PF IN

100PF 5% 6.3V 2 CERM 01005

PP_PA =PPBATT_VCC_BB 1

CRITICAL

NOSTUFF

C4236

NOSTUFF

2.2NH+/-0.1NH-0.6A 50_B7_DPLX_ANT 50_B7_DUPLX_RX

OUT

50_B7_ANT 1

L4229

100_B20_DUPLX_RX_P OUT

L4228

0.5PF

100_B20_DUPLX_RX_N OUT

0201

+/-0.05PF 25V 2 CERM 201

+/-0.05PF 25V 2 COG-CERM 0201

NOSTUFF

CRITICAL

BAND PA POWER MODE PA_BS PA_ON_B20_B7 PA_R1 ===================================================== OFF X X 0 X B20 HPM 0 1 0 B20 LPM 0 1 1 B7 HPM 1 1 0 B7 LPM 1 1 1

A PAGE TITLE

CELL: BAND 7/20 PAD DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY:

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

42 OF 121 SHEET

35 OF 54

BAND 5/8 PAD D

D PP_PA =PPBATT_VCC_BB

PA_ON_B5_B8 PA_BS 1

C4322

0.22UF

20% 6.3V 2 X5R 01005

C4323

0.22UF

20% 6.3V 2 X5R 01005

C4318

0.1UF

20% 6.3V 2 X5R-CERM 01005

C4319

2 01005

CRITICAL

C4316

1.2PF

C4327

1.2PF

+/-0.1PF 2 16V NP0-C0G 01005

NOSTUFF

L4315

2.2NH+/-0.1NH-200MA 32

50_B8_TX_SAW_OUT

C4317

2.2PF

+/-0.1PF 16V 2 NP0-C0G 01005-1

CRITICAL

13 14

RX_P_B5 RX_N_B5

11 10

RX_P_B8 RX_N_B8

CRITICAL

1.2PF

28 33 34 35

C4325

100PF

R4300

5% 6.3V 2 CERM 01005

49.9 1% 1/32W MF 2 01005

OUT

C4320

2.7NH+/-0.1NH-0.50A CPL_IN 4 CPL_OUT 20

U4358

SKY77493 LGA

50_B5_DPLX_ANT

50_B5_ANT

0201

CRITICAL

GND

50_MBPA_CPL_IN

ANT_B5 16 ANT_B8 8 THRM_PAD

C4326

+/-0.1PF 16V 2 NP0-C0G 01005

C4324

50_PA_ISO

2 01005

50_B5_TX_PAD_IN 26 RFIN_B5 50_B8_TX_PAD_IN 28 RFIN_B8

1 3 5 6 7 9 12 15 17 18 19 21 22 23 27

100PF

31 32 33 34 35 36 37 38 39 40 41 42

28 33 34 35 37

5% 6.3V 2 CERM 01005

VBATT 29

L4314

50_B5_TX_SAW_OUT

20% 6.3V 2 X5R 0201-1

2.2NH+/-0.1NH-200MA 32

PA_R1

1.0UF

VMODE 30

VEN_B5_B8 24 BS 25

VCC 2

38 37 35 34 33 54 38 37 35 34 33 25 24

L4316

0.5PF

+/-0.05PF 2 25V COG-CERM 0201

CRITICAL

NOSTUFF

C4321

18PF 1

50_B8_DPLX_ANT 100_B8_DUPLX_RX_N

OUT

100_B8_DUPLX_RX_P

OUT

100_B5_DUPLX_RX_N

OUT

100_B5_DUPLX_RX_P

OUT

50_B8_ANT

2% 25V C0H-CERM 0201

L4317

22NH-100MA 0201

NOSTUFF 2

BAND PA POWER MODE PA_BS PA_ON_B5_B8 PA_R1 ===================================================== OFF X X 0 X B5 HPM 0 1 0 B5 LPM 0 1 1 B8 HPM 1 1 0 B8 LPM 1 1 1

A PAGE TITLE

CELL: BAND 5/8 PAD DRAWING NUMBER

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY:

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

43 OF 121 SHEET

36 OF 54

2G PA

2G PA GAIN MODES BAND MODE GAIN MODE PA_R1 PCL RANGE ======================================================= LOW BAND GSM ULTRA LOW HIGH 16 TO 19 LOW BAND LOW HIGH 14 TO 15 GSM LOW 7 TO 13 LOW BAND GSM MEDIUM LOW LOW BAND GSM HIGH 5 TO 6 HIGH BAND GSM ULTRA LOW HIGH 10 TO 15 HIGH BAND LOW HIGH GSM 7 TO 9 HIGH BAND GSM HIGH LOW 0 TO 6 LOW BAND EDGE LOW HIGH 15 TO 19 LOW BAND EDGE LOW 10 TO 14 MEDIUM HIGH LOW BAND EDGE LOW 8 TO 9 HIGH BAND EDGE LOW HIGH 9 TO 15 HIGH BAND EDGE HIGH LOW 2 TO 8

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

38 36 35 34 33

PP_PA IN

C4485

4.7UF

C4488 0.1UF

20% 6.3V 2 X5R-CERM1 402

20% 4V 2 X5R 01005

L4440

240OHM-350MA 54 38 36 35 34 33 25 24

=PPBATT_VCC_BB

PP_BATT_VCC_2G_PA

0201

C4467

C4472

2.7PF 29

50_XCVR_2G_HB_TX

12PF 50_TX_G_HB_MCH

50_TX_G_HB_PAIN

1 +/-0.1PF 16V NP0-C0G 01005-1

C4489

C4487 1.0UF

56PF

5% 16V CERM 01005

5% 16V 2 NP0-C0G 01005

20% 10V 2 X5R-CERM 0201-1

L4436 2.7NH+/-0.1NH-200MA V2G 14

VBATT 7

01005

U4410

SKY77355 C4484

50_XCVR_2G_LB_TX

0.00 2

HB_GSM_RF_IN

LB_GSM_RF_IN

PA_R1

VMODE0

GSM_PA_LB_EN GSM_PA_HB_EN

4 5

PA_ON2 PA_ON3

CRITICAL

33PF

50_TX_G_LB_MCH

0% 1/32W MF 01005

50_TX_G_LB_PAIN

5% 16V NP0-C0G 01005

CRITICAL 1

C4471

36 35 34 33 28

C4483 100PF

5% 16V 2 NP0-C0G 01005

NOSTUFF

C4486 100PF

5% 16V 2 NP0-C0G 01005

2 9 10 12 13

+/-0.1PF 16V 2 NP0-C0G 01005

GND GND GND GND GND

6.0PF

HB_GSM_RF_OUT 11

L4437

3.2NH+/-0.1NH-0.45A-025OHM 50_TX_G_HB_PAOUT

50_TX_G_HB_ASM

OUT

0201

LB_GSM_RF_OUT 8

CRITICAL

L4438 3.6NH+/-0.1NH-400MA

THRM_PAD THRM_PAD THRM_PAD THRM_PAD THRM_PAD THRM_PAD THRM_PAD THRM_PAD THRM_PAD

LGA

0201

NOSTUFF 2

15 16 17 18 19 20 21 22 23

L4435 29

R4437 50_TX_G_LB_PAOUT

0.00 2 1% 1/20W MF 0201

50_TX_G_LB_ASM

OUT

L4439 3.6NH+/-0.1NH-400MA 0201

NOSTUFF 2

A PAGE TITLE

CELL: 2G PA DRAWING NUMBER

Apple Inc.

051-0886

NOTICE OF PROPRIETARY PROPERTY:

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SIZE

REVISION

A.0.0 BRANCH

PAGE

44 OF 121 SHEET

37 OF 54

PA DC/DC CONVERTER D

=PPBATT_VCC_BB

C4502

56PF

C4503 0.01UF

5% 2 16V NP0-C0G 01005

10% 2 6.3V X5R 01005

C4504 10UF

20% 2 6.3V CERM 0402

A3 B3

54 37 36 35 34 33 25 24

PVIN VDD

L4500

U4500 PLACE NEAR U11.D2

BB_PDM

1.00K 1% 1/32W MF 01005

R4534 BB_PDM_FILT 1

C4500 1000PF

10% 6.3V 2 X5R-CERM 01005

1.00K

DCDC_EN

C2 EN

BGA

CRITICAL

C3 BP

1% 1/32W MF 01005

DCDC_ADJ 1

DCDC_MODE

D2 VCON

C4545 1000PF

PGND

10% 6.3V 2 X5R-CERM 01005

SW A2 SW B2

DCDC_OUT

PP_PA

OUT

33 34 35 36 37

PIFE20161T-SM

CRITICAL

CRITICAL 1

FB D4

D3 MODE

A1 B1

R4500

1.5UH-2.0A-0.137OHM

LM3258 28

C1 SGND C4 BGND

PLACE NEAR U1.H3

C4507 10UF

20% 6.3V 2 CERM-X5R 0402

ACB A4 ACB B4

CRITICAL 1

C4508 3300PF

10% 2 6.3V X5R 01005

A PAGE TITLE

CELL: PA DCDC CONVERTER DRAWING NUMBER

Apple Inc.

051-0886

NOTICE OF PROPRIETARY PROPERTY:

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SIZE

REVISION

A.0.0 BRANCH

PAGE

45 OF 121 SHEET

38 OF 54

PRIMARY ASM D

40 39 33 32 25 14

PP_LDO14_2V65

C4669 100PF

1 = PARTIAL B40

5% 6.3V 2 CERM 01005

0 = FULL B40

VDD

C4640

SW4601

1.8NH+/-0.1NH-600MA 50_TXRX_B38_B40_SPDT

6 RF1

0201 28

C4622

50_FULL_B40_SPDT

RF3 2

50_B38_B40_SPDT

C4668

100PF 5% 2 6.3V CERM 01005

PP_LDO14_2V65 1

RF2 4

GND 1

+/-0.1PF 25V 2 C0G-CERM 201 IN

1 VC

B40_FILT_SELECT

L4642 0.3PF

40 39 33 32 25 14

XFLGA

CRITICAL

CXA4403GC

C4641 0.1UF

100PF 5% 6.3V 2 CERM 01005

20% 4V 2 X5R 01005

VDD 26

R4605 1

50_PRI_ANT_COAX

5% 1/20W MF 201

U4617

RF1495

1 9 11 13

THRM PAD

LGA ANT1 TRX1 TRX2 ANT2 TRX3 HBTX TRX4 LBTX TRX5 CRITICAL TRX6 RF1 TRX7 RF2 TRX8 VC1 TRX9 VC2 TRX10 VC3 VC4 VC5

L4613 2 20

50_ASM_ANT 50_ANT2_TERM

10 12

50_TX_G_HB_ASM 50_TX_G_LB_ASM

3 19

50_TXRX_B38_B40_ASM 50_RF2_TERM

56NH-100MA-3.9OHM 0201

21 22 23 24 25

ANT_SEL_0 ANT_SEL_1 ANT_SEL_2 ANT_SEL_3 ANT_SEL_4

4 5 6 7 8 14 15 16 17 18

50_B3_ANT 50_B2_ANT 50_B34_B39_RX_ASM 50_B20_ANT 50_B7_ANT 50_B5_ANT 50_B8_ANT 50_DCS_RX_ASM 50_B1_ANT 50_B34_B39_TX_ASM

GND GND GND GND

R4607 49.9

1% 1/20W MF 2 201

R4608 49.9

1% 1/20W MF 2 201

C4639 100PF

5% 6.3V 2 CERM 01005

C4663 100PF

5% 6.3V 2 CERM 01005

C4664 100PF

5% 6.3V 2 CERM 01005

C4665 100PF

5% 6.3V 2 CERM 01005

28 33 40

24 28 33 40

24 28 40

28 40

C4666 100PF

5% 6.3V 2 CERM 01005

A PAGE TITLE

CELL: ASM AND HB LTE FRONT-END DRAWING NUMBER

Apple Inc.

051-0886

A.0.0

NOTICE OF PROPRIETARY PROPERTY:

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SIZE

REVISION

BRANCH

PAGE

46 OF 121 SHEET

39 OF 54

RX DIVERSITY D

CRITICAL 39 33 32 25 14

50_DRX_ANT

27PF

50_DRX_ASM_MCH

5% 1/20W MF 201

PP_LDO14_2V65

C4794

R4701

NOSTUFF

C4798

0.01UF

5% 6.3V NP0-C0G 0201

10% 2 6.3V X5R 01005

C4739

56PF 5% 2 16V NP0-C0G 01005

L4743

3.0NH+/-0.1NH-0.45A 7

0201

VDD

U4714 HFQSWBUUA-239 50_DIVERSITY_SWITCH_MATCH

39 33 28 24

39 28 24

39 28

C4710

56PF

5% 16V 2 NP0-C0G 01005

C4736

56PF

C4737

56PF

5% 16V 2 NP0-C0G 01005

100_XCVR_GPS_RX_MATCH_N 100_XCVR_GPS_RX_MATCH_P

C4738

56PF

5% 16V 2 NP0-C0G 01005

50_GPS_DRX_MOD_IN

C4755 OUT

VC1 VC2 VC3 VC4

17 18 14

GPS OUT GPS OUT GPS IN

12 11

BAND 38 IN BAND 40 IN

CRITICAL

BAND 5+18 OUT 25 BAND 5+18 OUT 26

100_XCVR_B5_B18_DRX_P 100_XCVR_B5_B18_DRX_N

OUT

BAND 8,20 OUT 23 BAND 8,20 OUT 24

100_XCVR_B8_B20_DRX_P 100_XCVR_B8_B20_DRX_N

OUT

100_XCVR_B7_B38_B40_DRX_P 100_XCVR_B7_B38_B40_DRX_N

OUT

100_XCVR_B1_B2_B3_B34_B39_DRX_P OUT 100_XCVR_B1_B2_B3_B34_B39_DRX_N

BAND 7,38,40 OUT 19 BAND 7,38,40 OUT 20 BAND 1,2,3,34,39 OUT 21 BAND 1,2,3,34,39 OUT 22 AUX1 33 AUX2 9

5.6NH-3%-140MA 2 100_XCVR_GPS_RX_N 1

OUT

50_DRX_MOD_TERM

THRM PAD 1

2 8 10 13 15 16 27 28 29 30 31 32 34

ANTENNA

6 5 4 3

35 36 37 38

LGA

GND GND GND GND GND GND GND GND GND GND GND GND GND

39 33 28

ANT_SEL_0 ANT_SEL_1 ANT_SEL_2 ANT_SEL_3

R4739

49.9 1% 1/20W MF 2 201

01005 1

L4742 4.7NH-3%-160MA 01005

C4756 29

OUT

5.6NH-3%-140MA 2 100_XCVR_GPS_RX_P 1 01005

C4797

56PF 41

50_GPS_LNA_OUT

5% 16V NP0-C0G NOSTUFF 01005

L4746

L4740

10NH-3%-140MA 01005

50_B38_DRX_MOD_IN

5% 1/20W MF 201

C4799

6.8NH-3%-0.3A 0201

CRITICAL 2

U4722 885035 BAW-DUAL-RX-B38-B40

R4711

LGA

5.6PF

50_B38_B40_DRX_AUX2_OUT

50_B38_B40_DRX_FILT_IN

+/-0.1PF 25V NP0-C0G 0201

8 B38_ANT

B38_RX 1

7 B40_ANT

B40_RX 4

50_B38_DRX_FILT_OUT

L4747

50_B40_DRX_FILT_OUT

50_B40_DRX_MOD_IN

5% 1/20W MF 201

GND

C4708

2 3 5 6 9 10

2.3NH+/-0.1NH-0.50A-0.2OHM 0201 1

L4701 5.6NH-3%-0.35A

0201

L4765

CRITICAL

3.0NH+/-0.1NH-0.45A 0201

NOSTUFF

A PAGE TITLE

CELL: RX DIVERSITY DRAWING NUMBER

Apple Inc.

051-0886

NOTICE OF PROPRIETARY PROPERTY:

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

SIZE

REVISION

A.0.0 BRANCH

PAGE

47 OF 121 SHEET

40 OF 54

GPS CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

CELL

FL4802

150OHM-25%-200MA-0.7DCR 1

PP_GPS_LNA_2V5

PP_LDO5_GPS_LNA_2V5

01005

CELL 1

CRITICAL

C4809 0.1UF

787MHZ TRAP

2400MHZ TRAP

CELL

ANT

5% 1/20W MF 201

C4803

HB/LB

2 1

50_GPS_LNA_IN

TSNP6 CRITICAL

5 AI

CRITICAL

50_GPS_LNA_OUT

OUT

GND

L4807 1.3PF

0201

NOSTUFF

0201

15NH+/-3%-0.25A-0.7OHM

NOSTUFF

CELL CRITICAL

+/-0.1PF 25V 2 C0G-CERM 201

L4805

10NH-3%-250MA

A0 3 PON 6

L4803

0201

2 0201

+/-0.05PF 16V CERM 01005

CRITICAL

27NH-3%-0.140A-2.3OHM

2.0NH+/-0.1NH-0.6A 50_GPS_FILT4

0.9PF

+/-0.1PF 25V C0G 0201

L4802

CELL

C4805

5.0PF

GND

CRITICAL

50_GPS_FILT2

50_GPS_DIV_SW_CONN

2 4 5 7 8 9

50_GPS_DIV_TRI_ANT

CRITICAL

CRITICAL CELL

GPS/GNSS 1 50_GPS_FILT1

VCC CELL

U4801 BGA824N6

C4807

0201

LGA CELL

L4801

CRITICAL CELL

2 0201

SASLE1G58AB0F57

L4806

4.7NH-3%-0.35A

8.2NH+/-3%-0.25A-0.7OHM

FL4801

CRITICAL

CELL

L4804

CELL

20% 2 6.3V X5R-CERM 01005

NOSTUFF

2 2

50_GPS_FILT3 1

C4804 1.8PF

+/-0.1PF 2 16V NP0-C0G 01005-1

900MHZ TRAP

CELL CRITICAL

50_DRX_ANT

OUT

B CELL

GPS_DRX_ANT

J4802

MM8930-2600B

CELL

F-RT-SM

J4800

CELL

MM5829-2700

R4801 50_GPS_ANT_COAX

C4801 0.2PF

+/-0.1PF 25V 2 COG-CERM 201

NOSTUFF

50_GPS_ANT_TEST 2

5% 1/20W MF 201

CRITICAL

1 R

50_GPS_DIV_SW_CONN

GND 1

C4802 0.2PF

6 5 4 3

F-ST-SM

+/-0.1PF 25V 2 COG-CERM 201

NOSTUFF

TOP MOUNT

SYNC_MASTER=RADIO_MLB_87

SYNC_DATE=10/29/2013

PAGE TITLE

CELL: GPS DRAWING NUMBER

Apple Inc.

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

48 OF 121 SHEET

41 OF 54

ANTENNA FEEDS D

PRI_ANT COAX CELL

J4910 MM5829-2700 F-ST-SM

50_PRI_ANT_COAX

SYNC_MASTER=RADIO_MLB_87

SYNC_DATE=10/29/2013

PAGE TITLE

CELL: ANTENNA FEEDS DRAWING NUMBER

Apple Inc.

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

49 OF 121 SHEET

42 OF 54

NOSTUFF

J5700 MLB-X200

L5700

HB-SM 52 43 16

52 43 16

52 43

52 43 16 52 43 16

NOTE:

SPKR_R_CONN_N SPKR_R_CONN_P

FERR-70-OHM-4A

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31

CONN_DET_L E75_DPAIR2_CONN_N PPVBUS_E75_USB_CONN

E75_DPAIR1_CONN_N SPKR_L_CONN_N SPKR_L_CONN_P

SPKR_R_CONN_N 16 SPKR_R_CONN_P 16 PPOUT_E75_ACC_ID2_CONN 43

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32

E75_DPAIR2_CONN_P PPVBUS_E75_USB_CONN

PPOUT_E75_ACC_ID1_CONN

43 52 43

PPVBUS_E75_USB_CONN

43 52

=PPVBUS_USB_EMI

0603

DZ5700

C5701

27PF

27V-100PF

43 52

C5700

R5700

0.01UF

1% 2 25V NP0-C0G 201

0402

100K

10% 2 25V X7R 402

1% 1/20W MF 2 201

C5702 27PF

1% 2 25V NP0-C0G 201

C5703 6.8PF

+/-0.25PF 2 25V CERM 201

43 52

E75_DPAIR1_CONN_P SPKR_L_CONN_N SPKR_L_CONN_P

43 52

16 43 52 16 43 52

SPKR_L_CONN_N AND SPKR_L_CONN_P WERE SWAPPED ON 5/22/12 PER RADAR #11526818

L5703

90-OHM-50MA TCM0605-1

SYM_VER-1

E75_DPAIR1_CONN_P 52 43

E75_DPAIR1_CONN_N 52 43

CRITICAL

D5700

E75_DPAIR1_P 11

E75_DPAIR1_N 11

D5702 ESD0P2RF-02LS

TSSLP-2-1 1

CRITICAL

ESD0P2RF-02LS

=PPVCC_MAIN_DOCK

TSSLP-2-1 1

NOSTUFF

R5790

NOSTUFF 1

R5705

100K

CONN_DET_L

CRITICAL

DZ5702

14.2V-6PF

+/-0.25PF 25V 2 CERM 201

10K

OUT

C5704

R5791 0.00

0% 1/32W MF 2 01005

1% 1/32W MF 01005

6.8PF

0201-1

PMU_E75_ACC_DET_L

R5706 1

0.00 2 0% 1/32W MF 01005

1% 1/32W MF 2 01005

CRITICAL

DZ5710 SM-201

L5704

DSF01S30SC

90-OHM-50MA TCM0605-1

SYM_VER-1

E75_DPAIR2_CONN_P

52 43

TS_CON_DET_L OUT

E75_DPAIR2_P 11

E75_DPAIR2_CONN_N

52 43

CRITICAL

D5701

B 11

CRITICAL

D5703

ESD0P2RF-02LS

L5701

E75_DPAIR2_N

ESD0P2RF-02LS

TSSLP-2-1

FERR-22-OHM-1A-0.055OHM 52 43

PPOUT_E75_ACC_ID1_CONN C

CRITICAL

0201

DZ5703

14.2V-6PF

+/-0.5PF 16V 2 NP0-C0G-CERM 01005

0201-1

PPOUT_E75_ACC_ID1

C5705

0.055 OHM DCR

8.2PF

L5702

FERR-22-OHM-1A-0.055OHM 52 43

PPOUT_E75_ACC_ID2_CONN C

A A

CRITICAL

DZ5704 14.2V-6PF

+/-0.5PF 2 16V NP0-C0G-CERM 01005

0201-1

PPOUT_E75_ACC_ID2

0201 1

C5707

0.055 OHM DCR

8.2PF SYNC_MASTER=N/A

SYNC_DATE=04/18/2011

PAGE TITLE

IO:

FILTERS & HOTBAR CONN DRAWING NUMBER

Apple Inc.

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

57 OF 121 SHEET

43 OF 54

WIFI/BT: MODULE MODULE ISOLATION

XW5890 52 48

PMU_GPIO_WLAN_REG_ON

SHORT-10L-0.25MM-SM 1 2

52 48

PMU_GPIO_BT_REG_ON

SHORT-10L-0.25MM-SM 1 2

PMU_GPIO_CLK_32K_WLAN

SHORT-10L-0.25MM-SM 1 2

PMU_GPIO_WLAN_REG_ON_R

XW5891

PMU_GPIO_BT_REG_ON_R

PMU_GPIO_CLK_32K_WLAN_R

XW5892

XW5893

SHORT-10L-0.25MM-SM 1 2

UART_WLAN2BB_LTE_COEX

=PPVCC_MAIN_WLAN =PP3V3_S2R_WIFI_PA

UART_WLAN2BB_LTE_COEX_R

C5880

10UF

28 24

UART_BB2WLAN_LTE_COEX_R

UART2_WLAN2SOC_TX_R

XW5895 53 5

OUT

SHORT-10L-0.25MM-SM 1 2

UART2_WLAN2SOC_TX

=PP1V8_S2R_VDDIO_WLAN_BT

1 NOSTUFF

XW5896 53 5

SHORT-10L-0.25MM-SM 1 2

UART2_SOC2WLAN_TX

R5805

UART2_SOC2WLAN_TX_R

10K

5% 1/32W MF 2 01005

XW5897 53 5

HSIC1_SOC2WLAN_HOST_RDY

SHORT-10L-0.25MM-SM 1 2

10UF

20% 2 6.3V CERM-X5R 0402-2

XW5894 SHORT-10L-0.25MM-SM 1 2

UART_BB2WLAN_LTE_COEX

HSIC1_SOC2WLAN_HOST_RDY_R

52 44

20% 2 6.3V CERM-X5R 0402-2

PMU_GPIO_CLK_32K_WLAN_R

PMU_GPIO_WLAN_REG_ON_R

PMU_GPIO_BT_REG_ON_R

10K

53 4

5% 1/32W MF 2 01005

53 4

BI BI

3 23

U5811

BAW-2436MHZ

R5830 1%

2.4-5.0GHZ SM LOW(2.4GHZ) 3

RF_G_0_DIPLEXER

0.00 2 1

RF_G_0_BAW_ANT

C5811

2.0NH+/-0.1NH-0.6A IN 1

OUT

RF_G_0_BAW_MOD

4 2

+/-0.05PF 2 25V CERM 201

CRITICAL

L5811

L5810

0201

8.2NH+/-3%-0.25A-0.7OHM

CRITICAL

1.0NH+/-0.1NH-0.75A

R5810

F-ST-SM

C5814

CRITICAL

MM4829-2702

RF_0_ANT 1

NOSTUFF 4

C5810 0.5PF

10NH-3%-250MA

J5810

C5817 0.2PF

+/-0.1PF 25V 2 COG-CERM 201

0.00 2 1% 1/20W MF 0201

RF_0_ANT_MATCH_T

RF_A_0_DIPLEXER

NOSTUFF 1

20% 2 6.3V CERM-X5R 0402-2

CLK_32K

C5800

C5801

4.7UF

20% 6.3V 2 X5R-CERM1 402

NOSTUFF

C5816

0.2PF

RF_A_0_MATCH

CRITICAL

0201

C5815

0.2PF

+/-0.1PF 25V 2 COG-CERM 201

51 50 55 56

UART_WLAN2BB_LTE_COEX_R UART_BB2WLAN_LTE_COEX_R PMU_GPIO_BT_HOST_WAKE GPIO_BT_WAKE

BT_UART_RXD BT_UART_TXD BT_UART_RTS* BT_UART_CTS*

37 38 36 39

UART1_SOC2BT_TX UART1_BT2SOC_TX UART1_BT2SOC_RTS_L UART1_SOC2BT_RTS_L

BT_PCM_CLK BT_PCM_SYNC BT_PCM_OUT BT_PCM_IN

41 42 43 44

I2S4_SOC2BT_BCLK I2S4_SOC2BT_LRCK I2S4_BT2SOC_DATA I2S4_SOC2BT_DATA

BT_GPIO5/LTE_COEX_UART_TX BT_GPIO4/LTE_COEX_UART_RX BT_GPIO1/HOSTWAKE BT_GPIO0/BTWAKE

44 44 48 52

OUT

5 53

U5800

WL_REG_ON

WIFI-BT-DOPPELBOCK BT_REG_ON

LGA

JTAG_SEL

HSIC_DATA HSIC_STROBE

SDIO_CLK NC 6 SDIO_CMD NC 8 SDIO_DATA0 NC 9 SDIO_DATA1 NC 10 SDIO_DATA2 NC 11 SDIO_DATA3 NC

CRITICAL

0201

GND

RF_G_0_MATCH_MOD

5 3 2

ANT(COMMON) 5

GND

HIGH(5.0GHZ) 1

CRITICAL

885061 LGA

1/20W MF 0201

CRITICAL

10UF

CRITICAL 4

HSIC1_WLAN_DATA HSIC1_WLAN_STB

13 14

U5810

C5882

JTAG_WLAN_SEL

R5800

CRITICAL

44 54

C5881

RF_VCC_FEM 70 RF_VCC_FEM 71

OUT

VBAT 16 VBAT 17

28 24

C5813 0.2PF

+/-0.1PF 2 25V COG-CERM 201

+/-0.05PF 2 25V COG-CERM 0201

GPIO0/WL_HOST_WAKE GPIO1/HOST_READY GPIO2/WL_TCK GPIO3/WL_TMS GPIO4/WL_TDI GPIO5/WL_TDO GPIO12/WL_TRST* GPIO9/AGG_CHANNEL GPIO10/HSIC_DEVICE_READY GPIO11/HSIC_RESUME GPIO15/WLAN_UART_TX GPIO14/WLAN_UART_RX GPIO6 GPIO7 GPIO8

RF_SW_CTRL11

I2SWS NC 46 I2SDO NC 48 I2SDI NC 49 I2SCLK NC 67 79

RF_A_0 RF_A_1

62 74

RF_G_0 RF_G_1

GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL

22 PMU_GPIO_WLAN_HOST_WAKE OUT HSIC1_SOC2WLAN_HOST_RDY_R 44 20 TP_JTAG_WLAN_TCK 27 52 28 JTAG_WLAN_TMS_TX_BLANK 26 JTAG_WLAN_TDI_OSCAR_A 24 JTAG_WLAN_TDO_OSCAR_B 25 TP_JTAG_WLAN_TRST_L 52 19 NC 1 HSIC1_WLAN2SOC_DEVICE_RDY 2 HSIC1_WLAN2SOC_REMOTE_WAKE 52 UART2_WLAN2SOC_TX_R 53 UART2_SOC2WLAN_TX_R 30 NC 29 WLAN_GPIO7 31

5 53

IN OUT

5 53

OUT

C R5804 1

WLAN_TX_BLANK

28 52

0% 1/32W MF 01005

48 53

R5801 1

0.00 2 OSCAR2RADIO_CONTEXT_A IN

19 28 52

0% 1/32W MF 01005

R5802 1 OUT

5 53

OUT

5 53

0.00 2 OSCAR2RADIO_CONTEXT_B IN

19 28 52

0% 1/32W MF 01005

44 44

=PP1V8_S2R_VDDIO_WLAN_BT

44 54

R5803

VIO 35

0.00 2

10K =PP1V8_S2R_VDDIO_WLAN_BT

44 54

DUMMY 57 NC

5% 1/32W MF 2 01005

5 12 15 18 21 32 34 40 45 54 58 59 60 61 63 64 65 66 68 69 72 73 75 76 78 80 81 82 83 84 85 86 87 88

52 48

CRITICAL CRITICAL

U5820

J5820 MM4829-2702

NOSTUFF 4

C5827 0.2PF

+/-0.1PF 25V 2 COG-CERM 201

0.00 2 1% 1/20W MF 0201

5 COM

RF_1_ANT_MATCH_T

NOSTUFF 1

CRITICAL

C5821

HI 1

1.1NH+/-0.1NH

LO 3

C5826 0.2PF

NOSTUFF

GND

+/-0.1PF 25V 2 COG-CERM 201

RF_G_1_DIPLEXER 1

RF_G_1_MATCH_MOD

CRITICAL

0201

C5822

0.2PF

6 4 2

RF_1_ANT 1 1

R5820

F-ST-SM

DPX205850DT-9038A1SJ

CRITICAL

C5820 0.5PF

+/-0.1PF 2 25V COG-CERM 201

+/-0.05PF 2 25V CERM 201

SYNC_MASTER=WIFI_DEV

SYNC_DATE=05/20/2013

PAGE TITLE

WIFI/BT: MODULE

CRITICAL

C5824

1.0NH+/-0.1NH-0.75A 1

RF_A_1_DIPLEXER

NOSTUFF 1

C5825 0.2PF

+/-0.1PF 2 25V COG-CERM 201

2 0201

DRAWING NUMBER

Apple Inc.

RF_A_1_MATCH CRITICAL 1

C5823 0.2PF

NOTICE OF PROPRIETARY PROPERTY:

+/-0.05PF 2 25V COG-CERM 0201

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

58 OF 121 SHEET

44 OF 54

XW7520 SM 46

BATT_SNS

NET_SPACING_TYPE=ANLG MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

54 45

=PPBATT_POS_CONN

TP7500 1

P/N 516S0906

CRITICAL

TP-P55

J7500

NOSTUFF

FL7500

CPB2304-0101F

240-OHM-0.2A-0.8-OHM

48 5

UART5_BATT_RTXD

13 F-ST-SM 9 10

BATT_SWI_CONN

0201-2

52 48 45

C7522

BATT_NTC NET_SPACING_TYPE=ANLG

C7523

33PF

5% 16V NP0-C0G 2 01005

C7524

1000PF 10% 16V X7R-CERM 2 0201

C7525

C7526

27PF

2 4 6 8

4.7PF

5% 16V NP0-C0G 2 01005

+/-0.1PF 16V NP0-C0G 2 01005

11 14

1 3 5 7

=PPBATT_POS_CONN 45 54 BATT_SWI_CONN 45 BATT_NTC 45 48 52

TP7501 1 A

TP-P55

NOSTUFF

TP7503 1

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TP-P55

NOSTUFF

TABLE_ALT_ITEM

155S0644

155S0823

RADAR:8391945

FL7500,L1702,L1800,L1920,L2602,L2700,L2701,L2702,L2800,L2960,L2961,L2962,L2963,L38014_RF

SYNC_MASTER=N/A

SYNC_DATE=N/A

PAGE TITLE

POWER: BATTERY CONNECTOR DRAWING NUMBER

Apple Inc.

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

75 OF 121 SHEET

45 OF 54

PLACEMENT_NOTE=PLACE NEAR L8225.1 PLACEMENT_NOTE=PLACE NEAR L8225.1

CRITICAL

C8190 1

C8140 1

C8141 1

20% 6.3V 2 TANT-POLY B1G-1

100UF

CRITICAL 1

100UF

ESR MAX=70MOHM

PPVCC_MAIN CRITICAL

C8150

C8151

10UF

20% 2 6.3V CERM-X5R 0402

CRITICAL

C8152

10UF

20% 2 6.3V CERM-X5R 0402

CRITICAL

C8153

10UF

20% 2 6.3V CERM-X5R 0402

CRITICAL

C8154

10UF

20% 2 6.3V CERM-X5R 0402

C8155

10UF

20% 2 6.3V CERM-X5R 0402

CRITICAL

C8156

10UF

20% 2 6.3V CERM-X5R 0402

CRITICAL 1

CRITICAL

C8157

C8158

10UF

20% 2 6.3V CERM-X5R 0402

CRITICAL 1

10UF

20% 2 6.3V CERM-X5R 0402

C8144

1.0UF

20% 2 6.3V CERM-X5R 0402

C8142 82PF

5% 2 25V CERM 0201

20% 2 6.3V X5R 0201-1

CRITICAL

C8143

L8100

18PF

1.0UH-3.51A-0.036OHM

5% 2 25V C0G-CERM 0201

CRITICAL 1

C8160 10UF

PLACE TWO 10UF CAP AT EACH VDD INPUT

10UF

20% 6.3V 2 CERM-X5R 0402

CRITICAL 1

C8161

10UF

20% 6.3V 2 CERM-X5R 0402

CRITICAL 1

C8162

10UF

20% 6.3V 2 CERM-X5R 0402

CRITICAL 1

C8163

10UF

20% 6.3V 2 CERM-X5R 0402

CRITICAL 1

C8164

C8165 10UF

20% 6.3V 2 CERM-X5R 0402

CRITICAL 1

C8166 10UF

20% 6.3V 2 CERM-X5R 0402

CRITICAL 1

C8167 10UF

C8168 10UF

20% 6.3V 2 CERM-X5R 0402

CRITICAL 1

C8169 10UF

C8170 10UF

20% 6.3V 2 CERM-X5R 0402

CRITICAL 1

C8171 10UF

20% 6.3V 2 CERM-X5R 0402

L8101

BUCK0_LX1

10UF

MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.20MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=0.5 MM

20% 6.3V 2 CERM-X5R 0402

DIDT=TRUE

L8112

L8102

NOSTUFF

R8170

46 11

4.7K 2 1

OVP_SW_EN_L

SW_CHGA CRITICAL K

PIME061D-SM 2

DCR=54MOHM MAX

SOD-123W

5% 1/20W MF 201

Q8104

PLACE_NEAR=U8100.R17:2MM

FDMC6683

R8172

MLP3.3X3.3

BATT_SNS

BATT_SNS_R

PLACE_NEAR=U8100.R17:10MM

5% 1/20W MF 201

D RDSON=0.0136@VGS=-2.5V 5 ID=12.0A

1 PLACE_NEAR=U8100.R17:10MM

NOSTUFF 1

R8173

C8149

499

0.022UF

LAYOUT NOTE R8172- PLACE NEAR PMU C8149- PLACE NEAR PMU R8173- PLACE NEAR PMU

1% 1/20W MF 2 201

10% 25V 2 X7R 0402

PPBATT_VCC

54 52 46

ACT_DIO MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM NET_SPACING_TYPE=ANLG

MOSFET CHANNEL

FDMC6676BZ

USB_VBUS_DETECT

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM VOLTAGE=6.0V

P-TYPE

RDS(ON)

27 MOHM @-4.5V

IMAX

6.9 A

VGS MAX

+/- 25V

PLACE_NEAR=U8100.F18:2MM

4.7UF

3 2 1

NOSTUFF

R81161

CRITICAL

Q8123

470K

4.7UF

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM VOLTAGE=6.0V

DZ8120 BZT52C10LP LLP

FDMC6676BZ MLP3.3X3.3

G 4

C8147

10% 35V 2 X5R-CERM 0603

LAYOUT NOTE: PLACE RIGHT AT THE PIN

PLACE_NEAR=U8100.F16:10MM

CRITICAL

C8145

2.2UF

10% 25V X5R-CERM 2 603

NOTE: 10V ZENER

VBUS_PROT_G 1

54 52

R8130

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=ANLG

LAYOUT NOTE: PLACE RIGHT AT THE PIN

220K

1% 1/20W MF 201 2

PPVBUS_USB_DCIN

46 11

USB REVERSE VOLTAGE PROTECTION

R17 P17

VBAT IBAT_S

M19 N19 P19 R19

IBAT0 IBAT1 IBAT2 IBAT3

N17

ACT_DIO

F18 F19 G18 H18 J18 K18 L18 L19

4.7K 2 5% 1/20W MF 201

C8146

10% 25V 2 X5R-CERM 0201

=PPVCC_MAIN_CPU

54 46

=PPVCC_MAIN_GPU

54 46

VDD_BUCK0_23

V2 V3 54 46

U8 V8

=PPVCC_MAIN_SOC

54 52 49 48 47 46

A4 B4

PPVCC_MAIN

=PPVCC_MAIN_CPU CRITICAL 1

C8175 10UF

20% 2 6.3V CERM-X5R 0402

CRITICAL 1

C8176 10UF

20% 2 6.3V CERM-X5R 0402

CRITICAL 1

C8177 10UF

20% 2 6.3V CERM-X5R 0402

CRITICAL 1

C8178 10UF

20% 2 6.3V CERM-X5R 0402

CRITICAL

C8179

10UF

20% 2 6.3V CERM-X5R 0402

CRITICAL 1

C8180 10UF

20% 2 6.3V CERM-X5R 0402

A8 B8

CRITICAL 1

C8181

U4 V4

10UF

20% 2 6.3V CERM-X5R 0402

=PPVCC_MAIN_GPU

DIDT=TRUE

VDD_BUCK3

VDD_BUCK4

VDD_BUCK5

C8182 10UF

20% 6.3V 2 CERM-X5R 0402

CRITICAL 1

C8183 10UF

20% 6.3V 2 CERM-X5R 0402

CRITICAL 1

C8184 10UF

20% 6.3V 2 CERM-X5R 0402

CRITICAL 1

C8185 10UF

20% 6.3V 2 CERM-X5R 0402

CRITICAL 1

C8186

20% 6.3V 2 CERM-X5R 0402

P18 R18

54 46

=PPVCC_MAIN_SOC

54 52 46

CRITICAL 1

C8187 10UF

20% 6.3V 2 CERM-X5R 0402

CRITICAL

DIDT=TRUE

C8188

10UF

C8193 10UF

20% 6.3V 2 CERM-X5R 0402

BUCK1_LX2

R8100 0.5

SWITCH_NODE=TRUE

15UF 20% 2 4V X5R 0402

15UF

20% 4V 2 X5R 0402

C8121 15UF

XW8103

SWITCH_NODE=TRUE

CRITICAL

CRITICAL 1

C8122

C8124 15UF

XW8104

SWITCH_NODE=TRUE

20% 2 4V X5R 0402

CRITICAL

CRITICAL 1

C8125

MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.20MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=0.5 MM

ADDITIONAL DISTRIBUTED 27UF (NO DERATING)

PP1V2_S2R CRITICAL 1

C8127 15UF

XW8105

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.20MM

20% 4V 2 X5R 0402

2 PILE25201D

BUCK4_FB

CRITICAL

CRITICAL 1

C8128

CRITICAL 1

C8130 15UF

XW8106

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.20MM

CRITICAL

CRITICAL 1

C8131

MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.20MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=0.5 MM

PP3V3_S2R CRITICAL

PILE25201D 1 1

C81A0 10UF

XW8107

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.20MM

20% 6.3V 2 CERM-X5R 0402

2 SM

PP1V8_S2R PP1V8_SW1 PP1V8_SW2 PP1V8_S2R_SW3

PP1V2_S2R PP1V2_SW1 PP1V2_S2R_SW2 1

C8136 1UF

10% 6.3V 2 CERM 402

C8137 1.0UF

20% 6.3V 2 X5R 0201-1

C81A8 1.0UF

20% 6.3V 2 X5R 0201-1

C8138 1.0UF

20% 6.3V 2 X5R 0201-1

C8139 1UF

10% 6.3V 2 CERM 402

CRITICAL 1

C81A1 10UF

20% 6.3V 2 CERM-X5R 0402

CRITICAL 1

10UF

C81A3 10UF

20% 6.3V 2 CERM-X5R 0402

50 52 54

CRITICAL

52 54

C81A4 10UF

CRITICAL 1

C81A5 10UF

20% 6.3V 2 CERM-X5R 0402

CRITICAL 1

C81A6

CRITICAL 1

10UF

C81A7 10UF

20% 6.3V 2 CERM-X5R 0402

46 47 52 54 52 54 52 54

SYNC_MASTER=J72_MLB_C

SYNC_DATE=11/26/2012

PAGE TITLE

PMU: ANYA PAGE 1

C81A9

DRAWING NUMBER

1.0UF

20% 6.3V 2 X5R 0201-1

Apple Inc.

051-0886

SIZE

REVISION

NOTICE OF PROPRIETARY PROPERTY: C8137 0201 OKAY IF GRAPE HAS EXT FET

52 54

CRITICAL 1

C81A2

46 47 52 54

20% 6.3V 2 CERM-X5R 0402

PMU_VPUMP

20% 4V 2 X5R 0402

ADDITIONAL DISTRIBUTED 32UF (NO DERATING)

2.2UH-2.35A-0.073OHM 1

C8132 15UF

20% 4V 2 X5R 0402

L8111

52 54

CRITICAL 1

15UF

20% 4V 2 X5R 0402

2 SM

BUCK6_LX0

PPVDD_SRAM

PILE20161D-SM

BUCK5_FB

20% 4V 2 X5R 0402

ADDITIONAL DISTRIBUTED 64UF (NO DERATING)

1.0UH-3.33A-66MOHM MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.20MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=0.5 MM

C8129 15UF

20% 4V 2 X5R 0402

L8110

46 47 52 54

CRITICAL 1

15UF

20% 4V 2 X5R 0402

2 SM

BUCK5_LX0

C8126 15UF

20% 4V 2 X5R 0402

L8109

46 47 52 54

CRITICAL 1

15UF

20% 4V 2 X5R 0402

2 SM

BUCK4_LX0

52 54

C8123

PP1V8_S2R CRITICAL

1.0UH-3.51A-0.036OHM

20% 6.3V 2 X5R 0201-1

ADDITIONAL DISTRIBUTED 64UF (NO DERATING)

MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.20MM

1.0UF

15UF

20% 4V 2 X5R 0402

15UF

20% 2 4V X5R 0402

2 PILE25201D

BUCK3_FB

C8135

C8120

CRITICAL 1

15UF

20% 2 4V X5R 0402

2 SM

MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.20MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=0.5 MM

15UF 20% 2 4V X5R 0402

CRITICAL 1

PPVDD_SOC CRITICAL 1

BUCK3_LX0

20% 6.3V 2 X5R 0201

C8116

ADDITIONAL DISTRIBUTED 27UF (NO DERATING)

L8108

0.22UF

C8119 15UF

1.0UH-3.51A-0.036OHM

C8196

15UF 20% 2 4V X5R 0402

CRITICAL 1

C8118

2 PILE25201D

MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.20MM

BUCK2_FB

DIDT=TRUE

52 54

CRITICAL

C8115

CRITICAL

MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.20MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=0.5 MM

DIDT=TRUE

CRITICAL 1

BUCK2_LX0

DIDT=TRUE

C8114

CRITICAL 1

L8107

DIDT=TRUE

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM VOLTAGE=4.7V

C8117

1.0UH-3.51A-0.036OHM

VPUMP A11

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM VOLTAGE=4.6V

C8113 15UF

20% 4V 2 X5R 0402

XW8102 1

MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.20MM

DIDT=TRUE

CRITICAL 1

20% 2 4V X5R 0402

15UF

PILE25201D

BUCK1_FB

B10 B11 C11 A9 B9 C9 BUCK4_SW1 C10 BUCK4_SW2 A10

1% 1/16W MF 402 2

20% 4V 2 X5R 0402

C8111

CRITICAL 1

MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.20MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=0.5 MM

C1 C2 F6 A1 A2 A3

PPBATT_POS_RC 1

20% 4V 2 X5R 0402

L8106

VCC_MAIN

C8194

15UF

PILE25201D

BUCK6_FB

10UF

C8109

CRITICAL

SWITCH_NODE=TRUE

1.0UH-3.51A-0.036OHM

DIDT=TRUE

C8112

20% 2 4V X5R 0402

MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.20MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=0.5 MM

VDD_BUCK6

CRITICAL

15UF

20% 4V 2 X5R 0402

15UF

L8105

PPBATT_VCC

CRITICAL

C8108

PPVDD_GPU

NOTE: FOR NO BATTERY SITUATION

20% 4V 2 X5R 0402

CRITICAL 1

CRITICAL

SWITCH_NODE=TRUE

M18 N18

10UF

15UF

2 PILE25201D

BUCK1_LX1

T16 VCC_MAIN_S

CRITICAL 1

C8107

15UF

20% 4V 2 X5R 0402

1.0UH-3.51A-0.036OHM

VBUCK4

B1 B2 B3

54 46

VDD_BUCK2

CRITICAL

MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.20MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=0.5 MM

B13 B14 VBUCK3 C14 A12 B12 C12 BUCK3_SW1 C13 BUCK3_SW2 A13 BUCK3_SW3 A14

VDD_BUCK1_2

15UF 20% 2 4V X5R 0402

L8104

U7 V7 BUCK2_LX0 BUCK2_FB P7

BUCK6_FB BUCK6_BYP0 BUCK6_BYP1 BUCK6_BYP2

VDD_BUCK1_01

C8104

1.0UH-3.51A-0.036OHM

N1 N2 BUCK1_LX0 R1 R2 BUCK1_LX1 U1 U2 BUCK1_LX2 BUCK1_FB M6

BUCK6_LX0

C8110 15UF

BUCK1_LX0

U5 V5 BUCK5_FB P6

VDD_BUCK0_01

P1 P2 V1

BUCK5_LX0

F1 F2 K1

15UF 20% 2 4V X5R 0402

CRITICAL

C8106

20% 4V 2 X5R 0402

CRITICAL 1

XW8101

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.20MM

A7 B7 BUCK4_LX0 BUCK4_FB E7

VBUS

2 PILE25201D

BUCK0_FB

A5 B5 BUCK3_FB E6

D17 HV_CHG_DIS

TP_HV_CHG_EN

0.01UF

BUCK3_LX0

C16 VBUS_OVP_OFF

OVP_SW_EN_L_R NOSTUFF 52

LAYOUT NOTE: R8146, C8146 CAN BE ANYWHERE BET.TRISTAR AND PMU

54 46

VCENTER

DIDT=TRUE

E1 E2 BUCK0_LX0 G1 G2 BUCK0_LX1 J1 J2 BUCK0_LX2 L1 L2 BUCK0_LX3 BUCK0_FB H6

L17

R8146 OVP_SW_EN_L

CHG_LX0 CHG_LX1 CHG_LX2 CHG_LX3

F16 F17 G16 G17 H16 H17 J17 K16 K17 L16

PPVBUS_PROT

CRITICAL

C8148

MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.20MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM VOLTAGE=6.0V

PLACE_NEAR=U8100.L18:2MM

CRITICAL

10% 35V 2 X5R-CERM 0603 52 11

1% 1/20W MF 201

PMU_VCENTER

XW8114

SHORT-0201 2 1

G19 H19 J19 K19

L8103

CRITICAL 1

15UF

20% 4V 2 X5R 0402

PILE25201D

MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.20MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=0.5 MM

SYM 1 OF 4

PMEG4030ER

CRITICAL

D8100

20% 2 4V X5R 0402

52 54

CRITICAL

C8103

1.0UH-3.51A-0.036OHM

FCBGA

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.20 MM NET_SPACING_TYPE=PWR DIDT=TRUE SWITCH_NODE=TRUE

USB/BAT BUCK

PPVCC_MAIN

C8105 15UF

CRITICAL

BUCK0_LX3

D2089A0

VCC-MAIN SWITCHED POWER

54 52 49 48 47 46

CRITICAL 1

15UF

20% 2 4V X5R 0402

CRITICAL

SWITCH_NODE=TRUE

U8100

2.2UH-20%-5.5A-0.054OHM

C8102

PILE25201D

MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.20MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=0.5 MM DIDT=TRUE

CRITICAL

C8101

CRITICAL

SWITCH_NODE=TRUE

OMIT_TABLE

CRITICAL 1

15UF

20% 2 4V X5R 0402

1.0UH-3.51A-0.036OHM

CRITICAL

C8100 15UF

1.0UH-3.51A-0.036OHM

C8172

BUCK0_LX2

CRITICAL

PILE25201D

CRITICAL

SWITCH_NODE=TRUE

CRITICAL 1

PPVDD_CPU

MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.20MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=0.5 MM DIDT=TRUE

BUCK0_LX0

ESR MAX=70MOHM

CRITICAL

VCC_MAIN BYPASS

CRITICAL

C8159

46 47 48 49 52 54

A.0.0 BRANCH

PAGE

81 OF 121 SHEET

46 OF 54

OMIT_TABLE

LDO INPUTS C8203

1UF

10% 6.3V 2 CERM 402

54 52 49 48 47 46

PPVCC_MAIN

54 52 49 48 47 46

PPVCC_MAIN

PP1V2_S2R 1

C8201 1UF

10% 6.3V 2 CERM 402

CRITICAL

L8225

D8228

4.7UH-3.2A 54

=PPVCC_MAIN_LED

C8226

WLED_LX_A MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.20 MM

PMEG4010BEA

NET_SPACING_TYPE=PWR DIDT=TRUE SWITCH_NODE=TRUE

(PPLED_OUT_A)

2 A

R8227

PIME051E-SM

CRITICAL

SOD-323

10UF

20% 6.3V CERM-X5R 2 0402

LED_IO_1_A

LED_IO_2_A

1.00

CRITICAL 1

C8250 4.7UF

10% 35V 2 X5R-CERM 0603

CRITICAL 1

C8251 4.7UF

10% 35V 2 X5R-CERM 0603

CRITICAL 1

C8252 4.7UF

10% 35V 2 X5R-CERM 0603

CRITICAL 1

C8253 4.7UF

10% 35V 2 X5R-CERM 0603

CRITICAL 1

C8254 4.7UF

10% 35V 2 X5R-CERM 0603

C8259

LED_IO_3_A

56PF 2% 50V 2 NP0-C0G-CERM 0201

LED_IO_4_A

1.00

LED_IO_6_A

1.00

LED_IO1_A_R LED_IO2_A_R LED_IO3_A_R LED_IO4_A_R LED_IO5_A_R LED_IO6_A_R

NC_WLED_LXB0

NC_WLED_LXB1 NC_VOUT_WLED_B NC_WLED1_B NC_WLED2_B NC_WLED3_B

R8239

R8240 18

1% 1/32W MF 01005

1.00

1% 1/32W MF 01005

LED_IO_5_A

R8232 1

R8235 18

1% 1/32W MF 01005

PPLED_OUT_A

1.00 1% 1/32W MF 01005

R8231 18

54 52

PPVCC_MAIN

54 52 49 48 47 46

1.00

NC_WLED4_B

NC_WLED5_B

1% 1/32W MF 01005

NC_WLED6_B

T18 B16 U9 U10 U14 U15 B15 B17 U16 T17

VDD_LDO1_3_4 VDD_LDO2 VDD_LDO5 VDD_LDO6 VDD_LDO7 VDD_LDO8 VDD_LDO9 VDD_LDO10 VDD_LDO11 VDD_LDO13

C18 C19 D16 E14 F14 G14 H14 J14 J16

WLED_LXA0 WLED_LXA1 VOUT_WLED_A WLED1_A WLED2_A WLED3_A WLED4_A WLED5_A WLED6_A

E18 E19 E16 K14 L14 M14 M16 N14 P14

WLED_LXB0 WLED_LXB1 VOUT_WLED_B WLED1_B WLED2_B WLED3_B WLED4_B WLED5_B WLED6_B

LDO INPUT LDO

LCM/GRAPE

C8200

LCD BACKLIGHT

CRITICAL

LDO OUTPUTS

FCBGA

SYM 2 OF 4

1 CAP PER PIN

54 52 46

U8100

D2089A0

PP1V8_S2R

VLDO1 VLDO2 VLDO3 VLDO4 VLDO5 VLDO6 VLDO7 VLDO8 VLDO9 VLDO10 VLDO11 VLDO13 ON_BUF VDD_LCM_SW VDD_BOOST_LCM BOOST_LCM_LX LCM_FB VDD_LCM VLCM1 VLCM2 LCM2_EN VLCM3

U19 A16 U18 T19 V9 V10 V14 V15 A15 A17 V16 U17 T10

(50MA; 2.5-3.3V) (100MA; 1.65-1.805V; BUCK3) (50MA; 2.5-3.3V) (50MA; 2.5-3.3V) (1000MA; 2.5-3.6V) (150MA; 2.5-3.6V) (300MA; 1.7-3.0V) (300MA; 1.7-3.0V) (300MA; 1.2-3.0V) (150MA; 0.6-1.3V) (300MA; 1.7-3.0V) (300MA; 1.7-3.0V) (5MA; 1.8V; ON_BUFF)

PP3V0_SPARE1 PP1V7_VA_VCP PP3V0_S2R_SENSOR PP3V0_ALS PP3V0_UVLO

47 52 54 16 47 52 54 47 52 54 47 52 54 47 52 54

PP3V3_ACC PP3V0_S2R_TRISTAR NC_LDO8 PP1V3_CAM PP1V0_SOC PP2V6_CAM_AF PP2V9_CAM PP1V8_ALWAYS

47 52 54 47 52 54 54 47 52 54

CRITICAL

47 52 54 54 47 52 47 52 54

L8229

47 52 54

10UF

20% 25V 2 X5R-CERM 0603

PMU_XTAL PMU_EXTAL

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR DIDT=TRUE

2.2UH-1.05A-0.195OHM

C17 =PPVCC_MAIN_VDD_LCM 54 A18 PP6V0_LCM_HI (NOTE: 2MHZ) B19 LCM_LX C15 U11 52 PP6V0_LCM_VBOOST V11 (100MA; 5.0-6.0V) PP5V25_GRAPE 54 V12 (100MA; 5.0-6.0V) NO_TEST=TRUE NC_VLCM2 E8 NC_LCM2_EN 1 C8212 1 U12 (5MA; 5.0-6.0V) NO_TEST=TRUE NC_VLCM3

XTAL1 V18 XTAL2 V17

XTAL

54 52 46

CRITICAL

MAKE_BASE=TRUE VLS201612E-SM VOLTAGE=6.0V MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM

D8230 PMEG2005AEL A

MAKE_BASE=TRUE VOLTAGE=6.0V MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM

SOD882

CRITICAL

C8211 4.7UF

20% 10V 2 X5R-CERM 0402

C8210 2.2UF

20% 10V 2 X5R-CERM 402

CRITICAL

C8290 4.7UF

20% 10V 2 X5R-CERM 0402

CRITICAL

1% 1/32W MF 01005

Y8200 32.768K-20PPM-12.5PF 2

CRITICAL

C8215

CRITICAL 1

2012-1

18PF

C8216 18PF

5% 25V C0G-CERM 2 0201

5% 2 25V C0G-CERM 0201 TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR PART NUMBER

197S0399

197S0392

BOM OPTION

REF DES

COMMENTS:

Y8200

RDAR://PROBLEM/9936684

TABLE_ALT_ITEM

C8280 56PF

5% 25V 2 NP0-C0G-CERM 0201

C8281 56PF

5% 25V 2 NP0-C0G-CERM 0201

C8282 56PF

5% 25V 2 NP0-C0G-CERM 0201

C8283 56PF

5% 25V 2 NP0-C0G-CERM 0201

C8284 56PF

5% 25V 2 NP0-C0G-CERM 0201

LDO BYPASS

C8285 56PF

5% 25V 2 NP0-C0G-CERM 0201

54 52 47

PP3V0_SPARE1 PP1V7_VA_VCP PP3V0_S2R_TRISTAR PP3V0_ALS PP3V0_UVLO PP3V3_ACC

54 52 47

PP3V0_S2R_SENSOR

54 52 47 54 52 47 16 54 52 47 54 52 47 54 52 47

CRITICAL

C8237

C8235

C8234

C8233

C8232

C8231

C8230

2.2UF 10% 6.3V 2 X5R 402

54 52 47 54 52 47 54 52 47 54 52 47 54 52 47

4.7UF

10UF

20% 6.3V 2 X5R 402

20% 6.3V CERM-X5R 2 0402

CRITICAL

2.2UF

10UF

10% 6.3V 2 X5R 402

20% 6.3V CERM-X5R 2 0402

CRITICAL

C8240

C8239

C8238

10UF

20% 6.3V CERM-X5R 2 0402

2.2UF

10% 6.3V 2 X5R 402

PP1V3_CAM PP1V0_SOC PP2V6_CAM_AF PP2V9_CAM PP1V8_ALWAYS

C8242 0.22UF

20% 6.3V 2 X5R 0201

C8241 10UF

20% 6.3V CERM-X5R 2 0402

10UF

20% 6.3V CERM-X5R 2 0402

4.7UF

20% 6.3V X5R-CERM1 2 402

4.7UF

20% 6.3V X5R-CERM1 2 402

SYNC_MASTER=J85 MLB_C

SYNC_DATE=12/03/2012

PAGE TITLE

PMU: ANYA PAGE 2 DRAWING NUMBER

Apple Inc.

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

82 OF 121 SHEET

47 OF 54

1 TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR PART NUMBER

138S0739

138S0706

REVIEW: VERIFY NC ON TDEV2 IS OK

BOM OPTION

REF DES

COMMENTS: TABLE_ALT_ITEM

C8308

R8303

I2C ADDRESS: 0111100X (0X78)

C8305

200K

0.1UF

1% 1/20W MF 2 201

C8306

10% 6.3V 2 CERM-X5R 0201

OMIT_TABLE

U8100

D2089A0

FCBGA

SYM 3 OF 4 13 5

17 5

R8399 11

PMU_USB_BRICKID

0.00 2

1% 1/20W MF 0201 5

CRITICAL

R8327

C8327 100PF

5% 16V 2 NP0-C0G 01005

10KOHM-1%-0.31MA 0201 PLACE_NEAR=U4000.1:10MM

PA_NTC_P

PA_NTC_N

11 5

PLACE_SIDE=TOP

(TEMP1 - NEAR BB)

IN IN IN

R12 P16 N16 R11

PMU_ACC_ID PMU_USB_BRICKID_R ADC_IN7

T8 GPIO_SOC2PMU_KEEPACT (INTERNAL PULL-DOWN) T9 PMU_SHDWN

(INTERNAL PULL-DOWN) R5 WDOG_SOC2PMU_RESET_IN R6 TS2PMU_RESET_IN R7 SOCHOT1_L R8 RESET_SOC_L 52 24 11 10 8 4 OUT T15 (PULLUP INSIDE SOC) GPIO_PMU2SOC_IRQ_L 5 OUT

52 11 5

52 5

53 5

1 PLACE_NEAR=U8100.R13:10MM

CRITICAL

R8321

BOARD_TEMP3_P

PLACE XW AND CAP CLOSE TO PMU PLACE_NEAR=U8100.R9:10MM

5% 16V 2 NP0-C0G 01005

0201 PLACE_NEAR=U5800.30:10MM

C8321 100PF

10KOHM-1%-0.31MA

IN IN

PLACE_NEAR=U8100.R9:10MM

D5 D6 D7 D8 NC_ANYA_BUTTON4 PMU_E75_ACC_DET_L T7

GPIO_BTN_HOME_L GPIO_BTN_ONOFF_L GPIO_BTN_SRL_L

BOARD_TEMP3_N

XW8327 1

E12 E13

DWI_AP_CLK DWI_AP_DO NC_DWI_AP_DI

(INTERNAL PULL-DOWN) E11 (INTERNAL PULL-DOWN) E10 E9 NO_TEST=TRUE

2 NET_SPACING_TYPE=BOARD_TEMP

PLACE_SIDE=TOP

I2C0_SCL_1V8 I2C0_SDA_1V8

(TEMP3 - TOP SIDE NEAR WIFI)

NET_SPACING_TYPE=BOARD_TEMP PLACE_NEAR=U8100.R13:10MM

NET_SPACING_TYPE=BOARD_TEMP

XW8321 1

CRITICAL

R8322

NET_SPACING_TYPE=BOARD_TEMP

BOARD_TEMP4_P

100PF

NET_SPACING_TYPE=BOARD_TEMP PLACE_NEAR=U8100.R14:10MM

XW8322

5% 16V 2 NP0-C0G 01005

0201 PLACE_NEAR=UJ000.8:10MM

C8322

NET_SPACING_TYPE=BOARD_TEMP

PLACE_NEAR=U8100.R14:10MM

10KOHM-1%-0.31MA

BOARD_TEMP4_N

NET_SPACING_TYPE=BOARD_TEMP

2 52 45

BATT_NTC

PMU_TCALNET_SPACING_TYPE=ANLG

PLACE_SIDE=TOP

NET_SPACING_TYPE=ANLG

PLACE_NEAR=U8100.L4:10MM

(TEMP4 - TOP SIDE NEAR SIM)

XW8323 1

C8340

CRITICAL

R8323

PLACE_SIDE=TOP

BOARD_TEMP5_P

KEEPACT SHDN RESET_IN1 RESET_IN2 RESET_IN3 RESET* IRQ* SCL SDA DWI_CK DWI_DI DWI_DO TDEV1 TDEV2 TDEV3 TDEV4 TDEV5 TDEV6 TDEV7 TDEV8 TBAT TCAL

T12 V13 M17 T11 U13 T13

PMU_IREF PMU_VREF PMU_VDD_REF NET_SPACING_TYPE=ANLG NET_SPACING_TYPE=ANLG NET_SPACING_TYPE=ANLG

R8340

1UF

10% 2 6.3V CERM-X5R 0201

PLACE_NEAR=U8100.M17:4MM

C8308 1.0UF

10% 2 10V X5R 402-1

20% 10V 2 X5R-CERM 0201-1

PMU_VDD_RTC PMU_ADC_REF

NET_SPACING_TYPE=ANLG

OUT_32K T14

CRITICAL

0.1UF

C8307

NET_SPACING_TYPE=ANLG MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM

NC_PMU_OUT_32K_CLK_GPS

C8310 1000PF

GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17

T6 T5 T4 R3 P3 N3 M3 L3 K3 J3 H3 G3 F3 E3 D3 C3 C4

PMU_GPIO_CLK_32K_OSCAR PMU_GPIO_CLK_32K_WLAN PMU_GPIO_BT_REG_ON PMU_GPIO_WLAN_REG_ON PMU_GPIO_PMU2BBPMU_RST_R_L UART5_BATT_RTXD PMU_GPIO_BT_HOST_WAKE PMU_GPIO_WLAN_HOST_WAKE PMU_GPIO_BB2PMU_HOST_WAKE PMU_GPIO_CODEC_HS_INT_L PMU_GPIO_MB_HALL1_IRQ GPIO_TS2SOC2PMU_INT PMU_GPIO_MB_HALL2_IRQ PMU_GPIO_MB_HALL3_IRQ PMU_GPIO_CODEC_RST_L PMU_GPIO_OSCAR2PMU_HOST_WAKE PMU_GPIO_BB_VBUS_DET

AMUX_A0 AMUX_A1 AMUX_A2 AMUX_A3 AMUX_AY AMUX_B0 AMUX_B1 AMUX_B2 AMUX_B3 AMUX_BY

E4 F4 G6 J6 G4 K4

NC_PPVDD_CPU_SOC_SENSE NC_PPVDD_GPU_SOC_SENSE

OUT

19 52

OUT

44 52

OUT

44 52

OUT

44 52

10% 6.3V 2 X5R-CERM 01005

R8330 1.00K2

PMU_GPIO_PMU2BBPMU_RST_L

1 5 45

44 52

44 53

24 28 52

5 11

IN OUT

24 26 52

15 52

OUT

5% 1/32W MF 01005

NOTE:

NEW ON J85

15 5 19

24 27 52

NC_PPVDD_SOC_SOC_SENSE NC_ADC_SMPS1_MSMC_1V05 NC_AMUX_AY

NC_PPVDD_CPU_RAIL_SENSE NC_PPVDD_GPU_RAIL_SENSE

J4 K6 L6 H4

NC_PPVDD_SOC_RAIL_SENSE NC_ADC_SMPS3_MSME_1V8 NC_AMUX_BY

0201 1/20W MF

PLACE_NEAR=U8100.M4:10MM

100PF

0201 PLACE_NEAR=U1600.A1:10MM

C8323

XW8324

5% 16V 2 NP0-C0G 01005

10KOHM-1%-0.31MA

ACC_ID BRICK_ID ADC_IN7 ADC_IN31

IREF VREF VDD_REF VDD_REF_A VDD_RTC ADC_REF

3.92K 0.1%

5% 16V NP0-C0G 2 01005

PLACE_NEAR=U8100.L4:10MM

100PF

2 SM

R9 R10 R13 R14 L4 M4 N4 P4 R16 R15

BUTTON1 BUTTON2 BUTTON3 BUTTON4 ACC_DET

ANALOG MUX

0.01UF

DIGITAL ANALOG INPUT INPUT 32K REFRENCES CLK

C8302

10% 2 6.3V X5R 01005

WDOG

0.01UF

RESET

C8301

10% 2 6.3V X5R 01005

PLACE_NEAR=U8100.T11:3MM

GPIO

0.01UF

I2C & DWI

C8300

10% 2 6.3V X5R 01005

TEMPERATURE

BOARD_TEMP5_N

RESISTOR FOR TEMP CALIBRATION

2 SM

2 PLACE_NEAR=U8100.N4:10MM

(TEMP5 - TOP SIDE NEAR NAND)

XW8325 1

2 SM

1 PLACE_NEAR=U8100.M4:10MM

CRITICAL

R8324

PLACE_NEAR=U8100.P4:10MM

100PF 5% 16V 2 NP0-C0G 01005

10KOHM-1%-0.31MA

C8324

0201 PLACE_NEAR=J2800.1:10MM

BOARD_TEMP6_P BOARD_TEMP6_N

XW8326 1

2 SM

PLACE_SIDE=TOP

(TEMP6 TOP SIDE NEAR REAR CAM)

1 PLACE_NEAR=U8100.N4:10MM

CRITICAL

R8325

0201 PLACE_NEAR=U0600.W19:10MM

PLACE_SIDE=BOTTOM

C8325

BOARD_TEMP7_P BOARD_TEMP7_N

100PF

10KOHM-1%-0.31MA

5% 16V 2 NP0-C0G 01005

(TEMP7 - BOTTOM SIDE NEAR SOC) BUCK6 POWER IS ON IN HIBERNATE DUE TO WIFI PAS SWITCH NEEDED TO GATE POWER TO NAND AND SOC REVIEW: CHECK FOR POWER SEQUENCING VOILATIONS BETWEEN PP1V8 AND PP3V3

1 PLACE_NEAR=U8100.P4:10MM

CRITICAL

R8326

BOARD_TEMP8_P

100PF

0201 PLACE_NEAR=U8100.K9:10MM

PLACE_SIDE=BOTTOM

C8326

5% 16V 2 NP0-C0G 01005

10KOHM-1%-0.31MA

BOARD_TEMP8_N

54 52 49 47 46

=PP3V3_S2R_SWITCH 1

PPVCC_MAIN 1

C8350

10% 16V 2 X5R-CERM 0201

2 6.3V X5R

0201-1

U8350 SLG5AP1443V

VCC_MAIN_PP3V3SW_RAMP 7 54 12

20%

CRITICAL

VDD

0.1UF

C8355 1.0UF

(TEMP8 - BOTTOM SIDE NEAR PMU)

=PP1V8_NAND

CAP

TDFN

PP3V3_SW

52 54

SYNC_MASTER=J72_MLB_C

SYNC_DATE=11/26/2012

R8352 100K

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR PART NUMBER

BOM OPTION

REF DES

COMMENTS: 2 RDAR://PROBLEM/8380367

107S0150

107S0208

R8321,R8322,R8323,R8324,R8325,R8326

118S0764

118S0717

R8340

RDAR://PROBLEM/8380367

TABLE_ALT_ITEM

5% 1/32W MF 01005

CRITICAL

GND

C8352

PAGE TITLE 1

PMU: ANYA PAGE 3

CRITICAL

C8356

DRAWING NUMBER

10UF

4700PF

20% 10V 2 X5R-CERM 0402-2

10% 10V 2 X7R 201

Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY:

TABLE_ALT_ITEM

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

83 OF 121 SHEET

48 OF 54

OMIT_TABLE

U8100 D2089A0 FCBGA SYM 4 OF 4 M1 M2

VSS_BUCK01

T1 T2

VSS_BUCK1_12

H1 H2

VSS_BUCK0_12

U6 V6

VSS_BUCK25

A6 B6

VSS_BUCK34

D1 D2

VSS_BUCK06

D18 VSS_WLED D19 B18 VSS_LCM A19 D15 V19 D4 C5 C6 C7 C8 D9 D10 D11 D12 D13 D14 E17 F7 F8 F9 F10 F11 F12 F13 G7 G8 G9 G10 G11 G12 G13 H7 H8 H9

THROTTLER

XW8410 54 52 48 47 46

PPVCC_MAIN

SHORT-10L-0.1MM-SM 1 2

VCC_MAIN_UVLO_SENSE

R84511 4.7K 1% 1/32W MF 01005 2

NOSTUFF 1

R8450

=PP3V0_SPARE1

150K 1% 1/32W MF 01005 2

MAIN_UVLO_SENSE_R

0.1UF

20% 6.3V 2 X5R-CERM 01005

R84101 75K 1% 1/32W MF 01005 2

NOSTUFF

R8420 150K 2

UVLO_COMP_NEG B2

1% 1/32W MF 01005

NOSTUFF 1

C8460 R8411

100PF

5% 6.3V 2 CERM 01005

50K

MAX9039BEBT+ UCSP

VCC

U8400

UVLO_COMP_REF

1.00K2

SOCHOT0_L

OUT

5 52

Q8440

DMN2990UFA DFN0806-VML0806-COMBO-N78

R8435 100K

UVLO_COMP_REF

0.00 2

ADD A VIA PER PIN FOR ALL VSS_* AND VSSA_* PINS

B3 A1

1% 1/32W MF 01005 2

THROTTLER_OUT

R8425 49

APN 353S4103 A2

VSS

0% 1/32W MF 01005

REF

=PP3V0_UVLO

R8445 SOCHOT0_R_L

VEE

C8400

VSS

H10 H11 H12 H13 J7 J8 J9 J10 J11 J12 J13 K7 K8 K9 K10 K11 K12 K13 L7 L8 L9 L10 L11 L12 L13 M7 M8 M9 M10 M11 M12 M13 N6 N7 N8 N9 N10 N11 N12 N13 P8 P9 P10 P11 P12 P13 R4 T3 U3

5% 1/32W MF 2 01005

R8430 UVLO_COMP_POS

1% 1/32W MF 01005

255K 2 1% 1/32W MF 01005

SYNC_MASTER=J72_MLB_C

SYNC_DATE=11/26/2012

PAGE TITLE

PMU: ANYA PAGE 4 DRAWING NUMBER

Apple Inc.

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

84 OF 121 SHEET

49 OF 54

SWITCH TO GATE POWER TO SOC AND NAND.

NEEDED FOR J72 ROUTING.

CRITICAL

U8550

TPS22924X A2 B2

=PP1V8_S2R_EXT_SWITCH 1

CSP

VIN

VOUT

A1 B1

PP1V8_EXT_SW

52 54

C8550 10UF

20% 10V 0402-2

54 52 46

C2 ON

PP1V8_SW1

GND

2 X5R-CERM 1

C8555

0.01UF 10% 6.3V 01005

2 X5R

SYNC_MASTER=J85 MLB_C

SYNC_DATE=11/26/2012

PAGE TITLE

POWER: PP1V8_SW DRAWING NUMBER

Apple Inc.

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

85 OF 121 SHEET

50 OF 54

DEBUG 54 5

TP9002 1

=PP1V8_S2R_MISC

TP-P55

SEP EEPROM UNPROGRAMMED P/N: 335S0894

=PP1V8_EEPROM

C9000 0.22UF

CRITICAL

VCC

20% 2 6.3V X5R 0201

U9000

CAT24C08C4A 5

SEP_I2C0_SCL

B1 SCL

WLCSP

SDA B2

SEP_I2C0_SDA

VSS

SYNC_MASTER=J72_MLB_C

SYNC_DATE=11/26/2012

PAGE TITLE

SEP: EEPROM & SOC DEBUG DRAWING NUMBER

Apple Inc.

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

90 OF 121 SHEET

51 OF 54

RF TEST POINTS TP93001

GPIO_CODEC_IRQ_L 5 A TP-P5 TP93041 PMU_GPIO_CODEC_HS_INT_L A TP-P5 TP93031

BATT_NTC

47 54 47 54

PPLED_OUT_A A TP-P5 PP3V0_UVLO A TP-P5 PP3V0_SPARE1 A TP-P5 TP93981 SOCHOT0_L A TP-P5

BOARD_TEMP3_P A TP-P5 BOARD_TEMP4_P A TP-P5 TP93141 BOARD_TEMP5_P A TP-P5 TP93151 BOARD_TEMP6_P A TP-P5 TP93161 BOARD_TEMP7_P A TP-P5 TP93171 BOARD_TEMP8_P A TP-P5 TP93181 CLK_32K_SOC2CUMULUS A TP-P5

A TP-P5 PMU_GPIO_BT_REG_ON A TP-P5 TP93841 PMU_GPIO_CLK_32K_OSCAR A TP-P5 TP93851 PMU_GPIO_CLK_32K_WLAN A TP-P5 PMU_USB_BRICKID_R

A TP-P5 PP1V0_SOC A TP-P5 TP93891 PP1V2_S2R A TP-P5 TP93901 PP1V2_S2R_SW2 A TP-P5 TP93911 PP1V2_SW1 A TP-P5 TP93881

TP93931

PP_SMPS1_MSMC_1V05 25 27 A TP-P5 TP9301 PP_SMPS3_MSME_1V8 24 25 27 28 30 A TP-P5 TP93G51 PP_SMPS5_DSP_1V05 25 A TP-P5 TP93E11 PP_LDO1 25 A TP-P5 TP93H91 TP_BB_TEST_MODE_0 27 A TP-P5 TP93I01 TP_BB_TEST_MODE_1 27 A TP-P5 TP9302 SIMCRD_RST_CONN 10 24 28 A TP-P5 TP93B9 SIMCRD_CLK_CONN 10 24 28 A TP-P5 TP93E7 SIMCRD_IO_CONN 10 24 28 A TP-P5 TP93E8 SIM_TRAY_DETECT 10 24 28 A TP-P5 TP93F31 PP_LDO6_RUIM_1V8 10 24 25 27 A TP-P5 TP93J2 GPIO_SOC2BB_RADIO_ON_L 5 24 26 A TP-P5 TP93J3 GPIO_SOC2BB_RST_L 5 24 26 A TP-P5 TP93J4 PMU_GPIO_PMU2BBPMU_RST_L 24 26 48 A TP-P5 TP93811 PMU_GPIO_BB2PMU_HOST_WAKE 24 28 48 A TP-P5 TP93J5 PS_HOLD_PMIC 24 26 A TP-P5 TP93271 DEBUG_RST_L 24 27 A TP-P5 TP93061 BB_JTAG_RTCLK 24 27 A TP-P5 TP93071 BB_JTAG_TCK 5 24 27 A TP-P5 TP93081 BB_JTAG_TDI 5 24 27 A TP-P5 TP93091 BB_JTAG_TDO 5 24 27 A TP-P5 TP93101 BB_JTAG_TMS 5 24 27 A TP-P5 TP93111 BB_JTAG_TRST_L 5 24 27 A TP-P5 TP93J6 USB_BB_N 11 24 53 A TP-P5 TP93J7 USB_BB_P 11 24 53 A TP-P5 TP93G61 RESET_SOC_L 4 8 10 11 24 48 A TP-P5 TP93J8 PMU_GPIO_BB_VBUS_DET 24 27 48 A TP-P5

44 48 44 48 19 48

PP1V7_VA_VCP

PP1V8_ALWAYS

46 47 54

46 54

16 47 54

47 54

48 5 13

PP1V8_EXT_SW A TP-P5 PP1V8_GRAPE_FILT A TP-P5 TP93A21 PP1V8_GRAPE_SW A TP-P5 TP93A31 PP1V8_PLL_SOC_F A TP-P5 TP93A41 PP1V8_S2R A TP-P5

15 15 15

13 5 48 43

SOC_TESTMODE

4 10

TP-P5

TP93H11

5 13

TP93H21

5 13

SPI1_GRAPE_CS_L A TP-P5 SPI1_GRAPE_MISO A TP-P5 SPI1_GRAPE_MOSI A TP-P5 TP93H41 SPI1_GRAPE_SCLK_R A TP-P5 TP93H51 SPKR_L_CONN_N A TP-P5 TP93H61 SPKR_L_CONN_P A TP-P5 TP93H71 SPKR_R_CONN_N A TP-P5 TP93H81 SPKR_R_CONN_P A TP-P5 TP93H31

5 13 13 16 43 16 43 16 43 16 43

TP93I11

TP93I21

4 46 47 54

TP93A61

TP93A71

46 50 54

PP1V8_S2R_SW3_COMP A TP-P5 PP1V8_SW1 A TP-P5 TP93A81 PP1V8_SW2 A TP-P5 TP93A91 PP1V8_XTAL A TP-P5 TP93B01 PP2V6_CAM_AF A TP-P5

TP93G91

50 54

15 15

25 30

46 54

TP93A11

PP_SMPS4_RF2_2V05

TP-P5

47 54

TP-P5

TP93A01

TP-P5

TP93951

TP93G41

44 48

TP93G11

DISPLAY_SYNC_R A TP-P5 TP93291 DWI_AP_CLK A TP-P5 TP93301 E75_DPAIR1_CONN_N A TP-P5 TP93311 E75_DPAIR1_CONN_P A TP-P5 TP93321 E75_DPAIR2_CONN_N A TP-P5 TP93331 E75_DPAIR2_CONN_P A TP-P5 TP93341 FMI0_CE0_L A TP-P5 TP93351 FMI1_CE0_L A TP-P5 TP93361 GND A TP-P5 TP93371 GND_AUDIO_CODEC A TP-P5 TP93381 GPIO_BTN_HOME_FILT_L A TP-P5 TP93391 GPIO_BTN_ONOFF_L_FILT A TP-P5 TP93401 GPIO_BTN_SRL_L_FILT A TP-P5 TP93411 GPIO_BTN_VOL_DOWN_L_FILT A TP-P5 TP93421 GPIO_BTN_VOL_UP_L_FILT A TP-P5 TP93431 GPIO_FORCE_DFU A TP-P5 TP93441 GPIO_GRAPE_IRQ_L A TP-P5 TP93451 GPIO_GRAPE_RST_L A TP-P5 TP93461 GPIO_SOC2BB_WAKE_MODEM A TP-P5 TP93471 GPIO_SPKAMP_KEEPALIVE A TP-P5 TP93481 I2C0_SCL_1V8 A TP-P5 TP93491 I2C0_SDA_1V8 A TP-P5 TP93501 I2C2_SCL_1V8 A TP-P5 TP93511 I2C2_SDA_1V8 A TP-P5 TP93521 ISP0_CAM_REAR_CLK A TP-P5 TP93531 ISP0_CAM_REAR_SCL A TP-P5 TP93541 ISP0_CAM_REAR_SDA A TP-P5 TP93551 ISP0_CAM_REAR_SHUTDOWN_L A TP-P5 TP93561 ISP1_CAM_FRONT_CLK A TP-P5 TP93571 ISP1_CAM_FRONT_SCL A TP-P5 TP93581 ISP1_CAM_FRONT_SDA A TP-P5 TP93591 ISP1_CAM_FRONT_SHUTDOWN_L A TP-P5 TP93601 JTAG_SOC_SEL A TP-P5 TP93611 JTAG_SOC_TCK A TP-P5 TP93621 JTAG_SOC_TDI A TP-P5 TP93631 JTAG_SOC_TMS A TP-P5 TP93641 JTAG_SOC_TRST_L A TP-P5 TP93651 JTAG_WLAN_SEL A TP-P5 TP93661 OSCAR2RADIO_CONTEXT_A A TP-P5 TP93671 OSCAR2RADIO_CONTEXT_B A TP-P5 TP93681 WLAN_TX_BLANK A TP-P5 TP93691 LAT_SW1_CTL A TP-P5 TP93701 LAT_SW2_CTL A TP-P5 TP93711 A TP-P5 TP93721 LED_IO1_A_R A TP-P5 TP93731 LED_IO2_A_R A TP-P5 TP93741 LED_IO3_A_R A TP-P5 TP93751 LED_IO4_A_R A TP-P5 TP93761 LED_IO5_A_R A TP-P5 TP93771 LED_IO6_A_R A TP-P5 TP93781 MIKEY_TS_N A TP-P5 TP93791 MIKEY_TS_P A TP-P5

TP93871

5 49

TP93211

TP93281

PMU_GPIO_BT_HOST_WAKE

TP93831

47 54

TP93201

CODEC_HP_DET_R A TP-P5 CODEC_HP_HS3 A TP-P5 TP93221 CODEC_HP_HS3_REF A TP-P5 TP93231 CODEC_HP_HS4 A TP-P5 TP93241 CODEC_HP_HS4_REF A TP-P5 TP93251 CODEC_HP_LEFT A TP-P5 TP93261 CODEC_HP_RIGHT A TP-P5

TP93821

45 48

TP93961 TP93971

OVP_SW_EN_L_R

TP-P5

15 48

TP93051

TP93131

TP-P5

TP93121

TP93801

46 54 8 47 54

TP_JTAG_SOC_TDO A TP-P5 TP_JTAG_WLAN_TCK A TP-P5 TP93I31 TP_JTAG_WLAN_TRST_L A TP-P5 TP93I41 UART0_SOC_RXD A TP-P5 TP93I51 UART0_SOC_TXD A TP-P5 TP93I61 UART3_BB2SOC_TX A TP-P5 TP93I71 UART3_SOC2BB_TX A TP-P5 TP93I81 UART6_TS_ACC_RXD A TP-P5 TP93I91 UART6_TS_ACC_TXD A TP-P5 TP93J01 USB_SOC_N A TP-P5 TP93J11 USB_SOC_P A TP-P5

44 5 11 5 11 5 11 24 28

STANDOFFS: P/N 860-1657

STD9300 STDOFF-3.3X1.8R1.28H-SM 1

STD9301 STDOFF-3.3X1.8R1.28H-SM

STANDOFF: P/N 860-1683

STD9302 STDOFF-3.3X2.2R1.35H-SM-1 1

PLATED THROUGH HOLES DRILL SIZE: 1.1MM X 0.4MM PLATING SIZE: 1.4MM X 0.7MM

SL9300 TH-NSP 1 SL-1.1X0.4-1.4X0.7

5 11 24 28

5 11 5 11

SL9303 TH-NSP

4 11

SL-1.1X0.4-1.4X0.7

SL9304 TH-NSP

TP93J91

PP3V0_ALS A TP-P5 TP93JA1 PP2V9_CAM A TP-P5 TP93JB1 PP1V3_CAM A TP-P5 TP93JC1 PMU_GPIO_WLAN_REG_ON A TP-P5

6 12 6 12

TP93B81

PP3V0_S2R_HALL_FILT

47 54

SL-1.1X0.4-1.4X0.7

47 54

SL9305 TH-NSP

47 54

44 48

SL-1.1X0.4-1.4X0.7

TP-P5

TP93C01

A A

PP3V0_S2R_SENSOR

47 54

TP-P5

TP93C11

PP3V0_S2R_TRISTAR

47 54

TP-P5

TP93C31

PP3V3_ACC A TP-P5 PP3V3_S2R A TP-P5 TP93C51 PP3V3_SW A TP-P5 TP93C61 PP5V25_GRAPE_FILT A TP-P5

TP93C41

5 13 5 13 5 28

MH9300

47 54

3P25R2P5 1

46 54 48 54 13

5 16

TP93C81

PP6V0_LCM_VBOOST A TP-P5 PPBATT_VCC A TP-P5 TP93D01 PPLED_BACK_REG_A A TP-P5 TP93D11 PPOUT_E75_ACC_ID1_CONN A TP-P5 TP93D21 PPOUT_E75_ACC_ID2_CONN A TP-P5 TP93D31 PPVBUS_PROT A TP-P5 TP93D41 PPVBUS_USB_DCIN A TP-P5 TP93D51 PPVCC_MAIN A TP-P5 TP93D61 PPVCC_MAIN_LCD_SW_CONN A TP-P5 TP93D71 PPVDD_CPU A TP-P5 TP93D81 PPVDD_GPU A TP-P5 TP93D91 PPVDD_SOC A TP-P5 TP93E01 PPVDD_SRAM A TP-P5

5 11 48

TP93C91

5 11 48 5 16 5 16 7 23 7 23 7 23 7 23 7 20 7 20 7 20 7 20 4 10

47 46 54

18 43 43

860-1688

11 46

MH9302

46 54

WASHER-BTN-MLB-X221 TH

46 47 48 49 54

18 46 54 46 54 46 54

NEAR BUTTON FLEX CONN

46 54

4 11 4 4 11 4 10 44 19 28 44 19 28 44 28 44 14 24 28 14 28

SYNC_MASTER=J85 MLB_C

SYNC_DATE=12/03/12

PAGE TITLE

TEST:

TP/HOLES/FIDUCIALS DRAWING NUMBER

Apple Inc.

47 47

051-0886

NOTICE OF PROPRIETARY PROPERTY:

47 11 15 11 15

SIZE

REVISION

A.0.0 BRANCH

PAGE

93 OF 121 SHEET

52 OF 54

FOR FRANK (SEG)

EE CHARACTERIZATION TP PP9450 P4MM SM PP9451 SM

NAND

P4MM

PP9401 PP SM P4MM PP9402 PP SM P4MM PP9403 PP SM P4MM

FMI0_DQS

FMI0_AD<3>

PLACE_SIDE=BOTTOM PLACE_NEAR=U0652.D34:2MM PLACE_SIDE=BOTTOM PLACE_NEAR=U0652.C34:2MM

FMI0_DQS

PLACE_NEAR=U0652.D34:2MM

PP9410 PP SM P4MM PP9411 PP SM P4MM PP9412 PP SM P4MM PP9413 PP SM P4MM

TP_TCKC_U1400

PP PP

PPVDD_SOC_SOC_SENSE

PLACE_NEAR=U0652.V31:1MM

PPVDD_CPU_SOC_SENSE

PLACE_NEAR=U0652.AN30:1MM

6 12 53 6 12

6 12 53

TP_TMSC_U1400

TP_U1400_RB0

TP_U1400_RB1

WIFI

DWI PP9405 PP SM P4MM

PLACE_SIDE=BOTTOM PLACE_NEAR=U8100:2MM

DWI_AP_DO

PP9480 PP SM P4MM PP9481 PP SM P4MM PP9482 PP SM P4MM PP9483 PP SM

5 48

AUDIO PP9406 PP SM P4MM

I2S0_CODEC_ASP_MCK

HSIC1_WLAN2SOC_DEVICE_RDY

5 44

HSIC1_WLAN2SOC_REMOTE_WAKE

5 44

PMU_GPIO_WLAN_HOST_WAKE

44 48

HSIC1_SOC2WLAN_HOST_RDY

5 44

P4MM

PLACE_NEAR=U1900:2MM

5 15

FUNC_TEST=TRUE

GPIO_BT_WAKE

I76

5 44

FOR HSIC CHARACTERIZATION

PP9416 PP SM P4MM PP9417 PP SM P4MM

I2S2_CODEC_XSP_LRCK

PLACE_NEAR=U1900:2MM

I2S2_CODEC_XSP_DOUT

PLACE_NEAR=U1900:2MM

5 15

C PP9419 PP SM P4MM PP9420 PP SM P4MM PP9421 PP SM P4MM PP9422 PP SM P4MM PP9423 PP SM P4MM PP9424 PP SM P4MM PP9425 PP SM P4MM PP9426 PP SM

I2S1_SPKAMP_MCK

PLACE_NEAR=U2040:2MM

I2S1_SPKAMP_BCLK

PLACE_NEAR=U2040:2MM

I2S1_SPKAMP_LRCK

PLACE_NEAR=U2040:2MM

PP9460 PP SM P4MM

HSIC1_WLAN_DATA

PLACE_NEAR=U0652.AM33:3MM

PP9462 PP SM P4MM PP9463 PP SM P4MM

HSIC1_WLAN_DATA

PLACE_NEAR=U5800.13:3MM

HSIC1_WLAN_STB

PLACE_NEAR=U5800.14:3MM

PP9468 PP SM P4MM PP9469 PP SM

UART1_BT2SOC_TX

PLACE_NEAR=U0652:3MM

UART1_SOC2BT_TX

PLACE_NEAR=U5800:3MM

PP9471 PP SM P4MM PP9472 PP SM P4MM

UART2_WLAN2SOC_TX

PLACE_NEAR=U0652:3MM

UART2_SOC2WLAN_TX

PLACE_NEAR=U5800:3MM

4 44 53

5 15 4 44 53

4 44

5 16 5 16 5 16

5 44 5 44

P4MM

I2S1_SPKAMP_DOUT

I2S1_SPKAMP_DIN

PLACE_NEAR=U2040:2MM PLACE_SIDE=BOTTOM PLACE_NEAR=U0652:2MM

SPI2_CODEC_SCLK

PLACE_NEAR=U1900:2MM

SPI2_CODEC_MOSI

SPI2_CODEC_MISO

PLACE_NEAR=U1900:2MM PLACE_SIDE=BOTTOM PLACE_NEAR=U0652:2MM

5 16 5 16

5 44 5 44

5 15 5 15 5 15

P4MM

GRAPE

BASEBAND I192

OSCAR PP9428 PP SM P4MM PP9429 PP SM P4MM

UART4_SOC2OSCAR_TXD

UART4_OSCAR2SOC_RXD

PLACE_SIDE=BOTTOM PLACE_NEAR=U2400:2MM PLACE_SIDE=BOTTOM PLACE_NEAR=U0652:2MM

I193

USB_BB_P

FUNC_TEST=TRUE

USB_BB_N

FUNC_TEST=TRUE

11 24 52 11 24 52

FOR HSIC CHARACTERIZATION

5 19 5 19

PP9465 PP SM P4MM PP9466 PP SM

UART5

HSIC2_BB_STB

PLACE_NEAR=U0652.B27:3MM

HSIC2_BB_DATA

PLACE_NEAR=U3400.C7:3MM

4 24 27 4 24 27

P4MM

PROX

HIGH SPEED, NO TEST I141 I140 I139 I138 I142 I144 I145 I143 I146 I149

CAMERA

PP9440 P4MM SM PP PP9441 P4MM SM PP PP9442 P4MM SM PP PP9443 P4MM SM PP PP9444 P4MM SM PP PP9445 P4MM SM PP PP9446 P4MM SM PP PP9447 P4MM SM PP

I150

MIPI1C_CAM_FRONT_CLK_P

PLACE_NEAR=U0652.AR33:3MM

MIPI1C_CAM_FRONT_CLK_N

PLACE_NEAR=U0652.AR34:3MM

MIPI1C_CAM_FRONT_DATA_P<0>

PLACE_NEAR=U0652.AT33:3MM

MIPI1C_CAM_FRONT_DATA_N<0>

PLACE_NEAR=U0652.AT34:3MM

MIPI0C_CAM_REAR_CLK_P

PLACE_NEAR=U0652.AU25:3MM

I148

7 20 53

I147 I152

7 20 53

I151 I153

I187

7 20 53

I186

7 23 53

I188

MIPI0C_CAM_REAR_CLK_N

PLACE_NEAR=U0652.AV25:3MM

I190

7 23 53

I189

MIPI0C_CAM_REAR_DATA_P<0>

PLACE_NEAR=U0652.AU27:3MM

MIPI0C_CAM_REAR_DATA_N<0>

PLACE_NEAR=U0652.AV27:3MM

NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE

EDP_DATA_P<0..3> EDP_DATA_N<0..3> EDP_DATA_EMI_P<0..3> EDP_DATA_EMI_N<0..3> EDP_DATA_EMI_CONN_P<0..3> EDP_DATA_EMI_CONN_N<0..3>

NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE

7 23 53 7 23 53 7 23 53 7 23 53 23 23 23 23 7 20 53 7 20 53 7 20 53 7 20 53 20 20 20

SYNC_MASTER=J72_MLB_C

SYNC_DATE=11/26/2012

PAGE TITLE

7 20 53

I185

MIPI0C_CAM_REAR_CLK_P MIPI0C_CAM_REAR_CLK_N MIPI0C_CAM_REAR_DATA_P<0..3> MIPI0C_CAM_REAR_DATA_N<0..3> MIPI0C_CAM_REAR_CLK_FILT_P MIPI0C_CAM_REAR_CLK_FILT_N MIPI0C_CAM_REAR_DATA_FILT_P<0..3> MIPI0C_CAM_REAR_DATA_FILT_N<0..3> MIPI1C_CAM_FRONT_CLK_P MIPI1C_CAM_FRONT_CLK_N MIPI1C_CAM_FRONT_DATA_P<0> MIPI1C_CAM_FRONT_DATA_N<0> MIPI1C_CAM_FRONT_CLK_FILT_P MIPI1C_CAM_FRONT_CLK_FILT_N MIPI1C_CAM_FRONT_DATA_FILT_P<0> MIPI1C_CAM_FRONT_DATA_FILT_N<0>

TEST: EE TP/PP

7 18

DRAWING NUMBER

7 18 18

Apple Inc.

18 18

NOTICE OF PROPRIETARY PROPERTY:

7 23 53

SIZE

A.0.0

7 23 53

051-0886 REVISION

BRANCH

PAGE

94 OF 121 SHEET

53 OF 54

POWER CONNECTIONS BUCK0 PPVDD_CPU

52 46

CHARGER MAIN

=PPVDD_CPU

MAKE_BASE=TRUE

52 49 48 47 46

PPVCC_MAIN

=PPVCC_MAIN_AUDIO =PPVCC_MAIN_LED =PPVCC_MAIN_DOCK =PPVCC_MAIN_DEV =PPVCC_MAIN_CPU =PPVCC_MAIN_GPU =PPVCC_MAIN_SOC

MAKE_BASE=TRUE

BUCK1 52 46

PPVDD_GPU

BUCK5

=PPVDD_GPU

LDO7

LDO7 SHOULD BE ON IN HIBERNATE

MAKE_BASE=TRUE

PPVDD_SRAM

52 46

=PPVDD_SRAM_CPU =PPVDD_SRAM_SOC

MAKE_BASE=TRUE

52 47

PP3V0_S2R_TRISTAR

=PP3V0_S2R_TRISTAR

MAKE_BASE=TRUE 9

BUCK2 52 46

PPVDD_SOC

=PPVDD_SOC

BUCK6

BUCK3 PP1V8_S2R MAKE_BASE=TRUE

=PP1V8_S2R_MISC 5 51 =PP1V8_S2R_VDDIO_WLAN_BT 44 =PP1V8_S2R_TRISTAR 11 =PP1V8_S2R_DDR 8 =PP1V8_S2R_GRAPE 13 =PP1V8_S2R_EXT_SWITCH 50 =PP1V8_S2R_REAR_CAMERA =PP1V8_S2R_MESA =PP1V8_S2R_VDD_CORE_GPS =PP1V8_S2R_VDD_IO_GPS

PP3V3_S2R

52 46

=PP3V3_S2R_SWITCH =PP3V3_S2R_WIFI_PA

MAKE_BASE=TRUE

NC_LDO8

MAKE_BASE=TRUE

NO_TEST=TRUE

=PP3V3_NAND =PP3V3_USB_SOC

=NC_LDO8

12 4

52 46

PP3V0_SPARE1

=PPBATT_POS_CONN =PPBATT_VCC_BB

BACKUP RAIL. CAN BE BOOSTED TO MEET 1.1V MIN ON CAMERA IF NEEDED.

PP1V3_CAM

=PP1V3_CAM_FRONT =PP1V3_CAM_REAR

45 24 25 33 34 35 36 37 38

=PPBATT_AUDIO

USB POWER INPUT

20 52 47

PPBATT_VCC MAKE_BASE=TRUE

LDO1

=PP3V3_EDP_PU

MAKE_BASE=TRUE

=PP1V8_AUDIO =PP1V8_DMIC =PP1V8_CAM_FRONT =PP1V8_CAM_REAR =PP1V8_PROX

13 18

MAKE_BASE=TRUE

52 47

PP1V8_SW1

BATTERY PP3V3_SW

52 48

BUCK3_SW 52 50 46

MAKE_BASE=TRUE

LDO9 C

=PPVCC_MAIN_VDD_LCM =PPVCC_MAIN_WLAN =PPVCC_MAIN_GPS

LDO8

=PPVCC_MAIN_GRAPE =PPVCC_MAIN_LCD =PPVCC_MAIN_NAVAJO

MAKE_BASE=TRUE

52 47 46

15 16 47

=PP3V0_SPARE1

MAKE_BASE=TRUE

22 52 46

PPVBUS_USB_DCIN

=PPVBUS_USB_EMI

=PP1V8_ALWAYS

MAKE_BASE=TRUE

52 50

PP1V8_EXT_SW MAKE_BASE=TRUE

LDO10

=PP1V8_VDDIO18_SOC =PP1V8_SOC =PP1V8_MIPI_SOC =PP1V8_EDP_SOC =PP1V8_NAND_SOC =PP1V8_NAND =PP1V8_PLL_SOC =PP1V8_SPKRAMP =PP1V8_EEPROM =PP1V8_BEACON

8 9 52 47

4 5 7 10 18

PP1V8_SW2 PP1V8_S2R_SW3 MAKE_BASE=TRUE

12 48

52 47 16

PP1V7_VA_VCP

=PP1V7_VA_VCP

15 16

ON_BUF

LDO11

=PP1V8_GRAPE

=PP3V0_S2R_HALL =PP3V0_S2R_GYRO =PP3V0_S2R_ACCEL

=PP3V0_S2R_COMP

52 47

PP3V0_S2R_SENSOR MAKE_BASE=TRUE

=PP1V8_S2R_GYRO =PP1V8_S2R_ACCEL =PP1V8_S2R_OSCAR

LDO3 SHOULD BE ON IN HIBERNATE COMPASS, ACCEL, GYRO, PROX ARE ON OSCAR HALL EFFECT NEEDS TO BE ON IN HIBERNATE

52 47

PP1V8_ALWAYS MAKE_BASE=TRUE

PP2V6_CAM_AF

=PP2V6_CAM_REAR_AF

MAKE_BASE=TRUE

BACKLIGHT BOOST

LDO13

47 PPLED_OUT_A

=PPLED_REG_A

MAKE_BASE=TRUE

52 54

LDO4 PP1V8_S2R_SW3_COMP

7 7

MAKE_BASE=TRUE

PP1V8_S2R_SW3_COMP

54 52

MAKE_BASE=TRUE

=PP1V0_USB_SOC =PP1V0_MIPI_SOC =PP1V0_EDP_PAD_DVDD_SOC

LDO2

LDO3 52 46

PP1V0_SOC MAKE_BASE=TRUE

=PP1V8_S2R_COMP

52 47

PP2V9_CAM

=PP2V9_CAM_FRONT =PP2V9_CAM_REAR

MAKE_BASE=TRUE

20 23

MAKE_BASE=TRUE

PP1V8_S2R_SW3 SHOULD BE ON IN HIBERNATE CURRENTLY POWERS OSCAR AND 1.8V RAIL ON SENSOR

52 47

PP3V0_ALS

=PP3V0_ALS =PP3V0_PROX

MAKE_BASE=TRUE

=PP3V0_HP_ALS =PP3V0_IO_ALS

BUCK4 52 47 46

PP1V2_S2R MAKE_BASE=TRUE

20 22

SHOULD IO ALS POWER HERE?

=PP1V2_S2R_DDR =PP1V2_S2R_DDR_SOC =PP1V2_S2R_CAM_REAR

LDO5

52 47

PP3V0_UVLO

=PP3V0_UVLO

MAKE_BASE=TRUE

BUCK4_SW 52 46

PP1V2_SW1 MAKE_BASE=TRUE

VLCM1

LDO6 =PP1V2_VDDQ_DDR =PP1V2_VDDIOD_SOC =PP1V2_HSIC_SOC

8 8

52 47

PP3V3_ACC

=PP3V3_ACC

MAKE_BASE=TRUE

PP5V25_GRAPE

=PP5V25_GRAPE

MAKE_BASE=TRUE

SYNC_MASTER=J72_MLB_C

SYNC_DATE=11/26/2012

PAGE TITLE

52 46

PP1V2_S2R_SW2

=PP1V2_S2R_OSCAR

POWER: ALIASES 19

DRAWING NUMBER

MAKE_BASE=TRUE

PP1V2_S2R_SW2 SHOULD BE ON IN HIBERNATE PROVIDE 1.2V TO OSCAR

Apple Inc.

051-0886

SIZE

REVISION

A.0.0 BRANCH

PAGE

121 OF 121 SHEET

54 OF 54