Sponsored by:
INTRODUCTION FROM THE 64TH ECTC PROGRAM CHAIR ALAN HUFFMAN The 64th Electronic Components and Technology Conference (ECTC) Walt Disney World Swan and Dolphin Resort, Lake Buena Vista, Florida, USA • May 27 - 30, 2014 On behalf of the Program and Executive Committees, it is my pleasure to invite you to join us for the 64th Electronic Components and Technology Conference (ECTC), which will be held at the Walt Disney World Swan and Dolphin Resort in Lake Buena Vista, Florida, USA, May 27-30, 2014. This premier international conference is sponsored by the IEEE Components, Packaging, and Manufacturing Technology Society (CPMT). The ECTC Program Committee has selected more than 300 papers that will be presented in 36 oral sessions and 5 interactive presentation sessions, including a student interactive presentation session. The oral sessions will feature peer-reviewed papers on 3D and TSV technologies, wafer level packaging, electrical and mechanical modeling, RF packaging, system design, and optical interconnects. Session topics will cover advanced packaging technologies, material development and characterization, reliability, assembly and manufacturing, and interposers. Four interactive presentation sessions showcase peer-reviewed papers in a format that encourages more in-depth discussion and interaction with authors about their work. Similarly, the student interactive presentation session will focus on the research being done at academic institutions around the world by emerging scientists and engineers. The Program Committee has created sessions covering the ongoing technological challenges of established disciplines, as well as addressing emerging topics of interest to the industry. Authors from companies, research institutions, and universities from more than 25 countries will present their work at ECTC, illustrating the conference’s global focus. ECTC will also feature panel and special sessions with industry experts covering a number of important and emerging topic areas. On Tuesday, May 27 at 10 a.m., Karlheinz Bock will chair a session entitled “Flexible Electronics - Packaging Technology and Application Trends” where a panel of experts will discuss the recent advancements and market perspectives for this emerging technology area. Tuesday at 2 p.m., Manos Tentzeris will chair a special session sponsored by the Electronic Components & RF technical subcommittee on “Wireless Power Transfer Systems.” The ECTC Panel Discussion “Emerging Technologies and Market Trends of Silicon Photonics” on Tuesday, May 27 at 7:30 p.m. will be chaired by Ricky Lee and Jie Xue and features panelists from various segments of the industry to discuss the growing influence of photonics technologies on microelectronic systems. Nancy Stoffel will chair the ECTC Plenary Session titled “Influence of Packaging on System Integration and Performance” on Wednesday evening at 7:00 p.m. where a panel of experts will discuss system integration and the role that component packaging technologies play. On Thursday evening at 8:00 p.m., the CPMT Seminar titled “Latest Advances in Organic Interposers” will be moderated by Kishio Yokouchi and Venky Sundaram. 2
Supplementing the technical program, ECTC will also offer several Professional Development Courses (PDCs) and Technology Corner Exhibits. ECTC will offer 18 PDCs for 2014 covering a wide array of technical areas and organized by the PDC Committee chaired by Kitty Pearsall. The PDCs will take place on Tuesday, May 27 (8:00 a.m. – 5:30 p.m.) and are taught by distinguished experts in their respective fields. The Technology Corner Exhibits will showcase the latest products and technologies offered by leading companies in the electronic components, materials, packaging, and services fields. Technology Exhibits will be open Wednesday and Thursday. ECTC also offers attendees numerous opportunities for networking and discussion with colleagues during coffee breaks, daily luncheons, and nightly receptions. I am also pleased to announce that Dr. Peter Bocko of Corning Glass Technologies will be the invited keynote speaker at the ECTC Luncheon on Wednesday. Whether you are an engineer, a manager, a student, or an executive, ECTC offers something for everyone in the packaging industry. I invite you to make your plans now to join us for the 64th ECTC and be a part of the exciting technical and professional opportunities. I also want to take this opportunity to thank our sponsors, exhibitors, authors, speakers, PDC instructors, session chairs, program committee members, as well as all the volunteers who help to make the 64th ECTC another success. I look forward to meeting you in Lake Buena Vista May 27 – 30, 2014. Alan Huffman 64th ECTC Program Chair RTI International, USA Phone: +1-919-248-9216 Email: huffman@rti.org
Index
ECTC Registration ................................................................. 3, 29, 30 General Information .............................................................................3 Hotel Information ..........................................................................3, 29 2014 Special Session .............................................................................4 2014 Electronic Components & RF Special Session ........................4 2014 ECTC Panel Session....................................................................4 2014 ECTC Plenary Session ...............................................................4 2014 CPMT Seminar.............................................................................5 ECTC Luncheon Keynote Speaker.....................................................5 Luncheons and Receptions .................................................................5 Executive and Program Committees .............................................6-7 Professional Development Courses ............................................8-13 Area Attractions ................................................................................ 13 Program Sessions ..........................................................................14-29 2014 Technology Corner Exhibits .................................................. 29 Conference Overview ...................................................................... 31
64th ECTC ADVANCE REGISTRATION Advance Registration Online registration is available at www.ectc.net. For more information on registration rates, terms, and conditions see page 30. Register early … save $100 or more! All applications received after May 9, 2014 will be considered Door Registrations. Those who register in advance can pick up their registration packets at the ECTC Registration Desk in the Dolphin Convention Center on the Lobby Level in front of Australia 3. Please note that the Swan and Dolphin are two separate buildings and all ECTC meetings will be taking place in the Walt Disney World Dolphin Resort. On-Site Registration Schedule Registration will be held in the Dolphin Convention Center on the Lobby Level in front of Australia 3. Monday, May 26, 2014 3:00PM to 5:00PM Tuesday, May 27, 2014 6:45AM to 5:00PM*
Wednesday, May 28, 2014 Thursday, May 29, 2014 Friday, May 30, 2014
*6:45AM to 8:00AM (AM PD Courses & Special Morning Session Only)
6:45AM to 4:00PM 7:30AM to 4:00PM 7:30AM to 12:00PM
The above schedule for Tuesday will be rigorously enforced to prevent students from being late for their courses.
General Information Conference organizers reserve the right to cancel or change the program without prior notice. **Please note that the Walt Disney World Swan and Dolphin Resort are two separate buildings and ALL ECTC meetings will be taking place in the Walt Disney World Dolphin Resort. While booking your hotel reservation please make sure to specify that you require to be placed in the Walt Disney World DOLPHIN Resort.** While these two buildings are located adjacent to each other and share many of the same social / resort function areas we want to ensure you have a most convenient experience while at ECTC. Loss Due to Theft Conference management is not responsible for loss or theft of personal belongings. Security for each individual’s belongings is the individual’s responsibility. ITHERM 2014 This year ITHERM is co-located with ECTC. All ITHERM sessions will take place in the SWAN building of the Walt Disney World Swan and Dolphin Resort. ALL ECTC sessions, and the co-location of exhibits, will take place in the DOLPHIN building.
ECTC Sponsors With 63 years of history and experience behind us, ECTC is recognized as the premier semiconductor packaging conference and offers an unparalleled opportunity to build relationships with more than 1,000 individuals and organizations committed to driving innovation in semiconductor packaging. We have a limited number of sponsorship opportunities in a variety of packages to help you get your message out to attendees. These include Gala, Program, Internet Interface, and several other sponsorship options that can be customized to your company’s interest. If you would like to enhance your presence at ECTC and increase your impact with a sponsorship, please take a look at our sponsorship brochure on the website www.ectc.net under “Sponsors.” To sign-up for sponsorship, or to get more details, please contact David McCann at david.mccann@ globalfoundries.com or +1-518-222-6128. Hotel Accommodations Rooms for ECTC attendees have been reserved at the Walt Disney World Dolphin, of the Walt Disney World Swan and Dolphin Resort. The special conference rate is: $179.00 / Run of the House Please note these rooms are on a first come, first serve basis. If a specific category is no longer available, attendees will be offered the next best available accommodation. These prices include single or double occupancy in one room. Please note that rooms offering two beds are limited and subject to availability and should be requested at the time of reservations. Room reservations must be made directly with the hotel by Friday, May 2, 2014 at 5pm ET to ensure our preferred conference rate. All reservations made after the cut off date of Friday, May 2, 2014 at 5pm ET will be accepted on a space and rate available basis. If you need to cancel a reservation, please do so AT LEAST 5 DAYS prior to arrival for a full refund. Each attendee is subject to the terms and polices set by each hotel. Transportation Services Enjoy a complimentary water taxi from the resort’s dock, running to and from Epcot® and Disney’s Hollywood Studios™. Complimentary shuttle buses also transport guests from the hotel entrance to Magic Kingdom® Park, Disney’s Animal Kingdom® Theme Park, Downtown Disney® area, and Disney’s Blizzard Beach Water Park and Disney’s Typhoon Lagoon Water Park. There is, unfortunately, no courtesy transportation between the hotel and the airport.
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2014 ECTC Special Session
2014 ECTC Panel Session
Flexible Electronics – Packaging Technology and Application Trends
Emerging Technologies and Market Trends of Silicon Photonics
Tuesday, May 27, 2014 • 10:00 a.m. – 12:00 p.m. Chair: Karlheinz Bock, Fraunhofer EMFT & University of Berlin
Tuesday, May 27, 2014 • 7:30 p.m. – 9:00 p.m. Chairs: Ricky Lee, Hong Kong University of Science and Technology Jie Xue, Cisco Systems, Inc.
A key driver for flexible electronics is the flexible display, now announced for 2014, where the control electronics need to become flexible and to be integrated with flexible displays on the same base substrate. Such free form factor of flexible electronics together with new substrate materials for organic films and boards now promise that organic and flexible electronics, as well as printed interconnects, will be found in high-performance smart phones. These technologies allow additional space for larger batteries, enable integrated cooling for the high performance processors and advanced new sensors, merge the board with the housing for new smart functions, combine optical and electrical interconnect technologies, and allow higher frequency applications with integrated wave guides and antenna arrays. Additionally, there is the potential to reduce cost compared to existing board and packaging technologies, and similar technologies can be applied to many markets, such as biological and medical applications like smart skin or as flexible, soft, and biocompatible systems for implantables. Moreover, the new organic substrates may allow lower-cost, high-performance organic interposers for 2.5D and 3D integration combined with thin glass and/or silicon partial interposers in the years to come. This special session brings speakers from university, consulting, governmental research center, and companies together to cover a wide spectrum of visions, technologies, applications, business models, and strategies to embrace the role of flexible electronics in advanced packaging.
Silicon photonics is the study and application of photonic systems which use silicon as an optical medium. The silicon is usually patterned with sub-micrometer precision, into microphotonic components. These operate in the infrared, most commonly at the 1.55 micrometer wavelength used by most fiber optic telecommunication systems. Silicon photonic devices can be made using existing semiconductor fabrication techniques, and because silicon is already used as the substrate for most integrated circuits, it is possible to create hybrid devices in which the optical and electronic components are integrated onto a single microchip. Consequently, silicon photonics is being actively researched by many electronics manufacturers and research institutions. This panel session will feature representatives from different segments of the industry to introduce the technologies and industries of silicon photonics to the attendees of ECTC. Emphasis will be placed on the emerging technologies and market trends. 1. 2. 3. 4. 5. 6.
1. Vivek Subramanian – University of California-Berkeley 2. Jonathan Melnick – LUX Research 3. Christoph Kutter – Fraunhofer EMFT 4. Mitsuru Hiroshima – Panasonic 5. Luigi G. Occhipinti – ST Microelectronics
2014 Electronic Components & RF Special Session
2014 ECTC Plenary Session
Wireless Power Transfer Systems
Packaging Influence on System Integration and Performance
Tuesday, May 27, 2014 • 2:00 p.m. – 4:30 p.m. Chair: Manos Tentzeris, Georgia Institute of Technology The emerging area of wireless power transfer systems (WPTS) finds a wide variety of applications such as wearable systems, wireless charging of mobile devices and home appliances, hybrid vehicles, autonomous or energy-efficient wireless and sensor modules, implantable electronics, wireless inter-chip / intra-chip communication, Internet of Things, and machine-to-machine interactions. An efficient miniaturized flexible wireless power transfer module could be critical for the mobile devices of the future, effectively eliminating batteries and allowing for ultra-lightweight conformal packaging and integration approaches. Utilizing the package as an ambient energy harvester as well as a sensing “smart skin” could further contribute to the development of “zero-power” integrated modules. The panel will address the major issues and challenges imposed by advanced ultra-miniaturized and highly-efficient WPTS on the frontiers of electronic components and packaging. Topics including novel power harvesting options from ambient RF energy, advances in active devices (ex. GaN and SiC) and rectifier designs, multi-domain simulations, and mixed-signal design, new designs and materials for high Q inductive links, magnetic resonance coupling with high power transfer efficiency, thin film rechargeable high-density batteries, integrated ultra-miniaturized capacitors for output power noise filters, and advanced packaging materials and processes. The panelists include distinguished experts from both industry and academic institutions. 1. Alex Lidow – EPC 2. Ravi Iyer – Intel Corporation 3. Yogesh Ramadass – Texas Instruments 4. Mark Hunsinger – Qualcomm Technologies, Inc. 5. Robert Andosca – Microgen Systems
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Michael Watts – MIT Stéphane Bernabe – CEA-LETI John Cunningham – Oracle Jean Trewhella – IBM Corporation Peter De Dobbelaere – Luxtera Madeleine Glick – APIC Corporation
Wednesday, May 28, 2014 • 7:00 p.m. – 9:00 p.m. Chair: Nancy Stoffel, GE Global Research Systems designers must find ways to satisfy customer needs through design synthesis and validation throughout the product lifecycle. The oft-competing goals of performance and power improvement, form factor and cost reduction underlie many efforts to create more highly integrated systems. In recent years many new products in the handheld, mobile, and gaming sectors have both driven and incorporated advances in component packaging technologies. In this panel session you will hear from technology leaders with broad and diverse system level perspectives representing servers, mobile networks, phones and handheld devices, and electronics for the military and aerospace. They will discuss their system level requirements, challenges, how component packaging & integration technologies play a role, and what advances in packaging are required to realize next generation systems. We will also have representation from the supplier side, where industry leaders will describe how efforts to create more highly integrated systems in package (SiP) will address current and emerging needs. 1. Peter Brofman – IBM Corporation 2. Stephane Lessard – Ericsson 3. Adrian Wong – Google 4. Li Li – Cisco Systems, Inc. 5. Nozad Karim – Amkor
These sessions are open to all conference attendees.
ECTC Luncheon Keynote Speaker Glass: The Art, Mythology and Technological Agility of a Material of the Information Age
Wednesday, May 28, 2014 • 12:00PM Presenter: Peter L. Bocko, Ph.D. Chief Technology Officer Corning Glass Technologies Using glass in emerging semiconductor packaging platforms is currently being vigorously researched and debated in the electronics industry. To provide a timely perspective, three aspects of glass will be presented: glass’ evolving role since antiquity, technologically in the immersive information environment, and culturally as a vehicle for artistic expression. “A Day Made of Glass,” Corning’s futurist video viral hit, portrayed glass as the central medium of an “interconnectivity immersion” future with ubiquitous displays connected by unlimited bandwidth. Suddenly, glass was cool! In parallel, the art world has experienced a thriving period of glass art creativity. Glass as a versatile medium is reflected between the worlds of technology and human artistic expression. Dr. Peter L. Bocko is chief technology officer for Corning Glass Technologies and is recognized as one of the foremost glass experts in consumer electronics. He is known for his contributions to the flat panel display revolution and is a frequently invited speaker on consumer electronics futures at industry events. As an occasional media commentator, Bocko most recently appeared in a featured role in the PBS Nova Special “Hunting the Elements” with David Pogue.
LUNCHEONS Tuesday PDC Luncheon All individuals attending a PDC course are invited to join us for lunch on Tuesday, May 27. Proctors and instructors are welcome too! Wednesday Conference Luncheon Please be sure not to miss our Wednesday luncheon with guest speaker Dr. Peter L. Bocko of Corning Glass Technologies. All conference attendees are welcome! Thursday CPMT Luncheon Our sponsor, the IEEE Components, Packaging and Manufacturing Technology Society, will be sponsoring lunch on Thursday for all conference attendees! Friday Program Chair Luncheon Please stick around for Friday’s lunch as our Program Chair will host this event. We will honor conference paper award recipients and raffle off a vast array of prizes including a hotel stay, free conference registrations, and many other things!
2015 iNEMI Roadmap North American Workshop
Tuesday, May 27, 2014 • 8:00AM - 6:00PM Since 1994, iNEMI (the International Electronics Manufacturing Initiative) has been developing a biennial technology roadmap spanning a 10-year horizon. In 2004, iNEMI expanded the initiative to proactively include global input. This year ECTC is hosting one of the several regional meetings intended to solicit input for the 2015 iNEMI Roadmap. Open to all conference attendees. 65th Electronic Components and Technology Conference Sheraton San Diego Hotel & Marina San Diego, CA USA • May 26-29, 2015
General Chair’s Speakers Reception
Mark Your Calendar NOW!
(by invitation only)
2014 CPMT Seminar
Tuesday, May 27, 2014 • 6:00PM - 7:00PM
ECTC Student Reception
Tuesday, May 27, 2014 • 5:00PM - 6:00PM Host: Valerie Oberson – IBM Corporation Students, have you ever wondered what career opportunities exist in the industry and how you could use your technical skills and innovative talent? If so, you are invited to attend the ECTC Student Reception, where you will have the opportunity to talk to industry professionals about what helped them be successful in their first job search and reach their current positions. You will have the chance to enjoy good food and network with industry leaders and achievers. Don’t miss the opportunity to interact with people that you would not have the chance to meet otherwise! Sponsored by IBM Corporation.
Exhibitor Reception
Wednesday, May 28, 2014 • 5:30PM - 6:30PM
64th ECTC Gala Reception
Thursday, May 29, 2014 • 6:30PM
All badged attendees and their guests are invited to attend a reception hosted by Gala Reception sponsors.
Latest Advances in Organic Interposers Thursday, May 29, 2014 • 8:00 p.m. – 10:00 p.m. Chairs: Kishio Yokouchi, Fujitsu Venky Sundaram, Georgia Institute of Technology Organic interposers leveraging existing manufacturing infrastructure provide a compelling alternative to high cost silicon interposers for fine pitch 2.5D and 3D integration. Fine-pitch-via interposer technology is now considered a mainstream approach for next generation high density and 3D packaging. Thru-Si via (TSV) interposers were the first to market with fine line RDL but have cost implications. Research in thru-glass vias (TGVs) in glass interposers is growing due to its potential for low cost and superior electric properties. This seminar will provide two perspectives: user-driven needs for interposers in high-performance and mobile applications, and the possibility of “Organic Fine Pitch Interposer (<5/5µm L/S)” from leading edge suppliers. A brief panel discussion with audience interaction will follow the technical presentations. 1. Yasumitsu Orii – IBM Japan, Ltd. 2. Suresh Ramalingam – Xilinx Inc. 3. Tadashi Kodaira – Shinko Electric Industries Co. Ltd. 4. Mitsuya Ishida – Kyocera SLC Technologies Corp.
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2014 Executive Committee General Chair Wolfgang Sauter IBM Corporation wsauter@us.ibm.com +1-802-922-3083
Vice-General Chair Beth Keser Qualcomm, Inc. beth@qti.qualcomm.com +1-858-658-3332 Program Chair Alan Huffman RTI International huffman@rti.org +1-919-248-9216 Assistant Program Chair Henning Braunisch Intel Corporation +1-480-552-0844 braunisch@ieee.org Sponsorship Chair Jr. Past General Chair David McCann GLOBALFOUNDRIES david.mccann@globalfoundries.com +1-518-222-6128 Sr. Past General Chair Rajen Dias Intel Corporation rajen.c.dias@intel.com +1-480-554-5202 Finance Chair Patrick Thompson Texas Instruments, Inc. patrick.thompson@ti.com +1-214-567-0660 Publications Chair Steve Bezuk Qualcomm CDMA Technologies sbezuk@qti.qualcomm.com +1-858-651-2770 Publicity Chair Eric D. Perfecto IBM Corporation perfecto@us.ibm.com +1-845-894-4400 Treasurer Tom Reynolds T3 Group LLC t.reynolds@ieee.org +1-850-897-7323 Exhibits Chair Joe Gisler Vector Associates gislerhj.ECTC@mediacombb.net +1-480-288-6660
Advanced Packaging Chair John Knickerbocker IBM Corporation knickerj@us.ibm.com +1-914-945-3306 Assistant Chair Christopher Bower X-Celeprint Ltd. cbower@x-celeprint.com +1-919-522-5022
Muhannad Bakir Georgia Institute of Technology Daniel Baldwin Engent, Inc. Omar Bchir Qualcomm, Inc. Rozalia Beica Yole Developpement Jianwei Dong Dow Electronic Materials Paul M. Harvey IBM Corporation Altaf Hasan Intel Corporation Erik Jung Fraunhofer IZM Sam Karikalan Broadcom Corporation Beth Keser Qualcomm, Inc. Young-Gon Kim IDT Jeffrey A. Knight Elliot Manufacturing John H. Lau ITRI Raj N. Master Microsoft Corporation Luu T. Nguyen Texas Instruments Deborah Patterson Amkor Technology, Inc. Raj Pendse STATS ChipPAC, Inc. Peter Ramm Fraunhofer EMFT Subhash L. Shinde Sandia National Laboratory
Web Administrator Sam Karikalan Broadcom Corporation samk@broadcom.com +1-949-926-7296
Joseph W. Soucy Draper Laboratory
Professional Development Courses Chair Kitty Pearsall Boss Precision, Inc. kitty.pearsall@gmail.com +1-512-845-3287
James Jian Zhang Micron Technology, Inc.
Arrangements Chair Lisa Renzi Renzi & Company, Inc. lrenzi@renziandco.com +1-703-863-2223 CPMT Representative C. P. Wong Georgia Institute of Technology cp.wong@mse.gatech.edu +1-404-894-8391
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2014 Program Committee
E. Jan Vardaman TechSearch International, Inc.
Applied Reliability Chair Scott Savage Medtronic Microelectronics Center scott.savage@medtronic.com +1-480-303-4749 Assistant Chair Vikas Gupta Texas Instruments gvikas@ti.com +1-214-567-3160 Jo Caers Royal Philips
Sridhar Canumalla Microsoft Corporation
Hirofumi Nakajima Consultant
Tim Chaudhry Broadcom Corporation
Valerie Oberson IBM Corporation
Tz-Cheng Chiu National Cheng Kung University
Tom Poulin Aerie Engineering
Darvin R. Edwards Edwards Enterprises
Tom Swirbel Motorola, Inc.
Deepak Goyal Intel Corporation
Paul Tiner Texas Instruments
Dongming He Qualcomm, Inc.
Sean Too Microsoft Corporation
Toni Mattila Aalto University
Andy Tseng Taiwan Semiconductor Mfg. Company, Ltd.
Keith Newman Hewlett-Packard
Shaw Fong Wong Intel Corporation
Donna M. Noctor Siemens Industry, Inc.
Jie Xue Cisco Systems, Inc.
John H. L. Pang Nanyang Technological University
Jin Yang Intel Corporation
S. B. Park Binghamton University
Tonglong Zhang Nantong Fujitsu Microelectronics Ltd.
Lakshmi N. Ramanathan Microsoft Corporation
Electronic Components & RF Chair Manos M. Tentzeris Georgia Institute of Technology etentze@ece.gatech.edu +1-404-385-6006
Ephraim Suhir University of California, Santa Cruz Jeffrey Suhling Auburn University Dongji Xie NVIDIA Corporation Assembly & Manufacturing Technology Chair Shichun Qu Fairchild Semiconductor shichun.qu@fairchildsemi.com +1-408-822-2064 Assistant Chair Shawn Shi Medtronic Corporation shawn.shi@medtronic.com +1-480-929-5614 Sai Ankireddi Soraa, Inc. Sharad Bhatt Shanta Systems, Inc. Claudius Feger IBM Corporation Mark Gerber Texas Instruments Paul Houston Engent Sa Huang Medtronic Corporation Vijay Khanna IBM Corporation Chunho Kim Medtronic Corporation Wei Koh Pacrim Technology Choon Heung Lee Amkor Technology Mali Mahalingam Freescale Semiconductor, Inc.
Assistant Chair Nanju Na IBM Corporation nananju@us.ibm.com +1-512-286-9677 Amit P. Agrawal Cisco Systems, Inc. Eric Beyne IMEC Prem Chahal Michigan State University Craig Gaw Freescale Semiconductor, Inc. Apostolos Georgiadis Centre Tecnologic de Telecomunicacions de Catalunya (CTTC) Abhilash Goyal Oracle T. S. Horng National Sun Yat-Sen University Rockwell M. Hsu Tiva Systems, Inc. at Cisco Systems, Inc. C. P. Hung Advanced Semiconductor Engineering, Inc. Lih-Tyng Hwang National Sun Yat-Sen University Mahadevan K. Iyer Texas Instruments, Inc. Timothy G. Lenihan TGL Consulting Li Li Freescale Semiconductor, Inc. Sebastian Liau ITRI Lianjun Liu Freescale Semiconductor, Inc.
Debendra Mallik Intel Corporation
Albert Lu Singapore Institute of Manufacturing Technology
Jae-Woong Nah IBM Corporation
Andrea Paganini IBM Corporation
Albert F. Puttlitz Mechanical Eng. Consultant
Tim Chen Darbond Technology Co., Ltd.
Tony Mak Middlesex Community College
Jai Agrawal Purdue University
P. Markondeya Raj Georgia Institute of Technology
Yu-Hua Chen Unimicron
Tom Reynolds T3 Group LLC
Bing Dang IBM Corporation
Dan Oh Altera Corporation
Vasudeva P. Atluri Renavitas Technologies
Luca Roselli University of Perugia
Don Frye Donâ&#x20AC;&#x2122;s Material Development & Innocentrix
Gamal Refai-Ahmed PreQual Technologies Corporation
Mark Bachmann University of California, Irvine
Clemens Ruppel TDK
C. Robert Kao National Taiwan University
Hideki Sasaki Renesas Electronics Corporation
Dong Wook Kim Qualcomm, Inc.
Grit Sommer Infineon Technologies AG
Chin C. Lee University of California, Irvine
Frank Theunis Qualcomm Technologies Netherlands B.V.
Grace Yi Li Intel Corporation
Leena Ukkonen Tampere University of Technology
Kwang-Lung Lin National Cheng Kung University
Interconnections Chair Matthew Yao GE Energy Management matthew.yao@ge.com +1-412-963-3244
Daniel D. Lu Henkel Corporation
Assistant Chair Li Li Cisco Systems, Inc. LiLi2@cisco.com +1-408-527-0801
Hongtao Ma Lightera Corp. Mikel Miller Draper Laboratory Kyung-Wook Paik KAIST Mark Poliks i3 Electronics, Inc.
Sandeep Sane Intel Corporation Jaemin Shin Samsung Electronics Co., Ltd. Suresh K. Sitaraman Georgia Institute of Technology G. Q. (Kouchi) Zhang Delft University of Technology (TUD) Optoelectronics Chair Kannan Raj Oracle kannan.raj@oracle.com +1-858-526-9208
Karlheinz Bock Fraunhofer EMFT John Cunningham Oracle Rabindra N. Das Endicott Interconnect Technologies, Inc. Steve Greathouse Plexus Corporation Joana Maria IBM Corporation Goran Matijasevic University of California, Irvine
Assistant Chair Stefan Weiss II-VI Laser Enterprise GmbH sweiss@laserenterprise.com +41-44-455-8732
Dave Peard Henkel Corporation
Fuad Doany IBM Corporation
Jintang Shang Southeast University
Gordon Elger Technische Hochschule Ingolstadt
Klaus-Juergen Wolter Technische Universitaet Dresden
Z. Rena Huang Rensselaer Polytechnic Institute
Allison Xiao Henkel Corporation
Koneru Ramakrishna Hewlett-Packard Company
William Chen Advanced Semiconductor Engineering, Inc.
Dwayne Shirley Qualcomm Technologies, Inc.
Kathy Cook Ziptronix
Ivan Shubin Oracle
Rajen Dias Intel Corporation
Yoichi Taira IBM Corporation
Bernd Ebersberger Intel Mobile Communications
Lejun Wang Qualcomm Technologies, Inc.
Takaaki Ishigure Keio University
Jimin Yao Intel Corporation
Takafumi Fukushima Tohoku University
Myung Jin Yim Intel Corporation
Soon Jang ficonTEC USA
Tom Gregorich Micron
Tieyu Zheng Microsoft Corporation
Harry G. Kellzi Teledyne Microelectronic Technologies
Changqing Liu Loughborough University
Modeling & Simulation Chair Zhaoqing Chen IBM Corporation zhaoqing@us.ibm.com +1-845-435-5595
Michael Leers Fraunhofer ILT
Interactive Presentations Chair Mark Poliks i3 Electronics, Inc. mark.poliks@i3electronics.com +1-607-727-7104
Assistant Chair Yong Liu Fairchild Semiconductor Corporation yong.liu@fairchildsemi.com +1-207-761-3155
Alex Rosiewicz Gooch & Housego
Ramachandra Achar Carleton University
James E. Morris Portland State University
Andrew Shapiro JPL
Kemal Aygun Intel Corporation
Lou Nicholls Amkor Technology, Inc.
Wendem Beyene Rambus, Inc.
Hiren Thacker Oracle
Gilles Poupon CEA LETI
Daniel de Araujo Nimbic, Inc.
Katsuyuki Sakuma IBM Corporation
L. J. Ernst Ernst Consultants
Lei Shan IBM Corporation
Xuejun Fan Lamar University
Katsuaki Suganuma Osaka University
Xiaoxiong (Kevin) Gu IBM Corporation
Chuan Seng Tan Nanyang Technological University
Bruce Kim City University of New York
Materials & Processing Chair Diptarka Majumdar Superior Graphite diptarka@yahoo.com + 1-919-418-8025
Pradeep Lall Auburn University
Wei-Chung Lo ITRI Nathan Lower Rockwell Collins, Inc. James Lu Rensselaer Polytechnic Institute Voya Markovich Microelectronic Advanced Hardware Consulting, LLC
Assistant Chair Stephanie Potisek Dow Chemical slpotisek@dow.com +1-979-238-9573 Choong Kooi Chee Intel Corporation
Michael Lamson Consultant En-Xiao Liu Institute of High Performance Consulting, A*STAR
Masanobu Okayasu Oclaro Japan, Inc.
Henning Schroeder Fraunhofer IZM
Masao Tokunari IBM Corporation Jean Trewhella IBM Corporation Shogo Ura Kyoto Institute of Technology Ping Zhou LDX Optronics, Inc. Special Topics (Emerging Technologies) Chair Nancy Stoffel General Electric stoffel@ge.com +1-518-387-4529
Assistant Chair Ibrahim Guven University of Arizona guven@email.arizona.edu +1-520-626-2257 Swapan Bhattacharya Georgia Institute of Technology Rao Bonda Amkor Technology Mark Eblen Kyocera America, Inc. Michael Mayer University of Waterloo Nam Pham IBM Corporation Patrick Thompson Texas Instruments, Inc. Professional Development Courses Chair Kitty Pearsall Boss Precision, Inc. kitty.pearsall@gmail.com +1-512-845-3287
Sheng Liu Huazhong University of Science and Technology
Assistant Chair C. S. Premachandran GLOBALFOUNDRIES premachandrancs@globalfoundries.com +1-518-305-7317
Assistant Chair Jeffrey Suhling Auburn University jsuhling@eng.auburn.edu +1-334-844-3332
Erdogan Madenci University of Arizona
Isaac Robin Abothu Siemens Medical Solutions USA Inc.
Eddie Kobeda IBM Corporation
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PROFESSIONAL DEVELOPMENT COURSES
Tuesday, May 27, 2014 Kitty Pearsall, Chair Boss Precision, Inc. kitty.pearsall@gmail.com +1-512-845-3287 Jeff Suhling, Assistant Chair Auburn University jsuhling@eng.auburn.edu +1-334-844-3332
MORNING COURSES 8:00 AM – 12:00 PM 1. LEAD-FREE SOLDER JOINT RELIABILITY MATERIAL CONSIDERATION Course Leader: Ning-Cheng Lee – Indium Corporation Course Objectives: This course covers the detailed material considerations required for achieving high reliability for lead-free solder joints. The reliability discussed includes joint mechanical properties, development of type and extent of intermetallic compounds (IMC) under a variety of material combinations and aging conditions and how those IMCs affect the reliability. The failure modes, thermal cycling reliability, and fragility of solder joints as a function of material combination, thermal history, and stress history will be addressed in detail, and novel alloys with reduced fragility will be presented. Electromigration, corrosion, and tin whisker growth will also be discussed. Furthermore, the reliability of through-hole solder joints will be reviewed, and recommendations will be provided, particularly for thick boards. The emphasis of this course is placed on the understanding of how the various factors contributing to the failure modes, and how to select proper solder alloys and surface finishes for achieving high reliability. Also presented are the desirable future alloys and fluxes in order to meet the challenge of miniaturization. Course Outline 1. Implementation Status 2. Prevailing Materials Alloys and Finishes 3. Surface Finishes Issues of ENIG, Immersion Ag, and Immersion Sn 4. Mechanical Properties Shear, Pull, and Creep 5. Intermetallic Compounds Effect of Cu, Ni, Other Additives, and Heat History 6. Failure Modes Grain Deterioration, Orientation, Mixed Alloys, and Interfacial Voiding 7. Thermal Cycle Reliability Effect of Cycling Condition, Surface Finishes, and Reflow Temperature 8. Reliability of Through-Hole Joints Large and Thick Boards, Partially Filled Through-hole 9. Fragility Effect of Surface Finishes, Alloys, Reflow, Strain Rate, Aging, Cycling, and IMC 10. Electromigration Effect of Current Density, Back Stress, and Cu UBM Thickness
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11. Corrosion SAC and Performance of Surface Finishes Under Harsh Conditions 12. Tin Whisker – Causes of Formation, Methods for Control
timely failure analysis of next generation package technologies. A discussion on the strategies for use of these techniques and a flow chart for failure analysis will be included.
Who Should Attend: Anyone interested in achieving high reliability lead-free solder joints and who wants to know how to achieve it should take this course.
Course Outline: 1. Package technology – Trends, drivers & challenges 2. Failure analysis challenges offered by package technology roadmap 3. Introduction to the methodology of failure analysis of organic packages 4. Current analytical capabilities for package fault isolation and failure analysis 5. Strategies to use these techniques to identify failures and understand failure mechanisms 6. Analytical capabilities to support next generation packaging technologies 7. Typical failure analysis flow charts for opens and shorts. 8. Failure modes/mechanisms including chip/package interactions, 1st/2nd level interconnections and package/board substrates. 9. Failure analysis case studies
2. WAFER LEVEL PACKAGING Course Leader: Luu Nguyen – Texas Instruments Course Objectives: This course will provide an overview of the Wafer Level-Chip Scale Packaging (WL-CSP) technology. The market drivers, end applications, benefits, and challenges facing industry-wide adoption will be discussed. Typical WL-CSP configurations (bump on pad, bump on polymer, fan-out) will be reviewed in terms of their construction, manufacturing processes, materials and equipment, and electrical and thermal performance, together with package and board level reliability. Since the technology marks the convergence of fab, assembly, and test, discussion will address questions on the industrial supply chain such as: Course Outline: 1. Does it fit best with front-end or back-end processing? 2. Will it be applicable and cost-effective for memory and other complex devices such as ASICs and microprocessors? 3. Are the current standards for design rules, outline, and reliability applicable? Extensions to higher pin count packages and other areas such as RF and MEMS will be reviewed. 4. Future trends will also be covered -- Enhanced lead-free solder balls -- Large die size -- Wafer level underfill -- Thin and ultra-thin WL-CSP -- RDL (redistribution layer) -- Stacked WL-CSP -- MCM in “reconstituted wafers” -- Embedded components, etc. Who Should Attend: The course will be useful to the following groups of engineers: Newcomers to the field who would like to obtain a general overview of WL-CSP and R&D practitioners who would like to learn new methods for solving CSP problems and are considering WL-CSP as a potential alternative for their packaging solutions. 3. PACKAGE FAILURE ANALYSIS - FAILURE MECHANISMS AND ANALYTICAL TOOLS Course Leaders: Rajen Dias and Deepak Goyal – Intel Corporation Course Objectives: The technical course will provide an overview of the failure modes and mechanisms observed in organic packages. A brief introduction to the methodology of failure analysis of these packages will be described. The focus of the course will be on package failure mechanisms highlighted by case studies and on analytical tools and techniques currently used and the future direction for the tools and techniques required for successful and
Who Should Attend: Engineers and technical managers who are involved in package technology development, reliability assessment of packages and failure analysis should attend. 4. NEXT FRONTIER IN ELECTRONICS: SYSTEMS SCALING FOR SMART MOBILE SYSTEMS Course Leader: Rao R. Tummala – Georgia Institute of Technology Course Objectives: Transistor scaling, starting with the invention of the transistor in 1949, made electronics the largest single, $1.5T global industry, serving a variety of individual industries that span computing, communications, consumer, automotive and others. The basis for this industry is a result of singular focus in transistor scaling, leading to a 5B transistor chip, involving dozens of semiconductor companies around the globe. But the electronics landscape is changing, driven by a new industry that integrates all these individual industries into so-called “Smart Mobile Systems” that promise to perform every imaginable function, in the smallest size and lowest cost that every global person could afford. Such a new frontier, however, requires revolutionary technologies referred to as System Scaling, in contrast to transistor scaling during the last 60 years. Smart mobile systems are expected to drive unparalleled electronics technology paradigms in system miniaturization, functionality, and cost. The system scaling technologies are many that need to be explored, developed, integrated, interconnected, tested and commercialized. The new system scaling technologies include new electrical, mechanical and thermal designs, new system substrate
IMPORTANT NOTICE It is extremely important to register in advance to prevent delays at door registration. Course sizes are limited.
materials and processes, integration of ultra-thin actives, exploration and integration of ultra-thin passives, miniaturized and innovative thermal structures, thin film power storages such as batteries, and interconnections between all of these. These need to perform a variety of circuits and system functions that range from digital, analog, RF, wireless health, power, bio, MEMS and network sensors. This course presents the vision, strategy, challenges, and status of system scaling technologies. Course Outline: 1. 2D, 2.5D, and 3D Substrates 2. Off-chip Electrical and Optical Interconnections 3. Board level Interconnections 4. Advanced Passives and their Integration with Actives 5. Electrical Designs 6. Thermal Designs 7. Mechanical Designs Who Should Attend: This is a new course on a strategic topic of great interest to industry R&D executives, senior managers and technical leaders who are developing both short and long-term strategies for their companies in every electronic technology. 5. POLYMERS AND NANOCOMPOSITES FOR ELECTRONIC AND PHOTONIC PACKAGING: RECENT ADVANCES ON MATERIALS AND PROCESS Course Leaders: C. P. Wong – Georgia Institute of Technology; Daniel Lu – Henkel Corporation Course Objectives: Polymers and nanocomposites are widely used in electronic and photonic packaging as adhesives, encapsulants, insulators, dielectrics, molding compounds and conducting elements for interconnects. These materials also play a critical role in the recent advances of low-cost, high performance novel No Flow Underfills, Reworkable Underfills for Ball Grid Array (BGA), Chip Scale Packaging (CSP), System in a Package (SIP), Direct Chip Attach (DCA), Flip-Chip (FC), Paper-thin IC and 3D Packaging, Conductive Adhesives (both ICA and ACA), Embedded Passives (high K polymer composites), nano particles and nanofunctional materials such as CNTs and graphenes. It is imperative that both material suppliers, formulators and their users have a thorough understanding of polymeric materials and the recent advances on nano materials and their importance in the advances of the electronic packaging and interconnect technologies. Course Outline: 1. Fundamentals of Polymers and Materials Science and Engineering 2. Materials Needs for Next Generation Electronic Packaging 3. Novel Nanocomposites for Flip-Chip Underfills Applications 4. Recent Advances on Nano Lead-free Alloys for High-performance Components 5. Interconnects 6. Low-cost High-performance Lead-free
Interconnect Materials and Processes 7. Recent Advances on CNTs as Thermal Interface Materials (TIMs) 8. Lotus Effect Coating for Self-cleaning Applications 9. Fundamentals of Electrically Conductive Adhesives (ECAs) 10. Recent Advances on Conductive Adhesives 11. Recent Advances on Nano Conductive Adhesives Who Should Attend: Engineers, scientists, and managers involved in the design, process, and manufacturing of IC electronic components and hybrid packaging, electronic material suppliers involved in materials manufacturing and research & development should attend. 6. POWER ELECTRONICS PACKAGING, RELIABILITY, AND THERMAL MANAGEMENT Course Leader: Patrick McCluskey – University of Maryland Course Objectives: Power electronics are becoming ubiquitous in engineered systems as they replace traditional ways to control the generation, distribution, and use of energy. They are used in products as diverse as home appliances, cell phone towers, aircraft, wind turbines, radar systems, and smart grids. This widespread incorporation has resulted in significant improvements in efficiency over previous technologies, but it also has made it essential that the reliability of power electronics be characterized and enhanced. Recently, increased power levels, made possible by new compound semiconductor materials, combined with increased packaging density have led to higher heat densities in power electronic systems, especially inside the switching module, making thermal management more critical to performance and reliability of power electronics. Following a review of heat transfer principles and thermal management techniques, along with prognostic health management approaches to assess and ensure reliability, this short course will present the latest developments in the packaging, assembly, and thermal management of power electronic modules and systems, along with modeling and testing techniques. This course will emphasize thermal packaging techniques capable of addressing performance limits and reliability concerns associated with increased power levels and power density in power electronic components. Course Outline: 1. Introduction to Packaging for Reliable Power Electronic Systems 2. Passive Thermal Management Techniques (Thermal Interface and Phase Change Material) 3. Active Thermal Management Techniques (Air, Single Phase Liquid, Two Phase, Thermoelectric) 4. Durability Assessment (Failure Modeling, Simulation, Testing, and Condition Monitoring)
5. Reliability and Thermal Packaging of Active Devices (Si, SiC, GaN) 6. Reliability and Thermal Packaging of Switching Modules 7. Reliability in Assembly Level Thermal Packaging (Boards, Passives, Solder) Who Should Attend: This course is intended for new and established engineers and technical managers in the field of electronic packaging who would like to learn more about the thermo-mechanical issues involved in reliably packaging devices and circuits for applications involving high voltage, current, and power dissipation. 7. FUNDAMENTAL CONCEPTS OF RELIABILITY AND MECHANICS IN ELECTRONIC PACKAGING Course Leaders: Shubhada Sahasrabudhe and Sandeep Sane – Intel Corporation Course Objectives: The objective of this course is to provide an overview of an integrated methodology that combines the fundamentals of reliability and solid mechanics to perform knowledge based decision making. The methodology is about comprehensively understanding mechanics of failures and correlating it to empirical observations. This unified method drives proactive product risk assessment at use conditions (UC) and optimizes future product designs for reliability. The course will introduce key elements of reliability like UC, accelerated/ life tests, methods of statistical data analysis, acceleration factor models for different failure mechanisms, and use of statistics to project reliability performance at UC. It will provide an overview of the basic concepts of solid mechanics such as stress-strain curves, characterization of material behavior, stress analysis methods including FEA, and fundamentals of fracture mechanics. Deriving on these concepts, the course will introduce a unified methodology for using mechanics based reliability assessment. Comprehensive case studies highlighting different package risk areas will be introduced to showcase the application of methodology to real examples. The concepts of design for reliability and experiment planning will be discussed. Hands-on exercises will help students reinforce the skills learned. Course Outline: 1. Introduction to Quality and Reliability 2. Overview of key components of reliability statistics and accelerated testing 3. Hands-on Class Exercise - I 4. Introduction to solid mechanics 5. Key components of solid mechanics: stress/ strain curves, material characterization, Finite Element Analysis 6. Overlapping areas between reliability and mechanics 7. Overview of the unified reliability assessment methodology using mechanics 8. Unified reliability assessment methodology applied to packaging - Case Study 1
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9. Unified reliability assessment methodology applied to packaging - Case Study 2 10. Hands-on Class Exercise - II 11. Summary of key learning Who Should Attend: Engineers working on Packaging, Reliability and Materials should attend this class. 8. PRODUCT QUALIFICATION AND SUPPLY CHAIN RESPONSIBILITIES Course Leader: Michael Pecht – University of Maryland Course Objectives: Electronic products are changing very rapidly, customers have more choices, tremendous price pressure exists on suppliers, and there is pressure to test quickly. However, the traditional test and qualification standards are not working. During the past 10 years, there has been an increasingly large number of products that have passed qualification tests but have failed in the field. The resulting costs of these failures have been in the hundreds of millions of dollars for many companies. This short course presents the role of qualification in product development and the responsibilities within product supply chains. A process to establish proper qualification methods will be provided. Virtual qualification, accelerated testing, target application requirements, and failure mechanisms and models will be discussed. In addition, various advanced qualification techniques, including prognostics and in-situ product monitoring methods will be overviewed. Course Outline: 1. Role of qualification in product development 2. Traditional test and qualification standards 3. Virtual qualification, accelerated testing, etc. 4. Advanced qualification techniques 5. Role of suppliers in qualification within the supply chain 6. Summary Who Should Attend: All packaging engineers with a desire to learn or enhance their knowledge on what it takes to ensure a high reliable, high quality product going out the door to the field.
AFTERNOON COURSES 1:15 PM – 5:15 PM 9. HIGH-FREQUENCY MODELING AND OPTIMIZATION OF INTERCONNECTIONS IN ELECTRONIC PACKAGING Course Leaders: Ivan Ndip and Michael Toepper – Fraunhofer IZM Course Objectives: Novel electronic packaging and system-integration concepts are continuously being developed to meet the ever-increasing demand for low-cost and high-performance systems. To ensure highspeed signal transmission, all interconnections in chip packages/interposer and PCBs must be capable of supporting broadband signals without degrading signal/power integrity beyond
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acceptable limits. Furthermore, the choice of the right packaging material for interposers/boards plays a crucial role in the cost and performance of the entire system. The objective of this course is to provide and illustrate methods for efficient high-frequency modeling and optimization of interconnections in electronic packaging, considering signal/power integrity and EMC effects in different packaging materials/structures. The properties of materials (laminates, silicon, ceramics, and glass) for advanced packaging will first be presented. This will be followed by an illustration of methods for high-frequency modeling and optimization of bond wires, impedance-controlled transmission lines, and through-hole vias in laminates, silicon, ceramic, and glass substrates. The performance of transmission lines and vias in different packaging materials for interposer/board applications will be compared. Finally, methods for suppressing noise coupling and EMC-related effects in power distribution networks will be discussed. The modeling, simulation and measurement results will be presented in a wide frequency range, from 100 MHz to 100 GHz. Course Outline: 1. Materials for advanced packaging (laminates, silicon, ceramics, and glass) 2. Basic concepts for efficient high-frequency design 3. High-frequency modeling/optimization of transmission-lines on laminates, silicon, ceramic, and glass substrates/interposers 4. In-depth study of vertical interconnections (examples: bond wires and through-hole vias) 5. Modeling and optimization of bond-wires considering their realistic shapes and bonding parameters 6. Methods for modeling and optimization of vias considering geometrical/return-path discontinuities 7. Illustration of these methods using throughhole vias in laminates, silicon, and glass 8. Through Silicon Vias (TSVs) 9. Modeling and analysis of slow-wave, skineffect, and quasi-TEM modes in TSVs 10. Effects of low, medium, and high-resistivity silicon on TSV performance 11. New concepts/structures for improving TSV performance in low/medium resistivity silicon 12. Through Glass Vias (TGVs) 13. Impact of glass substrates with different alkaline content on TGV performance 14. Effects of geometrical configurations and dimensions of TGVs on their performance 15. Comparison of transmission lines and through-hole vias in different packaging materials 16. Methods for minimizing noise coupling and EMC-related issues in Power Distribution Networks Who Should Attend: Engineers, researchers, designers, technical managers, and graduate students involved in the process of electrical modeling/layouts/ design/fabrication/integration of electronic packages, interposers, printed circuit boards, and interconnections in different packaging technologies (ceramic, glass, silicon, and laminates) should attend this class.
10. SHOCK–IMPACT RELIABILITY OF PORTABLE ELECTRONICS Course Leader: Pradeep Lall – Auburn University Course Objectives: Portable electronics such as smartphones, tablets and laptops may be subjected to shock and vibration in transportation handling and normal usage. Fine-pitch electronic components are placed in ever closer vicinity of the product housing. The products may be dropped from ear-level, waist-level or desk-level depending on application. Electronic components may be subjected to several thousand G’s of acceleration often causing damage to interconnects and silicon devices mounted on the circuit-board in addition to LED displays. Presently, the JEDEC test standard JESD22-B111 is used to test component robustness. However, ensuring robustness of products in shock-impact is more involved comprising decisions regarding modeling of individual components, interfaces, board assemblies, housing materials and interactions. An analyst must make decisions regarding model complexity, constitutive behavior, initial conditions and multi-surface contact during the drop event. High-speed experimental techniques are needed to capture the event. Course Outline: In this course, the topics covered will include: 1. Approaches for measurement of shock-level in products 2. High-speed strain measurement 3. Methods for data analysis 4. Methods for modeling board assemblies subjected to shock-impact 5. Model development for portable products 6. Algorithms for data reduction and parameter extraction 7. Approaches for life prediction 8. Statistical assessment of uncertainty of system survivability in mechanical shock Who Should Attend: Designers of electronic packaging, reliability engineers at part manufacturers and OEMS, component engineers responsible for qualifying new technology. The course is intended to introduce the students to shock-survivability modeling and experimental techniques for electronic systems. Specifically the students will have the knowledge needed to: • • • •
Identify solutions for ensuring shock survivability of products and systems Use experimental and computational methods for ensuring shock survivability Develop finite element models for board assemblies and portable products Predict life under mechanical shock
11. MOISTURE AND MEDIA INFLUENCE ON MICROELECTRONIC PACKAGE RELIABILITY Course Leaders: Tanja Braun and Hans Walter – Fraunhofer IZM Course Objectives: Many electronic products used in different applications, such as automotive and medical applications, are exposed to extreme loading profiles such as high temperatures, random vibrations, or humid and even wet environments. Absorbed moisture has a plasticizing effect on the
physical properties of polymers. Furthermore, moisture leads to corrosion of metallic parts of the devices; therefore molding compounds are used to protect sensible electronics. Polymer systems, for example epoxy molding compounds, adhesives, underfills etc., tend to absorb water molecules and exhibit a swelling behavior. Since most other materials involved do not swell when exposed to moisture, a stress between the materials is induced which is similar in origin (dimensional change in materials) and magnitude as the thermal mismatch induced stresses or chemical shrinkage. Consequently, moisture plays an important role in the reliability of microelectronic applications. Thus it is important to know both absorption and desorption properties of polymers used in such devices. For the indication of failure mechanisms and to estimate the lifetime of electronic products, temperatures and moisture concentration at more elevated levels than usual are used to accelerate tests. The workshop provides a comprehensive overview on moisture and other media-induced changes in properties of micro relevant materials used for microelectronic packaging in automotive or medical applications. Related reliability issues will be discussed and application examples shown. Course Outline: 1. Introduction to moisture sorption, diffusion and swelling in polymers 2. Overview of state of the art measurement equipment 3. Important aspects of encapsulation technologies for non-hermetic packaging 4. Moisture and media induced changes in material properties 5. Simulation of small molecule transport and swelling by FEM and molecular dynamics 6. Package reliability enhancement e.g. by introduction of barrier layer Who Should Attend: The course is aimed at engineers in the field of microelectronic package design and reliability engineering, which will learn about incorporation of moisture induced phenomena into design rules for best device performance. It is also aimed at engineers at management level who are provided with knowledge that enables them to make decisions on materials and design options. 12. 3D IC PACKAGING AND 3D SI INTEGRATION Course Leader: John Lau – Industrial Technology Research Institute Course Objectives: 3D IC packaging and 3D IC integration are different. In general, the TSV (through-silicon via) separates 3D IC packaging from 3D IC integration because the latter use TSVs, but 3D IC packaging does not. TSV is the heart of 3D IC integration. It provides the opportunity for the shortest chip-to-chip, and the smallest pad size and pitch of interconnects. The potential high volume manufacturing of 3D IC integration is: (1) memory-chip stacking, (2) wide I/O memory (or logic-on-logic), (3) wide I/O DRAM, wide I/O 2, HMC, and HBM, and (4) wide I/O interface (or 2.5D IC integration). In this presentation, the supply chains and the critical steps such as FEOL, MOL, BEOL, TSV, MEOL (middle-end-of-line),
assembly, and test and their ownerships for high-volume manufacturing for those 4 groups of 3D IC integration will be discussed. The 3D IC packaging, which has been keeping 3D IC integration away from volume production, will be briefly mentioned first. Key enabling technologies such as TSV forming and filling, front and backside metallization, RDL, temporary bonding and de-bonding, and microbumping, assembly and reliability will be presented and discussed. All the materials are based on the papers and books published by the lecturer and others. Course Outline: 1. 3D IC Packaging 2. TSV Technology 3. Micro Bumping, Assembly, and Reliability 4. 3D IC Integration 5. 2.5D IC Integration 6. Supply Chains and Ownerships for 2.5D/3D IC Integration 7. Thermal Management of 2.5D/3D IC Integration 8. 3D MEMS/IC Integration 9. 3D LED/IC Integration 10. Summary Who Should Attend: If you (students, engineers, and managers) are involved with any aspect of the electronics, LED, MEMS, and optoelectronic industry, you should attend this course. It is equally suited for R&D professionals and scientists. 13. POLYMERS IN SEMICONDUCTOR PACKAGING INCLUDING 2.5D AND 3D INTEGRATION Course Leader: Jeffrey Gotro – InnoCentrix, LLC Course Objectives: The course will provide a broad overview of polymers used in semiconductor packaging and the important structure-property-processperformance relationships. We will cover in more depth the chemistries, material properties, and process considerations for adhesives, underfills, coatings and mold compounds. Additionally, we will provide an introduction to common thermal analysis methods (DSC, DMA, TMA, and TGA) used to characterize thermosetting polymers used in semiconductor packaging. Finally, the course will provide an introduction to the rheological performance of polymer-based materials used in packaging semiconductors. In most cases, adhesives, underfills, mold compounds and coatings are applied as a viscous liquid and then cured. The flow properties of these materials are critical to performance in high volume manufacturing. The course will provide an introduction to rheology measurements and examples of rheology issues in semiconductor packaging. Course Outline: 1. Thermosetting polymers versus thermoplastics 2. Temperature dependence of physical properties 3. Thermosetting polymers; curing, curing mechanisms, network formation 4. Overview of key chemistries used (epoxies, acrylates, polyimides, bismaleimides) 5. Chemistry of die attach adhesives (paste and film) and capillary underfills 6. Mold compound chemistry and technology
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Polymer challenges in 2.5D and 3D packaging Polymers used in embedded wafer level packaging Packaging substrate materials Introduction to rheological characterization methods; types of rheometers and basic techniques Introduction to the rheological properties of adhesives Key rheology properties; shear thinning, viscosity, rheology changes during curing Rheology during curing (chemorheology) Thermosetting polymers versus thermoplastics
Who Should Attend: Packaging engineers involved in the development, production, and reliability testing of semiconductor packages would benefit from the course. R&D professionals interested in gaining a basic understanding of the structure/property/ process/performance relationships in polymers and polymer-based materials used in electronic packaging will also find this course valuable. 14. FLIP CHIP TECHNOLOGY Course Leaders: Eric Perfecto – IBM Corporation; Shengmin Wen – Amkor Technology Course Objectives: This course will cover all aspects of the flip chip technology used in today’s flip chip products, including the lead free solder bumping and highly customized Cu Pillar bumping technologies. Single chip, multichip, single unit based BGA package as well as strip based chip scale packages, chipon-chip, and 2.5D/3D flip chip packages will all be discussed and demonstrated. It will detail and compare the various UBM and solder depositions methods. It will include process considerations when joining various method bumped dies to various types of substrate (organic laminate, ceramic and Si substrates). This course will cover the accelerated reliability tests, the failure types and the analytical tools used to identify defect root cause. A substantial portion of this course will be covering the Cu Pillar flip chip technologies with highly customized bumping and assembly process that are applied to flip chip packages inside today’s mobile devices. Failure modes and solutions associated with flip chip assembly implementation, such as barrier consumption, Kirkendall void formation, BEOL dielectric cracking, electromigration, etc. will be included respectively in the related subjects of the whole course. The students are encouraged to bring topics and technical issues from their daily job function for group discussions. Course Outline: 1. Introduction to flip chip 2. UBM metal selection 3. Flip chip solder deposition processes 4. Cu Pillar bumping 5. C4 and Cu Pillar fabrication issues 6. C4 and Cu Pillar electromigration 7. Chip-package interaction and white bump
IMPORTANT NOTICE It is extremely important to register in advance to prevent delays at door registration. Course sizes are limited. 11
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Polyimide and redistribution options Cu Pillar flip chip summary Flip chip and Cu Pillar assembly NCP and thermal compression bonding Substrates technologies (2D & 2.5D) for Cu Pillar flip chip assembly 13. Integration options in Cu Pillar assembly and failure modes 14. Cu Pillar reliability Who should Attend: The targeted audience includes scientists, engineers and managers currently using flip chip (w/solder or Cu Pillar) or considering moving from wirebonding, as well as reliability, product or applications engineers who need a deeper understanding of flip chip advantages, limitations and failure mechanisms. 15. PACKAGE FAILURE MECHANISMS, RELIABILITY, AND SOLUTIONS Course Leader: Darvin Edwards – Edwards Enterprises Course Objectives: Major failure mechanisms for FC-BGA, plastic leaded, no lead, and TSV package types will be reviewed. These will include ILD damage under bumps and wire bonds, Cu vs. Au wire bond sensitivities, problems associated with delamination in the package, solder joint reliability, and system level problems such as drop and bend reliability. For each failure mechanism, the failure analysis techniques needed to verify the mechanism will be summarized. Key parameters that influence the failures will be highlighted. Process parameters, design techniques and materials selections that improve the reliability behavior of the packages will be provided with an emphasis on solving each of the issues. A brief discussion of reliability models as related to each failure mechanism will also be covered to give an understanding of the probability for field failure occurrence. The use of design guidelines to ensure that the failure modes are designed out will be encouraged. A methodology of test structures combined with qualification by similarity will be highlighted as a process for early detection of chip/package interaction failure mechanisms. The use of test structures to calibrate finite element models will be described. Course Outline: 1. Introduction and description of packages to be covered 2. Failure analysis techniques 3. FC-BGA package failure mechanisms 4. Molded package failure mechanisms 5. New failure mechanisms associated with TSV and Cu wire bond technologies 6. Materials characteristics and how they impact failure modes 7. Reliability models for failure mechanisms 8. Common test structures for mechanism identification and elimination 9. Qual by Similarity (QBS) methods 10. Using test structures for model calibration Who Should Attend: This class is intended for those responsible for package reliability, package development, package design, and package processing where knowledge of package failure mechanisms will prove useful.
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Both beginning engineers and those skilled in the art will benefit from the holistic description of the failure mechanisms, the FA techniques, and the solutions. 16. STATISTICS FOR ENGINEERING Course Leader: Patrick Thompson – Texas Instruments Course Objectives: This course will address the use of statistics in engineering design and test. A collection of data can be organized, analyzed and interpreted through the use of statistical techniques and models. The designer can leverage these to optimize a product design, increase the product quality and reliability as well as provide predictive control during the manufacturing process. This course will explore the various techniques and models used in industry today. The importance of sampling on various applications will be highlighted. Design of experiments and its advantages and varied approaches will be reviewed. Course Outline: 1. Engineering statistics – What it can do for you 2. Statistical techniques and models 3. Sampling techniques 4. Design of experiments 5. Examples of applications of these techniques Who Should Attend: Any materials and package engineer with an interest in product optimization, process control, product quality and reliability should attend this course. 17. THERMAL MATERIALS AND METROLOGY FOR ADVANCED PACKAGING Course Leaders: Ravi Mahajan – Intel Corporation; Kenneth Goodson – Stanford University Course Objectives: This course will explain the architectural motivations behind the evolution of packaging, examine key trends in package scaling, and describe how technology and market conditions constrain and guide packaging directions. In particular, we will examine the motivations behind the demand for 3D architectures and then describe some of the associated packaging challenges and solutions. The course will also describe the fundamental heat transfer phenomena and innovative material systems that are emerging in advanced packaging research and development. We will then focus on packaging materials as they influence and challenge the development of assembly processes, the stress state in the package, and thermal management. We will also describe the state of the art in metrology and modeling techniques including thermal properties, temperature, and stress analysis, followed by a discussion of real life applications. Some of the key upcoming challenges and future technology needs for the semiconductor industry will be discussed. Finally, we will summarize the exploratory DARPA/DoD investments on thermal materials for extreme heat fluxes and power densities, which may seed innovative commercial solutions in coming years.
Course Outline: 1. Introduction 2. Basic functions and constraints of a package 3. Market evolution of compute devices in the commercial space 4. Scaling driven trends for key physical attributes of the package 5. Evolution of package architectures & interconnects 6. Function of bandwidth demand and platform physical constraints 7. Challenges with manufacturing of 3D package architectures 8. Thermal challenges/potential solutions to unique to 3D architectures. 9. Thermal materials and metrologies 10. Advanced thermal materials and solutions 11. Spectrum of measurement techniques for thermal management including materials characterization 12. Modeling approaches at a fundamental physics level and in the packaging environment 13. Exploratory research 14. DARPA/DoD investments on thermal materials for extreme heat fluxes and power densities 15. Relevant frontier research including heat transport fundamentals at the nanoscale 16. Concluding remarks 17. Key upcoming packaging/materials challenges and future technology needs for the semiconductor industry 18. Key areas of academic research and corporate development moving forward Who Should Attend: This course is intended for packaging engineers and researchers in academia and research institutes who are involved in R&D for advanced package architectures and thermal management. The course is designed to be interactive and should be of interest to both newcomers and established technologists in both academia and industry. The course will feature both very applied information about trends and packaging solutions as well as fundamental information about the heat conduction mechanisms and related measurement and modeling strategies that are relevant. 18. THERMO-ELECTRICAL CO-DESIGN OF 3D CHIP STACKS Course Leaders: Avram Bar-Cohen and Ankur Srivastava – University of Maryland Course Objectives: This PDC focuses on the thermo-electrical co-design of three-dimensional chip stacks, which are poised to become the next packaging paradigm in the electronic industry. While this paradigm provides significant improvements in device density, interconnect delays, system integration, and computational efficiency, it is expected to lead to higher heat densities along with decreased access to individual chips and on-chip hotspots. Elevated chip and hotspot temperatures can be expected to lead to higher leakage power and slower switching transistors as well as higher thermal stresses in the chips and interconnects, thus compromising the performance and reliability of such chip stacks. Embedded cooling, utilizing microfluidics and
thermoelectric microcoolers, combined with high conductivity substrates and thermal interconnects, can overcome these stacking limitations. But, integration of chip layout and functional partitioning with thermal and mechanical design is essential to the successful exploitation of this packaging paradigm. This PDC throws light on the importance of “co-design” due to greater need for embedded cooling in 3D ICs. We underscore the need for better unification of the thermal and fluidic aspects of the system into an integrated co-design environment that enables designers to estimate the impact of the cooling solutions on the electrical aspects and vice versa. Such a co-design approach would be imperative for unlocking the high performance and energy efficiency of 3D ICs. Course Outline: 1. Packaging history and trends 2. Microfabrication of 3D chip stacks 3. Thermal management requirements for chips, chip stacks, and MMICs 4. Gen-2 remote cooling state-of-the-art: spreaders, TIMs, heat sinks, coldplates 5. Gen-3 embedded cooling options: microfluidics, conductive substrates, thermal interconnects, thermoelectric coolers 6. Electronic design automation 7. Thermo-electrical co-design case studies - Microfluidic channels and TSVs - 3D unified micro-fluidic thermal interconnect networks - Gate level optimizations unlocked by co-design - 3D CPU architectures enabled by co-design: impact on performance and energy efficiency 8. Future challenges and opportunities - Thermal management - Manufacturing issues - Integration issues Who Should Attend: IC package design engineers and managers that are looking to learn about the electrical performance design challenges and techniques; packaging SI/PI engineers to refresh their conceptual understanding of the fundamentals and the challenges posed by process limitations should attend this class.
CONTINUING EDUCATION UNITS
The IEEE Components, Packaging and Manufacturing Technology Society (CPMT) has been authorized to offer Continuing Education Units (CEUs) by the International Association for Continuing Education and Training (IACET) for all Professional Development Courses that will be presented at the 64th ECTC. CEUs are recognized by employers for continuing professional development as a formal measure of participation and attendance in “non-credit” self-study courses, tutorials, symposia and workshops. Complete details, including voluntary enrollment forms, will be available at the conference. All costs associated with ECTC Professional Development Courses CEUs will be underwritten by the conference, i.e. there are no additional costs for Professional Development Courses attendees to obtain CEU credit.
AREA ATTRACTIONS In the heart of the Walt Disney World®
Resort, the award-winning Walt Disney World Swan and Dolphin Resort is your gateway to Central Florida’s greatest theme parks and attractions. The resort is located in between Epcot® and Disney’s Hollywood StudiosTM, and nearby Disney’s Animal Kingdom® Theme Park and Magic Kingdom® Park. Come discover our 17 world-class restaurants and lounges, sophisticated guest rooms with Westin Heavenly Beds® and the luxurious Mandara Spa. Enjoy five pools, two health clubs, tennis, nearby golf, and many special Disney benefits, including complimentary transportation to Walt Disney World Theme Parks and Attractions, and the Extra Magic Hours benefit. Just minutes from the Walt Disney World Swan and Dolphin Resort is Downtown Disney’s West Side and Marketplace. Downtown Disney’s West Side showcases top-notch restaurants, a 24-screen AMC Pleasure Island movie theater, and other uncommon shops. Here you’ll also find the exquisite Cirque du Soleil La Nouba live entertainment show and the DisneyQuest Indoor Interactive theme park. Downtown Disney Marketplace provides an appealing place to take a break from Disney Theme Parks and Water Parks. Check out the largest Disney character store in the world. Or, for more of a respite, relax and dine at a lakeside restaurant. Should you decide to explore outside the Greater Lake Buena Vista area, Orlando boasts other parks and recreation areas tailor made for whatever your pleasure. Favorites include Universal Orlando, SeaWorld, Gatorland, and Winter Park.
IMPORTANT NOTICE AM PD Courses 1 through 8 or PM PD Courses 9 through 18 run concurrently. Make sure you indicate specific course numbers you plan to attend when you register online. See page 30 for registration information.
Coming to ECTC 2014!
Glass Learning Theater
May 28 - 29, 2014 5th Floor Northern Hemisphere Foyer
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Program Sessions: Wednesday, May 28, 8:00-11:40 a.m. Session 1: Interposer Technologies
Session 2: Advances in Copper Pillar & Solder Based Flip Chip Technologies
Session 3: Dynamic Mechanical Characterization
Committee: Advanced Packaging
Committee: Interconnections
Committee: Applied Reliability
Session Co-Chairs: Subhash L. Shinde – Sandia National Laboratory Tel: +1-505-284-2965 Email: slshind@sandia.gov
Session Co-Chairs: Tom Gregorich – Micron Email: tmgregorich@gmail.com
Session Co-Chairs: Darvin R. Edwards – Edwards Enterprises Tel: +1-972-571-7638 Email: darvin.edwards1@gmail.com
John Knickerbocker – IBM Corporation Tel: +1-914-945-3306 Email: knickerj@us.ibm.com
Bernd Ebersberger – Intel Corporation Tel: +49-89-998853-53281 Email: bernd.ebersberger@intel.com
Tim Chaudhry – Broadcom Corporation Tel: +1-949-926-5977 Email: timchaudhry@gmail.com
8:00 am – Various Bumping Volume Integration on 2.5D/3D Silicon TSV Interposer Ming-Hsien Yang, Shih-Liang Peng, Chen-Yu Huang, Chan-Lean Liu, Yi-Che Lai, Hsein-Wen Chen, Stephen Chen, and Steve Chiu – Siliconware Precision Industries Co., Ltd.
8:00 am – Challenges and Opportunities of 28nm Chip Package Interaction with Cu Bump at Fine Pitch Andy Bao, Yangyang Sun, Lily Zhao, Michael Han, and Geoffrey Yeap – Qualcomm Technologies, Inc.
8:00 am – Transient Dynamics Model and DIC Analysis of New Design for JEDEC JESD22-B111 Test Board Pradeep Lall, Kalyan Dornala, Di Zhang, and Jeff Suhling – Auburn University; Dongji Xie – Nvidia Corporation; Ife Hsu – Intel Corporation; Andy Zhang – Texas Instruments, Inc.
8:25 am – Process Integration, Improvements, and Testing of TSV Si Interposers for Embedded Computing Applications Scott Goodwin, John Lannon, Allan Hilton, Alan Huffman, Matthew Lueck, Erik Vick, Garry Cunningham, Dean Malta, Christopher Gregory, and Dorota Temple – RTI International
8:25 am – Electromigration for Advanced Cu Interconnect and the Challenges with Reduced Pitch Bumps Nokibul Islam, Kyungoe Kim, and Gwang Kim – STATS ChipPAC, Inc.
8:25 am – Interconnect Reliability Prediction for Wafer Level Packages (WLP) for Temperature Cycle and Drop Loading Conditions Tong Cui, Ahmer Syed, Steven Xu, Rey Alvarado, Beth Keser, and Mark Schwarz – Qualcomm Technologies, Inc.
8:50 am – Mechanically Flexible Interconnects (MFIs) with Highly Scalable Pitch and Large Stand-off Height for Silicon Interposer Assembly on Motherboard Chaoqi Zhang, Hyung Suk Yang, and Muhannad Bakir – Georgia Institute of Technology
8:50 am – Electromigration Performance of Cu Pillar Bump for Flip Chip Packaging with Bump on Trace by Using Thermal Compression Bonding Kuei Hsiao Kuo, Jason Lee, F. L. Chien, Rick Lee, and Cindy Mao – Siliconware Precision Industries Co., Ltd.; John Lau – ITRI
8:50 am – A Novel Drop Test Methodology for Highly Stressed Interconnects in Automotive Electronic Control Units Hossein Shirangi and Thomas Heinrich – Robert Bosch GmbH; Zi Wang – University of Stuttgart; Rahul Unnikrishnan – RWTH Aachen University
Refreshment Break: 9:15-10:00 a.m.
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10:00 am – Advancements in Fabrication of Glass Interposers Aric Shorey, John Keech, and Scott Pollard – Corning, Inc.; Matthew Lueck and Alan Huffman – RTI International
10:00 am – Flip-Chip Bonding Alignment Accuracy Enhancement Using Self-Aligned Interconnection Elements to Realize LowTemperature Construction of UltrafinePitch Copper Bump Interconnections Thanh-Tung Bui, Naoya Watanabe, Fumiki Kato, Katsuya Kikuchi, and Masahiro Aoyagi – National Institute of AIST
10:00 am – Early-State Crack Detection Method for Heel Cracks in Wire Bond Interconnects Michael Krüger and Klaus-Dieter Lang – Technical University Berlin; Stefan Trampert and Nils Nissen – Fraunhofer IZM
10:25 am – Large Area Interposer Lithography Warren Flack, Robert Hsieh, Gareth Kenyon, and Manish Ranjan – Ultratech Inc.; John Slabbekoorn and Andy Miller – IMEC
10:25 am – Development of Second Level Connection Method for Large Size CPU Package Shunji Baba, Masateru Koide, Manabu Watanabe, Kenji Fukuzono, and Tsuyoshi Yamamoto – Fujitsu Advanced Technologies, Ltd.; Seiki Sakuyama, Kozo Shimizu, Keishiro Okamoto, and Daisuke Mizutani – Fujitsu Laboratories, Ltd.
10:25 am – Study of Vibration Fatigue Life for Lead Free Solders with Testing and Modeling Masazumi Amagai – Texas Instruments, Inc.
10:50 am – Minimizing Interposer Warpage by Process Control and Design Optimization Mikael Detalle, Bart Vandevelde, Philip Nolmans, Joke Messemaeker, Mario Gonzalez, Andy Miller, Antonio La Manna, Gerald Beyer, and Eric Beyne – IMEC
10:50 am – Development of Fine Pitch Area Array Cu Pillar/Lead Free Solder Bumps for Large 28nm Die in Large Organic Flip Chip Packages John Osenbach, Suzanne Emerich, David Crouthamel, and Steven Cate – LSI Corporation; Danny Brady and Seung Min Hwang – Amkor Technology, Inc.
10:50 am – Crack Monitoring and Life Modeling Technique towards a High Thermal Cyclic and Mechanical Reliability of fcBGA Solder Joint Dongji Xie, Zhongming Wu, Min Woo, and Tom McMullen – NVIDIA Corporation
11:15 am – High Performance Integrated Passive Devices and Through Glass Via Interposer Technology Using Photosensitive Glass Jong-Min Yook, Dongsu Kim, and Jun Chul Kim – Korea Electronics Technology Institute
11:15 am – ELK Delam Improvement Methodology on CuBOP Package Nistec Chang, Albert Lan, and Mark Liao – Siliconware Precision Industries Co., Ltd.
11:15 am – Impacts of Fatigue Parameters on the Fatigue Reliability of Lead-Free Solder in Electronic Packaging Assembly Huili Xu – University of Texas, Arlington; Taekyu Lee – Cisco Systems, Inc.
Program Sessions: Wednesday, May 28, 8:00-11:40 a.m. Session 4: Bio & Flexible Electronics
Session 5: Silicon Photonics & LEDs
Session 6: Adhesives, Underfills, and Thermal Interface Materials
Committee: Emerging Technologies
Committee: Optoelectronics
Committee: Materials & Processing
Session Co-Chairs: Joana Maria – IBM Corporation Tel: +1-914-945-2649 Email: joanamaria@us.ibm.com
Session Co-Chairs: Fuad Doany – IBM Corporation Tel: +1-914-945-2831 Email: doany@us.ibm.com
Session Co-Chairs: Stephanie Potisek – Dow Chemical Tel: +1-979-238-9573 Email: slpotisek@dow.com
C. S. Premachandran – GLOBALFOUNDRIES Tel: +1-518-305-7317 Email: premachandrancs@globalfoundries.com
Stefan Weiss – II-VI Laser Enterprise GmbH Tel: +41-44-455-8732 Email: sweiss@laserenterprise.com
Don Frye – Don’s Material Development & Innocentrix Tel: +1-310-487-0148 Email: don3569a@gmail.com
8:00 am – MEMS-Based Heart Monitoring System with Integrated Pacing Function Fjodors Tjulkins, Anh Tuan Thai Nguyen, Nils Hoivik, Knut Aasmundtveit, Lars Hoff, Erik Andreassen, and Kristin Imenes – Vestfold University College
8:00 am – Assembly of Mechanically Compliant Interfaces between Optical Fibers and Nanophotonic Chips Tymon Barwicz, Yoichi Taira, Hidetoshi Numata, Nicolas Boyer, Stephane Harel, Swetha Kamlapurkar, Simon Laflamme, Sebastian Engelmann, Yurii Vlasov, and Paul Fortier – IBM Corporation; Shotaro Takenobu – Asahi Glass Corporation
8:00 am – Interfacially Engineered Cu Nanowire-Indium Composites as Next Generation Thermal Interface Materials Tarang Mungole, Kathryn Mireles, and Indranath Dutta – Washington State University; Jia Liu – Pacific Northwest National Lab
8:25 am – Archipelago Platform for Realization of Skin-Mounted Wearable and Stretchable Electronics Yung-Yu Hsu, Milan Raj, Briana Morey, Mitul Dalal, Xianyan Wang, Cole Papakyrikos, Gil Huppert, and Roozbeh Ghaffari – MC10 Inc.
8:25 am – Proposal of Integrated-Optic Wavelength-Selective Modulator in Straight Waveguide by Controlling Coupling Efficiency of Distributed Bragg Reflector Shogo Ura, Testunosuke Miura, Satoshi Kawanami, and Yasuhiro Awatsuji – Kyoto Institute of Technology; Kenji Kintaka – National Institute of Advanced Industrial Science and Technology
8:25 am – Engineered Thermal Interface Material Lyndon Larson, Yin Tang, David Plante, Cassandra Hale, and Loren Durfee – Dow Corning Corporation; Annique LaVoie, Taryn Davis, Sushumna Iruvanti, Richard Langlois, and Rebecca Wagner – IBM Corporation
8:50 am – Inkjet Printing in Manufacturing of Stretchable Interconnects Toni Liimatta, Eerik Halonen, Hannu Sillanpää, Juha Niittynen, and Matti Mäntysalo – Tampere University of Technology
8:50 am – Porous Silicon Technology, a Breakthrough for Silicon Photonics: From Packaging to Monolithic Integration Marco Balucani, Konstantin Kholostov, Alexi Klyshko, Alessio Benetti, Alessandro Belardini, and Concita Sibilia – Sapienza University of Rome; Massimo Izzi and Mario Tucci – Enea Casaccia; Hanna Bondarenko and Vitaly Bondarenko – Belarusian State University of Informatics and Radioelectronics
8:50 am – Novel Highly Moisture Resistant Optical Adhesives and Their High Power Resistivity Seiko Mitachi – Tokyo University of Technology; Kazushi Kimura – The Yokohama Rubber Co. Ltd
Refreshment Break: 9:15-10:00 a.m. 10:00 am – Ultra Small Hearing Aid Electronic Packaging Enabled by Chip-inFlex Susie Johansson and John Dzarnoski – Starkey Hearing Technologies
10:00 am – High Power Density LED Modules with Silver Sintering Die Attach on Aluminum Nitride Substrates Marc Schneider, Benjamin Leyrer, Christian Herbold, and Stefan Maikowske – Karlsruhe Institute of Technology
10:00 am – Time, Temperature, and Mechanical Fatigue Dependence of Underfill Adhesion Joseph Cremaldi and Noshir Pesika – Tulane University; Eric Lewandowski, Michael Gaynes, and Peter Brofman – IBM Corporation
10:25 am – Fabrication of Silicon Based Microfluidics Device for Cell Sorting Application Bivragh Majeed, Chengxun Liu, Lut Van Acker, Robert Daily, Deniz Sabuncuoglu, and Liesbet Lagae – IMEC; Tomokazu Miyazaki – JSR
10:25 am – Effect of Optical Design on the Thermal Management for SMART TV LED Backlight Systems Kivanc Karsli – Vestel AS; Mehmet Arik – Ozyegin University
10:25 am – Study on Isotropic Electrically Conductive Adhesive for Medical Device Applications Shawn Shi, Scott Sleeper, and Chunho Kim – Medtronic, Inc.
10:50 am – A Novel 3D Neural Probe with Integrated Channel and Its Package Yong Xu – Wayne State University; Sheng Liu, Chaojun Liu, Gang Cao, and Xingming Fu – Huazhong University of Science & Technology
10:50 am – Wafer Level LED Packaging with Optimal Light Output and Thermal Dissipation for High-Brightness Liang Wang, Gabe Guevara, Rey Co, Ron Zhang, Ilyas Mohammed, and Bel Haba – Invensas Corporation
10:50 am – Effect of Aligned Nanofiber in Nanofiber Solder Anisotropic Conductive Films (ACFs) on the Solder Ball Movement for Flex-on-Flex (FOF) Assembly Tae Wan Kim and Kyung-Wook Paik – KAIST
11:15 am – CMOS Multiplexer for Portable Biosensing System with Integrated Microfluidic Interface Tetiana Voitsekhivska, Eike Suthau, and Klaus-Juergen Wolter – Technical University Dresden
11:15 am – High Power Laser Packaging Challenges and Standardization Eric Zhou and Jeffrey Morris – LDX Optronics, Inc.; Hanguo Wang – UCLA
11:15 am – Adhesive Enabling Technology for Directly Plating Metal on Molding Resin Kwonil Kim, Kenichiroh Mukai, Brian Eastep, Anirudh Kashyap, and Lee Gaherty – Atotech USA Inc.
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Program Sessions: Wednesday, May 28, 1:30-5:10 p.m. Session 7: Interposers & 3D Integration
Session 8: Flip Chip Packaging & Advanced Substrate
Session 9: Interconnect Reliability
Committee: Interconnections
Committee: Advanced Packaging
Committee: Applied Reliability
Session Co-Chairs: Katsuyuki Sakuma – IBM Corporation Tel: +1-845-894-5605 Email: ksakuma@us.ibm.com
Session Co-Chairs: Young-Gon Kim – IDT Tel: +1-408-360-1545 Email: young.kim@idt.com
Lou Nicholls – Amkor Technology, Inc. Tel: +1-480-786-7687 Email: lou.nicholls@amkor.com
Omar Bchir – Qualcomm, Inc. Tel: +1-858-210-9541 Email: obchir@gmail.com
Session Co-Chairs: Tz-Cheng Chiu – National Cheng Kung University Tel: +886-6-2757575 Email: tcchiu@mail.ncku.edu.tw
1:30 pm – Modeling, Design, and Demonstration of Low-Temperature Cu Interconnections to Ultra-Thin Glass Interposers at 20 µm Pitch Tao Wang, Vanessa Smet, Venky Sundaram, Pulugurtha Raj, and Rao Tummala – Georgia Institute of Technology; Makoto Kobayashi – Namics Corporation; Taiji Sakai – Fujitsu Laboratories Ltd.
1:30 pm – Chip Package Interaction: An Experimental Study on White Bump Mitigation Using Flat Laminates Yi Pan, Jeffrey A. Zitz, David L. Questad, and Kamal Sikka – IBM Corporation
1:30 pm – Towards a Quantitative Mechanistic Understanding of the Thermal Cycling of SnAgCu Solder Joints Peter Borgesen, Debora Schmitz, Luke Wentlent, and Sa’D Hamasha – Binghamton University; Liang Yin – GE Global Research; Awni Qasaimeh – Tennessee Technological University
1:55 pm – Low-Cost Through Silicon Holes (TSHs) Interposers for 3D IC Integration under Thermal Cycling and Drop Tests John Lau, Ching-Kuan Lee, Chau-Jie Zhan, ShengTsai Wu, Yu-Lin Chao, Ming-Ji Dai, Heng-Chieh Chien, Wei-Chung Lo, and Ming-Jer Kao – Industrial Technology Research Institute (ITRI)
1:55 pm – Design and Package Technology Development of Face-to-Face Die Stacking as a Low Cost Alternative for 3D IC Integration Zhe Li, M. J. Lee, and John Xie – Altera Corporation
1:55 pm – Exploration of Aging Induced Evolution of Solder Joints Using Nanoindentation and Microdiffraction Jeffrey C. Suhling, Md. Hasnine, Barton C. Prorok, Michael J. Bozack, and Pradeep Lall – Auburn University
2:20 pm – Cu Pattern Density Impacts on 2.5D TSI Warpage Using Experimental and FEM Analysis Kuo Ming Chen, Chien Li Kuo, Yung Chang Lin, Ming Tse Lin, Chu Fu Lin, Chun Ting Yeh, and Chung Yen Wu – United Microelectronics Corporation (UMC)
2:20 pm – From C4 to Micro-Bump: Adapting Lead Free Solder Electroplating Processes to Next-Gen Advanced Packaging Applications Julia Woertink, Yi Qin, Jonathan Prange, Pedro LopezMontesinos, Inho Lee, Yil-Hak Lee, Masaaki Imanari, Jianwei Dong, and Jeffrey Calvert – Dow Chemical Company
2:20 pm – Accessing Adhesive Induced Risk for BGAs in Temperature Cycling Guruprasad Arakere, Min Pei, and Milena Vujosevic – Intel Corporation
Vikas Gupta – Texas Instruments Tel: +1-214-567-3160 Email: gvikas@ti.com
Refreshment Break: 2:45-3:30 p.m.
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3:30 pm – A Resilient 3D Stacked Multicore Processor Fabricated Using Die-Level 3D Integration and Backside TSV Technologies Kangwook Lee, Hiroyuki Hashimoto, Masaki Onishi, Yutaka Sato, Marippan Murugesan, Jichel Bae, Takafumi Fukushima, Tetsu Tanaka, and Mitsumasa Koyanagi – Tohoku University
3:30 pm – Development of New 2.5D Package with Novel Integrated Organic Interposer Substrate with Ultra-Fine Wiring and High Density Bumps Kiyoshi Oi, Satoshi Otake, Noriyoshi Shimizu, Shoji Watanabe, Yuji Kunimoto, Takashi Kurihara, Toshinori Koyama, and Masato Tanaka – Shinko Electric Industries Company, Ltd.; Lavanya Aryasomayajula and Zafer Kutlu – GLOBALFOUNDRIES
3:30 pm – Study on the Evaluation of Cu Dendrite Formation on SCSP Packages Peter Tortorici, Shawn Shi, Michael Sandlin, and Scott Savage – Medtronic, Inc.
3:55 pm – 3D Stacking Induced Mechanical Stress Effects Vladimir Cherman, Geert Van der Plas, Joeri De Vos, Andrej Ivankovic, Melina Lofrano, Mario Gonzalez, Kris Vanstreels, Teng Wang, Robert Daily, and Wei Guo – IMEC
3:55 pm – Package Embedded Decoupling Capacitor Impact on Core Power Delivery Network of ARM SoC for Microserver Applications Gawon Kim, Sunghwan Min, Ling Yang, Anil Gundurao, Eileen You, and Harpreet Gill – Samsung Semiconductor Inc.; Seungyong Cha, Younghoon Kim, Se-Ho You, and Seungbae Lee – Samsung Electronics Corporation
3:55 pm – Prediction of the Lifetime of a Cu-Al Wire Bonded Contact for Different Mould Compounds René Rongen, G. M. O’Halloran, Amar Mavinkurve, Leon Goumans, and Mark-Luke Farrugia – NXP Semiconductors
4:20 pm – Impact of Grain Structure and Material Properties on Via Extrusion in 3D Interconnects Tengfei Jiang, Chenglin Wu, Jay Im, Rui Huang, and Paul Ho – University of Texas, Austin; Vidhya Ramachandran, Mark Nakamoto, and Riko Radojcic – Qualcomm, Inc.
4:20 pm – Embed Glass Interposer to Substrate for High Density Interconnection Dyi-Chung Hu, Yin-Po Hung, Yu-Hua Chen, and Ra-Min Tain – Unimicron Technology Corporation; Wei-Chung Lo – Industrial Technology Research Institute (ITRI)
4:20 pm – The Corrosion Performance of Cu Alloy Wire Bond on Al Pad in Molding Compounds of Various Chlorine Contents under Biased-HAST Ying-Ta Chiu, Tzu-Hsing Chiang, Yin-Fa Chen, Ping-Feng Yang, and Louie Huang – Advanced Semiconductor Engineering, Inc.; Kwang-Lung Lin – National Cheng Kung University
4:45 pm – TSV-less 3D Stacking of MEMS and CMOS via Low Temperature Al-Au Direct Bonding with Simultaneous Formation of Hermetic Seal Chuan Seng Tan, Arsalan Razzaq, Shen Lin Chua, and Hao Yu – Nanyang Technological University; Keng Hoong Wee – DSO National Laboratory; King Ho Li – Temasek Laboratories@NTU
4:45 pm – First Demonstration of a Surface Mountable, Ultra-Thin Glass BGA Package for Smart Mobile Logic Venky Sundaram, Vanessa Smet, and Rao Tummala – Georgia Institute of Technology; Yoichiro Sato – Asahi Glass Company; Toshitake Seki and Yutaka Takagi – NGK-NTK; Makoto Kobayashi – NAMICS Corporation
4:45 pm – The Effect of Nickel Microalloying on Microstructure and Thermal Fatigue Reliability of SAC105 and SAC205 Solders Richard Coyle – Alcatel-Lucent; Keith Sweatman and Keith Howell – Nihon Superior; Babak Arfaei – Universal Instruments; Richard Parker and Stuart Longgood – Delphi Electronics; Elizabeth Bendetto – Hewlett Packard
Program Sessions: Wednesday, May 28, 1:30-5:10 p.m. Session 10: Novel Materials & Processes
Session 11: Innovative Packaging Technologies
Session 12: Power Integrity & Passive Component Modeling
Committee: Materials & Processing
Committee: Assembly & Manufacturing Technology
Committee: Modeling & Simulation
Session Co-Chairs: Ivan Shubin – Oracle Tel: +1-858-526-9032 Email: ivan.shubin@oracle.com
Session Co-Chairs: Paul Tiner – Texas Instruments Tel: +1-469-471-3565 Email: p-tiner@ti.com
Session Co-Chairs: Wendem Beyene – Rambus Inc. Tel: +1-408-462-8366 Email: wbeyene@rambus.com
Bing Dang – IBM Corporation Tel: +1-914-945-1568 Email: dangbing@gmail.com
Shichun Qu – Fairchild Semiconductor Tel: +1-408-822-2064 Email: shichun.qu@fairchildsemi.com
Daniel de Araujo – Nimbic, Inc. Tel: +1-512-487-1027 Email: daniel@nimbic.com
1:30 pm – Flexible Non-Volatile Cu/CuxO/Ag ReRAM Memory Devices Fabricated Using Ink-Jet Printing Technology Simin Zou and Michael Hamilton – Auburn University
1:30 pm – A New Era in Manufacturable, Low-Temperature and Ultra-Fine Pitch Cu Interconnections and Assembly without Solders Vanessa Smet, Tao Wang, Zihan Wu, Pulugurtha Markondeya Raj, and Rao Tummala – Georgia Institute of Technology; Makoto Kobayashi – NAMICS Corporation
1:30 pm – Package Embedded Inductors for Integrated Voltage Regulators William Lambert, Michael Hill, Kaladhar Radhakrishnan, Leigh Wojewoda, and Anne Augustine – Intel Corporation
1:55 pm – Ultra-High Refractive Index LED Encapsulant Chia-Chi Tuan, Ziyin Lin, Yan Liu, Kyoung-Sik Moon, and Ching-Ping Wong – Georgia Institute of Technology; Sehoon Yoo – Korea Institute of Industrial Technology; Myong-Gi Jang – EI Lighting Co. Ltd.
1:55 pm – Enabling Fine Pitch Cu & Ag Alloy Wire Bond Assessment for 28nm Ultra Low-k Structure John Beleran, Ninoy Milanes, Ko Lwin Kyaw, and Gaurav Mehta – United Test and Assembly Center, Ltd.; Ranjan Rajoo and Kai Chong Chan – GLOBALFOUNDRIES
1:55 pm – Power Supply Filter for PLL Circuit in Digital Systems Nam Pham, Faraydon Parkbaz, and Zhenrong Jin – IBM Corporation
2:20 pm – A Novel Methodology for WaferSpecific Feed-Forward Management of Backside Silicon Removal by Wafer Grinding for Optimized Through Silicon Via Reveal Frank Wei, Yu Iijima, and Tyson Alvanos – Disco Hi-Tec America, Inc.; Hideo Takizawa, Osamu Sato, and Naoki Sugase – Lasertec Corporation; Christopher Rosenthal – Lasertec USA Inc.; John Garant and Richard F. Indyk – IBM Corporation
2:20 pm – Assembly of Multiple Chips on Flexible Substrate Using Anisotropic Conductive Film for Medical Imaging Applications Hoang-Vu Nguyen, Kristin Imenes, and Knut Aasmundtveit – HiVe-Vestfold University College; Trym Eggen and Bjørnar Sten-Nilsen – GE Vingmed Ultrasound AS
2:20 pm – Coaxial Through-Package Vias (TPVs) for Enhancing Power Integrity in 3D Double-Side Glass Interposers Gokul Kumar, Saumya Gandhi, Jonghyun Cho, Venky Sundaram, Raj Pulugurtha, and Rao Tummala – Georgia Institute of Technology; Joungho Kim – KAIST
Refreshment Break: 2:45-3:30 p.m. 3:30 pm – Thermal Characterization of Power Devices Using Graphene Based Film Nan Wang, Pengtu Zhang, Carl Zandén, and Johan Liu – Chalmers University of Technology; Lilei Ye and Yifeng Fu – SHT Smart High Tech AB
3:30 pm – High Frequency High Current Point of Load Modules with Integrated Planar Inductors Wenli Zhang, Yipeng Su, David Gilham, Mingkai Mu, Qiang Li, and Fred C. Lee – Virginia Polytechnic Institute and State University
3:30 pm – Modeling of Switching Noise in Power Distribution Network for 3D TSVBased Systems Huanyu He and Jianqiang Lu – Rensselaer Polytechnic Institute; Xiaoxiong Gu – IBM Corporation
3:55 pm – High Performance Phase Change Thermal Interface Materials Based on Porous Graphitic Carbon Spheres-Paraffin Wax Composite Zhihua Cao, Gongping Zhang, Xianzhu Fu, and Rong Sun – Shenzhen Institutes of Advanced Technology; Kai Zhang and Matthew M. F. Yuen – Hong Kong University of Science and Technology; C. P. Wong – The Chinese University of Hong Kong
3:55 pm – Integrated Microprobe Array and CMOS MEMS by TSV Technology for BioSignal Recording Application
3:55 pm – Characterization of On-Die Power Supply Noise in FCBGA (Flip-Chip Ball Grid Array) Packages Hyunho Baek and William Eisenstadt – University of Florida
4:20 pm – High Sensitivity In-Plane Strain Measurement Using a Laser Scanning Technique Hanshuang Liang, Teng Ma, Hoa Nguyen, George Chen, Hao Wu, Hanqing Jiang, and Hongbin Yu – Arizona State University
4:20 pm – Material Characterization of a Novel Lead-Free Solder Material: SACQTM Tak Sang Yeung, Henry Sze, Keith Tan, Javed Sandhu, Chong Wei Neo, and Edward Law – Broadcom Corporation
4:20 pm – An Enhanced Power Integrity Analysis Flow Based on the Interdependence Between Simultaneous Switching Output Noise and Static IR Drop Minghui Han, Amir Amirkhany, and Wei Xiong – Samsung Display
4:45 pm – Evaluation of Biocompatible Passivation Layers by Aging Tests for the Packaging of Silicon Microsystems in Medical Devices Jorge Mario Herrera Morales, Jean-Charles Souriau, François Berger, and Gilles Simon – CEA-LETI
4:45 pm – Lithography Challenges for 2.5D Interposer Manufacturing Klaus Ruhmer, Joe Battaglia, and Philippe Cochet – Rudolph Technologies, Inc.
4:45 pm – Improving the Target Impedance Method for Core Power Decoupling Guang Chen, Cuong Nguyen, Yujeong Shim, and Dan Oh – Altera Corporation
Lei-Chun Chou, Shih-Wei Lee, Po-Tsang Huang, Shang-Lin Wu, Ching-Te Chuang, and Kuan-Neng Chen – National Chiao Tung University; Chih-Wei Chang – University of California, Los Angeles; Jin-Chern Chiou – National Chiao Tung University and China Medical University; Wei Hwang – National Chiao Tung University and Advanced Semiconductor Engineering, Inc.; ChungHsi Wu, Kuo-Hua Chen, Chi-Tsung Chiu, and Ho-Ming Tong – Advanced Semiconductor Engineering, Inc.
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Program Sessions: Thursday, May 29, 8:00-11:40 a.m. Session 13: 3D Process Integration & Die Stacking
Session 14: TSV Fabrication & Its Reliability Impact
Session 15: Solder Joint Reliability
Committee: Advanced Packaging
Committee: Interconnections
Committee: Applied Reliability
Session Co-Chairs: Rozalia Beica – Yole Developpement Email: rbeica@gmail.com
Session Co-Chairs: Li Li – Cisco Systems, Inc. Tel: +1-408-527-0801 Email: LiLi2@cisco.com
Session Co-Chairs: Keith Newman – Hewlett-Packard Tel: +1-650-857-4482 Email: keith.newman@hp.com
Wei-Chung Lo – ITRI Tel: +886-3-591-7024 Email: lo@itri.org.tw
Toni Mattila – Aalto University Tel: +358-405009909 Email: toni.mattila@aalto.fi
8:00 am – Process Development to Enable 3D IC Multi-Tier Die Bond for 20µm Pitch and Beyond Y. H. Hu, C. S. Liu, M. T. Chen, M. D. Cheng, H. J. Kuo, M. J. Lii, and D. C. H. Yu – Taiwan Semiconductor Manufacturing Company; A. LaManna, K. J. Rebibis, T. Wang, S. V. Huylenbroeck, R. Daily, G. Capuz, D. Velenis, G. Beyer, and E. Beyne – IMEC
8:00 am – Correlation between Cu Microstructure and TSV Cu Pumping Jo De Messemaeker, Olalla Varela Pedreira, Harold Philipsen, Eric Beyne, Ingrid De Wolf, and Kristof Croes – IMEC; Tom Van der Donck – KU Leuven
8:00 am – Dependence of Solder Joint Reliability on Solder Volume, Composition and PCB Surface Finish Babak Arfaei – Universal Instruments; Francis Mutuku and Eric Cotts – State University of New York, Binghamton; Keith Sweatman – Nihon-Superior; Ning-Cheng Lee – Indium Corporation; Richard Coyle – Alcatel-Lucent
8:25 am – Factors in Selection of Temporary Wafer Handler for 3D Integration Bing Dang, Bucknell Webb, Cornelia Tsang, Paul Andry, and John Knickerbocker – IBM Corporation
8:25 am – TSV Reliability Model under Various Stress Tests Ben-Je Lwo, Frank M. S. Lin, and Kuo-Hsin Huang – National Defense University
8:25 am – The Effects of Aging on the Fatigue Life of Lead Free Solders Jeffrey C. Suhling, Muhannad Mustafa, Jordan Roberts, and Pradeep Lall – Auburn University
8:50 am – Optimization and Challenges on TSV MEOL Integration D. H. Kim, D. H. Lee, Y. C. Seo, J. S. Park, S. C. Han, B. R. Jang, J. H. Khim, Y. S. Chung, S. M. Seo, and C. Lee – Amkor Technology Korea
8:50 am – Development of Process and Design Criteria for Stress Management in Through Silicon Vias Ole Hölck, Max Nuss, Tobias Prewitz, Peggy John, Conny Fiedler, Matthias Böttcher, Hans Walter, and Olaf Wittler – Fraunhofer IZM; Klaus-Dieter Lang – Technical University Berlin
8:50 am – Solder Joint Height Impact on Temperature Cycle Reliability of BGA Components with Thermal Enabling Load Yun Ge, Jeffery Cook, Min Pei, Milena Vujosevic, Bite Zhou, and Suddhasattwa Nad – Intel Corporation
Jianwei Dong – Dow Electronic Materials Email: jianweidong@dow.com
Refreshment Break: 9:15-10:00 a.m.
18
10:00 am – TSV Integration on 20nm Logic Si: 3D Assembly and Reliability Results Rahul Agarwal, Sebastian Dej, Sukeshwar Kannan, Sara Thangaraju, Jens Paul, and Dan Smith – GLOBALFOUNDRIES; Dave Hiner, Kiwook Lee, Dohyeong Kim, Jongsik Paek, and Sunggeun Kang – Amkor Technology, Inc.
10:00 am – High Speed Fabrication of Through Silicon Vias (TSVs) Array by MetalAssisted Chemical Etching (MaCE) and Effect of External Field Liyi Li – Georgia Institute of Technology
10:00 am – Controlling the Sn Grain Morphology of C4 Solder Bumps Gregory Parks and Eric Cotts – State University of New York at Binghamton; Minhua Lu and Eric Perfecto – IBM Corporation
10:25 am – TSV MEOL (Mid End of Line) and Packaging Technology of Mobile 3D Stacking Duk Ju Na – STATS ChipPAC, Inc.
10:25 am – Replacing the PECVD-SiO2 in the Through-Silicon Via of High-Density 3D LSIs with Highly Scalable Low Cost Organic Liner: Merits and Demerits Murugesan Mariappan, Takafumi Fukushima, Jichel Beatrix, Hiroyuki Hashimoto, Yutaka Sato, Kangwook Lee, Tetsu Tanaka, and Mitsumasa Koyanagi – Tohoku University; Hirohsi Nohira – Tokyo City University
10:25 am – The Impact of Microstructure Evolution, Localized Recrystallization and Board Thickness on Sn-Ag-Cu Interconnect Board Level Shock Performance Tae-Kyu Lee and Weidong Xie – Cisco Systems, Inc.; Thomas R. Bieler – Michigan State University; ChoongUn Kim – University of Texas, Arlington
10:50 am – Thermally Enhanced Three Dimensional Integrated Circuit (TE3DIC) Packaging Michael Weatherspoon, Steven Snyder, Andrew King, Erin Walters, and Jason Thompson – Harris Corporation GCSD; Phillip Tyler – Georgia Institute of Technology
10:50 am – Investigation of a TSV-RDL In-Line Fault-Diagnosis System and Test Methodology for Wafer-Level Commercial Production Runiu Fang, Xin Sun, Yunhui Zhu, Guanjiang Wang, Yichao Xu, Yong Guan, Yudan Pi, Jing Chen, and Yufeng Jin – Peking University; Min Miao and Minggang Sun – Beijing Information Science and Technology University
10:50 am – Thermal Cycle Fatigue Life Prediction for Flip Chip Solder Joints Robert Darveaux – Skyworks Solutions, Inc.
11:15 am – Effect of Misalignment in Bonding on Filler Trap Formation in 3D IC Microbumps Yingxia Liu and Henry Chen – University of California, Los Angeles; Dong-Wook Kim and Sam Gu – Qualcomm, Inc.
11:15 am – Bonding Technologies for Chip Level and Wafer Level 3D Integration Katsuyuki Sakuma, Spyridon Skordas, Richard Langlois, Matthew Angyal, Kamal Sikka, and John Knickerbocker – IBM Corporation
11:15 am – High Thermo-Mechanical Fatigue and Drop Impact Resistant Ni-Bi Doped Lead Free Solder Santosh Kumar, Youngwoo Lee, Jaeyeol Son, Jaehong Lee, Huijoong Kim, Eungjae Kim, Hogun Cha, and Jeongtak Moon – MK Electron Company, Ltd.
Program Sessions: Thursday, May 29, 8:00-11:40 a.m. Session 16: Advances in Signal Integrity & High-Speed System Design
Session 17: Emerging Wireless Technologies & Design
Session 18: WLCSP, Flip Chip, and PoP
Committee: Modeling & Simulation
Committee: Electronic Components & RF
Committee: Assembly & Manufacturing Technology
Session Co-Chairs: Xiaoxiong (Kevin) Gu – IBM Corporation Tel: +1-914-945-2292 Email: xgu@us.ibm.com
Session Co-Chairs: Amit P. Agrawal – Cisco Systems, Inc. Tel: +1-408-424-2732 Email: amiagra2@cisco.com
Session Co-Chairs: Valerie Oberson – IBM Corporation Tel: +1-450-534-7767 Email: voberson@ca.ibm.com
Kemal Aygun – Intel Corporation Tel: +1-480-552-1740 Email: kemal.aygun@intel.com
Lih-Tyng Hwang – National Sun Yat-Sen University Tel: +886-7-5252000 ext. 4485 Email: FiftyOhm@mail.nsysu.edu.tw
Sa Huang – Medtronic Corporation Email: sa.huang@medtronic.com
8:00 am – Optimal Relaxation of I/O Electrical Requirements under Packaging Uncertainty by Stochastic Methods Xu Chen, Juan Ochoa, Jose Schutt-Aine, and Andreas Cangellaris – University of Illinois, Urbana-Champaign
8:00 am – Highly Efficient and Misalignment Insensitive Wireless Power Transfer Systems Stavros Georgakopoulos, Olutola Jonah, and Daerhan Daerhan – Florida International University; Manos Tentzeris – Georgia Institute of Technology
8:00 am – Wafer-Level Non Conductive Films for Exascale Servers Akihiro Horibe, Hiroyuki Mori, and Yasumitsu Orii – IBM Corporation; Satomi Kawamoto, Hiromi Sone, and Masaaki Hoshiyama – NAMICS Corporation
8:25 am – An Accurate and Convenient Lumped/Discrete Port De-Embedding Method for the 3D Integration and Packaging Full-Wave Modeling by Splitting and Absorbing the Error-Cancelling Network Zhaoqing Chen – IBM Corporation
8:25 am – A Wireless Charging and NearField Communication Combination Module for Mobile Applications Hiroki Shibuya, Tatsuaki Tsukuda, Hiroko Kubota, Tadashi Shimizu, Masahiro Dobashi, Shinji Nishizono, Mikio Baba, Hideki Sasaki, and Katsushi Terajima – Renesas Electronics Corporation
8:25 am – Bump Geometric Deviation on the Reliability of BOR WLCSP Yong Liu, Yumin Liu, and Shichun Qu – Fairchild Semiconductor Corporation
8:50 am – Design, Modeling, and Characterization of Passive Channels for Data Rates of 50 Gbps and Beyond Wendem Beyene, Yeon-Chang Ham, Dave Secker, and Don Mullen – Rambus, Inc.
8:50 am – Enhanced-Performance Wireless Conformal “Smart Skins” Utilizing InkjetPrinted Porous Carbon-Nanostructures Taoran Le, Ziyin Lin, Trang Thai, Yunnan Fang, Jimmy Hester, Ching-Ping Wong, and Manos Tentzeris – Georgia Institute of Technology
8:50 am – Experimental Identification of Warpage Origination during the Wafer Level Packaging Process Chunsheng Zhu, Wenguo Ning, Heng Lee, Jiaotuo Ye, Gaowei Xu, and Le Luo – Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
Refreshment Break: 9:15-10:00 a.m. 10:00 am – Low Loss Vias for CMOS and Through Glass/Silicon Via (TGV/ TSV) Structures Using Radial Superlattice Conductor Arian Rahimi, Cheolbok Kim, and Yong-Kyu Yoon – University of Florida
10:00 am – A Novel THz Imaging Array Using High Resistivity Metasurface Structures Kyoung Youl Park, Stephen Zajac, and Premjeet Chahal – Michigan State University
10:00 am – A Stress-Based Effective Film Technique for Wafer Warpage Prediction of Arbitrarily Patterned Films Gregory Ostrowicki and Siva Gurrum – Texas Instruments, Inc.
10:25 am – Design, Analysis, Demonstration and Characterization of First Large 2.5D Glass Interposer as a Superior Alternative to Silicon and Organic Interposers at 20 Micron Pitch Brett Sawyer, Hao Lu, Gokul Kumar, Tao Wang, Vanessa Smet, Sung Jin Kim, Venky Sundaram, and Rao Tummala – Georgia Institute of Technology; Yuya Suzuki – Zeon Corporation; Yutaka Takagi – NGK Spark Plug Co. Ltd.; Taiji Sakai – Fujitsu Laboratories, Ltd.
10:25 am – Magneto-Dielectric Characterization and Antenna Design Kyu Han, Madhavan Swaminathan, Markondeya Raj, Himani Sharma, and Rao Tummala – Georgia Institute of Technology; Vijay Nair – Intel Corporation
10:25 am – Drop Test and TCT Reliability of Buffer Coating Material for WLCSP Nobuhiro Anzai, Mitsuru Fujita, and Atsushi Fujii – Asahi Kasei E-Materials Corporation
10:50 am – Coupling Impact of Single Ended Signals to LVDS Interface June Feng, Chooi Ian Loh, and Dan Oh – Altera Corporation
10:50 am – Flexible Liquid Crystal Polymer Based Complementary Split Ring Resonator Loaded Quarter Mode Substrate Integrated Waveguide Filters for Compact and Wearable Broadband RF Applications David Senior – Universidad Tecnológica de Bolívar; Arian Rahimi, Pitfee Jao, and Yong-Kyu Yoon – University of Florida
10:50 am – Optimization of Compression Bonding Processing Temperature for Fine Pitch Cu-Column Flip Chip Nokibul Islam, Yonghyuk Jeong, Joonyoung Choi, Youjoung Choi, Nokibul Islam, and Eric Ouyang – STATS ChipPAC, Inc.
11:15 am – Analysis on Interference between Multi-Giga Bit Display Serial Link and RF Components in Smart Mobile Device Youchul Jeong, Jaemin Kim, and Baegin Sung – Silicon Image
11:15 am – A Dual Band Power Amplifier Based on Composite Right/Left-Handed Matching Networks Kyriaki Niotaki, Francesco Giuppi, Ana Collado, and Apostolos Georgiadis – CTTC; John Vardakas – Iquadrat S. L.
11:15 am – A Workability and Reliability Assessment of Various High Bandwidth PoP Structures Mike Hung, Timmy Lin, Louie Huang, Mark Wang, and Y. C. Ding – Advanced Semiconductor Engineering, Inc.
19
Program Sessions: Thursday, May 29, 1:30-5:10 p.m. Session 19: Progress in 3D Integration
Session 20: 3D Materials & Processing
Session 21: Wafer-Level & Fan-Out Packages
Committee: Assembly & Manufacturing Technology
Committee: Materials & Processing
Committee: Advanced Packaging
Session Co-Chairs: Shawn Shi – Medtronic Corporation Tel: +1-480-929-5614 Email: shawn.shi@medtronic.com
Session Co-Chairs: Myung Jin Yim – Intel Corporation Tel: +1-408-728-1393 Email: myungjin.yim@intel.com
Session Co-Chairs: Christopher Bower – X-Celeprint Ltd. Tel: +1-919-522-5022 Email: cbower@x-celeprint.com
Paul Houston – Engent Tel: +1-770-280-4238 Email: paul.houston@engentaat.com
Daniel D. Lu – Henkel Corporation Tel: +86-21-2891-8576 Email: daniel.lu@cn.henkel.com
E. Jan Vardaman – TechSearch International, Inc. Tel: +1-512-372-8887 Email: tsi@techsearchinc.com
1:30 pm – Development of the Technology to Control the Spatial Distribution of Plasma Using Double ICP Coil Toshiyuki Sakuishi, Takahide Murayama, Yasuhiro Morikawa, and Kou Kou Suu – ULVAC, Inc.
1:30 pm – Advanced Wafer Bonding and Laser Debonding Paul Andry, Russ Budd, Robert Polastre, Cornelia Tsang, Bing Dang, and John Knickerbocker – IBM Corporation
1:30 pm – Board Level Reliability and Surface Mount Assembly of 0.35mm and 0.3mm Pitch Wafer Level Packages Beth Keser, Rey Alvarado, Alan Choi, Mark Schwarz, and Steve Bezuk – Qualcomm Technologies, Inc.
1:55 pm – Defect Detection in Through Silicon Vias by GHz Scanning Acoustic Microscopy: Key Ultrasonic Characteristics Alain Phommahaxay, Ingrid De Wolf, Harold Philipsen, Gerald Beyer, Herbert Struyf, and Eric Beyne – IMEC; Tatjana Djuric, Peter Hoffrogge, and Peter Czurratis – PVA TePla Analytical Systems GmbH; Sebastian Brand – Fraunhofer Institute for Mechanics of Materials IWM
1:55 pm – Versatile Thin Wafer Stacking Technology for Monolithic Integration of Temporary Bonded Thin Wafers Thomas Uhrmann, Jürgen Burggraf, Julian Bravin, Harald Wiesbauer, Viorel Dragoi, Markus Wimplinger, Thorsten Matthias, and Paul Lindner – EV Group
1:55 pm – Encapsulated Wafer Level Package Technology (eWLCSP™) Tom Strothmann, Seung Wook Yoon, and Yaojian Lin – STATS ChipPAC, Inc.
2:20 pm – Temporary Spin-on Glass Bonding Technologies for Via-Last/Backside-Via 3D Integration Using Multichip Self-Assembly Hideto Hashiguchi, Takafumi Fukushima, Akihiro Noriki, Hisashi Kino, Kang-Wook Lee, Tetsu Tanaka, and Mitsumasa Koyanagi – Tohoku University
2:20 pm – Temporary Bonding for HighTopography Applications: Spin-on Material versus Dry Film Anne Jourdain, Alain Phommahaxay, Andy Miller, Kenneth Rebibis, Gerald Beyer, and Eric Beyne – IMEC; Alice Guerrero, Susan Bailey, Mark Privett, and Kim Arnold – Brewer Science
2:20 pm – Introduction of Enhanced Dielectric Material for Higher Reliability in Fan-Out WLP Vítor Henriques, Isabel Barros, Eoin O’Toole, José Campos, André Cardoso, Steffen Kroehnert, and Vitor Chatinho – NANIUM
Refreshment Break: 2:45-3:30 p.m.
20
3:30 pm – TSV Module Optimization for High Performance Silicon Interposers Cyprian Uzoh, Zhuowen Sun, Andrew Cao, BongSub Lee, Liang Wang, Guilian Gao, Hong Shen, and Sitaram Arkalgud – Invensas Corporation
3:30 pm – Development of New Concept Thermoplastic Temporary Adhesive for 3D-IC Integration Atsushi Kubo, Koki Tamura, Hirofumi Imai, Takahiro Yoshioka, Satoshi Oya, and Shoji Otaka – Tokyo Ohka Kogyo Co., Ltd.
3:30 pm – 24’’ x 18’’ Fan-Out Panel Level Packaging Tanja Braun, Karl-Friedrich Becker, Volker Bader, Joerg Bauer, and Rolf Aschenbrenner – Fraunhofer IZM; Steve Voges, Tina Thomas, Ruben Kahle, and Klaus-Dieter Lang – Technical University Berlin
3:55 pm – Study of TSV Thinning Wafer Strength Enhancement for 3DIC Package Genie Tsai – Siliconware Precision Industries Co., Ltd.
3:55 pm – Underfilling Techniques Comparison in 3D CtW Stacking Approach Arnaud Garnier, Amandine Jouve, Rémi Franiatte, and Séverine Chéramy – CEA-LETI
3:55 pm – Development and Characterization of New Generation Panel Fan-Out (P-FO) Packaging Technology Hong-Da Chang, David Chang, Kenny Liu, H. S. Hsu, Rui-Feng Tai, Hsiao-Chun Huang, Yi-Che Lai, Chang-Lun Lu, Chun-Tang Lin, and Shih-Kuang Chiu – Siliconware Precision Industries Co., Ltd.
4:20 pm – Challenges in 3D Die Stacking Juergen Grafe, Wahrmund Wieland, Stephan Dobritz, Juergen Wolf, and Klaus-Dieter Lang – Fraunhofer IZM
4:20 pm – High Throughput Thermal Compression NCF Bonding Toshihisa Nonaka, Yuta Kobayashi, Noboru Asahi, Koichi Fujimaru, Kazuyuki Matsumura, and Shoichi Niizeki – Toray Industries, Inc.; Yoshiyuki Arai, Toshifumi Takegami, Yoshinori Miyamoto, and Masatsugu Nimura – Toray Engineering Co., Ltd.; Hiroyuki Niwa – Toray International America Inc.
4:20 pm – Development of Exposed Die, Large Body to Die Size Ratio Wafer Level Package Technology John Osenbach, Suzanne Emerich, Steven Cate, and Larry Golich – LSI Corporation; Mark Chan, Yao Jian Lin, Seung Wook Yoon, and Kin Wong – STATS ChipPac, Inc.
4:45 pm – Wet Silicon Etch Process for TSV Reveal Yongqiang Lu, Sian Collins, Kevin Mclaughlin, and Craig Allen – SACHEM, Inc.; Laura Mauer, John Taddei, and Ramey Youssef – Solid State Equipment LLC
4:45 pm – Through Silicon Underfill Dispensing for 3D Die/Interposer Stacking S. W. Ricky Lee and Fuliang Le – Hong Kong University of Science & Technology
4:45 pm – 3D Rectangular Waveguide Integrated in Embedded Wafer Level Ball Grid Array (eWLB) Package Ernst Seler, Robert Weigel, and Amelie Hagelauer – University of Erlangen-Nuremberg; Maciej Wojnowski, Walter Hartner, Josef Böck, and Rudolf Lachner – Infineon Technologies
Program Sessions: Thursday, May 29, 1:30-5:10 p.m. Session 22: System-Level Thermal & Mechanical Models I
Session 23: Optical Interconnects
Session 24: Innovative Interconnections
Committee: Modeling & Simulation
Committee: Optoelectronics
Committee: Interconnections
Session Co-Chairs: Yong Liu – Fairchild Semiconductor Corporation Tel: +1-207-761-3155 Email: yong.liu@fairchildsemi.com
Session Co-Chairs: Hiren Thacker – Oracle Tel: +1-858-526-9442 Email: hiren.thacker@oracle.com
Session Co-Chairs: James E. Morris – Portland State University Tel: +1-503-725-9588 Email: j.e.morris@ieee.org
Sandeep Sane – Intel Corporation Tel: +1-480-552-2701 Email: sandeep.b.sane@intel.com
Ping Zhou – LDX Optronics, Inc. Tel: +1-865-981-8822 Email: pzhou@ldxoptronics.com
Nathan Lower – Rockwell Collins, Inc. Tel: +1-319-295-6687 Email: nplower@rockwellcollins.com
1:30 pm – Interplay and Influence of Thermomechanical Stress in Copper-Filled TSV Interposers Sheng-Tsai Wu and Heng-Chieh Chien – Industrial Technology Research Institute (ITRI); Cheng-Fu Chen – University of Alaska, Fairbanks
1:30 pm – Multicore 4 TX + 4 RX Optical Module Based on Holey SiGe Transceiver IC Fuad Doany, Daniel Kuchta, Alexander Rylyakov, Christian Baks, Shurong Tian, Mark Schultz, Frank Libsch, and Clint Schow – IBM Corporation
1:30 pm – Nanofiber Anisotropic Conductive Films (ACFs) Sang Hoon Lee and Kyung-Wook Paik – KAIST; Jong Won Lee and Dong Won Kim – H&S Hightech
1:55 pm – Analytical and Numerical Study on Vacancy-Based Electromigration Model Kasemsak Kijkanjanapaiboon and Xuejun Fan – Lamar University
1:55 pm – 336-Channel Electro-Optical Interconnect: Underfill Process Improvement and Reliability Results Shuki Benjamin, Kobi Hasharoni, and Avi Maman – Compass-EOS; Helge Luesebrink, Roland Steffek, Wolfgang Pleyer, and Christian Stömmer – PVA TePla AG
1:55 pm – Study of Fine Pitch MicroInterconnections Formed by Low Temperature Bonded Copper Nanowires Based Anisotropic Conductive Film Jing Tao, Alan Mathewson, and Kafil M. Razeeb – Tyndall National Institute
2:20 pm – Hygro-Thermo-Mechanical Analysis and Failure Prediction in Electronic Packages by Using Peridynamics Erdogan Madenci and Selda Oterkus – University of Arizona; Erkan Oterkus – University of Strathclyde; Yuchul Hwang, Jangyong Bae, and Sungwon Han – Samsung Electronics Company
2:20 pm – Development of Optical MultiChannel Connector for Rigid Waveguide to Fiber Optical Interconnection Kazumi Nakazuru, Naoki Takahashi, and Masatoshi Tsunoda – KYOCERA Connector Products Corporation; Satoshi Asai and Takahiro Matsubara – KYOCERA Corporation
2:20 pm – Carbon Nanofibers for Enhanced Solder-Based Nano-Scale Integration and Vertical Heat Spreading Solution at the Chip Level Phil Marcoux – PPM Associates/Smoltek-US; Vincent Desmaris and Anders Johansson – Smoltek
Refreshment Break: 2:45-3:30 p.m. 3:30 pm – A Cohesive Zone Method for Prediction of Interfacial Failure in Microelectronic Systems William Krieger, Sathyanarayanan Raghavan, Cherish Weiler, and Suresh Sitaraman – Georgia Institute of Technology
3:30 pm – Electro-Optical Backplane Demonstrator with Gradient-Index Multimode Glass Waveguides for Board-toBoard Interconnection Lars Brusberg, Henning Schröder, Julia Röder, and Daniel Weber – Fraunhofer Institute IZM; Richard Pitwon and Allen Miller – Xyratex Technology Ltd.; Simon Whalley – ILFA Feinstleitertechnik GmbH; Christian Herbst and Klaus-Dieter Lang – Technical University of Berlin
3:30 pm – Pressure-less Plasma Sintering of Cu Paste for SiC Die-Attach of HighTemperature Power Device Manufacturing Shijo Nagao, Sung-Won Park, Tohru Sugahara, and Ktsuaki Suganuma – Osaka University; Kazuya Kodani – Nissin, Inc.
3:55 pm – Damage Pre-Cursor Based Life Prediction of the Effect of Mean Temperature of Thermal Cycle on the SnAgCu Solder Joint Reliability Pradeep Lall, Kazi Mirza, and Jeff Suhling – Auburn University
3:55 pm – Three-Dimensional High-Density Channel Integration of Polymer Optical Waveguide Using the Mosquito Method Takaaki Ishigure, Daisuke Suganuma, and Kazutomo Soma – Keio University
3:55 pm – Bonding 1200 V, 150 A IGBT Chips (13.5 mm x 13.5 mm) with DBC Substrate by Pressureless Sintering Nanosilver Paste for Power Electronic Packaging Yun-Hui Mei, Shancan Fu, and Xin Li – Tianjin Key Laboratory of Advanced Joining Technology; GuoQuan Lu – Virginia Polytechnic Institute and State University
4:20 pm – Methodology Development of Warpage Analysis of Polymer Based Packaging Substrate Cheolgyu Kim, Taeik Lee, Hyeseon Choi, and TaekSoo Kim – KAIST; Min Sung Kim – Samsung ElectroMechanics
4:20 pm – Novel Trace Design for High Data-Rate Multi-Channel Optical Transceiver Assembled Using Flip-Chip Bonding Takatoshi Yagisawa, Takashi Shiraishi, Mariko Sugawara, and Kazuhiro Tanaka – Fujitsu Laboratories, Ltd.
4:20 pm – Flip Chip Based on Compliant Double Helix Interconnect for High Frequency Applications Pingye Xu and Michael Hamilton – Auburn University
4:45 pm – Simulations for the Impact of Warpage on the Accuracy of Attitude and Heading Reference System Shengzhi Zhang, Qiang Dan, Chaojun Liu, Sheng Liu, Xing Guo, and Ming Wen – Huazhong University of Science & Technology
4:45 pm – Modeling, Design, and Demonstration of Ultra-Miniaturized and High Efficiency 3D Glass Photonics Chia-Te Chou, Venkatesh Sundaram, Gee-Kung Chang, and Rao Tummala – Georgia Institute of Technology
4:45 pm – A TSV-Based Variable Bridge Spiral Inductor Khaled Mohamed – Mentor Graphics; Yehea Ismail – AUC University
21
Program Sessions: Friday, May 30, 8:00-11:40 a.m. Session 25: Recent Advances in 3D Package Reliability
Session 26: 3D Microbumps
Session 27: Sensors & MEMS Technologies
Committee: Applied Reliability
Committee: Interconnections
Committee: Advanced Packaging
Session Co-Chairs: Deepak Goyal – Intel Corporation Tel: +1-480-554-5203 Email: deepak.goyal@intel.com
Session Co-Chairs: Kathy Cook – Ziptronix Tel: +1-512-970-9930 Email: k.cook@ziptronix.com
Session Co-Chairs: Joseph W. Soucy – Draper Laboratory Tel: +1-617-258-2953 Email: jsoucy@draper.com
Jeffrey Suhling – Auburn University Tel: +1-334-844-3332 Email: jsuhling@auburn.edu
Lei Shan – IBM Corporation Tel: +1-914-945-2304 Email: leis@us.ibm.com
Daniel Baldwin – Engent, Inc. Tel: +1-678-990-3320 Email: dan.baldwin@engentaat.com
8:00 am – First Reliability Demonstration of Copper-Plated 30µm Diameter ThroughPackage-Vias at 60µm Pitch in Ultra-Thin Glass Interposers Kaya Demir, Vijay Sukumaran, Raghu Pucha, Venky Sundaram, and Rao Tummala – Georgia Institute of Technology; Yoichiro Sato – Asahi Glass Company
8:00 am – Formic Acid Treatment with Pt Catalyst for Cu Direct and Hybrid Bonding at Low Temperature Tadatomo Suga, Wenhu Yang, and Masatake Akaike – The University of Tokyo
8:00 am – A Novel 3D Packaging Concept for RF Powered Sensor Grains Walther Pachler and Wolfgang Bösch – Graz University of Technology; Peter Ramm, Josef Weber, and Armin Klumpp – Fraunhofer EMFT; Wolfgang Raberg, Reinhard Pufall, and Gerald Holweg – Infineon Technologies; Christian Zilch – Magna Diagnostic
8:25 am – 3D Integration of DRAM-on-Logic Using Via Last TSV Technology Kee-Wei Chung – Macrotech Technology Inc.
8:25 am – Direct Multichip-to-Wafer 3D Integration Technology Using Flip-Chip SelfAssembly of NCF-Covered Known Good Dies Yuka Ito – Tohoku University & Sumitomo Bakelite Co., Ltd.; Mariappan Murugesan, Takafumi Fukushima, Kang-Wook Lee, Tetsu Tanaka, and Mitsumasa Koyanagi – Tohoku University; Koji Choki – Sumitomo Bakelite Co., Ltd.
8:25 am – A Novel Sound Sensor and Its Package Used in Heart and Lung Sound Diagnosis Yong Xu – Wayne State University; Sheng Liu, Chaojun Liu, Gang Cao, and Xingming Fu – Huazhong University of Science & Technology
8:50 am – Minimization of Keep-Out Zone (KOZ) in 3D IC by Local Bending Stress Suppression with Low Temperature Curing Adhesive Hisashi Kino, Hideto Hashiguchi, Yohei Sugawara, Seiya Tanikawa, Takafumi Fukusima, Kang-Wook Lee, Mitsumasa Koyanagi, and Tetsu Tanaka – Tohoku University
8:50 am – Maskless Screen Printing Technology for 20µm Pitch and InSn Solder Interconnections in Display Applications Kwang-Seong Choi, Ga-Hye Kim, Haksun Lee, HyunCheol Bae, and Yong-Sung Eom – ETRI
8:50 am – Novel System-in-Package Design for LED Applications Mingzhi Dong and Jia Wei – Delft University of Technology - Beijing Research Center; Fabio Santagata – State Key Laboratory of Solid State Lighting, China; Cadmus Yuan – Institute of Semiconductors, Chinese Academy of Sciences; Kouchi Zhang – Delft University of Technology
Refreshment Break: 9:15-10:00 a.m.
22
10:00 am – Effect of Thermal Annealing on TSV Local Stress and Cu Deformation Xiangmeng Jing, Hongwen He, Daquan Yu, Wenqi Zhang, and Dongkai Shangguan – National Center for Advanced Packaging
10:00 am – Accelerated SLID Bonding Using Thin Multi-Layer Copper-Solder Stack for Fine-Pitch Interconnections Chinmay Honrao, Ting-Chia Huang, Vanessa Smet, P. Markondeya Raj, and Rao Tummala – Georgia Institute of Technology; Makoto Kobayashi – NAMICS Corporation
10:00 am – Implantable Device Including a MEMS Accelerometer and an ASIC Chip Encapsulated in a Hermetic Silicon Box for Measurement of Cardiac Physiological Parameter Jean-Charles Souriau, Laetitia Castagné, Guy Parat, and Gilles Simon – CEA-LETI; Karima Amara, Philippe D’hiver, and Renzo Dal Molin – Sorin CRM SAS
10:25 am – Effect of High Temperature Storage on the Stress and Reliability of 3D Stacked Chips Tengfei Jiang, Chenglin Wu, Jay Im, Rui Huang, and Paul Ho – University of Texas, Austin; Peng Su, Pierre Chia, and Li Li – Cisco Systems, Inc.; Ho-Young Son, Min-Suk Suk, and Kwang-Yoo Byun – SK Hynix Inc.
10:25 am – Study of Electro-Migration Resistivity of Micro Bump Using SnBi Solder Kei Murayama, Mitsuhiro Aizawa, and Mitsutoshi Higashi – Shinko Electric Industries Company, Ltd.
10:25 am – Capping Technologies for Wafer Level MEMS Packaging Based on Permanent and Temporary Wafer Bonding Kai Zoschke, Martin Wilke, Katrin Kaletta, CharlesAlix Manier, and Hermann Oppermann – Fraunhofer IZM; Matthias Wietstruck, Bernd Tillack, and Mehmet Kaynak – IHP GmbH; Klaus-Dieter Lang – Technical University Berlin
10:50 am – Nondestructive Failure Characterization of TSV Stacking Device through 3D Coupled Analysis: Failure Isolation and Computed Tomography Gyujei Lee, Joon-Ki Hong, and Namseog Kim – SK Hynix Semiconductor, Inc.
10:50 am – Electromigration of Solder Balls for Wafer-Level Packaging with Different Under Bump Metallurgies and Redistribution Layers Christine Hau-Riege, Beth Keser, Rey Alvarado, Ahmer Syed, Youwen Yau, Steve Bezuk, and Kevin Caffey – Qualcomm Technologies, Inc.
10:50 am – The Novel Assembly Method of a Field Deployable Biosensor Unit Peng Xu, Wei Wang, Fangmin Guo, Yuping Ge, and Shuhua Zhang – East China Normal University; Jiaotuo Ye and Le Luo – Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
11:15 am – Residual Stress Investigations at TSVs in 3D Micro Structures by HR-XRD, Raman Spectroscopy and fibDAC Uwe Zschenderlein and Bernhard Wunderle – Technische Universität Chemnitz; Dietmar Vogel and Ellen Auerswald – Fraunhofer ENAS; Ole Hölck – Fraunhofer IZM; Peter Ramm – Fraunhofer EMFT; Reinhard Pufall – Infineon Technologies
11:15 am – Low-Pressure Sintering Bonding with Cu and CuO Flake Paste for Power Devices Sungwon Park, Ryoji Uwataki, Shijo Nagao, Tohru Sugahara, and Katsuaki Suganuma – Osaka University; Yoshitaka Katoh, Hiroshi Ishino, and Kazuhiko Sugiura – Denso Corporation
11:15 am – SIMEIT-Project: Symbiosis of High Precision Inertial Sensor and Moderate Costs by Using 3D-System Integration Wolfram Steller, M. Juergen Wolf, and Klaus-Dieter Lang – Fraunhofer IZM; Christoph Meinecke – Technical University Chemnitz; Knut Gottfried – Fraunhofer ENAS; Gregor Woldt – MPD GmbH
Program Sessions: Friday, May 30, 8:00-11:40 a.m. Session 28: System-Level Thermal & Mechanical Models II
Session 29: Integrated RF & Power Modules
Session 30: Solders & Bonding
Committee: Modeling & Simulation
Committee: Electronic Components & RF
Committee: Materials & Processing
Session Co-Chairs: Pradeep Lall – Auburn University Tel: +1-334-844-3424 Email: lall@auburn.edu
Session Co-Chairs: Rockwell Hsu – Tiva Systems Inc. at Cisco Systems, Inc. Tel: +1-480-612-1469 Email: rohsu@cisco.com
Session Co-Chairs: Mikel Miller – Draper Laboratory Tel: +1-617-258-2844 Email: mrmiller@draper.com
Xuejun Fan – Lamar University Tel: +1-409-880-7792 Email: xuejun.fan@lamar.edu
P. Markondeya Raj – Georgia Institute of Technology Tel: +1-404 558 2615 Email: raj@ece.gatech.edu
Grace Yi Li – Intel Corporation Email: yi.li@intel.com
8:00 am – Mechanical Stress Management for Electrical Chip-Package Interaction (CPI) Wei Zhao, Mark Nakamoto, and Riko Radojcic – Qualcomm Technologies, Inc.
8:00 am – Modeling, Design and Demonstration of Multi-Die Embedded WLAN RF Front-End Module with UltraMiniaturized and High-Performance Passives Srikrishna Sitaraman, Fuhan Liu, Venky Sundaram, Sung Jin Kim, and Rao Tummala – Georgia Institute of Technology; Yuya Suzuki and Masakaz Hashimoto – Zeon Corporation; Vijay Nair and Telesphor Kamgaing – Intel Corporation; Frank Juskey – TriQuint Semiconductor
8:00 am – Wafer Injection Molded Solder: A New Fine Pitch Solder Bumping Technology on Wafers with Solder Alloy Composition Flexibility Jae-Woong Nah, Jeffrey Gelorme, Peter Sorce, Peter Brofman, Paul Lauro, Eric Perfecto, Mark McLeod, and Kazushige Toriyama – IBM Corporation; Takashi Nauchi – Senju Metal Industry Co., Ltd.; Akira Takaguchi – Senju System Technology Co., Ltd.
8:25 am – Cu Pillar Flip Chip Assembly: Chip Attach Process Failure Mode Study Shengmin Wen – Amkor Technology, Inc.
8:25 am – A Compact Four-Chip Package with 64 Embedded Dual-Polarization Antennas for W-Band Phased-Array Transceivers Xiaoxiong Gu, Duixian Liu, Christian Baks, Alberto Valdes-Garcia, Ben Parker, Md. R. Islam, Arun Natarajan, and Scott Reynolds – IBM Corporation
8:25 am – Reliability of Paste Based Transient Liquid Phase Sintered Interconnects Hannes Greve and F. Patrick McCluskey – University of Maryland
8:50 am – Mechanical and ThermoMechanical Stress Considerations in Applying 3D ICs to a Design Jia-Shen Lan – National Sun Yat-Sen University
8:50 am – Active Die Embedded Small Form Factor Radio Frequency Packages for Mobile Communication Devices Vijay Nair, Carlton Hanna, Ronald Spreitzer, and Johanna Swan – Intel Corporation
8:50 am – A Lead Free Joining Technology for High Temperature Interconnects Using Transient Liquid Phase Soldering (TLPS) Christian Ehrhardt and Klaus-Dieter Lang – Technical University Berlin; Matthias Hutter and Hermann Oppermann – Fraunhofer IZM
Refreshment Break: 9:15-10:00 a.m. 10:00 am – Modeling Microstructure Effects on Electromigration in Lead-Free Solder Joints Yong Liu, Jifa Hao, and Barry O’Connell – Fairchild Semiconductor Corporation; Jiamin Ni and Antoinette Maniatty – Rensselaer Polytechnic Institute
10:00 am – Design and Material Contributions to Second-Harmonic Nonlinearities in RF Silicon Integrated Passive Devices Robert Frye – RF Design Consulting, LLC; Robert Melville – Emecon, LLC; Kai Liu – STATS ChipPAC, Inc.
10:00 am – Developments of High-Bi Alloys as a High Temperature Pb-Free Solder Junghyun Cho and Sandeep Mallampati – State University of New York at Binghamton; Harry Schoeller – Universal Instruments Corporation; Liang Yin and David Shaddock – GE Global Research
10:25 am – Modeling and Experimental Demonstration of the Effect of Copper Through Package Vias (TPVs) on Thermal Performance of Glass Interposers Sangbeom Cho, Venky Sundaram, Yogendra Joshi, and Rao Tummala – Georgia Institute of Technology; Yoichiro Sato – Asahi Glass; Akira Mieno – Atotech
10:25 am – Integration of Magnetic Materials into Package RF and Power Inductors on Organic Substrates for SiP Applications Hao Wu, Shirong Zhao, Cheng Lv, and Hongbin Yu – Arizona State University; Donald Gardner, Shawn Hansen, and Zhihua Zou – Intel Corporation
10:25 am – The Quantum Theory of SolidState Atomic Bonding Chin C. Lee – University of California, Irvine
10:50 am – Failure Mechanism Investigation of Stacked Via Cracking in Organic Chip Carrier Shidong Li, Sushumna Iruvanti, and Randall Werner – IBM Corporation
10:50 am – Through Silicon Capacitor Co-Integrated with TSV as an Efficient 3D Decoupling Capacitors Solution for Power Management on Silicon Interposer Olivier Guiller, Sylvain Joblot, and Alexis Farcy – STMicroelectronics; Yann Lamy and Emmanuel Defay – CEA-LETI
10:50 am – Effective Method to Disperse and Incorporate Carbon Nanotube in Electroless Ni-P Alloy Deposits Sha Xu and Yan Cheong Chan – City University of Hong Kong; Xiaoxin Zhu, Hua Lu, and Chris Bailey – University of Greenwich
11:15 am – FEA Modeling for the Design and Reliability Performance of Wafer Level Chip Scale Package John Yang, Senthil Sivaswamy, Dough Hawks, and Befruz Tasbas – Peregrine Semiconductor
11:15 am – Ultrawideband Ultralow PDN Impedance of Decoupling Capacitor Embedded Interposers Using Narrow Gap Chip Parts Mounting Technology for 3D Integrated LSI System Katsuya Kikuchi and Masahiro Aoyagi – National Institute of AIST; Masaaki Ujiie and Shinya Takayama – Arena Company Ltd.
11:15 am – Electroless Ni-W-P Alloys as a Barrier Layer between Zn-Based High Temperature Solders and Cu Substrate Li Liu and Changqing Liu – Loughborough University
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Program Sessions: Friday, May 30, 1:30-5:10 p.m. Session 31: PoP, SiP, and Die Stacking
Session 32: Substrates
Session 33: Novel Test Methods
Committee: Advanced Packaging
Committee: Materials & Processing
Committee: Applied Reliability
Session Co-Chairs: Raj N. Master – Microsoft Corporation Tel: +1-650-693-1810 Email: rajm@microsoft.com
Session Co-Chairs: Dwayne Shirley – Qualcomm Technologies, Inc. Tel: +1-858-651-1925 Email: dshirley@qti.qualcomm.com
Session Co-Chairs: Lakshmi N. Ramanathan – Microsoft Corporation Tel: +1-425-421-3838 Email: laramana@microsoft.com
Deborah Patterson – Amkor Technology, Inc. Tel: +1-480-786-7891 Email: deborah.patterson@amkor.com
Yu-Hua Chen – Unimicron Tel: +886-3-5995899 ext. 2109 Email: yh_chen@unimicron.com
Sridhar Canumalla – Microsoft Corporation Tel: +1-425-538-4060 Email: scanuma@microsoft.com
1:30 pm – Fabrication and Reliability Evaluation of a Novel Package-on-Package (PoP) Structure Based on Organic Substrate Xiaofeng Sun, Lixi Wan, and Yuan Lu – Institute of Microelectronics, Chinese Academy of Sciences
1:30 pm – Improvement of Substrate and Package Warpage by Copper Plating Process Optimization Omar Bchir, Houssam Jomaa, Chin Kwan Kim, Layal Rouhana, Kuiwon Kang, Milind Shah, and Steve Bezuk – Qualcomm Technologies, Inc.
1:30 pm – Pad Crater Detection Using Acoustic Waveform Analysis W. Carter Ralph and Gregory Daspit – Southern Research Institute; Pradeep Lall – Auburn University; Elizabeth Benedetto, Aileen Allen, and Keith Newman – Hewlett Packard
1:55 pm – Strip Grinding Introduction for Thin PoP and CSP Jinseong Kim – Amkor Technology Korea
1:55 pm – Coreless Substrate with Unsymmetric Dielectric Layer Design to Improve Package Warpage Wei Lin, Bora Baloglu, Ken Stratton, Shengmin Wen, and Sai Priya Sundarraman – Amkor Technology, Inc.
1:55 pm – High Acceleration Board Level Reliability Drop Test Using Dual Mass Shock Amplifier Andy Zhang – Texas Instruments, Inc.
2:20 pm – Cost and Performance Effective Silicon Interposer and Vertical Interconnect for 3D ASIC and Memory Integration Li Li and Jie Xue – Cisco Systems, Inc.; Mitsutoshi Higashi, Akihito Takano, and Gary Ikari – Shinko Electric Industries Company, Ltd.
2:20 pm – Ultra Low CTE (1.8 ppm/°C) Core Material for Next Generation Thin CSP Tomohiko Kotake, Hikari Murai, Shin Takanezawa, Masato Miyatake, Masaaki Takekoshi, and Masahisa Ose – Hitachi Chemical Co., Ltd.
2:20 pm – Crack Propagation Relationships for SAC Leadfree Interconnects under Thermal Cycling Using X-Sectioning and Micro-CT Pradeep Lall, Mahendra Harsha, Aditya Agarwal, and Jeff Suhling – Auburn University
Refreshment Break: 2:45-3:30 p.m.
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3:30 pm – Assembly and Packaging of Non-Bumped 3D Chip Stacks on Bumped Substrates Bing Dang, Joana Maria, Qianwen Chen, JaeWoong Nah, Paul Andry, Cornelia Tsang, Christy Tyberg, Raphael Robertazzi, Katsuyuki Sakuma, Michael Scheuermann, Michael Gaynes, and John Knickerbocker – IBM Corporation
3:30 pm – A Novel Redistribution Layer Tailored by Nanotwinned Copper Decreases Warpage in Wafer Level Packaging Heng Li, Chunsheng Zhu, Gaowei Xu, and Le Luo – Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
3:30 pm – High Resolution and Fast Throughput-Time X-Ray Computed Tomography for Semiconductor Packaging Applications Mario Pacheco, Deepak Goyal, and Yan Li – Intel Corporation; John W. Elmer and Holly D. Barth – Lawrence Livermore National Laboratory
3:55 pm – The Miniaturization of a MicroBall Endoscope by SiP Approach Xunxun Zhu, Jian Cai, Yu Chen, Yingke Gu, Xiang Xie, Qian Wang, and Zhihua Wang – Tsinghua University; Xiaofeng Sun and Lixi Wan – Institute of Microelectronics, Chinese Academy of Sciences
3:55 pm – Demonstration of Low Cost 3-5 µm RDL Line Lithographic Layers on Glass Interposers Hao Lu, Brett Sawyer, Venky Sundaram, and Rao Tummala – Georgia Institute of Technology; Yutaka Takagi – NGK Spark Plugs Co. Ltd.; Yuya Suzuki – Zeon Corporation
3:55 pm – In-Situ Measurements of the Relative Thermal Resistance: Highly Sensitive Method to Detect Crack Propagation in Solder Joints Gordon Elger – Technische Hochschule Ingolstadt; Shri Vishnu Kandaswamy, Maarten von Kouwen, and Robert Derix – Philips Technology GmbH
4:20 pm – Design and Demonstration of Paper-Thin and Low-Warpage Single and Vertically Stackable Organic Packages for Smart Mobile Applications Sung Jin Kim, Zihan Wu, Fuhan Liu, Vanessa Smet, P. Markondeya Raj, Venky Sundaram, and Rao Tummala – Georgia Institute of Technology; Makoto Kobayashi – NAMICS Corporation
4:20 pm – Characterization of Thin Polymer Films with the Focus on Lateral Stress and Mechanical Properties and Their Relevance to Microelectronics Markus Woehrmann – Technical University Berlin; Hans Walter, Thorsten Fischer, and Michael Toepper – Fraunhofer IZM
4:20 pm – The Corrosion Failure Risk Assessment of Memory Module at Data Center in Harsh Environmental Conditions Sungwon Han, Jangyong Bae, Yuchul Hwang, and Youngsun Park – Samsung Electronics Company, Ltd.
4:45 pm – Manufacturing Readiness of BVA™ Technology for Ultra-High Bandwidth Package-on-Package Wael Zohni, Rajesh Katkar, and Rey Co – Invensas Corporation
4:45 pm – Thin Polymer Dry-Film Dielectric Material and a Process for 10 Micrometer Interlayer Vias in High Density Organic and Inorganic Substrates for 50 Micron Bump Pitch Yuya Suzuki – Zeon Corporation; Yutaka Takagi – NGK Spark Plug Co., Ltd.; Venky Sundaram and Rao Tummala – Georgia Institute of Technology
4:45 pm – Colour Shift in Remote Phosphor in LED Based Products Maryam Yazdan Mehr – Materials innovation institute (M2i); Willem Van Driel – Philips Lighting; Kouchi Zhang – Delft University of Technology
Program Sessions: Friday, May 30, 1:30-5:10 p.m. Session 34: Novel Packaging
Session 35: Innovations in Wirebond Technology
Session 36: Recent Advancement in Manufacturing Technology
Committee: Emerging Technologies
Committee: Interconnections
Committee: Assembly & Manufacturing Technology
Session Co-Chairs: Vasudeva P. Atluri – Renavitas Technologies Tel: +1-480-704-4846 Email: vpatluri@ieee.org
Session Co-Chairs: William Chen – Advanced Semiconductor Engineering, Inc. Tel: +1-408-250-4290 Email: william.chen@aseus.com
Session Co-Chairs: Jae-Woong Nah – IBM Corporation Tel: +1-914-945-1875 Email: jnah@us.ibm.com
Jai Agrawal – Purdue University Tel: +1-408-772-6727 Email: jaipagrawal@gmail.com
Gilles Poupon – CEA-LETI Tel: +33-438-785-399 Email: gilles.poupon@cea.fr
Mark Gerber – Texas Instruments Tel: +1-214-567-7402 Email: mark_gerber@att.net
1:30 pm – 3D Multifunctional System Integration in Flexible Substrates Karlheinz Bock, E. Yacoub-George, W. Hell, A. Drost, H. Wolf, D. Bollmann, C. Landesberger, G. Klink, H. Gieser, and C. Kutter – Fraunhofer EMFT
1:30 pm – Process Optimization and Reliability Study for Cu Wire Bonding Advanced Nodes Ivy Qin, Basil Milton, Hui Xu, Horst Clauberg, and Bob Chylak – Kulicke and Soffa, Inc.; Abe Hidenori, Dongchul Kang, Yoshinori Endo, Masahiko Osaka, and Shinya Nakamura – Hitachi Chemical Co., Ltd.
1:30 pm – High Uniformity and High Speed Copper Pillar Plating Technique Konstantin Kholostov, Aliaksei Klyshko, Rocco Crescenzi, and Marco Balucani – Sapienza University of Rome; Danilo Ciarniello, Paolo Nenzi, and Roberto Pagliucci – Rise Technology S.r.l.; Dario Bernardi – 2BG S.r.l.
1:55 pm – Preparation of a Micro Rubidium Vapor Cell and Its Integration in a ChipScale Atomic Magnetometer Yu Ji, Jintang Shang, and Youpeng Chen – Southeast University; Ching-Ping Wong – The Chinese University of Hong Kong
1:55 pm – Silver-Assisted Copper Wire Bonding Using Solid-State Process Yi-Ling Chen, Yuan-Yun Wu, and Chin C. Lee – University of California, Irvine
1:55 pm – Plasma-Based Die Singulation Processing Technology David Pays-Volard, Linnell Martinez, Kenneth Mackenzie, Thierry Lazerand, and Russell Westerman – Plasma-Therm, LLC
2:20 pm – Nanowires-Based High-Density Capacitors and Thinfilm Power Sources in Ultra-Thin 3D Glass Modules Saumya Gandhi, Ho-Yee Hui, Parthasarathi Chakraborti, P. Markondeya Raj, Michael Filler, Meilin Liu, and Rao Tummala – Georgia Institute of Technology
2:20 pm – Ag Alloy Wire Characteristic and Benefits Jensen Tsai, Albert Lan, Joseph Huang, and Otis Hong – Siliconware Precision Industries Co., Ltd.
2:20 pm – Removed Organic Solderability Preservatives (OSPs) by Ar/O2 Microwave Plasma to Improve Solder Joint in Thermocompression Flip Chip Bonding Jr-Wei Peng, Yan-Siang Chen, and Yi Chen – Advanced Semiconductor Engineering, Inc.; JiangLong Liang – Department of Materials Science and Engineering, National Cheng Kung University
Refreshment Break: 2:45-3:30 p.m. 3:30 pm – Development of a High Density Glass Interposer Based on Wafer Level Packaging Technologies Michael Toepper, Markus Woehrmann, Ivan Ndip, and Klaus-Dieter Lang – Fraunhofer IZM; Nils Juergensen – Fraunhofer ICT
3:30 pm – Copper versus Palladium Coated Copper Wire Process and Reliability Differences Chu-Chung Lee, Tuanh Tran, Andrew Mawer, Daniel Boyne, and Leo Higgins III – Freescale Semiconductor
3:30 pm – A PoP Structure to Support I/O over 2000 Dyi-Chung Hu, Puru Lin, Yu Hua Chen, and ChunTing Lin – Unimicron Technology Corporation
3:55 pm – Novel Sealing Technology for Organic EL Display and Lighting by Means of Modified Surface Activated Bonding Method Takashi Matsumae, Masahisa Fujino, and Tadatomo Suga – University of Tokyo
3:55 pm – Improving the Quality of Copper Wire Bond Connections Using a Detailed Friction Model Simon Althoff, Jan Christoph Neuhaus, Tobias Hemsel, and Walter Sextro – University of Paderborn
3:55 pm – Enabling Eutectic Soldering of 3D Opto-Electronics on Low Tg Flexible Interposers Meriem Ben-Salah Akin, Lutz Rissing, and Wolfgang Heumann – Leibniz University of Hanover
4:20 pm – Solder Joint Inspection with Induction Thermography Johannes Bohm, Klaus-Juergen Wolter, and Henning Heuer – Technical University Dresden
4:20 pm – High Aspect Ratio Lithography for Litho-Defined Wire Bonding Zahra Kolahdouz Esfahani, Henk van Zeijl, and Kouchi Zhang – Delft University of Technology
4:20 pm – Reduction of Thermal Expansion Coefficient of Electrodeposited Copper for TSV by Additive Kazuo Kondo, Shingo Mukahara, Taro Hayashi, Minoru Takeuchi, Takeyasu Saito, Naoki Okamoto, and Masayuki Yokoi – Osaka Prefecture University; Jin Onuki – Ibaragi University; Masaru Bunya – Nittobo Medical Co., Ltd.
4:45 pm – Development of B-Spline X-Ray Diffraction Imaging Techniques for Die Warpage and Stress Monitoring inside Fully Encapsulated Packaged Chips Patrick McNally, Chiu Soon Wong, Aidan Cowley, and Nick Bennett – Dublin City University; Andrej Ivankovic, Mario Gonzalez, Vladimir Cherman, Bart Vandevelde, and Ingrid De Wolf – IMEC; Andreas Danilewsky – Albert-Ludwigs-Universität Freiburg
4:45 pm – Comprehensive Intermetallic Compound Phase Analysis and Its Thermal Evolution at Cu Wirebond Interface In-Tae Bae and Dae Young Jung – State University of New York at Binghamton; Jenny Chang and Scott Chen – Advanced Semiconductor Engineering, Inc.
4:45 pm – Automated Inspection for 3Di Process Assurance James Wood, Eric Perfecto, and Vilmarie Soler – IBM Corporation; Thomas Luckenbach and Dror Milgrom – Camtek Ltd.
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Interactive Presentations: Wednesday, May 28, 9:00 - 11:00 a.m. and 2:00 - 4:00 p.m. Wednesday, May 28 Session 37: Interactive Presentations 1 9:00 a.m. - 11:00 a.m.
Thermal Management for Wafer Level Packaging (WLP) Tiao Zhou and Arkadii Samoilov – Maxim Integrated
Committee: Interactive Presentations Mark Poliks – i3 Electronics, Inc. Tel: +1-607-727-7104 Email: mark.poliks@i3electronics.com
Inkjet Printed Nano-Particle Cu Process for Fabrication of Re-Distribution Layers on Silicon Wafer Ayat Soltani, Juha Niittynen, Tero Kumpulainen, and Matti Mäntysalo – Tampere University of Technology
Ibrahim Guven – University of Arizona Tel: +1-520-626-2257 Email: guven@email.arizona.edu
Design of Multi-Sensor for the Safety Monitoring of the Heavy Machinery Long Li – Huazhong University of Science & Technology
Low Cost Fabrication of TSV-Based Silicon Interposer Using Wet Chemical Etching and Its Application in 3D Packaging Jiaotuo Ye, Xiao Chen, Wei Gai, Gaowei Xu, and Le Luo – Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
Novel TSV Process Technologies for 2.5D/3D Packaging Yasuhiro Morikawa, Toshiyuki Sakuishi, Takahide Murayama, Yuu Nakamuta, Akiyoshi Suzuki, and Koukou Suu – ULVAC, Inc. and NMEMS
Investigation of a Photodefinable Glass Substrate for Millimeter-Wave Radios on Package Telesphor Kamgaing, Adel Elsherbini, Torrey Frank, Sasha Oster, and Valluri Rao – Intel Corporation Design and Fabrication of Low-Pressure Piezoresistive MEMS Sensor for Fuel Cell Electric Vehicles Minkyu Lee, Kiyoung Nam, Seungyong Lee, Hakgu Kim, Chimyung Kim, Yongsun Park, and Byungki Ahn – Hyundai Motor Company; Taewan Kim and Hochul Seo – Sejong Industrial Company, Ltd. Demonstration of TCNCP Flipchip Reliability with 30µm Pitch Cu Bump and Substrate with Thin Ni and Thick Au Surface Finish Weihong Zhang, Shengping Hong, Weihong Zhang, Saihua Wu, Haijun Shen, Feng Zhou, and Xiaolong Yan – Nantong Fujitsu Microelectronics Ltd. Integrated Process Characterization and Fabrication Challenges for 2.5D IC Packaging Utilizing Silicon Interposer with Backside Via Reveal Process Cheng-Hsiang Liu, Chun-Ling Tsai, Hung-Hsien Chang, and Chang-Lun Lu – Siliconware Precision Industries Co., Ltd. Structure Effects on the Electrical Reliability of Fine-Pitch Cu Micro-Bumps for 3D Integration Byeong-Rok Lee, June-Bum Kim, Seung-Hyun Kim, and Byeong-Hyun Bae – Andong National University; Ho-Young Son, Tac-Keun Oh, Min-Suk Suh, and Kwang-Yoo Byun – Hynix Semiconductor, Inc. Demonstration of Low Cost TSV Fabrication in Thick Silicon Wafers Erik Vick, Dorota Temple, Rex Anderson, and John Lannon – RTI International; Chuan Li, Kirk Peterson, George Skidmore, and C. J. Han – DRS RSTA, Inc. X-Ray Micro-Beam Diffraction Measurement of the Effect of Thermal Cycling on Stress in Cu TSV: A Comparative Study Chukwudi Okoro, Lyle Levine, and Yaw Obeng – NIST; Ruqing Xu – Argonne National Laboratory; Klaus Hummler – SEMATECH Adhesive Enabling Technology for Directly Plating Copper onto Glass Lutz Brandt, Zhiming Liu, Hailuo Fu, and Sara Hunegnaw – Atotech USA Inc. Very Thin Packaging Approaches to Achieve Functionality Integration Prior to TSV Implementation Fernando Roa – Amkor Technology, Inc.
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Through-Glass Interposer Integrated High Quality RF Components Cheolbok Kim, Hyup Jong Kim, and Yong-Kyu Yoon – University of Florida; Aric Shorey and Windsor Thomas – Corning, Inc.; David Senior – Universidad Tecnologica de Bolivar Effect of Reduced TSV Confinement on Reliability of 3D Microelectronics Package David C. Woodrum, Xi Liu, and Suresh Sitaraman – Georgia Institute of Technology Increasing the Lifetime by Higher Temperatures: Solders vs. Silver Sintering Aaron Hutzler, Andreas Schletz, Adam Tokarski, Silke Kraft, and Sigrid Zischler – Fraunhofer IISB A Novel 20µm Pitch TSV Interconnection Method Using NCFs with Zn Nano-Particles Ji-Won Shin, Yong-Won Choi, and Kyoung-Wook Paik – KAIST; Un Byung Kang, Sun Kyung Seo, and Ji Hwan Hwang – Samsung Electronics Company, Ltd. New Die-Attachment Technologies for Power Electronic Assemblies Eike Möller, Adeel Ahmad Bajwa, and Jürgen Wilde – University of Freiburg, IMTEK; Eugen Rastjagaev – Infineon Technologies, Austria AG High Vacuum Wafer Level Packaging for HighValue MEMS Applications Stephane Nicolas, Florent Greco, Stephane Caplet, Caroline Coutier, Cyril Dressler, Marcel Audoin, Xavier Baillin, Ghalia Dehag, Frederic Souchon, and Stephane Fanget – CEA-LETI Thermal and Electrical Tests of Air-Gap TSV Cui Huang, Dong Wu, and Zheyao Wang – Tsinghua University Heterogeneous System Integration Pseudo-SoC Technology for Smart Health Care Intelligent Life Monitor Engine and Eco-System (Silmee) Hiroshi Yamada, Takuji Suzuki, and Shigenobu Minami – Toshiba Corporation; Yasuhiro Sato and Nobuhiro Ooshima – Toshiba Hokuto Electronics Corporation; Hiroyuki Hirai – Toshiba Design & Manufacturing Service Corporation Effects of Environmental Conditions on the Microstructure, Electrical Properties, and Interfacial Reliability of Printed Ag/Polyimide for Low-Cost Flexible Electronic Systems Byung-Hyun Bae, Min-Su Jeong, Byeong-Rok Lee, and YoungBae Park – Andong National University; Joung-Hoon Choo, Eun-Kuk Choi, and Jong-Sun Yoon – HICEL
A Study on the Fine Pitch Chip Interconnection Using Cu/SnAg Bumps and B-Stage Non-Conductive Films (NCFs) for 3D-TSV Vertical Interconnection Yongwon Choi, Jiwon Shin, and Youngsoon Kim – KAIST; Kyunglim Suk and Il Kim – Samsung Electronics Co., Ltd.
Wafer Level Warpage Characterization for Backside Manufacturing Processes of TSV Interposers Feng Jiang, Kai Xue, Xiangmeng Jing, Daquan Yu, and Dongkai Shangguan – National Center for Advanced Packaging; Qibin Wang – IME
Pathfinding Methodology for Optimal Design and Integration of 2.5D/3D Interconnects Farhang Yazdani – BroadPak Corporation; John Park – Mentor Graphics
Stretchable and Transparent Silicone/ZnO Nanocomposite for Advanced LED Packaging Xueying Zhao, Zhuo Li, and Liyi Li – Georgia Institute of Technology
Cost Effective Interposer for Advanced Electronic Packages Satoru Kuramochi, Sumio Koiwa, and Kousuke Suzuki – Dai Nippon Printing Co., Ltd.; Yoshitaka Fukuoka – Worldwide Electronic Integrated Substrate Technology Inc.
Warpage Characterization of Panel Fan-Out (P-FO) Package Hung Wen (Kenny) Liu, Yi Wei Liu, Jason Ji, Jash Liao, Agassi Chen, Yan-Heng Chen, Nicholas Kao, and Yi-Che Lai – Siliconware Precision Industries Co., Ltd.
Wednesday, May 28 Session 38: Interactive Presentations 2 2:00 p.m. - 4:00 p.m. Committee: Interactive Presentations Session Co-Chairs: Mark Eblen – Kyocera America, Inc. Tel: +1-858-614-2537 Email: mark.eblen@kyocera.com Michael Mayer – University of Waterloo Tel: +1-519-888-4024 Email: mmayer@uwaterloo.ca A Novel Double Layer NCF for Highly Reliable Micro-Bump Interconnection Ji-Won Shin, Yong-Won Choi, and Kyoung-Wook Paik – KAIST; Un Byung Kang, Ji Hwan Hwang, and Sun Kyung Seo – Samsung Electronics Company, Ltd. CO2-Laser Drilling of TGVs for Glass Interposer Applications Lars Brusberg, Robert Rund, and Henning Schröder – Fraunhofer IZM; Marco Queisser and Klaus-Dieter Lang – Technical University Berlin Effects of Pad Surface Finish on Interfacial Reliabilities of Cu-Pillar/Sn-Ag Bumps of 2.5D TSV-Interposer on PCB Applications Youngsoon Kim – Samsung Electro-Mechanics Company, Ltd.; Jiwon Shin, Youngwon Choi, and Kyungwook Paik – KAIST The Effect of Variations in the Reflow Profile on the Solidification Temperature, Microstructure and Room Temperature Fatigue Life of SnAgCu Solder Joints Francis Mutuku and Eric Cotts – Binghamton University; Babak Arfaei and Martin Anslem – Universal Instruments Corporation Development of the Thin Film with High Thermal Conductivity for Power Devices Hiroshi Takasugi, Shin Teraki, Tsuyoshi Kurokawa, and Issei Aoki – NAMICS Corporation Development of Electroless Iron-Nickel Plating Process for Microelectronic Applications Luo Yu, Sung K. Kang, Oblesh Jinka, Maurice Mason, Steven Cordes, and Lubomyr Romankiw – IBM Corporation Novel Conductive Paste Using Hybrid Silver Sintering Technology for High Reliability Power Semiconductor Packaging Howard (Hwa Il) Jin, Senthil Kanagavel, and Wai Foo Chin – Alpha Advanced Materials Novel Low Temperature Curable Photo-Sensitive Insulator Kenji Okamoto, Hikaru Mizuno, Tomohiko Sakurai, and Katsumi Inomata – JSR Novel Microprobe Array for Force and Neural Sensing: Simulation and Experiment Matin Mdabdul – Bangladesh University of Engineering and Technology; Ikedo Akihito, Kawano Takeshi, Sawada Sawada, and Ishida Makoto – Toyohashi University of Technology Chip Stacking Material and Assembly Data for Highly Silica Filled One Step Chip Attach Materials for Both Thermal Compression Bonding and Mass Reflow Processes Christopher Breach, Daniel Duffy, and David Eichstadt – Kester Process Compatibility of Conventional and LowTemperature Polyimide Materials for 2.5D and 3D IC Packaging: A User’s Perspective Guilian Gao, Bong-Sub Lee, Andrew Cao, and Ellis Chau – Invensas Corporation Optimization of CMP Process for Second TSV Reveal of Backside Process Considering Interaction Effect of Related Processes and Die Design Donghoon Lee, D. H. Kim, S. C. Han, J. S. Park, H. H. Jung, J. H. Kim, Y. S. Chung, S. M. Seo, and Choon Lee – Amkor Technology Korea; Y. S. Kim – Sungkyunkwan University Reliability Challenges for Cost Effective Package Materials: Enabling Ag Wire and Pure Sn Bump Ha-Young You, Jae-Young Jung, and Jung-Woo Pyun – Samsung Electronics Company, Ltd.
Interactive Presentations: Wednesday, May 28, 2:00 - 4:00 p.m. and Thursday, May 29, 9:00 - 11:00 a.m. Degradation Mechanisms in Electronic Mold Compounds Subjected to High Temperature in Neighborhood of 200°C Pradeep Lall, Shantanu Deshpande, Yihua Luo, and Michael Bozack – Auburn University; Luu Nguyen and Masood Murtuza – Texas Instruments, Inc. High Throughput Roller Type Nano-Pattern Transfer Technique on Both Rigid Flexible Substrates and Mold Deformation Analysis under Atmospheric Imprint Environment Yinsheng Zhong and Matthew M. F. Yuen – Hong Kong University of Science & Technology Capacitive Deionization of Water Coolant Using Hybrid Carbon Electrodes for High Power Electronic Applications Ziyin Lin, Zhuo Li, Kyoungsik Moon, and Chingping Wong – Georgia Institute of Technology Low Energy Harvesters: A Technology Survey Omer Farook, Chandra Sekhar, and Ashfaq Ahmed – Purdue University Calumet A Microfluidic Chip Integrated with a SonoTransducer Using Combined Resonance between Oscillations of Hemispherical Micro Glass Shell and Enclosed Microfluid Jiafeng Xu and Jintang Shang – Southeast University; Ching-Ping Wong – The Chinese University of Hong Kong RF Energy Harvesting Jai Agrawal and Parvizso Aminov – Purdue University Calumet Localized Metal Plating on Aluminum Back Side PV Cells Marco Balucani and Konstantin Kholostov – Sapienza University of Rome; Luca Serenelli, Massimo Izzi, and Mario Tucci – ENEA Casaccia Research Centre; Dario Bernardi – 2BG Sensitivity Enhancement of a Novel High Temperature Thermal Conductivity Sensor Using CMOS Technology and Modified TO5 Chip Package Sohab Sarfraz and R. Vasant Kumar – University of Cambridge; Florin Udrea – University of Cambridge, Cambridge CMOS Sensors Ltd. High-Aspect Ratio Slanted Etching of Micro- and Nanostructures on Silicon with Low Cost and Versatile Slanting Angles Liyi Li – Georgia Institute of Technology
Thursday, May 29 Session 39: Interactive Presentations 3 9:00 a.m. - 11:00 a.m. Committee: Interactive Presentations Session Co-Chairs: Patrick Thompson – Texas Instruments, Inc. Tel: +1-214-567-0660 Email: patrick.thompson@ti.com Rao Bonda – Amkor Technology, Inc. Tel: +1-480-786-7749 Email: rao.bonda@amkor.com Transferrable Fine Pitch Probe Technology Yang Liu, Steven L. Wright, Bing Dang, Paul S. Andry, Robert J. Polastre, and John Knickerbocker – IBM Corporation Improvement of the Crystallinity of Electroplated Copper Thin Films for Highly Reliable 3D Interconnections Hideo Miura, Chuanhong Fan, Osamu Asai, Ryosuke Furuya, and Ken Suzuki – Tohoku University Process, Assembly and Electromigration Characteristics of Glass Interposer for 3D Integration Chun-Hsien Chien, Ching-Kuan Lee, Chun-Te Lin, Hsun Yu, Heng-Chieh Chien, Yu-Min Lin, Chau-Jie Zhan, Cheng-Ta Ko, Wei-Chung Lo, and Yung Jean Lu – Industrial Technology Research Institute (ITRI) Improved PCB Via Pattern to Reduce Crosstalk at Package BGA Region for High Speed Serial Interface Yujeong Shim, Kyungsuk Oh, Cuong Nguyen, Alex Razmadze, and Janani Chandrasekhar – Altera Corporation A Wafer Level Through-Stack-Via Integration Process with One-Time Bottom-up Copper Filling Yunhui Zhu, Xin Sun, Runiu Fang, Xiao Zhong, Yuan Bian, Yong Guan, Min Miao, and Yufeng Jin – Peking University; Shenglin Ma – Xiamen University Five-Die Stacking, Three Dimensional Interconnect Using Au and Pillar Bumps Lung-Hua Ho, Fei-Jain Wu, Chih-Ming Kuo, Chia-Jung Tu, Chih-Hsien Ni, Shih-Chieh Chang, Kung-An Lin, ChuanYu Wu, Wei-Hsin Wu, and Yung Sheng Wu – Chipbond Technology Corporation Effect of Joint Shape Controlled by Thermocompression Bonding on the Reliability Performance of 40µm-Pitch Solder Micro Bump Interconnections Chau-Jie Zhan and Yu-Wei Huang – Industrial Technology Research Institute (ITRI); Chih Chen – National Chiao Tung University
Industrial Technology Research Institute (ITRI) Sue-Chen Liao – Industrial Technology Research Institute (ITRI)
Development of Microbump Joint Fabrication Process Using Cone Shape Au Bumps for 3D LSI Chip Stacking Fumito Imura, Shunsuke Nemoto, Naoya Watanabe, Wei Feng, Katsuya Kikuchi, Hiroshi Nakagawa, and Masahiro Aoyagi – National Institute of AIST
3D Integration and Assembly of Wireless Sensor Nodes for ‘’Green’’ Sensor Networks Jian Lu, Hironao Okada, Toshihiro Itoh, and Ryutaro Maeda – Advanced Industrial Science and Technology; Takeshi Harada – NMEMS Technology Research Organization
Effect of Polymer Liners in CNT Based Through Silicon Vias Brajesh Kumar Kaushik, Archana Kumari, Manoj Kumar Majumder, and Sanjeev Kumar Manhas – Indian Institute of Technology Roorkee
New Demultiplexer Component for Optical Polymer Fiber Communication Systems Sebastian Hoell, Matthias Haupt, and Ulrich H. P. Fischer – Harz University of Applied Sciences
Investigation of Low-Temperature Deposition High-Uniformity Coverage Parylene-HT as a Dielectric Layer for 3D Interconnection Thanh-Tung Bui, Naoya Watanabe, Fumiki Kato, Katsuya Kikuchi, and Masahiro Aoyagi – National Institute of AIST; Xiaojin Cheng – Loughborough University
Nanofiller Based Spin-on Materials Enabling Negligible Reflection of Silicon Photonic External Coupling Yoichi Taira, Kuniaki Suaoke, and Hidetoshi Numata – IBM Corporation Effect of Patterned Substrate on Light Extraction Efficiency of Chip-on-Board Packaging LEDs Huai Zheng, Zhili Zhao, Yiman Wang, Lang Li, Sheng Liu, and Xiaobing Luo – Huazhong University of Science & Technology
Arrays of Millimeter-Wave Silicon Waveguides for Interchip Communication on Glass Interposer Qidong Wang, Daniel Guidotti, Daquan Yu, Liqiang Cao, and Tianchun Ye – Institute of Microelectronics, Chinese Academy of Sciences Effect of Ag and Cu Content in Sn Based Pb-Free Solder on Electromigration Minhua Lu, Charles Goldsmith, Thomas Wassick, Eric Perfecto, and Charles Arvin – IBM Corporation
Low Loss Transmission Lines on Flexible COP Substrate by Standard Lamination Process Chang-Ho Liou, Wen-Ching Ko, Je-Ping Hu, and Chun-Ting Liu – Industrial Technology Research Institute (ITRI); HsinChia Lu, Yi-Fan Lin, and Shih-Keng Chuang – National Taiwan University Reliability Improvement of Solder Anisotropic Conductive Film (ACF) Joints by Morphological Control of Solder Joints Yoo-Sun Kim, Seung-Ho Kim, and Kyung-Wook Paik – KAIST FBEOL No-Aluminum Pad Integration in Pb-Free C4 Products for Environmental and Cost Benefits Ekta Misra, Thomas Wassick, Timothy Daubenspeck, David Questad, Krishna Tunga, and Gary Lafontant – IBM Corporation Preparing 25Gbps Electrical I/O for Exascale Computing Systems Lei Shan, Young Kwark, Renato Rimolo-Donadio, Christian Baks, Michael Gaynes, and Timothy Chainer – IBM Corporation; Manabu Hoshino, Toshihiko Jimbo, Junji Kodemura, and Ikkei Matsuura – Zeon Corporation SMT-Compatible, Large Low-CTE Package-to-PCB Interconnections with Solder Strain Relief Using Polymer Collars Gary Menezes, Vanessa Smet, Venky Sundaram, Pulugurtha Markondeya Raj, and Rao Tummala – Georgia Institute of Technology; Makoto Kobayashi – NAMICS Corporation Modeling of Crosstalk Effects in Coupled MLGNR Interconnects Based on FDTD Brajesh Kumar Kaushik, Ramesh Kumar Vobulapuram, and Patnaik Amalendu – Indian Institute of Technology Roorkee Characteristics of Ceramic BGA Using Polymer Core Solder Balls Hiroya Ishida and Kiyoto Matsushita – Sekisui Chemical Co., Ltd. Solder Paste Deposit Volume Repeatability: A Comparison of Jetting and Screen Printing Gustaf Mårtensson – Chalmers University of Technology; Tord Karlin – Micronic Mydata AB The Study of Bare Die FCBGA Die Damage in Response to Applied Mechanical Stress during Heat Sink Assembly Heidi S. Y. Ho and Daijiao Wang – Broadcom Corporation; Michael Johnson and C. J. Berry – Amkor Technology, Inc. Prognostication of Copper-Aluminum Wirebond Reliability under High Temperature Storage and Temperature-Humidity Pradeep Lall and Shantanu Deshpande – Auburn University Low-Frequency Testing of Through Silicon Vias for Defect Diagnosis in Three-Dimensional Integrated Circuit Stacking Technology Yichao Xu, Xin Sun, Guanjiang Wang, Runiu Fang, and Yufeng Jin – Peking University; Min Miao – Beijing Information Science & Technology University Fast Estimation of LEDs Accelerated Lifetime by Online Test Method Qi Chen, Quan Chen, and Xiaobing Luo – Huazhong University of Science & Technology Accelerated Vibration Reliability Testing of Electronic Assemblies Using Sine Dwell with Resonance Tracking Quang Su, James Pitarresi, Mohammad Gharaibeh, Aaron Stewart, and Gaurang Joshi – Binghamton University; Martin Anselm – Universal Instruments Corporation Methodology and Apparatus for Rapid Power Cycle Accumulation and In-Situ Incipient Failure Monitoring for Power Electronic Modules Roy Davis and Daniel Sprenger – Fairchild Semiconductor Corporation Reliability Testing of Wire Bonds Using Pad Resistance with van der Pauw Method Michael Mayer and Samuel Kim – University of Waterloo Fine-Pitch Probing on TSVs and Microbumps Using a Chip Prober Having a Transparent Membrane Probe Card Naoya Watanabe and Masahiro Aoyagi – Advanced Industrial Science and Technology; Michiyuki Eto and Kenji Kawano – STK Technology Co., Ltd.
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Interactive Presentations: Thursday, May 29, 2:00 - 4:00 p.m. and Friday, May 30, 8:30 - 10:30 a.m. Thursday, May 30 Session 40: Interactive Presentations 4 2:00 p.m. - 4:00 p.m. Committee: Interactive Presentations Session Co-Chairs: Mark Poliks – i3 Electronics, Inc. Tel: +1-607-727-7104 Email: mark.poliks@i3electronics.com Nam Pham – IBM Corporation Tel: +1-512-286-8011 Email: npham@us.ibm.com Thermal Management of 3D RF PoP Based on Ceramic Substrate Fengze Hou, Fengman Liu, Liqiang Cao, and Yuan Lu – National Center for Advanced Packaging; Yi He – Institute of Microelectronics, Chinese Academy of Sciences Copper Bump Pattern Optimization and Stress Comparison Study for DCA Packages Akash Agrawal, Owen Fay, and Mark Johnson – Micron Technology, Inc. Unit Model Description of Stresses in TSV/TGV/ TCV Interposers Cheng-Fu Chen – University of Alaska, Fairbanks Electrical-Thermal Characterization of Wires in Packages Kai Liu, Robert Frye, HyunTai Kim, YongTaek Lee, Gwang Kim, Susan Park, and Billy Ahn – STATS ChipPAC, Inc. Computational Investigation of Failure in Anodized Aluminum Sabrina Ball and Ibrahim Guven – The University of Arizona; Pankaj Sinha, Rajiv Rastogi, and Brian McCarson – Intel Corporation Study on Predicting the Residual Position of a Void Generated by Resin Flow Masayuki Mino – Hitachi, Ltd.; Tsutomu Kono – Hitachi, Ltd; Naoya Suzuki and Hiroshi Takahashi – Hitachi Chemical Co., Ltd. Modeling and Analysis of Temperature Effect on MEMS Gyroscope Ming Wen, Weihui Wang, Zhang Luo, Xing Guo, Shengzhi Zhang, and Sheng Liu – Huazhong University of Science & Technology Life Prediction and Classification of Failure Modes in Solid State Luminaires Using Bayesian Probabilistic Models Pradeep Lall, Peter Sakalaukus, and Junchao Wei – Auburn University Modeling for Reliability of Ultra Thin Chips in a System in Package Yong Liu and Richard Qian – Fairchild Semiconductor Corporation Development of Effective Thermal Characterization on Handheld Devices by Matrix Method Taiyu Chen and Chungfa Lee – Mediatek Heat Transfer Mechanism in Membrane Based Chemo-Resistive CMOS Gas Sensors Sohab Sarfraz and R. Vasant Kumar – University of Cambridge; Florin Udrea – University of Cambridge, Cambridge CMOS Sensors Ltd. A Novel Method to Predict Fluid/Structure Interaction in IC Packaging Chih-Chung Hsu – National Tsing Hua University; Tzu-Chang Wang and Yang-Kai Lin – CoreTech System (Moldex3D) Co., Ltd.
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Estimation of Mode Conversion and Crosstalk Impact from a Single-Ended Aggressor to a Differential Victim Using Statistical BER Analysis Arun Chada, James L. Drewniak, and Jun Fan – Missouri University of Science and Technology; Bhyrav Mutnury – Dell Inc.
Friday, May 31 Session 41: Student Interactive Presentations 8:30 a.m. - 10:30 a.m.
PDN Worst Case Power Noise and an Efficient Estimation Method Shiji Pan – University of California, Irvine; Jiangyuan Qian – Broadcom Corporation
Session Co-Chairs: Mark Poliks – i3 Electronics, Inc. Tel: +1-607-727-7104 Email: mark.poliks@i3electronics.com
Fast Calculation of Electromagnetic Interference by Through-Silicon Vias Aosheng Rong and Andreas Cangellaris – University of Illinois, Urbana-Champaign; Feng Ling – Nanjing University of Science and Technology Electrical Simulation and Analysis of Si Interposer for 3D IC Integration Xin Sun, Yunhui Zhu, Runiu Fang, Guanjiang Wang, Wengao Lu, Jing Chen, and Yufeng Jin – Peking University; Min Miao – Beijing Information Science & Technology University; Shenglin Ma – Xiamen University
Committee: Interactive Presentations
Ibrahim Guven – University of Arizona Tel: +1-520-626-2257 Email: guven@email.arizona.edu Connectors and Vibrations: Damages in Different Electrical Environments Tibebu Aboye and Ansel Berghuvud – Blekinge Institute of Technology; Therese Björnängen – Scania CV AB Assembly and Packaging Technologies for HighTemperature and High-Power GaN HEMTs Adeel Ahmad Bajwa, Roderich Zeiser, and Jürgen Wilde – University of Freiburg, IMTEK; Richard Reiner, Rüdiger Quay, and Oliver Ambacher – Fraunhofer Institute for Applied Solid State Physics; Yang Yang Qin – University of Freiburg. IMTEK
A SPICE Model of Multi-Mode Optical Fiber in Mid-Channel Link for Package System SI Transient Simulations Zhaoqing Chen – IBM Corporation
Analysis of Modes Effect on Signal/Power Integrity in Finite Cavity for Chip and Die Level Packaging Based on a Hybrid Full Wave Method Xin Chang and Leung Tsang – University of Washington
Next Generation Package-on-Package Solution to Support Wide IO and High Bandwidth Interface Hung-Hsiang Cheng – Advanced Semiconductor Engineering, Inc.
Controlled Silicon IC Thinning on Individual Die Level for Active Implant Integration Using a Purely Mechanical Process Vasiliki Giagka, Nooshin Saeidi, Andreas Demosthenous, and Nick Donaldson – University College London
Package-Level Electromagnetic Interference Analysis Namhoon Kim, Leo Hongyu Li, Sam Karikalan, and Reza Sharifi – Broadcom Corporation
Simulation and Optimization of a Micro Flow Sensor Xing Guo, Chunlin Xu, Shengzhi Zhang, Ming Wen, Xuebing Yuan, and Sheng Liu – Huazhong University of Science & Technology
A Path Finding Based SI Design Methodology for 3D Integration Darryl Kostka – CST of America; Bill Martin – E-System Design; Madhavan Swaminathan – Georgia Institute of Technology Design and Implementation of a 700-2600MHz RF SiP for Micro Base Station Yi He and Peng Wu – Institute of Microelectronics, Chinese Academy of Sciences; Fengman Liu, Anmou Liao, Jun Li, Xiaofeng He, and Liqiang Cao – National Center for Advanced Packaging Dielectric Lens Optimization for Conical Helix THz Antennas Paolo Nenzi, Volha Varlamava, Frank Silvio Marzano, Fabrizio Palma, and Marco Balucani – Sapienza University of Rome Design and Test of THz Circuits Using a Novel Embedded Active Fabrication Process Xianbo Yang, Amanpreet Kaur, and Premjeet Chahal – Michigan State University System Interconnect Design Budget and Hardware Tuning of PCIe Gen3 Links with Multi-Source IP Devices Si Win, Daniel Rodriguez, and Nanju Na – IBM Corporation A Low-Cost PCB Fabrication Process Jack Ou, Alberto Maldonado, Chio Saephan, and Farid Farahmand – Sonoma State University; John Kikuchi – Agilent Technologies; Michael Caggiano – Rutgers University Design of RF and Thermal Pads of CMOS PAs Using Copper to Copper Bonding Technology Lih-Tyng Hwang – NSYSU; An-Yu Kuo – Cadence Design Systems, Inc.
Adhesion and Reliability of Direct Metallization to Glass Interposers with TPVs Timothy Huang, Jialing Tong, Venky Sundaram, Raj Pulugurtha, and Rao Tummala – Georgia Institute of Technology; Akira Mieno – Atotech Analysis of Room-Temperature Bonded Compliant Bump with Ultrasonic Bonding Keiichiro Iwanabe, Takanori Shuto, and Tanemasa Asano – Kyushu University Effects of Alignment of Graphene Flakes on Electrical Property and Water Permeability of Graphene-Epoxy Composite Film Seong-Yoon Jung and Kyung-Wook Paik – KAIST The Effects of Self-Fluxing Additives in Solder Anisotropic Conductive Films (ACFs) on Solder Wettability and Joint Reliability of Flex-on-Board (FOB) Assemblies Seung-Ho Kim, Yongwon Choi, Yoosun Kim, and Kyung Wook Paik – KAIST Comparison of Thin Glass and Organic Package Warpage through Fabrication and Modeling Scott McCann, Venkatesh Sundaram, Rao Tummala, and Suresh Sitaraman – Georgia Institute of Technology Multi-Physics Optimization of TSV Placement in Low-Powered 3D ICs to Mitigate the Effects of Joule Heating and Temperature Gradients Fahad Mirza, Samir Iqbal, and Dereje Agonafer – University of Texas, Arlington A Feasibility Study of Flip-Chip Packaged Gallium Nitride HEMTs on Organic Substrates for Wideband RF Amplifier Applications Spyridon Pavlidis, A. Cagri Ulusoy, Wasif T. Khan, Outmane Lemtiri Chlieh, and John Papapolymerou – Georgia Institute of Technology
Comprehensive Design Optimization for 2.133 Gbps LPDDR3 Extension for Mobile Platform System Chanmin Jo, Baekkyu Choi, Jaemin Shin, Sangmin Lee, Seongjae Moon, Sungjoo Kim, and Woong Hwan Ryu – Samsung Electronics Company, Ltd.
Novel Band-Pass Filters on 50µm Thin Substrates with Through Glass Vias (TGV) Cheng Pang, Wenya Shang, Huijuan Wang, Xiaoli Ren, Jie Pan, Daquan Yu, and Dongkai Shangguan – National Center for Advanced Packaging
Proposition of a Chip Bonding Joint Monitoring Methodology under Thermal Fatigue Qualification Test for Space Applications Samuel Pin and Sophie Dareys – Centre National d’Etudes Spatiales; Laurent Michel and Marc Sartor – Institut Clément Ader; Marc Lambert – Thales Alenia Space
Parameter Optimization in Assembly Manufacturing Process for a Power Module Yong Liu and Yumin Liu – Fairchild Semiconductor Corporation
Study of Microwave Circuits Based on MetalInsulator-Metal (MIM) Diodes on Flex Substrates Amanpreet Kaur, Xianbo Yang, and Premjeet Chahal – Michigan State University
Interaction Effect between Electromigration and the Evolution of Eutectic Sn-58Bi Alloy Hongbo Qin, Wu Yue, Changbo Ke, and Xinping Zhang – South China University of Technology; Bin Li – Southern Methodist University
Interactive Presentations: Friday, May 30, 8:30 - 10:30 a.m. Effect of Polymer Liner on Through Silicon Via (TSV) Stresses and Reliability Christine Taylor, Xi Liu, Paragkumar Thadesar, Muhannad Bakir, and Suresh Sitaraman – Georgia Institute of Technology Minimizing Coupling of Power Supply Noise between Digital and RF Circuit Blocks in Mixed Signal Systems Satyanarayana Telikepalli, Madhavan Swaminathan, and David Keezer – Georgia Institute of Technology Directed Self-Assembly of Mesoscopic Dies Using Magnetic Force and Shape Recognition Anton Tkachenko, Robert F. Karlicek, Jr., and James J-Q. Lu – Rensselaer Polytechnic Institute High-Frequency Characterization of ThroughPackage Vias Formed by Focused Electrical Discharge in Thin Glass Interposers Jialing Tong, Venky Sundaram, and Rao Tummala – Georgia Institute of Technology; Yoichiro Sato – Asahi Glass Company Self-Patterning, Pre-Applied Underfilling Technology for Elimination of Filler Trapping at Bonding Pads Chia-Chi Tuan, Ziyin Lin, Yan Liu, Kyoung-Sik Moon, and Ching-Ping Wong – Georgia Institute of Technology
Modeling and Analysis of Frequency Shift of MEMS Gyroscope Subjected to Temperature Change Weihui Wang, Sheng Liu, Zhang Luo, Ming Wen, and Qiang Dan – Huazhong University of Science & Technology
Characterization of Alternate Power Distribution Methods for 3D Integration David Zhang, Satyan Telikepalli, Madhavan Swaminathan, and David Keezer – Georgia Institute of Technology
Laser-Based Conductive Film Forming with Gold Nanoparticles for Electrical Contacts Mitsugu Yamaguchi, Kazuhiko Yamasaki, and Katsuhiro Maekawa – Ibaraki University; Shinji Araga – Ibaraki Giken Co., Ltd.; Mamoru Mita – M&M Research Laboratory
Nanocomposite Pastes for Thermal and Mechanical Bonding Tingting Zhang and Howard Wang – Binghamton University
Interfacial Reactions between Cu and Sn, Sn-Ag, Sn-Bi, Sn-Zn Solder under Space Confinement for 3D IC Micro Joint Applications Ting-Li Yang, W. L. Shih, J. J. Yu, and C. R. Kao – National Taiwan University Study of Extreme Low Temperature and Load Solid-Phase Sn-Ag System Bonding Mechanism for 3D ICs Kiyoto Yoneta, Ryohei Sato, Yoshiharu Iwata, Koichiro Atsumi, Kazuya Okamoto, Yukihiro Sato, and Takumi Shigemoto – Osaka University
Study of High CRI White Light-Emitting Diode Devices with Multi-Chromatic Phosphor Min Zheng, Wen Ding, Maofeng Guo, Ye Zhang, Yaping Huang, Jin Wang, Deyang Xia, Minyan Zhang, Yukun Zhao, and Weihan Zhang – Xian Jiaotong University A Novel Molding Process for Wafer Level LED Packaging Using Uniform Micro Glass Bubble Arrays Yu Zou, Jintang Shang, and Yu Ji – Southeast University; Li Zhang, Dong Chen, and Chiming Lai – Jiangyin Changdian Advanced Packaging Corporation; Ching-Ping Wong – The Chinese University of Hong Kong
2014 TECHNOLOGY CORNER EXHIBITS Companies are being selective in choosing the conferences and trade shows where they will exhibit their products and services. Each year more companies have determined that ECTC provides them the best opportunity to identify superior prospects. The primary reason is that the engineers and managers who attend ECTC hold decision-making positions at the world’s leading electronics equipment and component manufacturers. The attendees are attracted by ECTC’s strong technical program. Authors in the field concur that ECTC offers the best forum for presenting their work. Exhibit hours will be from 9:00 AM to Noon and 1:30 to 6:30 PM on Wednesday, May 28, and 9:00 AM to Noon and 1:30 to 4:00 PM on Thursday, May 29. Registration is very active this year and nearly all of the booths in the exhibit hall have been reserved. Following is a list of exhibitors as of Jan. 30, 2014. The exhibit brochure, a current exhibitor list, and a booth layout showing the available booths can be found on the ECTC web site at www.ectc.net under Technology Corner Exhibits. If you need additional information or have questions, call Joe Gisler at +1-480-288-6660 or email at gislerhj.ECTC@mediacombb.net.
HOW TO REGISTER FOR ECTC
3D Glass Solutions 3D Systems Packaging Research Center 5N Plus, Inc. ACM Research, Inc. AGC AI Technology, Inc. Alpha Novatech, Inc. AMICRA Microtechnologies GmbH Amkor Technology, Inc. ASE Group Bergquist Company (The) C2MI-MiQro Innovation Collaborative Centre Camtek USA Carl Zeiss X-Ray Microscopy CEA-LETI CORWIL Technology Corp. CPS Technologies Corp. CST of America, Inc. CVInc Dassault Systemes SIMULIA DISCO Hi-Tec America, Inc. Doosan Electro-Materials America, LLC Dow Corning Corp. Dow Electronic Materials Dynaloy E-System Design EV Group Finetech, Inc. Flip Chip International, LLC Fraunhofer Center for Applied Microstructure Diagnostics CAM Fraunhofer Institute for Reliabilty and Microintegration IZM FujiPoly America Corp.
HD Microsystems Henkel Electronic Materials LLC Huntsman Advanced Materials Hysitron IBM Microelectronics - Packaging Development IEN Ga Tech IMAT, Inc. Industrial Technology Research Institute Insidix Interconnect Systems, Inc. Invensas J Devices JSR Micro, Inc. Kingyoup Optronics Co., Ltd. Kyocera America. Inc. MacDermid Electronics Solutions Malico, Inc. Mentor Graphics Mini-Systems, Inc. (MSI) MISJ, Inc. MJS Designs, Inc. Moldex3D North America NAGASE & Co., Ltd. NAMICS Technologies, Inc. NANIUM S.A. Newport Corp. Nikon Metrology, Inc. Nitto Denko America Nordson DAGE NTK Technologies, Inc. Ormet Circuits, Inc. PAC TECH USA - Packaging Technologies, Inc. Palomar Technologies Plasma-Therm LLC
Polymer Assembly Tech Promex Industries, Inc. PURE TECHNOLOGIES QualiTau Quik-Pak Royce Instruments RTI International Rudolph Technologies Samtec, Inc. Semiconductor Equipment Corp. Senju Comtek SET - Smart Equipment Technology Shin-Etsu MicroSi, Inc. Shinko Electric America Smoltek AB Sonoscan SPTS Technologies STATS ChipPAC SUSS MicroTec, Inc. TechSearch International, Inc. Tian Long WM Electronic Components Co. Tokyo Ohka Kogyo Co., Ltd. Toray Engineering Co., Ltd. Toray International America, Inc. Towa America Corp. Triton Micro Technologies, Inc. USHIO America World Scientific Publishing XIA LLC XYZTEC YOLE DEVELOPPEMENT Zeon Corp./Zeon Chemicals L.P. Ziptronix Zymet, Inc.
Hotel Reservations
Hotel Reservations for ECTC 2014 can be made one of two ways:
By Internet: Submit your registration electronically via www.ectc.net. Your registration must be received by the cutoff date, May 9, 2014, to qualify for the early registration discounts.
1) Contact The Walt Disney World Swan and Dolphin Resort at +1- 800-227-1500 (Reference the ECTC Conference to receive the conference rate of $179/night. In addition, please request your room be reserved in the Walt Disney World Dolphin Resort as the Swan and Dolphin are two separate buildings.)
You may contact our registration staff at lrenzi@renziandco.com for additional information. Payment can be made by Visa, MasterCard or American Express. Your registration must be received by the cutoff date to qualify for the early registration discounts.
Walt Disney World Swan and Dolphin Resort 1500 Epcot Resorts Boulevard Lake Buena Vista, FL 32830 OR…. 2) Log onto www.ectc.net Scroll down to the Location section on the homepage and click on “Read More.” 29
64th Electronic Components & Technology Conference 2014 ECTC Conference Registration Information Conference Registration
Advance Registration
Door Registration
$1,000
$1,100
Joint ECTC / ITHERM
Attendee (BOTH conferences – full)
IEEE Member
Attendee (full conference)
$695
$795
Speaker or Chair (full conference)
$575
$695
One-Day Registration
$525
$525
Speaker One-Day Registration
$395
$395
Non-IEEE member
Attendee (full conference)
$840
$960
Speaker or Chair (full conference)
$575
$695
One-Day Registration
$525
$525
Speaker One-Day
$395
$395
Exhibit Booth Attendant
$0
$0
Student
Attendee or Speaker (full conference)
$300
$300
Exhibits Only
not attending conference $20 Professional Development Courses (PDCs) Note: all PDCs include a luncheon
$20
IEEE Member
Full PDC (Both AM and PM)
$575
$675
One PDC (Both AM or PM)
$400
$475
Non-IEEE member
Full PDC (Both AM and PM)
$625
$675
Single PDC (Both AM or PM)
$450
$475
Student
Full PDC (Both AM and PM)
$125
$125
Extra Proceedings
$100
$100
Extra Luncheon Tickets
$50
$50
Cancellation Fee
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Other Registration Options
Please log onto: www.ectc.net/registration to register for the 2014 ECTC. There will be no refunds or cancellations after May 9, 2014. Please note that a $50 cancellation fee will be in effect for all cancellations made on or prior to May 9, 2014. Substitutions can be made at any time. For additional information about registration or ECTC please contact us at: Renzi & Company, Inc. c/o 2014 ECTC 1304 Roundhouse Lane, #311 Alexandria, VA 22314 email: lrenzi@renziandco.com *If you join IEEE and the Components, Packaging and Manufacturing Technology Society (CPMT) BEFORE you register for the 2014 ECTC, you can save on registration fees! To take advantage of this offer, simply follow: http://www.ieee.org/go/CPMT_professional At destination, create your IEEE Web Account. Once complete, proceed to the Shopping Cart and enter CPMT2014FREE in the promotion code box. Click “Recalculate Totals” and the Shopping Cart will be updated to show the discount. Use your new IEEE membership id number and register for ECTC at the discounted IEEE Member Rate. *Non-IEEE members can join IEEE and save $100 or more on ECTC registration and receive CPMT Society membership free for 2014. *IEEE members can join the CPMT Society free for the remainder of 2014 with ECTC registration.
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CONFERENCE OVERVIEW
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May 27, 2014 Morning Professional Development Courses 8:00 AM - 12:00 PM
Lead-Free Solder Joint Reliability Wafer Level Packaging Moisture and Media Influence on Microelectronic Package Reliability Next Frontier in Electronics: Systems Scaling for Smart Mobile Systems Polymers and NanoComposites for Electronic and Photonic Packaging Power Electronics Packaging, Reliability, and Thermal Management Fundamental Concepts of Reliability and Mechanics in Electronic Packaging Product Qualification and Supply Chain Responsibilities
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Special Session 10:00 AM - 12:00 PM “Flexible Electronics Packaging Technology and Application Trends” Special Electronic Components & RF Session 2:00 PM - 4:30 PM “Wireless Power Transfer System” Panel Session 7:30 PM - 9:00 PM “Emerging Technologies and Market Trends of Silicon Photonics”
Interposer Technologies Advances in Copper Pillar & Solder Based Flip Chip Technologies Dynamic Mechanical Characterization Bio & Flexible Electronics Silicon Photonics & LEDs Adhesives, Underfills, and Thermal Interface Materials
13 3D Process Integration & Die Stacking 14 TSV Fabrication & Its Reliability Impact 15 Solder Joint Reliability 16 Advances in Signal Integrity & High-Speed System Design 17 Emerging Wireless Technologies & Design 18 WLCSP, Flip Chip, and PoP
Interactive Presentation Sessions 37 & 38 9:00 AM - 11:00 AM 2:00 PM - 4:00 PM
Interactive Presentation Sessions 39 & 40 9:00 AM - 11:00 AM 2:00 PM - 4:00 PM
Technology Corner 9:00 AM - 12:00 PM 1:30 PM - 6:30 PM
Afternoon Professional Development Courses 1:15 PM - 5:15 PM
High-Frequency Modeling and Optimization of Interconnections in Electronic Packages Shock – Impact Reliability of Portable Electronics Package Failure Analysis – Failure Mechanisms and Analytic Tools 3D IC Integration and 3D IC Packaging Polymers in Semiconductor Packaging Including 2.5D and 3D Integration Flip Chip Technologies Package Failure Mechanisms, Reliability and Solutions Statistics for Engineering Thermal Materials and Metrology for Advanced Packaging Thermo-Electrical Co-Design of 3D Chip Stacks
May 29, 2014 Technical Sessions 8:00 AM - 11:40 AM
May 28, 2014 Technical Sessions 8:00 AM - 11:40 AM
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Interposers & 3D Integration Flip Chip Packaging & Advanced Substrate 9 Interconnect Reliability 10 Novel Materials & Processes 11 Innovative Packaging Technologies 12 Power Integrity & Passive Component Modeling
Plenary Session 7:00 PM - 9:00 PM “Influence of Packaging on System Integration and Performance”
25 Recent Advances in 3D Package Reliability 26 3D Microbumps 27 Sensors & MEMS Technologies 28 System-Level Thermal & Mechanical Models II 29 Integrated RF & Power Modules 30 Solders & Bonding
Student Interactive Presentations Session 41 8:30 AM - 10:30 AM Technical Sessions 1:30 PM - 5:10 PM
31 PoP, SiP, and Die Stacking 32 Substrates 33 Novel Test Methods 34 Novel Packaging 35 Innovations in Wirebond Technology 36 Recent Advancement in Manufacturing Technology
Technology Corner 9:00 AM - 12:00 PM 1:30 PM - 6:30 PM
Technical Sessions 1:30 PM - 5:10 PM
May 30, 2014 Technical Sessions 8:00 AM - 11:40 AM
Technical Sessions 1:30 PM - 5:10 PM
19 Progress in 3D Integration 20 3D Materials & Processing 21 Wafer-Level & Fan-Out Packages 22 System-Level Thermal & Mechanical Models I 23 Optical Interconnects 24 Innovative Interconnections
CPMT Seminar 8:00 PM - 10:00 PM “Latest Advances in Organic Interposers”
Session Summary by Interest Area 3D/TSV Topics S1, S7, S13, S14, S19, S20, S25, S26, S31
Interconnections S2, S7, S14, S24, S26, S35
Advanced Packaging S1, S8, S13, S21, S27, S31
Materials & Processing S6, S10, S20, S30, S32
Applied Reliability S3, S9, S15, S25, S33
Modeling & Simulation S12, S16, S22, S28
Assembly & Manufacturing Technology S11, S18, S19, S36
Optoelectronics S5, S23
Electronic Components & RF S17, S29
Interactive Presentations S37, S38, S39, S40, S41
Emerging Technologies S4, S34
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