Computer Organization
Rabie A. Ramadan Lecture 3
Instruction Set Architecture (ISA)
2
MIPS Processor
3
MIPS Processor
CPU:
• • •
Floating Point Processor – FPU (Coprocessor 1 – CP1):
• •
64-bit program counter – PC; two 64-bit registers – Hi & Lo, hold results of integer multiply and divide 32 64-bit general purpose registers – GPRs (s0 – s31);
32 64-bit floating point registers – FPRs (f0 – f31); five control registers;
• Coprocessor 0 – CP0 is incorporated on the MIPS CPU chip and it provides functions necessary to support operating system: exception handling, memory management scheduling and control of critical resources.
MIPS Processor
Coprocessor 0 (CP0) registers (partial list): • Status register (CP0reg12) – processor status and control; • Cause register (CP0reg13) – cause of the most recent exception; • EPC register (CP0reg14) – program counter at the last exception; • BadVAddr register (CP0reg08) – the address for the most recent address related exception; • Count register (CP0reg09) – acts as a timer, incrementing at a constant rate that is a function of the pipeline clock; • Compare register (CP0reg11) – used in conjunction with Count register; • Performance Counter register (CP0reg25);
Registers vs. Memory
Arithmetic instruction operands must be registers, — only 32 registers provided Compiler associates variables with registers
CPU
Memory
register file
IO
Main Memory Model (Cont.)
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Main Memory Model
Millions of cells
Word
• An entity that can be written to or read from the •
memory. Each word requires an address.
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Word Addressing ď Ź
Given M words , how many bits l are required to address them?
l = log 2 M
ď Ź
Example: to address 64 MB, we need
l = log 2 (64 * 2 20 ) = 26 bits
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Memory Organization
Viewed as a large, single-dimension array, with an address A memory address is an index into the array "Byte addressing" means that successive addresses are one byte apart 0
8 bits of data
1
8 bits of data
2
8 bits of data
3
8 bits of data
4
8 bits of data
5
8 bits of data
6
8 bits of data
...
MIPS Memory Organization ď Ź
ď Ź
Bytes are nice, but most data items use larger "words" For MIPS, a word is 32 bits or 4 bytes. 0
32 bits of data
... 4
32 bits of data
8
32 bits of data
12
32 bits of data
Registers hold 32 bits of data
Main Types of Instructions
Arithmetic • Integer • Floating Point
Memory access instructions • Load & Store
Control flow • Jump • Conditional Branch • Call & Return
MIPS arithmetic
Most instructions have 3 operands Operand order is fixed (destination first) Example 1: Java code: MIPS code:
Example 2: Java code: MIPS code:
A = E = add add sub
A = B + C add $s0, $s1, $s2
B + C + D; F - A; $t0, $s1, $s2 $s0, $t0, $s3 $s4, $s5, $s0
Instructions: load and store Example: Java code: MIPS code:
A[8] = h + A[8]; lw $t0, 32($s3) add $t0, $s2, $t0 sw $t0, 32($s3)
0
32 bits of data
4
32 bits of data
8
32 bits of data
12
32 bits of data
$s3 is the base register + 32 offset A[8] Remember arithmetic operands are registers, not memory!
Instructions Format
Instructions, like registers and words of data, are also 32 bits long
• •
Example: add $t0, $s1, $s2 Registers have numbers: $t0=9, $s1=17, $s2=18
Instruction Format: op
rs
rt
rd
000000
10001
10010
01000
5 bits
5 bits
6 bits
shamt 00000
5 bits
Can you guess what the field names stand for?
5 bits
funct 100000 6 bits
Instructions Format op
rs
rt
rd
000000
10001
10010
01000
5 bits
5 bits
6 bits
5 bits
shamt 00000 5 bits
funct 100000 6 bits
R format -- arithmetic and logic instructions op -- operation of the instructions Why two rs -- first source register number fields (op rt -- second source register and funct)? rd -- destination register shamt -- shift amount (This field is set to 0 in all but the shift instructions.) funct -- additional specification of operation (add , sub,..)
Instructions: Control Flow Decision making instructions alter the control flow, i.e., change the "next" instruction to be executed
MIPS conditional branch instructions: bne $t0, $t1, Label beq $t0, $t1, Label Example:
if (i==j) h = i + j;
bne $s0, $s1, Label add $s3, $s0, $s1 Label: ....
Instructions Format
Consider the load-word and store-word instructions, Only one field for the Introduce a new type of instruction format
• •
I-type for register – Load and control Example: lw $t0, 32($s2)
• • • •
op -- operation code rs -- register source rt -- used as destination register in this format address -- 16-bit constant for addressing
instructions in this class use at most two registers this is how to get constants into the registers
operation (op). Therefore, All formats are consistent.
Example
Mapping is straightforward addi uses the I format (immediate) Generally one to one correspondence Straightforward translation
Instructions: Unconditional Branch
MIPS unconditional branch instructions:
j label Example: if (i!=j) h=i+j; else h=i-j;
beq $s4, $s5, Lab1 add $s3, $s4, $s5 j Lab2 Lab1: sub $s3, $s4, $s5 Lab2: ... Is there any Operands in the Jump instructions ?
• J Instructions Format:
MIPS Instruction Formats Summary 6 bits
5 bits
5 bits
R format
OP
rs
rt
I format
OP
rs
rt
J format
OP
5 bits
5 bits
6 bits
rd
sa
funct
immediate
target
Instructions, like registers and words of data, are also 32 bits long R format -- arithmetic and logic instructions I format -- transfer and branch instructions J format -- jump instructions
MIPS assembly language Category
Arithmetic
Instruction add
Example add $s1, $s2, $s3
Meaning $s1 = $s2 + $s3
Three operands; data in registers
subtract
sub $s1, $s2, $s3
$s1 = $s2 - $s3
Three operands; data in registers
$s1 = $s2 + 100 $s1 = Memory[$s2 + 100] Memory[$s2 + 100] = $s1 $s1 = Memory[$s2 + 100] Memory[$s2 + 100] = $s1
Used to add constants
addi $s1, $s2, 100 lw $s1, 100($s2) load word sw $s1, 100($s2) store word lb $s1, 100($s2) Data transfer load byte sb $s1, 100($s2) store byte load upper immediate lui $s1, 100 add immediate
Conditional branch
Unconditional jump
$s1 = 100 * 2
16
Comments
Word from memory to register Word from register to memory Byte from memory to register Byte from register to memory Loads constant in upper 16 bits
branch on equal
beq
$s1, $s2, 25
if ($s1 == $s2) go to PC + 4 + 100
Equal test; PC-relative branch
branch on not equal
bne
$s1, $s2, 25
if ($s1 != $s2) go to PC + 4 + 100
Not equal test; PC-relative
set on less than
slt
$s1, $s2, $s3
if ($s2 < $s3) $s1 = 1; else $s1 = 0
Compare less than; for beq, bne
set less than immediate
slti
jump
j jr jal
jump register jump and link
$s1, $s2, 100 if ($s2 < 100) $s1 = 1;
Compare less than constant
else $s1 = 0
2500 $ra 2500
Jump to target address go to 10000 For switch, procedure return go to $ra $ra = PC + 4; go to 10000 For procedure call
MIPS addressing modes
1. Immediate addressing op
rs
rt
Immediate
The operand is constant within the instruction itself 2. Register addressing op
rs
rt
rd
...
funct
Registers Register
Operand is a register 3. Base addressing op
rs
rt
Memory
Address
+
Register
Byte
Halfword
Word
The operand is at the memory location whose address is the sum of a register and a constant in the instruction 4. PC-relative addressing op
rs
rt
Memory
Address
PC
+
Word
The address is the sum of the Pc and constant in the instruction Jump Address is 26 bits (inst) concatenated with upper PC bits
5. Pseudodirect addressing op
Address
PC
Memory
Word
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