Ecole Polytechnique Fédérale de Lausanne EPFL
Nano-Tera IcySoC
Vincent Camus, EPFL-ICLAB Nano-Tera Annual Plenary Meeting 2015
04/05/2015 Slide 1/10
Going to Ultra-Low Power
Data Center & Cloud
PC
Mobility
Wearable
IoT
SERVER
2 in 1
TABLET
GLASSES
SMART CITIES
STORAGE
DESKTOP
SMARTPHONE
PERSONAL ASSISTANT
SMART AGRICULTURE
NETWORKING
ALL IN ONE
PHABLET
SPORTS FASHION
SMART FACTORIES
Ian Yang, Intel Developer Forum - Shenzhen 2014. Nano-Tera Annual Plenary Meeting 2015 - IcySoC Project
04/05/2015
Slide 2
Gene’s Law
Power consumption reductions enable autonomous microsystems Gene A. Frantz, TI Developer Conf., 2008. Nano-Tera Annual Plenary Meeting 2015 - IcySoC Project
04/05/2015
Slide 3
The IcySoC Mission
Inexact Sub/Near-Threshold Systems for Ultra-Low-Power Devices Wearable health monitoring Environmental monitoring Internet of Things Personal electronics
Nano-Tera Annual Plenary Meeting 2015 - IcySoC Project
04/05/2015
Slide 4
PULP – Parallel Ultra-Low-Power Platform
PULP OpenRISC multi-core platform
Variation/performance adaptative architecture
Nano-Tera Annual Plenary Meeting 2015 - IcySoC Project
04/05/2015
Slide 5
Near/Sub-Threshold Circuits
Sub/near-threshold logic & memories Minimum energy point High process variation High frequency decrease Supply Voltage (V)
Nano-Tera Annual Plenary Meeting 2015 - IcySoC Project
04/05/2015
Slide 6
Approximate Circuits – A New Dimension Energy Fast Design, Considerable Energy
Slow Design, Low Energy
Delay Faster Design, Moderate Energy, Inexact
Nano-Tera Annual Plenary Meeting 2015 - IcySoC Project
04/05/2015
Slide 7
Approximate Circuits – A New Dimension
Errors Energy
Errors Energy
Errors Energy
Errors Energy
Nano-Tera Annual Plenary Meeting 2015 - IcySoC Project
04/05/2015
Slide 8
Approximate Computing – A New Paradigm
Multimedia
Perceptual limitations
Data mining no golden result
Web search
Application Resilience Noisy real world inputs
Communications
Iterative self healing
Pattern Recognition
Nano-Tera Annual Plenary Meeting 2015 - IcySoC Project
04/05/2015
Slide 9
The IcySoC Project
Technology
System
Approximate circuits
Sub/near-threshold logic & memories
PULP OpenRISC multi-core platform
Inexact arithmetic operators (adders, multipliers)
ALP 180 nm TSMC 65 nm FDSOI 28 nm
Variation/performance adaptative architecture
Reconfigurable and optimized accelerators (JPEG, MPEG4, G722)
Nano-Tera Annual Plenary Meeting 2015 - IcySoC Project
04/05/2015
Slide 10