Design of an efficient multiplier unit using dbns by GIAP Journals

“Design of an Efficient Multiplier Unit Using DBNS”

[Project Reference Book for Engineering Students] [Useful for projects in Digital Signal Processing (DSP) and Elliptic Curve Cryptography (ECC)]

Arnab Chowdhury Moyukh Laha Ayan Santra Biplab Bhadra Balmiki Ray (Authors are working as Assistant System Engineer trainee, TCS) GYANDHARA INTERNATIONAL ACADEMIC PUBLICATIONS, THANE, INDIA

“Design o of An Efficien nt Multiplier Unit using DBNS” by Arn nab Chowdhu ury, Moyukh Laha, Ayan Santra, Balmiki Roy, B Biplab Bhadrra hara International Acad demic Publiications (GIA AP) ©Gyandh The autho ors of the boo ok hereby tran nsfer any and all publishing g rights to GIA AP. The autho or hereby represents and warrants that the pro oject work is original. o

All rightss reserved. N No part of th his publicattion may be reproduced d or transmiitted, in any y form or b by any mean ns, without permission. Any person n who does any unauth horized act in n relation to this publlication shalll be liable t to criminal p prosecution n and civil cla aims for damagess 013 First Edition, July 20 ara Internattional Acade emic Publica ations (GIAP P) Gyandha Thane, M Maharashtra Californ nia New Delh hi Oman Allahabad d

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ACKNOWLEDGEMENT Intellectual guidance is the royal road to great success. This book owes its existence to many people without whose co‐operation and efforts the realizations would not have been possible. We would like to articulate our profound gratitude and indebtedness to our project guide Prof. Subhashis Maitra who has always been a constant motivation and guiding factor throughout the project time in and out as well. It has been a great pleasure for us to get an opportunity to work under him and complete the project and book successfully. We wish to extend our sincere thanks to Prof. Achintya Das, Prof. Kabita Purkait and Prof. Angsuman Sarkar for approving our project work and book with great interest and for their endless help throughout our project. We also take an opportunity to give thanks to all faculties of Department of Electronics and Communication Engineering, Kalyani Govt. Engineering College, West Bengal, who gave us support during this project. We are grateful to our parents who always supported us throughout the entire work. We would also like to thank our friends, for their cooperation and constantly rendered assistance. Authors

SALIENT FEATURES OF THE BOOK The basic aim of Multi Base Number System is to reduce the algebraic complexity and to enhance the speed of the existing algorithms. Both DBNS and TBNS have significant roles in this. There are a number of algorithms that are already being proposed, each having some merits and demerits. Due to the wide application of DBNS and TBNS, research work is still going on to deduce some efficient algorithms and implement them in DSP and ECC. In this book, we have represented any real number in both Double Base Number System and Triple Base Number System using some new algorithms. We have proposed seven algorithms to represent any integer or any real number in DBNS and TBNS. The algorithms differ from each other and the present algorithms in logic as well as in complexity. Here in this paper we discuss thoroughly about the algorithms. Analysis has been done in details, in terms of time complexity and also the variation of error with the increase in the value of the integer is calculated. We have also presented architecture of a multiplier unit in DBNS. We have designed the multiplier unit in VHDL and have discussed in details about each unit (adder, convertor, shifter, and look up table) present in the architecture. We have shown a block diagram of the architecture of a multiplier unit in TBNS as well. These methods are supposed to be efficient and can be widely used in the field of Digital Signal Processing (DSP) & Elliptic Curve Cryptography (ECC).

List of Contents Contents 1

Introduction

Page Number 01

1.1 What is numeral system

1.2 Residue Number System

Aim of the project

Existing algorithm

3.1 Introduction to DBNS

3.2 Tree based approach to DBNS

3.3 Algorithm of tree based DB‐Chain Search

3.4 Introduction to TBNS

3.5 Discussion about some new algorithm

3.6 Hybrid Binary Ternary Number System

3.7 Hybrid Binary Ternary Joint Sparse form

Proposed algorithm

Algorithm I

Algorithm II

Algorithm III

Algorithm IV

Algorithm V

Algorithm VI

Algorithm VII

Advancement in Context of Multipliers

5.1 High performance multiplier

Design of the architecture of the multiplier unit

6.1 Adder

6.2 Look Up Table

6.3 Converter

6.4 Shifter

6.5 Multiplier architecture

Application

7.1 Application in Digital Signal Processing

7.2 Application in the field of cryptography

Conclusion

References

DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS 1. INTRODUCTION Low performance ALUs never look upon the problem of time complexity. High performance, flexibility, space complexity and low power consumptions are the most important issues in the current signal processing architectures. The signal processing algorithms face many challenges in real‐time applications because of their high computational complexity. Therefore, the major issues have been the enhancement of speed of the arithmetic units.In general we can conclude that if the computational complexity of operations performed by an ALU, multiplications and additions in particular, can be reduced, it results in the design of a high performance ALU. Representation of an integer in DBNS & TBNS improved the performance of the ALU by reducing the complex computations. Now if we can express any real number in DBNS & TBNS with a minimal error, it will be a great boon for the industry that deals with DSP & ECC. 1.1 WHAT IS NUMERAL SYSTEM? A numeral system (or system of numeration) is a writing system for expressing numbers, that is, a mathematical notation for representing numbers of a given set, using digits or other symbols in a consistent manner. It can be seen as the context that allows the symbols "11" to be interpreted as the binary symbol for three, the decimal symbol for eleven, or a symbol for other numbers in different bases. Ideally, a numeral system will: a) Represent a useful set of numbers (e.g. all integers, or rational numbers) b) Give every number represented a unique representation (or at least a standard representation) c) Reflect the algebraic and arithmetic structure of the numbers. For example, the usual decimal representation of whole numbers gives every whole number a unique representation as a finite sequence of digits. However, when decimal representation is used for the rational or real numbers, such numbers in general have an infinite number of representations, for example 2.31 can also be written as 2.310, 2.3100000, 2.309999999..., etc., all of which have the same meaning except for some scientific and other contexts where greater precision is implied by a larger number of figures shown. Let us discuss about a type of numeral system known as Positional System. Arnab, Moyukh, Ayan, Biplab, Balmiki

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D DESIGN OF AN A EFFICIENT MULTIPLIE ER UNIT USIN NG DBNS Positional System working in baase‐10, ten different digitss 0, 1, ..., 9 are It is also kknown as place‐value notaation. Again w used and the position of a digit is used to signiffy the powerr of ten that tthe digit is to o be multiplieed with, as in n 304 = 3×100 0 + 0×10 + 4× ×1 or more prrecisely 3×102 + 0×101 + 4××100. Note th hat zero, whicch is not neeeded in the other o system ms, is of cruciial importancce here, in order to be ab ble to "skip" a power. Th he Hindu–Araabic numeral system, whicch originated in India and iis now used tthroughout th he world, is aa positional b base‐10 system m. Arithmetic is much easier in posiitional system ms than in the t earlier ad dditive ones;; furthermorre, additive systems s need a large nu umber of diffferent symb bols for the different powers of 10; a positionall system need ds only ten different symb bols (assumingg that it uses base 10). In a possitional basee‐b numeral system (witth b a natural number grreater than 1 known aas the radix), b basic symbols (or digits) correspond ding to the first b natural numbers inclluding zero are used. To generate thee rest of the numerals, th he position of o the symbol in the figurre is used. Th he symbol in the last position has its ow wn value, and d as it moves to the left itss value is mulltiplied by b. For example, in the deecimal system m (base‐10), th he numeral 4 4327 means (4 4×103) + (3×1 102) + (2×101) + (7×100), n noting that 10 00 = 1. In general, if b is the b base, one writes a number in the numeeral system o of base b by e expressing it in the form – – anbn + an −− 1bn − 1 + an − 2bn − 2 + ... + a0b0 and writingg the enumerrated digits anan‐1an − 2 ... a0 in descendin ng order. Thee digits are naatural numbeers between 0 0 and b − 1, in nclusive. If a text (such as this one) discu usses multip ple bases, an nd if ambiguity exists, th he base (itseelf representted in base‐10 0) is added in n subscript to the right of tthe number, like this: num mberbase. Unless specified by context, n numbers without subscriptt are considerred to be decimal. By using a dot to divide the digitss into two grroups, one caan also writee fractions in the positional system. Fo or example, tthe base‐2 nu umeral 10.11 denotes 1×21 + 0×20 + 1×2 2−1 + 1×2−2 = 2 2.75. In general, numbers in the base b syystem are of the form:

− bers bk and b−k are the weights of the co orrespondingg digits. The p position k is th he logarithm o of The numb

the corressponding weiight w, that iss Moyukh, Ayan,, Biplab, Balm miki Arnab, M

. The higheest used posiition is close tto Page e2

D DESIGN OF AN A EFFICIENT MULTIPLIE ER UNIT USIN NG DBNS the order of magnitud de of the number.The nu umber of tallyy marks requ uired in the u unary numerral system fo or describing tthe weight w would have beeen w. In the positional syystem, the nu umber of digits required to describe it is only

o describe the weight 100 00 , for k ≥ 0. E.g. to

n sincee then fourr digits are needed

. The number of digits d requireed (in posittions 1, 10, 100,... 1 only fo or

to describ be the positio on is simplicity in the decimal example). TTable 1

ositional Num mber System Table Illlustrating Po

Position

−1

−2

. . ..

Weight

Digit

Decimall example we eight 1000 100

Decimaal example digit

0.1

0.01

. . ..

n if and only iif it is rational; this does no ot Note thatt a number haas a terminatiing or repeating expansion depend on o the base. A number that terminattes in one baase may repeeat in another (thus0.3100 = 0.0100110 0011001...2). An irrational number stays s aperiod dic (with an n infinite number of non‐ repeatingg digits) in all integral basees. Thus, for example in b base‐2, π = 3.1415926...10 can be writteen as the ape eriodic 11.0010010000111 111...2. Putting ovverscores, n, or dots, , above the common digitts are a convention used d to represen nt repeatingg rational expaansions. Thuss:

If b = p is a prime number, one can define base‐‐p numerals w whose expanssion to the leeft never stop ps; these are called the p‐adic numberss.

Moyukh, Ayan,, Biplab, Balm miki Arnab, M

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D DESIGN OF AN A EFFICIENT MULTIPLIE ER UNIT USIN NG DBNS In certain n areas of computer scien nce, a modifiied base‐k po ositional systeem is used, called bijectiv c ve numeratio on, with digiits 1, 2, ..., kk (k ≥ 1), and d zero being represented d by an emp pty string. Th his establishe es a bijection between thee set of all such digit‐strings and the seet of non‐neggative integerrs, avoiding the t non‐uniq queness causeed by leadingg zeros. Bijecctive base‐k n numeration iss also called k‐ adic notattion, not to be confused w with p‐adic nu umbers. Bijecttive base‐1 is the same as unary. 1.2 RESIDUE NUM MBER SYSTEM M (RNS) r a large integeer using a set s of smalleer integers, so s A residue number system (RNS) represents that comp putation mayy be performeed more efficiently. It relie es on the Chin nese remaind der theorem o of modular aarithmetic forr its operation n. A residue number systtem is defined d by a set of N N integer con nstants, {m1, m m2, m3, ... , m mN }, referred tto as the mo oduli. Let M be the least com mmon multiple of all thee mi. Any arb bitrary integeer X smaller than M can t b be representted in the deefined residuee number sysstem as a sett of N smaller integers {x1, x2, x3, ... , xxN} with xi = X X modulo mi representing t r the residue class of X to th hat modulus. Note thatt for maximum m representaational efficieency it is impe erative that aall the moduli are co‐prime; that is, no o modulus maay have a com mmon factor w with any otheer. M is then tthe product o of all the mi. For example, RNS (4|2 2) has non co o‐prime modu uli, resulting iin the same rrepresentatio on for differen nt values. A. Operations on O n RNS numbers Once reprresented in R RNS, many arithmetic operations can b be efficiently performed on the encodeed integer. For F the follow wing operatio ons, consider two integerss, A and B, reepresented byy ai and biin an a RNS systeem defined byy mi (for i from m 0 ≤ i ≤ N). Ö Addittion and subtraction Addition (or subtractio on) can be accomplished by simply ad dding (or sub btracting) thee small integeer values, modulo their sp pecific moduli. That is, be calculated in RNS as can b

overflow in these operation ns. One has to check for o Ö Multiplication Multiplicaation can be accomplishe ed in a mann ner similar to o addition and subtraction n. To calculatte we caan calculate: Moyukh, Ayan,, Biplab, Balm miki Arnab, M

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D DESIGN OF AN A EFFICIENT MULTIPLIE ER UNIT USIN NG DBNS Again oveerflows are po ossible. Ö Division umber system ms is problem matic. A papeer describingg one possiblle algorithm is Division in residue nu e other hand, if B is coprim me with M (that is available at [1]. On the

) then

which can be easily calculaated by where

is multiplicative inveerse of B mod dulo M, and d

modulo

is mu ultiplicative inverse of

B. Practical Appliications e applicationss in the field d of digital co omputer arith hmetic. By deecomposing in this a largge RNS have integer in nto a set of smaller s integers, a large ccalculation caan be performed as a series of smalleer calculations that can be performed independenttly and in parallel. Ö Intege er Factorizatiion The

RN NS

can

im mprove

effiiciency

Let ,

of ttrial

divisio on.

Let

a semi

prime.

repreesent first N N primes. A Assume thaat . Then

, where

. The method of triaal division is the t method of o

on, and the RNS R automatiically eliminaates all Y and Z such that exhaustio

, that is

we only need to checkk

numbers below M. e RNS can automatically eeliminate all n numbers but 1, 7,11,13,17 7,19,23,29 mo od For example, N = 3, the % of numberss. For N = 25 when 30 or 73%

arre all prime n numbers belo ow 100, the R RNS eliminatees

about 88% % of numberss. One can seee from the ab bove formulaa the diminish hing returns ffrom the largeer sets of mo oduli. Ö Assocciated Mixed Radix System m A numbe er given by

in the RNS R can be naturally reepresented in

the associated mixed rradix system ((AMRS) Moyukh, Ayan,, Biplab, Balm miki Arnab, M

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D DESIGN OF AN A EFFICIENT MULTIPLIE ER UNIT USIN NG DBNS

Where

for

and

m the RNS to AMRS, the comparisson of numbers becomees Note thaat after convversion from straightfo orward. 1) The RN NS allows to reeduce power,, both in ASIC C‐SC and FPGA A implementaations. 2) The FP PGA impleme entation exploits both thee com‐plexityy reduction and a the locality of the RN NS representtation. These favorable propeerties of RNS aallow to extend the use off FPGA technology to pow wer constraineed DSP systems. Moyukh, Ayan,, Biplab, Balm miki Arnab, M

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS 2. AIM OF THIS PROJECT We can easily explain this in terms of the requirement of a high performance multiplier unit that can be used in ALUs. In logical operations, the basic operations are addition, subtraction, multiplication, and division. Among these entire basic operations, the computer performs the addition faster. The subtraction, multiplication, and division can be done by using the basic operation i.e. the addition. The subtraction operation can be performed by using complement method and the multiplication can be easily done by Booth’s multiplication method. The division operation can be done by a number of shifts and the add operation. In any processor the major units are Control Unit, ALU and Memory read write. Among these units the performance of any processor majorly depends on the time taken by the ALU to perform the specified operation. Multiplication is an important fundamental function in arithmetic operations. Multiplication based operations such as Multiply and Accumulate (MAC) and inner product are among some of the frequently used Computation Intensive Arithmetic Functions (CIAF) currently implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform (FFT), filtering and in microprocessors in its arithmetic and logic unit. Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. Here comes the main motive behind our project & the utility of DBNS and TBNS is understandable. It is well known that power consumption is one of main concerns for digital designers. Different levels of power optimization are possible:

Algorithm level

Architecture level

Arithmetic level

Implementation level

Technology level

In this project, we are mainly working on algorithm and architecture level. In last semester’s project presentation, we discussed about Double Base Number System, the existing algorithms (tree based approach) and their applications. We tried to design a multiplier unit based on DBNS. Now we introduce a few algorithms to convert any real number into Double Base Number System and Triple Base Number System. We start with a very simple algorithm that converts any integer into DBNS. The basic principle of the second algorithm is division of the integer by 6 (expressed as 2131). Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS Modification of this algorithm leads to the representation of an integer in TBNS. In the latter case, an integer is divided by 30 (expressed as 213151). We have designed another algorithm to convert any real number into Single Digit Double Base Number System and also can be used to calculate the complex additions of DBNS chains. Again a little modification to it results in the conversion of any real number into Single Digit Triple Base Number System. This is not the only algorithm to represent a floating point number in DBNS or TBNS. We have approached with a more general algorithm. Arnab, Moyukh, Ayan, Biplab, Balmiki

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∑ ,i

j ij

DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS 3. EXISTING ALGORITHMS Algebraic complexity of different Algorithms in Signal Processing and Cryptography leads to a major problem and Researchers are trying to develop new Algorithms to solve these problems. To enhance the speed of the existing Algorithms, different number systems have been found for point multiplication in elliptic curve cryptography and coefficient multiplication in digital signal processing mainly for digital filter design. Among the different number system, DBNS, DBC, HBTJSF, w‐NAF are efficient. Recently, to increase the speed again, TBNS, SDTBNS have been developed. There are different method to convert any integer or fraction into TBNS and hence SDTBNS. In many applications, the computational complexity of algorithms crucially depends upon the number of zeros of the input data in the corresponding number system. Number systems are often chosen to enable a reduction of the complexity of the arithmetic operations; the most popular are perhaps signed‐digit number systems. An analysis of the expected number of zeros in the representation of arbitrary integers in the binary signed digit number system shows that on average for long word lengths, 33 percent fewer adders are needed to perform multiplication than binary. In these number systems, we need on average, O [log N] nonzero digits to represent the integer N. 3.1 INTRODUCTION TO DOUBLE BASE NUMBER SYSTEM A number system using bases 2 and 3, allowing as digits only 0, 1, and requiring O[log N] nonzero digits is the ‘Double Base Number System (DBNS)’ [13] i.e. a representation having the form of :‐ x= ∑di,j2i3j ;

with di,j€{0,1} and i,j are non‐negative, independent integers.

i,j The general form of representation is – The binary number system is a special case (and valid member) of the above representation. The DBNS has an unusually simple 2D geometric interpretation, suitable for implementation via cellular automata. For e.g. we can express 54 by this tabular representation ‐

Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS

For each entry in the table, we multiply the corresponding row‐value and column‐value. Then we add up all such entries to get the value of the number represented by the table. Clearly, this representation is highly redundant. For every integer x, the representations with the minimum number of 2‐integers (less than, or equal to x) are called the canonical double‐base number representations. For example, 127 has 783 different representations, among which 3 are canonical (with only three 2‐integers). 127 = 2233 + 2132 + 2030 = 2233 + 2430 + 2031 = 2531 + 2033+ 2230. Finding the canonical DBNS representation of an integer from its binary representation is a difficult problem. A greedy algorithm was proposed which gives the so‐called near‐canonical double‐base number representation. The Greedy algorithm & the tree based approach to DBNS is discussed later on. 3.2 TREE BASED APPROACH TO DBNS Double base chains have been obtained with a greedy approach, relying on the search of the closest {2, 3} – integer to a given number. This approach tends to increase the length of the chain. Then tree based approach was introduced which is very well known to us now. The tree based approach has been generalized in order to obtain other kinds of double base chains. Before we go deep in the tree based approach to DBNS, we discuss the Greedy’s algorithm. Input: An integer n. 1. Initialize t = n, p = 1 and Integer Set =Ø. 2. While t! = 0 do the following: 2.1. Find the best approximation of t as z = 2a3b. 2.2. Set Integer Set = Integer Set U {p ∙ z} 2.3. If t < z, set p = −p. 2.4. Set t = |t − z|. 3. Return Integer Set. Output: A DBNS expansion of n. The length of the DBNS expansion of n is the size of Integer Set.

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS To find an expansion representing ‘n’, we can use a greedy‐type algorithm whose principle is to find at each step the best approximation of a certain integer (n initially) in terms of a {2, 3}‐integer, i.e. an integer of the form 2a3b. Then compute the difference and reapply the process. Applying this approach for n = 542788, we find that 542788 = 2837 − 2337 + 2433 – 2*32 – 2 For every positive integer n, the length of the DBNS expansion of n returned by the algorithm is O [log n/log logn]. As compared to the classical greedy approach, the tree based approach is not only simpler to implement and faster, experimentally it also returns shorter chains on average. The complexity analysis shows that the average length of a chain returned by this tree‐based approach is [log2n/4.6419]. First, let us assume that n is co‐prime to 6. We can start building a tree by considering two leaves corresponding to (n – 1) and (n + 1). After removing the powers of 2 and 3 from (n – 1) and (n + 1), we can reapply the process and for each node, add and subtract 1. Repeating this will create a binary tree. Eventually, one of its branches will reach 1 leading to a DB‐chain expansion. Obviously, this approach is too costly for integers in the cryptographic range, say those of length 160 bits and above. However, we can eliminate certain branches and hope that the overall length of the DB‐chain will not be affected too much. Fixing a bound B at the beginning, we can keep only the B smallest nodes before creating the next level of the tree. It is very important that the nodes that are kept are all different. 3.3 ALGORITHM of TREE BASED DB‐CHAIN SEARCH Before stating the algorithm [17], let us take an example –

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS

Figure 1: An example of Tree based approach to DBNS Input: An integer n and a bound B. •

Set t ← f(n)

•

Initialize a binary tree T with root node t

•

repeat

•

for each leaf node m in T insert 2 children

•

Left child ← f(m − 1)

Arnab, Moyukh, Ayan, Biplab, Balmiki

[f(n) = n/2v2(n)3v3(n)]

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS •

Right child ← f(m + 1)

•

Discard any redundant leaf node

•

Discard all but the B smallest leaf nodes

•

until a leaf node is equal to 1

•

return ┌

Output: A binary tree containing a DB‐chain computing n. 3.4 INTRODUCTION TO TBNS Even though DBNS schemes exhibit reasonably good performance for 8 bit multiplication, they are not efficient for higher bits. For further enhancement of the performance of arithmetic operations and to reduce the hardware complexities, a new concept called Triple Based Number Systems (TBNS) [15]. It was introduced for performance enhancement of the multiplier of the digital signal processors. We use 2, 3 and 5 to represent any integer in TBNS. Efficiency of this number system has been dealt already with in details and a comparison between TBNS and DBNS clearly indicate the advantages of the former in terms of speed, hardware complexity and power dissipation. To represent a wide range of numbers using DBNS, number of bits of the indices need to be increased. This in turn increases the address space of LUT (Look‐up‐table) exponentially and leads to the increase in access time, hardware requirements and design complexities. These drawback can be eliminated using the proposed number system, a novel concept and is known as “Single Digit Triple Based Number Systems (SDTBNS)” in which bases used are 2, 3 and 5. SDTBNS is an extension of TBNS (Triple Base Number System) where the numbers can be represented using the following equation Y = ∑i,j,kdi,j,k 2i3j5k For further enhancement of the performance of arithmetic operations and to reduce the hardware complexities, here we introduce SDTBNS, a modified version of SDDBNS. Any number Y in SDTBNS is represented as ‐ Y = 2i3j5k In TBNS and therefore, in SDTBNS one of the bases has been chosen as 5, since the decimal point shifting can be achieved easily only by adding or subtracting the indices of the bases 2 and 5. This cannot be achieved with other bases (like 7,11 etc.) and hence any number (integer and fraction) can be represented using the bases 2, 3 and 5.

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS 3.5 DISCUSSION ABOUT SOME NEW ALGORITHMS Different algorithms are proposed for DBNS and TBNS and are analysed already in details. Algorithms like Joint Binary‐Ternary Representation System (JBTRS), Triple Base Hybrid Joint Sparse Form (JSF), and Joint Double Base Chain (JDBC) are important in terms of complexity, efficiency. From different analysis it is clear that JTBNS is only comparable with HBTNS, but HBTNS requires a pre computation look‐up‐table. Also the number of doublers required for HBTNS is more than that required for JTBNS at the cost of adders. But the complexity to design a doubler is more than to design an adder. Hence JTBNS is advantageous from all respect.Here we discuss about the Hybrid Binary Ternary Number System & Hybrid Binary Ternary Joint Sparse Form. 3.6 HYBRID BINARY ‐ TERNARY NUMBER SYSTEM The Hybrid Binary‐Ternary Number System (HBTNS) was introduced by Dimitrov and Cooklev in for speeding‐up modular exponentiation. In this system, an integer is written as a sum of powers of 2 and powers of 3; i.e., it mixes bits and trits (radix‐3 digits) except that the digit 2 never occurs. The use of base 3 naturally reduces the number of digits required to represent a t‐bit integer. In fact, it can be shown that the average base β = 210/1333/13 ≈ 2.19617 and that the digit length is almost 12% smaller than the binary length (logβ (2) ≈ 0.88106) digits. More importantly, this number system is also very sparse; the average number of non‐zero digits in HBTNS is 5/13, leading to ≈ t/3 for a t‐bit number. Algorithm 1 computes the HBTNS of a positive integer.

Algorithm of HBTNS representation ‐

Input: An integer n > 0 Output: Arrays digits [], base [] 1: i = 0 2: while n > 0 do 3:

if n ≡ 0 (mod 3) then

else if n ≡ 0 (mod 2) then

else

base[i] = 3; digits[i] = 0; n = n/3;

base[i] = 2; digits[i] = 0; n = n/2;

Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS 8:

end if

10:

i = i + 1

base[i] = 2; digits[i] = 1; n = n/2;

11: end while 12: return digits [], base [] Let us take an example: The hybrid binary‐ternary representation of n = 703 = (1010111111)2has only 8 digits among which 3 only are non‐zero. Note that the binary representation requires 10 bits, out of which 8 are different from zero. Observe that the least significant digit is the left‐most value in digits [], such that 703 = 1 + 2133 + 2334 where digits[] = [1, 0, 0, 0, 1, 0, 0, 1], base [] = [2, 3, 3, 3, 2, 3, 2, 2]. 3.7 HYBRID BINARY TERNARY JOINT SPARSE FORM In this algorithm, the hybrid binary‐ternary joint sparse form [6] of a pair of integers is calculated by first checking whether both k1 and k2are divisible by 3. If this is the case, both digits are set to 0 and the base set to 3, otherwise we check whether they are both divisible by 2 and proceed accordingly. Finally, if the pair is not divisible by 3 or 2, we make both numbers divisible by 6 by subtracting ki mods 6 ‫א‬ {−2, −1, 0, 1, 2, 3} from ki, and then divide the results by 2. Therefore, in the next step, both numbers are divisible by 3 and we generate a zero column.

Algorithm of HBTJSF representation ‐

Input: Two positive integers as k1, k2 Output: Arrays hbt1[], hbt2[], base[] 1. i = 0 2. while k1> 0 or k2> 0 do 3.

if k1 ≡ 0 (mod 3) and k2 ≡ 0 (mod 3) then a. base[i] = 3; i. hbt1[i] = hbt2[i] = 0; ii. k1 = k1/3; k2 = k2/3; b. else if k1 ≡ 0 (mod 2) and k2 ≡ 0 (mod 2) then i. base[i] = 2; ii. hbt1[i] = hbt2[i] = 0;

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS iii. k1 = k1/2; k2 = k2/2; c. else i. base[i] = 2; ii. hbt1[i] = k1 mods 6; hbt2[i] = k2 mods 6; iii. k1 = (k1 − hbt1[i])/2; k2 = (k2 − hbt2[i])/2; d. end if e. i = i + 1 4. end while 5. return hbt1[], hbt2[], base[] The following example illustrates the advantage of the HBTJSF. For k1= 1225 and k2= 723, theJoint Sparse Form has joint Hamming weight 7, where 1225 = (1 0 1 01 0 0 1 0 0 1) 723 = (1 0 1 0 01 01 1 01 ) The interleaving w‐NAF (with w = 5 for 1225 and w = 4 for 723) 5‐NAF(1225) = (1 0 0 0 0 −13 0 0 0 0 0 9) 4‐NAF(723) = (0 0 0 3 0 0 0 −3 0 0 0 3) Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS 4. PROPOSED ALGORITHMS We have already discussed in details about the existing algorithms. Now we propose some new algorithms. If we can discuss the algorithms to convert any integer or any floating point number in DBNS, it will be very easy to understand the algorithms designed for TBNS. ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Algorithm I ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ The steps that are followed to implement the algorithm are – 1. Let us take a number as input (say n). 2. We divide the number by 2 and store it in a variable (say temp). 3. Now increase the power of 3 starting from 0, until 3j<= temp. 4. We take the value of j and then increase the power of 2 from 0 such that 3j * 2i<= n. Thus we get the power of 2. We can store the powers of 2 and 3 in an array to represent the number in DBNS. 5. Find the remainder such as ‐ rem = n – (3j * 2i) 6. Update the value of n i.e. n = rem and repeat the same procedure until n>1. 7. If rem = 1, represent it as 20 * 30. 8. Since all the indices of 2 and 3 are stored in arrays, we can represent any integer in DBNS. ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ We take the help of an example to illustrate the algorithm. Let the number (n) be 25. We follow these steps ‐ 1. The number (n) is divided by 2. The result is 12 (excluding the decimal). 2. Now we know 32 <= 12 and 33 >= 12. Thus we assign the value of j as 2. 3. Again 3222 > 25 and 3221 = 18 < 25. Thus the value of i is taken as 1. 4. The remainder obtained by following the condition is 25‐18 = 7. 5. Now n = 7. We follow the same steps for 7 and it is repeated till n>1. 6. When n=1, it is represented as 2030. 7. Therefore we express 25 in the following manner ‐ 25 = 3221 + 3121 + 3020. ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Algorithm II Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ The algorithm is shown in the following steps ‐ 1. Let us consider any integer ‘n’. 2. We then divide the number by 6 (2131). 3. Dividing any number by 6 means that it is either divisible by 6 or after dividing the number by 6, gives a quotient and a remainder that lies in the range of 1‐5. 4. Out of the remainders in the range, we can easily represent 1, 2, 3, and 4 using 2, and 3. Only 5 cannot be represented using 2 and 3. 5. Now we use the approach of SDDBNS to represent 5. By the help of a program we deduce the value of 5 as 2‐69345 with an error of 0.00096. 6. Now let us consider the quotient. The quotient may be greater than 6 or less than 6. If the quotient is greater than 6, repeat from step 2. Else repeat from step 4. The quotient is treated in the same manner as the remainder. 7. The process is terminated when either the remainder or the quotient is zero and thus we get the desired result in DBNS. ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ For example, 1. Let us take the same number 25 and divide it by 6 (2131). 2. Since the number (25) is not divisible by 6, after division, the quotient is 4& the remainder is 1. 3. Thus we can represent 25 in the following manner ‐ 25 = (2230*2131) + 2030= 2331 + 2030 Thus the error is introduced only when the remainder or the quotient is 5. For the other cases we can straight way represent the remainders or quotients in terms of 2 and 3. We observe that the two algorithms used to represent any integer approaches in different manners. The number represented using the first algorithm has no error in it. On the other hand, the second algorithm introduces a small error in it at the cost of reduced number of terms in DBNS chains. Now let us discus about the algorithms to represent any integer in TBNS. We use the number ‘30’ in an effective manner to determine the obtained representation. Then we will propose the algorithms to represent any real number. ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Algorithm III ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS The algorithm is shown in the following steps ‐ 1. Let us consider any integer ‘n’. 2. We then divide the number by 30. 3. Dividing any number by 30 means that it is either divisible by 30 or after dividing the number by 30 gives a quotient and a remainder that lies in the range of 1‐29. 4. Out of the remainders in the range, we can easily represent 1, 2, 3, 4, 5, 6, 8, 9, 10, 12, 15, 16, 18, 20, 24, 25 and 27 using 2, 3, and 5. The remaining remainders that cannot be represented by 2, 3, and 5 are 7, 11, 13, 14, 17, 19, 21, 22, 23, 26, 28, and 29. 5. If 7, 11, 13 can be represented in TBNS then we can easily represent 14, 21, 22, 26, and 28 in TBNS since they can be obtained by multiplying 21 or 22 or 31 i.e. The remaining numbers (17, 19, 23, and 29) has to be represented in the same way. To represent the remaining numbers in TBNS, we first check whether the remainder is divisible by 15, 10, 6, 5, 3, and 2 in descending order. That means that the divisibility of the remainder is first checked with 15, then 10 and this particular order is followed. Divisibility by these numbers signifies that the remainder can easily be represented using 2, 3, and 5. The reason behind checking the divisibility of remainders by 15, 10, 6, 5, 3, and 2 is shown in the table 1. Table 2: Remainders Represented using Bases 2, 3 and 5 Integers

Indices 2 (i)

5 (k)

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3 (j)

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS 18

If the remainder is not divisible by any of the following, it is checked whether the remainder is greater than 15 or not. If yes it is divided by 15 & again the remainder is checked using the same procedure i.e. from step 4. If the remainder >=10 &<15, it is divided by 10 & the divisibility of the remainder is checked and same procedure is repeated. If the remainder >=6 &<10, it is divided by 6 & the divisibility of the remainder is checked and same procedure is repeated. The same method is applied by following the specific order to represent the remainder in TBNS. 6. Now let us consider the quotient. The quotient may be greater than 30 or less than 30. If the quotient is greater than 30, repeat from step 2. Else repeat from step 4. The quotient is treated in the same manner as the remainder. 7. The process is terminated when either the remainder or the quotient is zero and thus we get the desired result in TBNS.Thus using this algorithm, we can represent any integer by the bases 2, 3, and 5 in an efficient manner. ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ If the remainder is not divisible by any of the following, it is checked whether the remainder is greater than 15 or not. If yes it is divided by 15 & again the remainder is checked using the same procedure i.e. from step 4. The algorithm is illustrated with an example. Let us take a number as 89. Then we follow these steps – 1. The number (89) is divided by 30. 2. Since the number (89) is not divisible by 30, after division, the quotient is 2 & the remainder is 29. 3. Since the remainder is not divisible by 10, 6, 5, 3, 2; we divide 29 by 15. The quotient is 1 & the remainder is 14. 4. Again 14 is divisible by 2. The quotient is 7. Finally 7 is again divided by 3, resulting the value of the quotient as 2 & remainder as 1. Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS 5. Thus we can represent 89 in the following manner ‐ 89 = (213050 * 213151) + (203151 + 213050 * (213050* 203150 +203050)) = 223151 + (203151 + 213050 * (213150 + 203050)) ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Algorithm IV ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Algorithm IV is nothing but a modified version of Algorithm III. To reduce the complexity of the algorithm, we need to modify the algorithm using an approximation. The approximation is used while representing the remainders. Instead of dividing by 15, 10, 6, 5, 3, and 2; we represent the remainders that cannot be represented using 2, 3, and 5 using Single Digit TBNS. Here the algorithm is discussed in details. The steps from 1‐5 are repeated as in Algorithm I. The modifications are:‐ Instead of checking the divisibility of the remainders, we introduce & apply the concept of SDTBNS. The remainders that cannot be expressed in terms of 2, 3, and 5; i.e. 7, 11, 13, 17 etc. are expressed in the form of 2i3j5k. ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ For example, 7 can be expressed using SDTBNS in the following way – 7 = 2‐35 *3‐45 *547, where the mod error is 0.000228. Similarly the other remainders can also be represented in SDTBNS as shown in the Table 2 below. The table gives an idea about the errors in representation of an integer in SDTBNS. The values of i, j, and k are assumed to be optimal both in accordance with accuracy and data bus width. Again the steps 7 and 8 of Algorithm III are repeated for the termination procedure. Thus any integer is expressed using the TBNS chain and the SDTBNS technique, which is assumed to be effective in the context

Signal

Processing

and

Elliptic

Curve

Cryptography.

Table 3: SDTBNS Representation of the Prime Numbers within the Range 30 and the Corresponding Errors

Remainder

Power of 2 (i)

Power of 3 (j)

Power of 5 (k)

Error (Mod)

‐35

‐45

0.000228

‐79

0.0001

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS 13

‐80

0.000027

‐22

0.000519

‐58

‐12

0.00007

‐53

‐56

0.000127

‐42

0.00022

Let us compare between the third and the fourth algorithm. We will work out with the same example i.e. 89, which was represented using Algorithm I. 4. The number (89) is divided by 30 5. Since the number (89) is not divisible by 30, after division, the quotient is 2 & the remainder is 29. 6. 29 can be expressed by SDTBNS in the form of :‐ 29 = 258 * 328 * 5‐42 The error in this case is 0.00022. 7. Thus we can represent 89 in the following manner ‐ 89 = (213050 * 213151) + 258 3285‐42 = 223151 + 258 3285‐42 We can easily differentiate between Algorithm III& Algorithm IV. In case of the first algorithm, we can represent any integer in TBNS without any error but the complexity increases as the integer value increases. It is much more generalized. On the contrary, in the case of the second algorithm we are representing an integer with a reduced complexity but by introducing some errors in the representation. The number of terms in the expression is also reduced. The figure shown below is the plot that illustrates the variation of error with respect to the change or increase in the powers of 30. This is an efficient tool to observe the efficiency of the algorithm.

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Error values for different powers of 30

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Error for 7 power 3

Error for 11

Error for 7 0.000228 0.00684 0.02052 0.6156

Error for 17

Error for 11 0.000103 0.00309 0.00927 0.2781

Error for 19

Error for 13 2.7E-05 0.00081 0.0243

Error for 23

power 0

power 1

power 2

0.729

Error for 17 0.000519 0.01557 0.4671 14.013 Error for 19 7.6E-05 0.00228 0.0684

2.052

Error for 23 0.000127 0.00381 0.1143

3.429

Error for 29 0.00022 0.0066

5.94

0.198

Error for 13

Error for 29

Powers of 30

Figure 2: Plot of powers of 30 against the calculated error

Let us now discuss some important points regarding the algorithms that are used to represent any integer in TBNS. 1. Maximum number that can be represented using this algorithm up to 3rd power of 30 is (29*303 + 29*302 + 29*30 + 29 = 80999) Percentage error = 0.00075 2. For any number that is to be represented using this algorithm, the maximum possible percentage error is 0.00305. From table 2, we find that the maximum error is occurring while representing 17 in SDTBNS. And as we know that error always gets cumulated in this algorithm, so maximum error occurs when the number is 474827, which can be written as ‐ (17*303 + 17*302 + 17*30 + 17) Error obtained in this case is 14.496, which is obtained from [(0.000519*303) + (0.000519*302) + (0.000519 * 30) + 0.000519]. To understand the above points, we illustrate them by taking the help of two examples – i.

14854 = (16*30+15) * 30 + 4 = 16*302 + 15*30 + 4

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS

= 24. (2.3.5)2 + (3.5) * (2.3.5) + 22

= 26.32.52 + 2.32.52 + 22.30.50 Percentage Error = 0 ii.

15719 = ((17*30+13) * 30) + 29 = (252.32.5‐22) * (2.3.5)2 + (2‐80.33.534) * (2.3.5) + (258.328.5‐42) = 254.34.5‐20+2‐79.34.535+258.328.5‐42 Percentage Error = 0.00297%

These algorithms can be used to represent any real numbers. It is discussed in details in the next portion. 3. In case of Algorithm III, as the value of the integer increases, the complexity also increases, which may lead to increase in redundancy. For example, a. 2357 = [((213050 * 213151) + 213250) * 213151] + (203151 + 213050) = (233252 + 223351) + (203151 + 213050) b. 1573 = 52*30 + 13 = (30+22)*30 + 13 = (213151 + 203151 + 213150 + 203050) * (213151) + (213051+203150) = 223252 + 213252 + 223251 + 213151 + 213051 + 203150 To give an idea about the variation of error with the increase in the value of the integer & the power of 30, we have plot a graph to illustrate the change. Now the algorithms shown above in the paper has applications only while representing an integer. But the real deal is to represent any real number in DBNS or TBNS. In this paper we can use the above four algorithms to represent any real number in DBNS or TBNS. Again we can use the same approach of SDDBNS or SDTBNS to represent the same real number in DBNS or TBNS. Let us discuss the algorithms in detail and then analyse them. We have discussed the algorithms that can be used to represent any integer to DBNS and then TBNS. Now let us explain the algorithms to represent any real number in DBNS or TBNS, which is the most interesting topic of this paper. ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Algorithm V ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ The algorithm is explained in the following steps ‐ 1. Let us consider any real number as ‘n’. Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS 2. We then separate the number into integer portion and decimal portion. 3. The integer part is expressed in either DBNS or TBNS using any of the four algorithms that are described in details or any other algorithm like tree based approach in case of DBNS. 4. Now to represent the decimal part in DBNS or TBNS, we first convert the decimal part in binary form. We need to take some approximation if the representation of the decimal part in binary reaches a recursive loop. In that case we take up to 8 digits. 5. Since we know the place values of each ‘0’ and ‘1’ we can use them to represent the decimal part in DBNS or TBNS. 6. We add the place values of each ‘1’ and find the result. For example, the ‘1’ at the 8th digit will have a place value as 2(8‐1). 7. The sum obtained is represented using any of the four algorithms that are shown above or any other algorithm to express it in TBNS or DBNS. 8. 2‐8 is then multiplied with the obtained DBNS or TBNS form. ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Thus we get our desired result and can easily represent any real number in DBNS or TBNS form without introducing large amount of error. Let us take an example to illustrate the above stated algorithm. 1. Let us take a real number as 6.675. 2. Now the integer part is 6 and the decimal part is 0.675. 3. 6 can be easily represented using any algorithm between I‐IV or by using any other algorithm that are already being proposed and used. 4. Now 0.675 is represented in binary form as (10101110)2. 5. We represent the above binary form as 2‐8 * (21+22+23+25+27) = 2‐8 * 174. 6. 174 can be expressed in DBNS or TBNS. The obtained result is multiplied with 2‐8. Error will vary according to the algorithm that is used to represent the number in either DBNS or TBNS. Error will be more in case of DBNS and less in case of TBNS. Instead of using the above algorithm to represent any real number in DBNS & TBNS we can approach with the concept of Single Digit Double Base Number System and Single Digit Triple Base Number System. Let us now discuss them in details. ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS Algorithm VI ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ The algorithm is discussed in details ‐ Input: Any real number ‘n’ Output: SDDBNS representation of the number 1. inti,j,s1=0,s2=0; 2. float e,e1=0.005,n1; 3. for j=‐100 to j<=100 do /* outer loop */ 4. for i=‐100 to i<=100 do /* inner loop */ 5. n1= 2i * 3j; 6. e = (n‐n1)/n; 7. if e<0 then e=‐(e); 8. if e<e1 then e1=e; s1=i; s2=j; 9. end inner loop 10. end outer loop 11. print the powers of 2 and 3and the error. ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ The above algorithm can only be implemented using any programming language like C or Java. Let us take an example – 1. Let the number be 5.67. 2. After computing the program we get the result as 5.67 = 277 * 3‐47 3. The error obtained is 0.002369. Now let us discuss similar type of algorithm to represent any real number in Single Digit Triple Base Number System (SDTBNS). Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ Algorithm VII ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ We follow the following steps – Input: Any real number ‘n’ Output: SDTBNS representation of the number 1. int i,j,k,s1=0,s2=0,s3=0; 2. float e,e1=0.005,n1; 3. for k=‐100 to k<=100 do /* outer loop */ 4. for j=‐100 to j<=100 do /* inner loop 2 */ 5. fori=‐100 to i<=100 do /* inner loop 1 */ 6. n1=2i * 3j * 5k; 7. e = (n‐n1)/n; 8. if e<0 then e=‐(e); 9. if e<e1 then e1=e; s1=i; s2=j; s3=k; 10. end inner loop 1 11. end inner loop 1 12. end outer loop 13. print the powers of 2, 3 and 5 and the error. ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ The above algorithm can only be implemented using any programming language like C or Java. Let us take an example – 1. Let the number be 5.67. 2. After computing the program we get the result as 5.67 = 2‐37 * 3‐41 * 545 3. The error is 0.000033.

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS Table 4: Comparison between the different algorithms with respect to various parameters

No. of

Maximum (or

Highest (or

Elements in

Minimum)

Lowest)

Percentage

Algorithms

the Chain

Power of 2

Power of 3

Power of 5

Power

Error

‐

‐68

‐

‐68

0.018720

‐5

‐

0.1654

‐19

0.00268

‐52

0.001046

‐5

‐

0.1314

‐8

0.00018

‐8

0.00018

‐8

‐

‐8

0.00018

‐76

‐

‐76

0.000149

Comparing the above two algorithms in terms of error obtained or the highest power of the bases, we can observe the importance of TBNS over DBNS. After discussing about all the algorithms in details, here we present two tables (Table 3 and Table 4) that can help us a lot in distinguishing the different algorithms and a designer can choose the best algorithm required for his purpose. The tables are shown below. We have used the same number to represent in either DBNS or TBNS so that we can compare by using some parameters. The integer and real number used is 1077 and 1077.36523 respectively. Table 5: A comparative study of the proposed algorithms

Requirement of

Capacity of

Algorithms

Applicable to

Computational

adders &

Error

Speed of

complexity

multipliers

Hardware requirement

operation

used 1

Integer

Low

High

Low

Errorless

Moderate

Integer

Moderate

High

Low

Errorless

Moderate

Integer

Moderate

Low

`High

Moderate

Fast

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS 4

Integer

Moderate

Low

High

Moderate

Fast

Integer

High

Least

High

Moderate

Slow

Integer

High

Least

High

Moderate

Slow

Any Real

High

Least

High

Moderate

Slow

High

Least

High

Moderate

Slow

High

Low

High

Moderate

Slow

High

Moderate

Low

Moderate

High

Moderate

Low

Slow

High

Low

High

Moderate

number 8

Any Real number

For both the tables shown above, algorithm 1 denotes the algorithm to represent any integer in DBNS as described in algorithm I, algorithm 2 denotes the algorithm to represent any integer in TBNS as described in algorithm III, algorithm 3 resembles algorithm II, algorithm 4 resembles algorithm IV, algorithms 5 and 6 approach SDDBNS and SDTBNS respectively to represent any integer, algorithms 7 and 8 approach SDDBNS and SDTBNS respectively to represent any real number, algorithms 9‐12 use algorithm V to represent the real number in either DBNS or TBNS by the help of algorithm IV, algorithm III, algorithm I & algorithm II respectively.

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS 5. ADVANCEMENT IN CONTEXT OF MULTIPLIERS Let us now discuss about the most important application of DBNS and TBNS. In microprocessors multiplication operation is performed in a variety of forms in hardware and software depending on the cost and transistor budget allocated for this particular operation. In the beginning stages of computer development any complex operation was usually programmed in software or coded in the micro‐code of the machine. Some limited hardware assistance was provided. Today it is more likely to find full hardware implementation of the multiplication in order to satisfy growing demand for speed and due to the decreasing cost of hardware. For simplicity, we will describe a basic multiplication algorithm which operates on positive n‐bit long integers X and Y resulting in the product P which is 2n bit long:

n‐1n‐1

P=XY=X * ∑ yiri= ∑ X*yiri

i=0i=0

This expression indicates that the multiplication process is performed by summing nterms of a partial product Pi. This product indicates that the ithterm Piis obtained by simple arithmetic left shift of X for the ipositions and multiplication by the single digit yi. For the binary radix (r=2), yiis 0 or 1 and multiplication by the digit yiis very simple to perform. The addition of n terms can be performed at once, by passing the partial products through a network of adders or sequentially, by adding partial products using an adder n times. The algorithm to perform the multiplication of X and Y can be described as: p(0) =0 pj+1=1/r(pj+ rnXyj)

for j=0…….n‐1

It can be easily proved that this recurrence results in p (n)=XY. 5.1 HIGH PERFORMANCE MULTIPLIERS The speed of multiply operation is of great importance in digital signal processing as well as in the general purpose processors today, especially since the media processing took off. In the past, multiplication was generally implemented via a sequence of addition, subtraction, and shift operations. Few of the names of high speed multipliers are given – Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS 5.1.1

Parallel Multipliers –

An alternative approach to sequential multiplication involves the combinational generation of all bit products and their summation with an array of full adders. This approach uses an n by narray of AND gates to form the bit products, an array of n * n adders (and half adders) to sum the n2 bit products in a carry‐save fashion. Finally a 2n Carry‐Propagate Adder (CPA) is used in the final step to finish the summation and produce the result. 5.1.2

Wallace/Dadda Multiplier –

C. S. Wallace introduced a way of summing the partial product bits in parallel using a tree of Carry Save Adders which became generally known as the “Wallace Tree”. This method was further refined by Dadda. With Wallace method, a three step process is used to multiply two numbers: (1) The bit products are formed (2) The bit product matrix is “reduced” to a two row matrix by using carry‐save adders (known as Wallace Tree) (3) The remaining two rows are summed using a fast carry‐propagate adder to produce the product. Although this may seem to be a complex process, it yields multipliers with delay proportional to the logarithm of the operand size n. 5.1.3 Three Dimensional optimization Method (TDM) – The further work in improving the speed of a multiplier by optimizing Partial Product Reduction Tree (PPRT) was extended by Oklobdzija, Villeger and Liu. Their approach was to optimize the entire PPRT in one pass, thus the name Three Dimensional optimization Method (TDM). The important aspect of this method is in sorting of fast inputs and fast outputs. It was realized that the most important step is to properly interconnect the elements used in the PPRT. Thus, appropriate counters (3:2 adders in a particular case) were characterized in a way which identifies delay of each input to each output. Interconnecting of the PPRT was done in a way in which signals with large delays are connected to "fast inputs" and signals with small delay to "slow inputs" in a way that minimizes the critical paths in the PPRT. 5.1.4

4:2 Compressor ‐

In 1981 Weinberger disclosed a structure which he called "4‐2 carry‐save module". This structure contained a combination of FA cells in an intricate interconnection structure which was yielding a faster partial product compression than the use of 3:2 counters. The structure actually compresses five partial product bits into three, however it is connected in such a way that four of the inputs are Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS coming from the same bit position of the weight j while one bit is fed from the neighbouring position j‐1 (known as carry‐in). The output of such a 4:2 module consists of one bit in the position j and two bits in the position j+1. 5.1.5

Booth Recoding Algorithm –

Booth's algorithm examines adjacent pairs of bits of the N‐bit multiplier Y in signed 2's complement representation, including an implicit bit below the least significant bit, y‐1 = 0. For each bit yi, for i running from 0 to N‐1, the bits yi and yi‐1 are considered. Where these two bits are equal, the product accumulator P remains unchanged. Where yi = 0 and yi‐1 = 1, the multiplicand times 2iis added to P; and where yi = 1 and yi‐1 = 0, the multiplicand times 2i is subtracted from P. The final value of P is the signed product. Booth recoding necessitates the internal use of 2's complement representation in order to efficiently perform subtraction of the partial products as well as additions. However, floating point standard specifies sign magnitude representation which is also followed by most of the non‐standard floating point numbers in use today. The Booth algorithm is widely used for two’s complement multiplication, since it is easy to implement. Booth recoding is performed within two steps: encoding and selection. The purpose of the encoding is to scan the triplet of bits of the multiplier and define the operation to be performed on the multiplicand.

Figure 3: Flow chart of Booth’s algorithm Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS 5.1.6

Hitachi's DPL Multiplier –

Hitachi's DPL multiplier was the first one to achieve under 5nS speed for a double‐precision floating‐ point mantissa imposed by the increasing demands on the operating frequency of modern micro‐ processors. This multiplier is of a regular structure including: (a) A Booth Recoder, (b) A Partial Product Reduction Tree (Wallace Tree) and (c) A final Carry Propagate Adder (CPA) 5.1.7

Inoue's Multiplier –

High speed multiplier published by Inoue employs two novel techniques in achieving very fast (4.1nS delay) 54*54 bit parallel multiplier implemented in 0.25u CMOS technology. The first novelty introduced is in a new design of the Booth Encoder and Booth selector for generation of partial products. If these many of multipliers are already used then what is the requirement of introducing a new multiplier unit using a new method of representing numbers? The answer is very simple. Multi‐ base number systems (especially DBNS & TBNS) reduce the complexity of the multipliers with a reduced number of logic gates. The main motive of VLSI design is to implement a chip with smaller area, faster speed & cheaper cost. Here lies the importance of our project. Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS 6

DESIGN OF THE ARCHITECTURE OF MULTIPLIER UNIT

The proposed multiplier is consisting of the following blocks – three adders, one look up table (LUT), and one shifter unit. The input to the multiplier is 4 i.e. the powers of 2 and 3.The basic need of the multiplier unit is that the numbers must be represented in Double Base Number System. It consists of simple ALU‐Adder unit which adds the exponents (viz. a1 & a2;b1 & b2;a1, a2& c). The output b1+b2 is fetched to the look‐up table which finds the relation: 3b1+b2=A*2c; where ‘A’&‘c’ are the constants. If we left shift A by (a1+a2+c) units using Barrel shifter, we can easily obtain the desired result i.e. the product of two numbers. Let us first show the simple block diagram of the multiplier and then discuss about the working principle of it. Suppose two number X and Y to be multiplied. Now X and Y can be represented by DBNS using any of the proposed algorithms as stated earlier. Let X = 2a1 * 3 b1 and Y=2a2 * 3b2 a. The binary value of a1, a2 and b1, b2 is to be given to the multiplier as input. Now the first adder (A1) adds a1 & a2 and the second adder (A2) adds b1 & b2. Result of A1 is s1 (a1+a2) and result of A2 is s2 (b1+b2). Now basically s1 is in the power of 2 and s2 is in the power of 3. b. Now we can represent 3s2 as α * 2s3i.e. 3s2= α * 2s3.Now as s2 is given to a LUT and for a particular value of s2, it produces two outputs that are‐ s3 and α. Thus we get the following representation ‐ 3s2= α *2s3. c. s3 is again given to the third adder (A3) along with s1. It produces the output N. The value of α is given to a Shifter. The input to the shifter is N and α. α is shifted by N amounts. As we know that shifting a number (binary) in left by one amount is basically same as multiplying the number by 2. Here we know the exact value by which the number to be shifted and as α is expressed in binary value, if it is shifted by N amount then it is same as multiplying α by 2N. α is obtained from the LUT for a particular value of power of 3 that is s2. So if α is left shifted by N amount then it is the result of X*Y i.e. Z (say). By this way the multiplication is done.

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS

Figure 4: Simple Block Diagram

Implemented Architecture

We have discussed in the previous paragraph about the proposed architecture of the multiplier. However during the implementation of this architecture using VHDL we have faced some problems because of the compatibility of the used software XILINX ISE DESIGN SUITE 13.2 for the simulation of the codes which are needed to implement the basic building blocks of the multiplier. That’s why we have changed it a little for the simulation purposes. It is almost the same as the proposed architecture. However we have included a new block that is ‘Converter’ which converts the binary value of N to integer. It is done only for simulation purpose. Input to ‘Converter’ is N and output is temp (say) which is an integer. For shifting the alpha value by a fixed amount we need loops and as loop can only be iterated by integer values that’s why we needed this. For the simplicity of design we have designed such a multiplier which can multiply any two numbers whose product is less than or equal to 1296. However this can be easily increased if needed using the same architecture. The adder, shifter and LUT is to be made larger in capacity. Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS A detailed discussion of each block as well as the total multiplier unit and how they are operating is done later. A simple diagram of the implemented architecture is given below.

Figure 5: Simple Diagram of Multiplier

Detailed discussion of each block of the multiplier

6.1 Adder We have designed a four bit adder using VHDL. Actually we have made 3 adders. However the basic architecture for each adder is same. A one bit adder is done by this simple logic– SUM= A XOR B XOR C; CARRY= (A AND B) OR (B AND C) OR (C AND A); Where A, B and C are the input of the one‐bit adder. Now this one‐bit adder is port‐mapped to make a four bit adder. Basically it is a ripple carry adder. Full VHDL code is not given for confidentiality. A simple port mapping command is given to clarify the concept ‐

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS ONEBIT0: ONEBIT PORT MAP (A(0),B(0),CIN,S(0), C11); Here A(0),B(0) and CIN are the input of the 1st one bit adder whereas S(0) is the sum o/p and C11 is the carry generated.

Figure 6: A Simple Block Diagram of a Four Bit Ripple Carry Adder Now the implemented adder using VHDL is shown in the following figure‐

Figure 7: Basic RTL & Technological Schematic of the Four‐bit Adder

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS

Figure 8: RTL Schematic of Four‐bit Adder with Internal One‐bit Block

Figure 9: Detailed RTL Schematic of the Four‐bit Adder

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS

Figure 10: Detailed Technological Schematic of Four‐bit Adder The output of a four bit adder, adding two values (0011) and (0100) is shown in the waveform shown below.

Figure 11: Waveform of the Output Obtained Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS 6.2 Look Up Table Look up table is such kind of block which for a particular value of input produces a particular value of the output.

Figure 12: Basic RTL & Technological Schematic of LUT As we have stated earlier, we have to convert the 3s2 value to (α * 2s3) and that is the reason behind using this concept of LUT.

Figure 13: Detailed RTL Schematic of LUT

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS Before presenting the technological schematic of LUT, let us take an example to demonstrate the function of LUT. 31 can be represented using the power of 2 as 31 = (1.5) * 21. Similarly, 32 = (2.25) * 22 and so on. But during the implementation of the LUT using the VHDL we find it difficult we represent a floating point number like 2.25. That’s why we have converted the floating number to a integer value and so changed the value of s3 accordingly to keep the value of the product (alpha) * 2s3 same. Example: 32 = (2.25) * 22 (0010)2 = (10.01)2 * (0010)2 (here only s2, α, s3 value is given not their powers) (0010)2 = (1001000)2 * (1101)2 This is because if power of 3 is given as input (here it is 2) then it produces α (here 10.01) and power of 2 (here 2) but as floating point number is hard to write in a VHDL code so we can change the ‘alpha’ value to integer (here 1001000) but as we do it we have to change the power of 2 value also. As (10.01)2 = (1001000)2 * (2‐5) so by adding the ‐5 value with the power of 2 we can send the final value. Here power of 2 is 2 so, we are actually sending (‐5+2) = ‐3 value i.e. (1101) in 2’s complement form. Thus we are getting the value of α and s3 (a3 in VHDL code) values from the LUT. In LUT we have given the mapped value of for each case which is needed to be produced for each value of s2.

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS

Figure 14: Detailed Technological Schematic of LUT

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS In the following figure, we have shown the output waveform where the input to Look UpTable (LUT) is 3(0011) and its producing α as (1101100) and s3 (a3) as (1110). The waveform describes the behavioural characteristics of the LUT, which is a very important part of our architecture.

Figure 15: Output Waveform of LUT 6.3 Converter In the proposed architecture there is no converter. However when we tried to implement the architecture we faced some problems because of the VHDL syntax and that’s why we have separated the block and connected with the main architecture.

Figure 16: Basic RTL & Technological Schematic of Converter Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS Basic architecture of the converter is shown above. The convertor is not required if the multiplier is to be implemented in hardware. This is only done to simulate the whole multiplier unit in XILINX DESIGN SUITE 13.2. It converts the N value to integer. N is the sum of s1 and s3 (a3). To shift the ‘alpha’ value by the needed the amount we need to iterate a loop but as loop cannot be iterated by STD_LOGIC_VECTOR value that’s why it is converted to integer.

Figure 17: Detailed RTL Diagram of Converter

Figure 18: Waveform of the Converter: [Input ‐‘slct’ (in std logic vector); Output – ‘temp’ (Integer)]

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS [However ‘temp’ is shown in binary form because XILINX cannot show integer value in simulation window.] 6.4 Shifter This block shifts the value of α by the N amount. N is the sum of s1 and s3 (a3). Input to this block is α which is taken from LUT and N and its integer value which are taken from convertor. α is kept 7 bit length and the result i.e. the o/p of shifter is kept 11‐bit length. We have designed the multiplier which can multiply any two numbers whose product is less than 1296. This is done for simplifying the simulation process. It can be made larger if needed. As to represent the 1296 value we need minimum 11 bits that’s why 11‐bit length is fixed, As stated earlier, the convertor converts the N value to integer, so, by using that integer value we iterate the ‘alpha’ by N amount by a loop designed within the shifter block. Output of the shifter block is the output of the multiplier i.e. product of the two number. The architecture of shifter unit is shown below –

Figure 19: RTL & Technological Schematic of Shifter

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS

Figure 20: Detailed RTL Schematic of Shifter

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS

Figure 21: Detailed Technological Schematic of Shifter

Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS 6.5 Multiplier Architecture In the previous section, we have discussed the each building block of the multiplier. In this section we are going to discuss the whole multiplier unit as a block and how the internal blocks are connected with each other and how they are operating as a whole.In the section ‘Implemented architecture’ we have discussed the multiplier block as a whole. We have used 3 adders, 1 LUT, 1 converter, 1 shifter. 1. First ‘a1’ and ‘b1’ (which are the binary value of power of 2 of the 2 different numbers) is given as the input to ADDER1. It produces the output S1 (All are 4‐bit length). 2. Now ‘a2’ and ‘b2’ (which are the binary value of power of 3 of the 2 different numbers) is given as the input to ADDER2. It produces the output S2 (All are 4‐bit length). 3. S2 is given to the LUT as input. LUT produces two output values α and ‘S3’ (α is 7‐bit long and S3 is 4‐bit long). 4. S1 and S3 (a3) value is given to the ADDER3 as input. It produces output N (All are 4‐bit long). 5. This N is given to the CONVERTER as input. Converter converts the N to integer and gives the output TEMP (integer) and TEMP4(std_logic_vector). TEMP4 is same as N. 6. The shifter is given the inputs‐‘alpha’ taken from LUT, TEMP & TEMP4 taken from CONVERTER. It produces the RESULT which is the output of the multiplier. 7. The blocks are port mapped in VHDL in the following way – i.

U0: ADDER PORT MAP (A1,A2,'0',S1, CARR1);

ii.

U1: ADDER PORT MAP (B1,B2,'0',S2,CARR2);

iii.

U2: LUT PORT MAP (S2,S3,ALPHA_ONE);

iv.

U3: ADDER PORT MAP (S1,S3,'0',N,CARR3);

U4: CONVERTOR PORT MAP (N,TEMP_THREE);

vi.

U5: SHIFTER PORT MAP (ALPHA_ONE,N,TEMP_THREE,RES);

vii.

RESULT <= RES;

The architecture of the multiplier which is built in VHDL is given below –

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS

Figure 22: Basic RTL & Technological Schematic of MULTIPLIER

Figure 23: Detailed RTL schematic of MULTIPLIER

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Figure 24: RTL Schematic of MULTIPLER Showing All the Internal Blocks with their Architecture The following figure is the i/p and o/p waveforms of the MULTIPLER as a whole. Input to multipler is X=22.31 and Y=22.32. I/P is given in the following way‐ 1. ‘a1’ as the power of 2 of X i.e. 2 (0010) 2. ‘b1’ as the power of 3 of X i.e. 1 (0001) 3. ‘a2’ as the power of 2 of Y i.e. 2 (0010) 4. ‘b2’ as the power of 3 of Y i.e. 1 (0010) The internal results are – 1. ‘s1’ as the sum of ‘a1’ and ‘a2’ i.e 4 (0100) 2. ‘s2’ as the sum of ‘b1’ and ‘b2’ i.e 3 (0011) 3. ‘s3’ as the one o/p of LUT i.e ‐2 (1110) 4. ‘n’ as the sum of ‘s1’ and ‘s3’ i.e 2 (0010) Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS 5. ‘alpha_one’(alpha) as the another LUT o/p i.e (1101100) The final result is ‐ ‘result’/ ‘res’=(00110110000) It’s value is 432 which is also the same with the product of X and Y i.e. Z = X * Y = (22 * 31) (22 * 32) = (24 * 33) = 432 = (00110110000)2. So, the simulated output is same as the actual output. That means simulation is right and the architecture is error free.

Figure 25: Detailed Technological Schematic of the MULTIPLIER Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS

Figure 26: Output Waveform of the Multiplier

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS All of the above values is shown using waveforms in the following figure with i/p and o/p of the multiplier.

Figure 27 : Block Diagram of a Multiplier Unit in TBNS We have already discussed about the architecture of the multiplier unit using DBNS in details. The above block diagram shows the architecture of a multiplier unit designed in TBNS. There is no such difference in the design of the multiplier unit using TBNS, just adding some more complexity to the design. It also consists of a simple ALU‐Adder unit which adds the exponents (viz. a1 &a2; b1 & b2; c1 & c2 and the other exponents as shown in the figure 3). The output c1+c2 is fetched to the look‐up table which finds the relation: 5c1+c2 = 2a3*3b3. Again the second look up table performs similar operations for the power of 3 i.e. 5b1+b2 +b3 = N * 2a4.If we left shift N by the sum obtained as (a1+a2+a3+a4) units using Barrel shifter, we can easily obtain the desired result i.e. the product of two numbers. Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS 7

APPLICATIONS

Tables 3 and 4 compares between the proposed algorithms. Instead of discussing about the application of each and every algorithm, we present the general application of the algorithms in details. We have discussed about the design of a multiplier unit. Now what is the need of designing a multiplier unit using DBNS and TBNS? The answer is described in details below. [1] In binary number representation, each bit has approximately 0.5 probability of being 1.But in DBNS, the number of bits that are logic 1 in the tabular representation could be much less. Effectively, we can reduce the number of 0Æ1 and 1Æ0 transitions, thus saving power. [2] It can be shown that expected number of bits that are ‘turned on’ in a DBNS representation of integer is O[log x/(log log x)], which is significantly lower than the corresponding number in the positional binary system, O(log x). As an example, consider the integer 2215; in binary system, number of ‘1’s ≈ 100 & in DBNS, number of ‘1’s ≈ 30 [3] An FIR filter implements the linear convolution: Yi=∑xkhi‐k

A well‐established technique to reduce the complexity is to select filter coefficients with a small number of nonzero binary digits. Canonic‐signed‐digit (CSD) representations allow a greater choice of coefficients with no increase of the number of nonzero digits. Such an approach, however, often leads to increases in the filter length to allow a desired spectral envelope to be matched. The DBNS representation typically allows single digit approximations with much greater coefficient space support than the CSD approach. There is also the advantage of reduced multiplication complexity. 7.1 APPLICATION IN DIGITAL SIGNAL PROCESSING Digital signal processing (DSP) is the technology that is omnipresent in almost every engineering discipline. A typical processor devotes a considerable amount of processing time in performing arithmetic operations, particularly multiplication operations. Multiplication is one of the basic arithmetic operations and it requires substantially more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all the instruction in typical processing units is multiplication. The core computing process is always a multiplication routine; therefore, DSP engineers are constantly looking for new algorithms and hardware to implement them.Applications involving multiplication by constant are common in digital signal processing, image processing, Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS control, and data communication. Finite impulse response (FIR) filters, discrete cosine transform (DCT), and discrete Fourier transform (DFT), for instance, are central operations in high‐throughput systems and they use a huge amount of such operations. Their optimization widely impacts the performance of the global system that uses them. For instance, the famous recoding presented by Booth can simplify both the multiplications by constants and the complete multiplications. This recoding and the algorithm proposed by Bernstein were widely used on processors without a multiplication unit. The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. Higher throughput arithmetic operations are important to achieve the desired performance in many real‐time signal and image processing application. One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. Reducing the time delay and power consumption are very essential requirements for many applications. This work presents a high performance multiplier architecture. Multiplier based on DBNS and TBNS is one of the fast and low power multiplier. Digital multipliers are the most commonly used components in any digital circuit design. They are fast, reliable and efficient components that are utilized to implement any operation. Depending upon the arrangement of the components, there are different types of multipliers available. Particular multiplier architecture is chosen based on the application. In many DSP algorithms, the multiplier lies in the critical delay path and ultimately determines the performance of algorithm. The speed of multiplication operation is of great importance in DSP as well as in general processor. In the past, multiplication was implemented generally with a sequence of addition, subtraction and shift operations. There have been many algorithms proposals in literature to perform multiplication, each offering different advantages and having trade off in terms of speed, circuit complexity, and area and power consumption. The multiplier is a fairly large block of a computing system. The amount of circuitry involved is directly proportional to the square of its resolution i.e. a multiplier of size n bits has n2 gates. For multiplication algorithms performed in DSP applications latency and throughput are the two major concerns from delay perspective. Latency is the real delay of computing a function, a measure of how long the inputs to a device are stable is the final result available on outputs. Multiplier is not only a high delay block but also a major source of power dissipation. That’s why if one also aims to minimize power consumption, it is of great interest to reduce the delay by using various delay optimization. In Multi Base Number System (DBNS, TBNS), Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS the calculations of the exponential power of the different prime bases are necessary. To calculate the exponential powers of numbers in a Single Base Number System the number is known as the base and the power as the exponent, but Booth’s Multiplication algorithm is required for the multiplication of the base with itself exponent times. Any number can be divided into some consecutive numbers. Using greedy method, those numbers are calculated as described by Double Base Number System. These numbers can be represented in triple base number system. For this calculations Booth algorithm can be used. This project deals with the efficient methods to calculate the exponential powers of prime base numbers 2, 3. Using these techniques if we reduce the number of operations then the construction of logic will be easier. As a result, fewer gates will be required. Less energy, less hardware will be needed for implementation. In this project, DBNS is applied to the binary number system and is used to develop digital multiplier architecture. DBNS is much more efficient in the multiplication of large numbers as it reduces the multiplication of two large numbers to that of two smaller ones. This project presents the design of a low power high speed algorithms for arithmetic logic units using DBNS. Employing this technique in the computation algorithms of the coprocessor has reduced the complexity, execution time, area, power. The double‐base number system is used in digital signal processing systems for over a decade because of its fast inner product operation and low hardware complexity.When there is only a single DBNS term, the multiplication can be done simply by adding the exponents. However, there are usually many DBNS terms, so an algorithm was developed to find the canonic DBNS (Greedy Algorithm and later on Tree based approach). In TBNS, the calculations of the exponential power of the different prime bases are necessary. Fewer gates will be required. Less energy, less hardware will be needed for implementation. In this paper, TBNS is applied to the binary number system and is used to develop digital multiplier architecture. TBNS is much more efficient in the multiplication of large numbers as it reduces the multiplication of two large numbers to that of two smaller ones. The algorithms can be implemented in the design of a low power high speed algorithms for arithmetic logic units using DBNS and TBNS. Employing this technique in the computation algorithms of the coprocessor will reduce the complexity, execution time, area, power. The TBNS technique has its maximum application in Fast Fourier Transform, where complex and large multiplications are required. In the case of the radix‐2 DIT‐FFT algorithm, the butterfly takes two inputs (X0, X1) and gives two outputs (Y0, Y1) by the formula ‐ Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS Y0=X0+X1ωк Y1=X0‐X1ωк where ω= twiddle factor. As this is basically a complex multiplication and addition so, by this proposed algorithm, FFT calculation can be done faster. Same is applicable in the case of DIF‐FFT algorithm. And by decimation more point DFT can be calculated efficiently. 7.2 APPLICATION IN THE FIELD OF CRYPTOGRAPHY Cryptography is the study of mathematical techniques related to aspects of information security such as confidentiality, data integrity, entity authentication, and data origin authentication. Triple Base Number System (TBNS) has found application in cryptography especially in Elliptic Curve Cryptography (ECC) [8]. Scalar multiplication is the bottleneck operation of the elliptic curve cryptography. It is to compute the result ‐ Q = rS when S and Q are points on the elliptic curve and r is a positive integer. The computation time of the operation strongly depends on the representation of r. r can be represented using the various algorithms in DBNS and TBNS. In Elliptic Curve Cryptography, signature verification is one of the most important step and this mainly requires a double‐scalar multiplication of the form [n] P+ [m] Q. It can be done by calculating separately the product values and then by adding them. But if this is done by a combined operation then this is called multi‐scalar multiplication. These algorithms can also be used for such operations. Let us take a problem of cryptography to understand how DBNS and TBNS are applied in Cryptography. Proposed Method – Alice wants to send a message M to Bob. She convents the message with equivalent numbers according to the following table. The working methodology of the proposed model is discussed stepwise. To encrypt the character, use the value of the character to determine the numeral in the table. A B C D E F G H I J K L M N O P Q R S T U V W X Y Z Null or Space 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 The working methodology of the proposed model is discussed stepwise – To encrypt the character, use the value of the character to determine the numeral in the table; the value of the character is converted into DBNS. The value of {di,j, ij} is obtained. This encrypted {di,j} is sent to Bob in public channel in hexadecimal form. Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS Example: Encryption: If Alice wants to send a message GOOD to Bob she converts message to a matrix – M = [6 14 14 3] 6 can be represented as ‐ 1*2030+1*2130+0*2230 +1*2031+ 0*2131+ 0*2231+0*2032+ 0*2132+0*2232 Therefore 6 is represented as {110100000} Similarly, 14 can be represented as 1*2030+0*2130+1*2230 +0*2031+ 0*2131+ 0*2231+1*2032+ 0*2132+0*2232 Therefore 14 is represented as {101000100} The cipher text is represented as {110100000101000100101000100000100000} This is further converted into hex code as ‐ ‘D05128820’ Decryption: The message D05128820 is converted into the equivalent code to obtain the cipher text C = {110100000101000100101000100000100000} These are taken as coefficients by bob to get the original text. This algorithm based on Double Based Canonical Number System, consists of data encryption at two levels. The cipher text so obtained becomes quite impossible to break or to interrupt. Thus the computational overhead is very low. It is almost impossible to extract the original information in the proposed method even if the algorithm is known. Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS 8

CONCLUSIONS

In the past, a thorough examination of the algorithms with the respect to particular technology has only been partially done. The merit of the new technology is to be evaluated by its ability to efficiently implement the computational algorithms. Therefore, it is important to develop computational structures that fit well into the execution model of the processor and are optimized for the current technology. In such a case, optimization of the algorithms is performed globally across the critical path of its implementation. Ability to integrate 100 millions of transistors onto the silicon has changed our focus and the way we think. Measuring the quality of the algorithm by the minimum number of devices used has simply vanished from the picture. However, new concerns such as power have entered it. In this work, we have proposed& discussed in details about few new algorithms in DBNS and TBNS, as a technique for representing numbers that allows potentially low complexity arithmetic operations using a variety of implementation media. The analysis of the algorithms in terms of error, length of the chain, highest powers of the bases distinguish the algorithms and show the advantages of them. Compared to the algorithms present to convert any real number in DBNS and TBNS, our algorithm is much more efficient and simple. The tables and graphical representation illustrates the accuracy of the proposed algorithms. The design of the architecture that converts any integer into TBNS & that performs the multiplication of two integers is simple & efficient. We have designed an efficient multiplier unit using DBNS in VHDL, which can be implemented in the field of Digital Signal Processing. We have shown how each unit of the multiplier works. We have also presented a block diagram of the multiplier using TBNS. As future works, we want to improve the proposed algorithms and try to reduce the computational complexities and errors. Also we want to design a system where we can implement the algorithms or we will implement the algorithms in a system. This can be a great boon for the Computer Science industry. Arnab, Moyukh, Ayan, Biplab, Balmiki

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS REFERENCES [1] H. Garner, “Number Systems and Arithmetic,” Advances in Computing, vol.6, pp. 133‐194, 1965 [2] G.W.Reitwiesner, “Binary Arithmetic,” Advances in Computing, vol.1, pp. 231‐308, 1960 [3] T. ElGamal, “A public key cryptosystem and a signature scheme based on discrete logarithms,” IEEE Transactions on Information Theory, vol. 31, no. 4, pp. 469 – 472, July 1985 [4] D. Hankerson, A. Menezes, and S. Vanstone, Guide to Elliptic Curve Cryptography, Springer, 2004 [5] A.D. Booth, “A Signed binary multiplication technique,” Quarterly Journal of Mechanics and Applied Mathematics, vol. 4, no. 2, pp. 236 – 240, 1951, reprinted in E.E. Swartzlander, Computer Arithmetic, Vol. 1, IEEE Computer Society Press Tutorial, Los Alamitos, CA, 1990 [6] Jithra Adikary, Vassil Dimitrov, and Laurent Imbert, “Hybrid Binary‐Ternary Joint Sparse” Form and its Application in Elliptic Curve Cryptography,” Draft, July 2, 2008. [7] M. Joye and S.M. Yen, “Optimal left‐to‐write binary signed‐digit exponent recording,” IEEE Transactions on Computer, vol. 49, no. 7, pp. 740 – 748, 2000 [8] M. Ciet, M. Joye, K. Lauter, and P.L. Montgomery, “Trading inversions for multiplications in Elliptic Curve Cryptography,” Designs, Codes and Cryptography, vol. 39, no. 2, pp. 189 – 206, May 2006. [9] J.A.Solinas, Low‐weight binary representation for pairs of integers”, Centre for Applied Cryptographic Research, University of Waterloo, Waterloo, ON, Canada, Research Report CORR 2001‐ 41, 2001. [10] Avanzi, R.M., Dimitrov, V.S., Doche, C., Sica, F.: Extending Scalar Multiplication using Double Bases, in: Lai, X., Chen, K.(Eds.), ASIACRYPT 2006, LNCS, vol. 4284, pp. 130 – 144, Springer, Heidelberg (2006). [11] C. Doche and L. Imbert, “Extended double‐base number system with applications to elliptic curve cryptography”, in Progress in Cryptography, INDOCRYPT’06, ser. Lecture Notes in Computer Science, vol.4329, Springer, 2006, pp. 335 – 348. [12] Dimitrov,V.S., Jullien, G.A., Miller, W.C.,: An Algorithm for Modular Exponentiation. Information Processing Letters 66(3), 155 – 159(1998) [13] V.S.Dimitrov, G.A.Jullien and W.C.Miller, “Theory and Application of Double‐Base Number System”, IEEE Transaction on Computers, vol.48, No.10, pp‐1098‐1106, October, 1999 [14] Pavel Sinha, Amitabha Sinha, Krishanu Mukherjee and Kenneth Alan Newton, “Triple Base Number Digital and Numerical Processing System”, Patent filed under E.S.P.Microdesign Inc., Pennsylvania, U.S.A., U.S.Pat. App. No. 11/488, 138 [15] S.Maitra, A.Sinha, “A Single Digit Triple Base Number System – A New Concept for

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DESIGN OF AN EFFICIENT MULTIPLIER UNIT USING DBNS Implementing High Performance Multiplier Unit for DSP Applications”, Proceedings of the sixth International Conference on Information , Communication and Signal Processing(ICICS2007), December, 10‐13,2007. [16] S.Maitra,A.Sinha, “Architecture of Mixed Radix Number System –A New Approach of Designing Digital Filter”, proceedings of the 10th IASTED International Conference on Signal and Image Processing(SIP2008), August, 18‐20,2008, Kailua‐Kona,HI,U.S.A. [17] Doche, C., Habsieger, L., A Tree‐Based Approach for Computing Double‐Base Chains, in: Y. Mu, W. Susilo and J. Seberry(Eds.), ACISP 2008, LNCS 5107, PP. 433‐446, 2008, Springer‐ Verlag Berlin Heidelberg 2008.

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