INTERNATIONAL ASSOCIATION OF ENGINEERING & TECHNOLOGY
ISBN NO : 378 - 26 - 138420 - 8
Design and Analysis of Low-Leakage High-Speed Domino Circuit for Wide Fan-In OR Gates. M.Chennakeshavulu1, K.Subramanyam2 Associate Professor, ECE, RGMCET, JNTUA, Nandyal, A.P, India
1
1Onlinechenna@yahoo.com
M.Tech Student, ECE, RGMCET, JNTUA, Nandyal, A.P, India
2
2Subbuking987@gmail.com
Abstract--Domino CMOS logic circuit relations finds a broad variety of applications in microprocessors, digital signal processors, and dynamic memory owing to their high speed and low device count. In this paper a new domino circuit is studied, which has a lower leakage and higher noise immunity, lacking dramatic speed degradation for wide fan-in gates. The system which is utilized in this paper is based on comparison of Power, Propagation Delay, Energy, and Energy Delay Propagation. The studied circuit technique decreases the parasitic capacitance on the dynamic node, yielding a smaller keeper for wide fan-in gates for the fast and robust circuits. Thus, the disputation current and consequently power consumption and delay are reduced. The leakage current is also decreased by exploiting the footer transistor in diode configuration, which results in increased noise immunity. This the studied technique is applying in 90nm, 130nm, and 180nm technology using TANNER tools. Index Terms: Domino logic,leakage-tolerant, noise immunity and wide fan-in. Fig. 1. Standard Footless Domino circuit.
I.INTRODUCTION CMOS gates are mostly designed using static logic and dynamic logic. DYNAMIC logic such as domino
As a result, it is complex to get satisfactory robustness– performance tradeoffs. In this paper comparison-based domino (CCD) circuits for wide fan-in applications in ultra deep sub micrometer technologies are studied. The originality of the studied circuits is concurrently increases performance and decreases leakage power consumption. In this paper we are studied High speed Domino circuits for wide(4,8,16) FAN –IN applications. The most well-liked dynamic logic is the conventional standard domino circuit as shown in Fig. 1. In this design, a pMOS keeper transistor is working to stop any undesired discharging at the dynamic node due to the leakage currents and charge distribution of the pull-down network in the evaluation phase .Hence
logic is widely used in lots of applications to get high performance, which cannot be get with static logic styles [1].But, the major drawback of dynamic logic families is that they are more sensitive to noise than static logic families. When the technology scales down, the supply voltage is reduced for low power, and the threshold voltage (Vth) is also scaled down to reach high performance. while reducing the threshold voltage exponentially increases the subthreshold leakage current, drop of leakage current and improving noise immunity are of main concern in robust and highperformance designs in recent technology generations, especially for wide fan-in dynamic gates [2], robustness and performance significantly degrade with increasing leakage current.
improving the robustness by using keeper transistor. The keeper ratio K is defined as K =
(1)
Where W and L denote the transistor size, and μn and μp are the electron and hole mobilities.Even if the
1 International Conference on Advancements in Engineering Research 26
www.iaetsd.in
INTERNATIONAL ASSOCIATION OF ENGINEERING & TECHNOLOGY
ISBN NO : 378 - 26 - 138420 - 8
keeper upsizing improves noise immunity it increases current contention between the keeper transistor and the evaluation network. Thus, it increases power consumption and evaluation delay of standard domino circuits. These problems are graver in wide fan-in dynamic gates due to the huge number of leaky nMOS transistors connected to the dynamic node. Hence, there is a tradeoff between robustness and performance, and the number of pull-down legs is limited. The existing techniques try to compromise one feature to gain at the expense of the other. Several circuit techniques are studied. These circuit techniques can be divided into 2 categories. In the 1st category, circuit techniques to modify the controlling circuit of the gate voltage of the keeper such as 1.Standrad Footless Domino(SFLD)[1], 2. Conditional-Keeper Domino (CKD)[3] 3. High-Speed Domino (HSD) [4],, 4. Leakage Current Replica (LCR) Keeper Domino [5], & 5. Controlled Keeper by Current-Comparison Domino (CKCCD) [6]. And the 2nd category, designs including the designs to vary the circuit topology of the footer transistor in the evaluation network such as 6. Diode Footed Domino (DFD) [2] and 7. Diode-Partitioned Domino (DPD)[7] These 2 category techniques are explained in given bellow.
larger keeper. The increase in size of delay element improves noise immunity but power dissipation and delay increases. 3. High-Speed Domino (HSD) : Here delay is introduced in clock by using two inverters as shown in Fig.3, in arrange to reduce the current during the PMOS keeper at the initial of evaluation phase which leads to reduce the power dissipation up to some extent. This makes it probable to use physically powerful keeper without performance degradation and improve the noise margin. Other than the power and area overhead of clock delay circuit remains. In precharge phase, when clock becomes LOW, transistor Mp1 turns ON and dynamic node is charged to logic HIGH and in the start of evaluation phase, Mp2 still turns ON which keeps the keeper transistor Mk to OFF condition. After delay completion Mp2 turns OFF.
2. Conditional-Keeper Domino (CKD): It is one of the standard versions of domino logic as shown in Fig.2. Here 2 keeper transistors are used. At the commencement of evaluation phase, the minor keeper K2 charges the dynamic node in case if all the inputs are LOW. Then after delay end, if dynamic node still remains charged, the NAND gate turns the better keeper transistor ON to stay the dynamic node HIGH for the rest of evaluation phase. If the dynamic node has discharged, the keeper transistors remain OFF.
Fig.3 High speed Domino (HSD)[3]
In connecting this, the inputs make the logic function as well as in case if input(s) are logic HIGH then provides discharge path for dynamic node and output changes to logic HIGH and Mk is in OFF condition as a logic high as (VDD-Vtn) voltage, where Vtn is NMOS threshold voltage, is passed to Mk which does not turn it into ON state. And if no input is HIGH then dynamic node is not discharged and output is still LOW. So Mn1 turns ON and pass logic LOW to Mk which turns it ON and dynamic node is kept at logic HIGH. In this way, keeper transistor prevents charge leakage in High speed domino logic. The difficulty with high speed domino logic (HSD) is that a voltage of VDD - Vtn is accepted through the NMOS transistor Mn1 which leads to a small dc current through the keeper transistor and pulldown network and also large noise at input terminals of PDN causes the dynamic node discharge because of no footer transistor. 4. Leakage Current Replica (LCR) Keeper Dom In LCR Keeper domino circuit the transistor size is varied as shown in Fig.4, the mirror transistor M1 is set to 7Lmin to reduce channel length modulation and reduce variation of the threshold voltage. The width of transistor M2 is same to the sum of the widths of the nMOS transistors of the PDN. The width of the keeper transistors of the gates, which are simulated using the LCR keeper, are varied to get the desired delay.
Fig.2 Conditional Keeper Domino [3]
This circuit has a few drawbacks such as decreasing delay of the inverters and the NAND gate has a few restrictions. Robustness can be achieved by using the
2 International Conference on Advancements in Engineering Research 27
www.iaetsd.in
INTERNATIONAL ASSOCIATION OF ENGINEERING & TECHNOLOGY
ISBN NO : 378 - 26 - 138420 - 8
6. Diode Footed Domino (DFD): Diode-footed domino [12] is reduced leakage current, enhanced performance and better strength as shown in fig.6 . In this circuit,M1 is the diode footer, which is in sequence with the evaluation network. Leakage current is reduced by M1 due to the stacking effect. Also M1 increases the switching threshold voltage of the gate and there by improves noise immunity. The mirror transistor and current feedback improve the robustness of the circuit against sub-threshold leakage and input noise in the deep submicron range.
Fig.4 Leakage Current Replica Domino [5]
5. Controlled Keeper by Current-Comparison Domino (CKCCD): The reference circuit [12] of the leakage current consists of transistors M5, M6, M7 and M8. The transistor M5 is off inactive mode and will be on in standby mode to decrease standby power. The size of the mirror transistor M3 is selected based on the leakage of the pull down transistors. The mirror current should be greater than the pull down leakage and minor than the lowest PDN discharge, current with at least one in put at the high logic level to make sure correct operation. Since the reference circuit is a replica circuit of the PDN, the reference current varied switch temperature presently similar to the PDN leakage current. Thus, the design is almost insensitive to temperature variations.
Fig6. Diode Footed Domino[2]
7. Diode-Partitioned Domino (DPD): In the DPD according to [7] each partition Consists of 4 legs to get the most excellent results as shown in fig.7. All inverters and keepers of the partitions are set to least size and the length of the major keeper transistor MK . The desired delay is achieved by varying the size of the precharge and keeper transistors.
Fig.5 Controlled Keeper by Current-Comparison Domino[6] Fig.7 Diode-Partitioned Domino
3 International Conference on Advancements in Engineering Research 28
www.iaetsd.in
INTERNATIONAL ASSOCIATION OF ENGINEERING & TECHNOLOGY
ISBN NO : 378 - 26 - 138420 - 8
8.Wide FAN-IN or gate Current comparision comparision Domino: This circuit is similar to a replica leakage circuit [7], in which a series diode-connection transistor M6 similar to M1 is added. In fact, as shown in Fig.8,.The circuit has five extra transistors and a shared reference circuit compared to standard footless domino (SFLD).
MEval are off. Also, the output voltage is raised to the high level by the output inverter. B. Evaluation Phase: In this phase, clock voltage is in the high level [CLK = “1”, CLK = “0” in Fig. 8] and input signals can be in the low level. Therefore, transistors Mpre and MDis are off, transistor M1, M2, Mk2, and MEval are on, and transistor Mk1 can become on or off depending on input voltages. Thus, two states may occur. First, all of the input signals remain high. Second, at least one input falls to the low level. In the first state, a little amount of voltage is established across transistor M1 due to the leakage current. Even if this leakage current is mirrored by transistor M2, the keeper transistors of the second stage (Mk1 and Mk2) compensate this mirrored leakage current. It is obvious that upsizing the transistor M1 and increasing the mirror ratio (M) increase the speed due to higher mirrored current at the expense of noiseimmunity degradation. In the second state, when at least one conduction path exists, the pull-up current flow is raised and the voltage of node A is decreased to nonzero voltage, which is equal to gate-source voltage of the saturated transistor M1.
Fig 8.Wide FAN-IN or gate Current comparision comparision Domino
The circuit can be well thought-out as two stages. The first stage reevaluation network includes the PUN and transistors MPre,MEval, and M1.The PUN.The second stage looks like a footless domino with one input [node A in fig5],without any charge sharing, one transistor M2 regardless of the Boolean function in the PUN,and a controlled keeper consists of two transistors. Only one pull-up transistor is connected to the dynamic node instead of the n-transistor in the n-bit OR gate to decrease capacitance on the dynamic node, yielding a higher speed. The input signal of the second stage is prepared by the first stage. In the evaluation phase, thus, the dynamic power consumption consists of two parts: one part for the first stage and the other for the second stage. A. Predischarge Phase: Input signals and clock voltage are in high and low levels, correspondingly, [CLK = “0”, CLK = “1” in Fig.8] in this phase. Then, the voltages of the dynamic node (Dyn) and node A have fallen to the low level by transistor MDis and raised to the high level by transistor Mpre, in that order. Hence, transistors Mpre, MDis, Mk1, and Mk2 are on and transistors M1, M2, and
9. SIMULATION RESULTS AND COMPARISONS These circuits are simulated using TANNER Tools TSPICE in the high-performance 180 nm, 130nm, and 90nm predictive technology. The supply voltage used in the simulations is 2 V in the wide fan-in (4, 8, 16, input)
OR-gate,circuit.The simulated dynamic circuits results of Power,Delay,Energy,Energy Delay Propagation as shown in given tables
4 International Conference on Advancements in Engineering Research 29
www.iaetsd.in
INTERNATIONAL ASSOCIATION OF ENGINEERING & TECHNOLOGY
ISBN NO : 378 - 26 - 138420 - 8
TABLE-I Comparisons of power, delay, energy, E.D.P of SFLD Wide FAN-IN Gates(4,8,16 in puts)
IN PUTS 4 in
8 in 16in
180nm
130nm Propaga tion Delay
Energy
E.D.P
3.5x -4 10 w
31ns
10.8x -13 10
3363.5 x10-22
3.43X 10-4w 3.52X 10-4w
31n
106x 10-13 109x 10-13
3296x 10-22 3382x 10-22
Averag e
Power
31n
90nm Propaga tion Delay
Energy
E.D.P
A.P
P.D
Ener gy
E.D.P
4.7x 10-4w
31ns
145.7x 10-13
4516x 10-22
6x 10-4w
30n
36x 10-13
1080x 10-22
4.59x 10-4w 4.6x 10-4w
31n
142.2x 10-13 142.6x 10-13
4410x 10-22 4420x 10-22
6.38x 10-4w 6.69x 10-4w
30n
191x 10-13 207x 10-13
5742x 10-22 6429x 10-22
Averag e
Power
31n
31n
TABLE-II Comparisons of power, delay, energy, E.D.P of CKD Wide FAN-IN Gates (4, 8, 16 in puts)
IN PUT
180nm Average
4 in
8 in 16 in
Power
1.34X 10-4w 1.3X 10-3w 1.17X 10-3w
130nm Propag ation Delay
Energy
31n
41.5x 10-13 39x 10-12 36.2x 10-12
30n 31n
E.D.P
Average
1287x 10-22 1170x 10-21 1124x 10-21
1.6x 10-3w 1.67x 10-3w 1.53x 10-3w
90nm
power
Propaga tion Delay
Energy
E.D.P
A.P
P.D
Energy
E.D.P
31n
49.6x 10-12 50.1x 10-12 47.4x 10-12
1537x 10-21 1503x 10-22 1470x 10-21
9.6x 10-3w 6.38x 10-4w 2.13x 10-3w
30n
288x 10-12 191x 10-13 63.9x 10-12
8640x 10-21 5742x 10-22 1917x 10-21
30n 31n
30n 30n
TABLE-III Comparisons of power, delay, energy, E.D.P of HSD Wide FAN-IN Gates (4, 8, 16 in puts)
IN PUT 4in
8in 16in
180nm
130nm
90nm
Average Power
Propaga tion Delay
Energy
E.D.P
Average power
Propaga tion Delay
Energy
E.D.P
A.P
P.D
Energy
E.D.P
3.6x 10-4w 3.59X 10-4w 3.65X 10-4w
31n
111.6x 10-13 111x 10-13 113x 10-13
3459x 10-22 3449x 10-22 3507x 10-22
4.65x 10-4w 4.69x 10-4w 4.73x 10-4w
31n
144x 10-13 145.3x 10-13 146.6x 10-13
4468x 10-22 4507x 10-22 4545x 10-22
6.5x 10-4w 6.5x 10-4w 6.77x 10-4w
30 n 30 n 30 n
195x 10-13 195x 10-13 203x 10-13
5850x 10-22 5850x 10-22 6093x 10-22
31n 31n
31n 31n
5 International Conference on Advancements in Engineering Research 30
www.iaetsd.in
INTERNATIONAL ASSOCIATION OF ENGINEERING & TECHNOLOGY
ISBN NO : 378 - 26 - 138420 - 8
TABLE-IV Comparisons of power, delay, energy, E.D.P of LCR Keeper Wide FAN-IN Gates (4, 8, 16 in puts)
IN PUT
180nm Propaga tion Delay
Energy
3.51x 10-4w 3.52X 10-4w
31n
3.57X 10-4w
31n
Average 4 in
8 in
16 in
130nm
Power
31n
90nm Propaga tion Delay
Energy
E.D.P
A.P
P.D
Energy
E.D.P
4.5x 10-4w 4.60x 10-4w
31n
4309x 10-22 4420x 10-22
6.37x 10-4w 6.37x 10-4w
30 n 30 n
191x 10-13 191x 10-13
5733x 10-22 5733x 10-22
4.64x 10-4w
31n
139x 10-13 142.6 x 10-13 143.8 x 10-13
4459x 10-22
6.62x 10-4w
31 n
205x 10-13
6361x 10-22
E.D.P
Average
108x 10-13 109x 10-13
3373x 10-22 3382x 10-22
110x 10-13
3430x 10-22
Power
31n
TABLE-V Comparisons of power, delay, energy, E.D.P of CKCCD Wide FAN-IN Gates (4, 8, 16 in puts)
IN PUT
180nm
130nm Propag ation Delay
Energy
2.3x 10-4w
30n
8 in
2.41X 10-4w
16 in
2.46X 10-4w
Average
4 in
Power
90nm Propaga tion Delay
Energy
E.D.P
A.P
P.D
Energy
E.D.P
3.2x 10-4w
31n
99.2x 10-13
3075x 10-22
6.06x 10-4w
30n
181x 10-13
5454x 10-22
2316x 10-22
3.19x 10-4w
31n
3065x 10-22
114x 10-13
3536x 10-22
3.2x 10-4w
31n
3065 x 10-22 3.7x 10-4w
31n
2364x 10-22
98.89 x 10-13 99.2x 10-13
31n
114x 10-13
3555x 10-22
E.D.P
Average
69x 10-13
2070x 10-22
31n
74.7x 10-13
31n
76.2x 10-13
power
3075x 10-22
TABLE-VI Comparisons of power, delay, energy, E.D.P of DFD Wide FAN-IN Gates (4, 8, 16 in puts)
IN PUT
180nm Average
4 in
8 in 16 in
Power
3.54X 10-4w 3.67X 10-4w 3.71X 10-4w
130nm Propag ation Delay
Energy
30n
106x 10-13 113x 10-13 115x 10-13
31n 31n
E.D.P
Average
3186x 10-22 3526x 10-22 3565x 10-22
4.71x 10-4w 4.79x 10-4w 4.86x 10-4w
power
90nm Propaga tion Delay
Energy
E.D.P
A.P
P.D
Energy
E.D.P
30n
141.1x 10-13 148.4x 10-13 150.5x 10-13
4239x 10-22 4603x 10-22 4670x 10-22
6.07x 10-4w 5.84x 10-4w 6.02x 10-4w
30 n 30 n 30 n
182x 10-13 175x 10-13 180x 10-13
5463x 10-22 5256x 10-22 5400x 10-22
31n 31n
6 International Conference on Advancements in Engineering Research 31
www.iaetsd.in
INTERNATIONAL ASSOCIATION OF ENGINEERING & TECHNOLOGY
ISBN NO : 378 - 26 - 138420 - 8
TABLE-VII Comparisons of power, delay, energy, E.D.P of DPD Wide FAN-IN Gates(4,8,16 in puts)
IN PUT
180nm Average
4 in
8 in 16 in
Power
3.70X 10-4w 3.67X 10-4w 3.66X 10-4w
130nm Propag ation Delay
Energy
30n
111x 10-13 113x 10-13 113x 10-13
31n 31n
E.D.P
Average
3330x 10-22 3526x 10-22 3517x 10-22
6.12x 10-4w 4.79x 10-4w 6.42x 10-4w
90nm
power
Propaga tion Delay
Energy
E.D.P
A.P
P.D
Energy
E.D.P
30n
183.6x 10-13 148.4x 10-13 192.6x 10-13
5508x 10-22 4603x 10-22 5778x 10-22
6.16x 10-4w 5.84x 10-4w 6.0x 10-4w
30 n 30 n 30 n
184x 10-13 175x 10-13 180x 10-13
5544x 10-22 5256x 10-22 5400x 10-22
31n 30n
TABLE-VIII Comparisons of power, delay, energy, E.D.P of CCD Wide FAN-IN Gates (4,8,16 in puts)
IN PUT
180nm Average
4 in
8 in 16 in
Power
1.07X 10-4w 8.34X 10-4w 0.92X 10-4w
130nm Propag ation Delay
Energy
1.53 n 1.29 n 12n
1.63x 10-13 10.7x 10-13 132x 10-22
E.D.P
Average
2.50x 10-22 13.8x 10-22 132x 10-22
2.25x 10-4w 1.39x 10-4w 1.57x 10-4w
90nm
power
Propaga tion Delay
Energy
E.D.P
A.P
P.D
Energy
E.D.P
0.9n
20.25x 10-13 1.807x 10-13 1.86x 10-13
18.2x 10-22 2.34x 10-22 2.22x 10-22
4.19x 10-4w 2.3x 10-4w 2.5x 10-4w
0.3 n 0.1 n 83 n
1.25x 10-13 0.23x 10-13 207x 10-13
0.3771x 10-22 0.023x 10-22 1722x 10-22
1.3n 1.19 n
4 3 2 1 0
4 in 8 in 16 in SFLD
CKD
HSD
LCR keeper
CKCCD
DFD
DPD
CCD
Fig.9. Comparison of power supply with same delay
10. CONCLUSION: The leakage current of the evaluation network of dynamic gates was considerably increased with technology scaling, particularly in wide domino gates, yielding reduced noise immunity and improved power consumption. So, new designs were required to get preferred noise robustness in wide fan-in circuits. Also, rising the fan-in not only reduced the worst case delay.
The main aim is to make the domino circuits extra robust and with low leakage without significant performance degradation or increased power consumption. This was done by comparing the evaluation current of the gate with the leakage current. Keeper size of very high fan-in gates. Using the highperformance 180 nm [3] at a power supply of 2 V, wide
7 International Conference on Advancements in Engineering Research 32
www.iaetsd.in
INTERNATIONAL ASSOCIATION OF ENGINEERING & TECHNOLOGY
ISBN NO : 378 - 26 - 138420 - 8
fan-in 4 to 16-bit OR gate circuit. The proposed design plus several existing circuit designs were simulated and compared, imulation results verified significant progress in leakage reduction and satisfactory speed for high-speed applications. moreover, they verified that. Thus, the CCD was above all suitable for implementing wide fan-in Boolean logic functions with high noise
immunity, lower area consumption, time delay, Energy, Energy, Delay Propagation and power consumption. Moreover, a normalized FOM, previously proposed by the authors, was modified to include standard deviation of delay.
REFERENCES: [1] J. M. Rabaey, A. Chandrakasan, and B. Nicolic, Digital Integrated Circuits: A Design Perspective, 2nd ed. Upper Saddle River, NJ:Prentice-Hall, 2003. [2] H. Mahmoodi and K. Roy, “Diode-footed domino: A leakage-tolerant high fan-in dynamic circuit design style,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 3, pp. 495–503, Mar. 2004. [3] Sumit Sharma “ A Novell High-speed low-power domino logic technique for static output in evaluation phase for high frequency inputs” IJERA march 2014.. [4] M. H. Anis, M. W. Allam, and M. I. Elmasry, “Energyefficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies,” IEEE Trans. Very Large Scale (VLSI) Syst., vol. 10, no. 2, pp. 71–78, Apr. 2002. [5] Y. Lih, N. Tzartzanis, and W. W. Walker, “A leakage current replica keeper for dynamic circuits,” IEEE J. Solid-State Circuits, vol. 42, no. 1,pp. 48–55, Jan. 2007. [6] A. Peiravi and M. Asyaei, “Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates, integration,” VLSI J., vol. 45, no. 1, pp. 22–32, 2012. [7] H. Suzuki, C. H. Kim, and K. Roy, “Fast tag comparator using diode partitioned domino for 64-bit microprocessors,” IEEE Trans. Circuits Syst., vol. 54, no. 2, pp. 322–328, Feb. 2007. [8] K. Roy, S. Mukhopadhyay, and H. MahmoodiMeimand, “Leakage current mechanisms and leakage reduction techniques in deep sub micrometer CMOS circuits,” Proc. IEEE, vol. 91, no. 2, pp. 305–327,Feb. 2003. [9] N. Shanbhag, K. Soumyanath, and S. Martin, “Reliable low-power design in the presence of deep submicron noise,” in Proc. ISLPED, 2000, pp. 295–302. [10] M. Alioto, G. Palumbo, and M. Pennisi, “Understanding the effect of process variations on the delay of static and domino logic,” IEEE Trans. Very Large Scale (VLSI) Syst., vol. 18, no. 5, pp. 697–710, May 2010. [11] H. Mostafa, M. Anis, and M. Elmasry, “Novel timing yield improvement circuits for high-performance lowpower wide fan-in dynamic OR gates,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 10, pp. 1785– 1797, Aug. 2011. [12] Ali Peiravi , Mohammad Asyaei “CurrentComparison-Based Domino: New Low-Leakage HighSpeed Domino Circuit for Wide Fan-In Gates” VOL. 21, NO. 5, MAY 2013
M.CHENNAKESAVALU, He completed B.Tech in 2003 at JNTUHyderabadand He completed M.Tech in 2010 at JNTUAnantapur.He got lecturership in UGCNET-2013.He has 10 years of teaching experience. He is working as ASSOC.professor in Dept of ECE, in RGMCET,Nandyal. He published Nearly12 papers in Various publication. His research areas are low power VLSI design and interconnects in NOC.He has professional memberships in MIETE. He guided 5 projects at master level.
K.SUBRAMANYAM received the B.E degree in electronics and communications engineering from the JNT University of Anantapur in 2008 to 2012. He is currently pursuing the M.E. degree in digital systems and computer electronics engineering from the JNT University of Anantapur. His current research interests include low-power, high-performance, and robust circuit design for deep-sub micrometer CMOS technologies.
8 International Conference on Advancements in Engineering Research 33
www.iaetsd.in