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DESIGN OF AN OPTIMISED LOW POWER FULL ADDER USING DOUBLE GATED MOSFET AT 45nm TECHNOLOGY T Nithyoosha1, M.Rajeswara Rao2 1
P.G Student in VLSI, Department of E.C.E, SIETK, Tirupati. 2 Assistant Professor, Department of E.C.E, SIETK, Tirupati. E-Mail to:nithyoosha705@gmail.com, raj_vlsi@yahoo.co.in
Abstract— Full adder performs addition in many computers and other processors. The performance of digital electronics circuit can be improved by improving the performance of the adder where adder is employed. A 10T double gated full adder is a choice for low power design. It achieves 31.25% reduction in active power and 95% reduction in leakage current as compared to 14T double gate full adder. The leakage current, average power and Delay is also calculated for the designed 10T and 14T full adder. Double Gate (DG) MOSFETs using lightly doped ultra thin layers seem to be a very promising option for ultimate scaling of CMOS technology Excellent short-channel effect immunity, high transconductance and ideal subthreshold factor have been reported by many theoretical and experimental studies on this device. Index Terms—Double gate MOSFET, full adder, leakage current, active power and delay.
1. INTRODUCTION
Cout = AB + A ⊕ B Cin
A B
(3)
s
Cin
Cout
Fig.1. Block Diagram of basic full adder circuit
2.1 DOUBLE GATE 14T FULL ADDER CIRCUIT
In very large scale integration (VLSI) systems, full adder circuit is used in arithmetic operations for addition, multipliers and Arithmetic Logic Unit (ALU). It is a building block of the application of VLSI, digital signal processing, image processing and microprocessors. Most of full adder systems are considered performance of circuits, number of transistor, speed of circuit, chip area, threshold loss and full swing output and the most important is power consumption. In the future, portable devices such as cell phone, laptop computer, tablet etc. need low power and high speed full adders.
Double gate MOSFET will be constructed by connecting two transistors in parallel as a way that their supply and drain are connected together. Double gate MOSFET can be classified in two types, based on biasing of gate. Once the front and back gate area unit connected along, initial kind is achieved and it is referred as three terminal devices. This device is used for direct replacement of single gate transistor. Second kind is achieved by independent gate control. In this section single bit full adder circuit is designed by using double gate MOSFET for improve the performance of adder in terms of power and leakage using 14 transistors.
The power consumption for CMOS circuit is given by the following equation: Pavg = Pdynamic + Pleak + Pshort-circuit =CLVdd VFclk + IleakVdd +IscVdd
(1)
Lowering the supply voltage would significantly lower the power consumption of the circuit. This basic concept of would be used to improve the performance of adder circuit. 2. FULL ADDER Full adder circuit is designed for addition binary logics. Sum signal (SUM) and carry out signal (Cout) are the output of I-bit full adder. Both of them are generated by input A, B and CIN, following Boolean equation as: SUM = A ⊕ B ⊕ Cin
(2)
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INTERNATIONAL CONFERENCE ON DEVELOPMENTS IN ENGINEERING RESEARCH, ICDER - 2014
Fig.4. Output waveform of double gate 14T full adder 2.2 DOUBLE GATE 10T FULL ADDER CIRUIT Fig.2. Schematic of 4T XOR This cell is constructed by using the 4T XOR gate. In the 14T full adder cell two 4T XOR gate are used. Fig3 shows the double gate 14T full adder circuit .Here 4T XOR is used gate to increase circuit density using this XOR gate, reduction in size of full adder is achieved and overall leakage is also reduced. Output waveform of 14T full adder is shown in fig.4
In this section one bit full adder circuit is presented by using double gate transistors for improve the performance of adder in terms of power and leakage. Fig5 shows the double gate 10T full adder circuit. This cell is made by using the 4T XOR gate. It is the essential component of full adder cell and generates the essential addition operation of adder cell. It behaves like a single half adder cell. Here 4T XOR gate is used to increase circuit density. Fig.2 shows the 4T XOR gate. Using this XOR gate, reduction in size of full adder is achieved and overall leakage is also reduced. The schematic of full adder is shown in fig.5 and output waveform is shown in fig.6.10T double gate full adder achieves 31.25% reduction in active power and 95% reduction in leakage current as compared to 14T double gate full adder.
Cout
A
B
Sum
Fig.3. Double gate 14T full adder C
Fig.5. Double gate 10T full adder
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INTERNATIONAL CONFERENCE ON DEVELOPMENTS IN ENGINEERING RESEARCH, ICDER - 2014
4. SIMULATION AND RESULT A single bit full adder circuit based on double gate MOSFET technique is proposed. It is used for measurement of leakage, power consumption and delay of the proposed circuit at 45nm technology with different supply voltage from 0.7v to 1.0v.
Fig.6. Output waveform of double gate 10T full adder 3. DOUBLE GATE MOSFET The MOS transistor model from COMSOL as a template is used to model the double gate MOSFET. Double gate transistors are developed to resolve short channel effect problems in actual MOSFET structures. So that such architectures are directly related to the constant Reduction of the feature size in microelectronic technology. At the present time, it seems that double gate devices- going to non-planar transistor. Architectures- could be a solution for sub-32nm Nodes. In addition, new design flexibility is allowed when gates are not interconnected. However, appropriate models must be developed. Threshold voltage (Vth) modeling of double gate (DG) MOSFETs was performed, for the first time, by considering barrier lowering in the short channel devices. As the gate length of DG MOSFETs scales down, the overlapped charge-sharing length (xh) in the channel which is related to the barrier lowering becomes very important. A fitting parameter δw was introduced semiempirically with the fin body width and body doping concentration for higher accuracy. The Vth model predicted well the Vth behavior with fin body thickness, body doping concentration, and gate length. Recently, bulk FinFETs have been considering very promising candidate for next generation memory cell transistors to be applicable to dynamic random access memory (DRAM) and flash memory. As the gate length of bulk FinFETs scales down, barrier lowering occurs in spite of low drain bias (VDS =0.05V) because the depleted charge-sharing length (xh) by source and drain in short channel is overlapped. To apply the devices to integrated circuits, it is strongly required to model threshold voltage (Vth) considering the barrier lowering in short channel. However, the Vth model has not been developed since the xh modeling in short channel devices is very complicated with device geometry and doping concentration. For Vth modeling of the devices, double-gate (DG) nature is key point and needs to be understood well. In this paper, we propose Vth model of DG MOSFETs based on the correction of xh considering barrier lowering, and verify the Vth model by comparing with device simulation in terms of gate length (Lg), fin width (Wfin) and body doping (Nb). Threshold voltages were extracted by using gm,max for a given VDS of 0.05 V in this paper.
4.1. LEAKAGE CURRENT Leakage current is the current that flows through the protective ground conductor to ground. In the absence of a grounding connection, it is the current that could flow from any conductive part or the surface of non-conductive parts to ground if a conductive path was available (such as a human body). There are always extraneous currents flowing in the safety ground conductor. Tunnelling leakage can also occur across junctions between heavily doped p-type and n-type. The basic equation of leakage current is shown in Eq.4 Ileak = Isub + Iox
(4)
Where, Isub = sub-threshold leakage current, Iox = gate-oxide leakage current.
Where, K1 and n are experimentally derived, W = gate width, Vth = threshold voltage, n = slope shape factor, Vθ = thermal voltage.
Where, K2 and α are derived experimentally, Tox = oxide thickness. Table 1 shows the leakage current of 10T and 14T full adder cell using double gate MOSFET at different supply voltage. Fig 7 and fig 8 shows the leakage current waveform of double gate 14T and 10T full adder cell at 0.7V. Table 1. Leakage current at difference voltages of 10t and 14t full adder Voltage 10T Full Adder (pA) 14T Full Adder (pA) 0.7
3.646
58.2
0.8
3.915
84.6
0.9
5.165
144
1.0
5.401
220
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INTERNATIONAL CONFERENCE ON DEVELOPMENTS IN ENGINEERING RESEARCH, ICDER - 2014 Fig.8. Leakage Current Waveform of Double Gate 10T Full Adder at 0.7V 4.2 ACTIVE POWER At the time of operating the power is dissipated by the circuit is known as active power. Active power includes both static power and dynamic power of the circuit. The basic equation of active power is shown in Eq. (7)
Pactive = Pdyanamic + Pstatic
(7)
=Pswitching + Pshort-circuit + Pleakage
Where, Cl = load capacitance, fclk = clock frequency, α = switching activity, Isc = short circuit current, Ileakage = leakage current, Vdd = supply voltage Table 2. Active power at difference voltages of 14t full adder Voltage 10T Full Adder(µW) 14T Full Adder (µW) Fig.7. Leakage Current Waveform of Double Gate 14T Full Adder at 0.7V There are two types of leakage current: ac leakage and dc leakage. Dc leakage current usually applies only to end-product equipment, not to power supplies. Ac leakage current is caused by a parallel combination of capacitance and dc resistance between a voltage source (ac line) and the grounded conductive parts of the equipment. The leakage caused by the dc resistance usually is insignificant compared to the ac impedance of various parallel capacitances.
0.7
9.34
13.7
0.8
15.21
23.56
0.9
21.95
39.69
1
29.61
61.52
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INTERNATIONAL CONFERENCE ON DEVELOPMENTS IN ENGINEERING RESEARCH, ICDER - 2014 Eq. (9) the propagation delay for an integrated circuit (IC) logic gate may differ for each of the inputs. If all other factors are held constant, the average propagation delay in a logic gate IC increases as the complexity of the internal circuitry increases.
Some IC technologies have inherently longer tpd values than others, and are considered "slower." Propagation delay is important because it has a direct effect on the speed at which a digital device, such as a computer, can operate. This is true of memory chips as well as microprocessors.
Fig.9. Active Power Waveform of Double Gate 14T Full Adder at 0.7V
Fig.11.Delay Comparison Graph of 10T and 14T Full Adder Circuit.
Fig.10. Active Power Waveform of Double Gate 10T Full Adder at 0.7V
5. CONCLUSION The analysis carried out while analyzing both l0T and 14T full adders individually and comparing them on the basis of calculation of active power, leakage current and delay by varying different parameters. The outcomes of the simulation show that l0T full adder to be a better option with improved performance over 14T structure. As compare to 14T double gate full adder active power of 10T full adder is reduced from 13.7μW to 9.34 μW at 0.7V. As compare to 14T double gate full adder Leakage current of 10T full adder is reduced from 58.2pA to 3.646pA at 0.7V.As compare to 10T double gate full adder Delay of 14T double gate full adder is reduced from 171.3ps to 151ps.
Table 2 shows the active power of 10T and 14T full adder cell using double gate MOSFET at different supply voltage. Fig 9 and fig 10 shows the active power waveform of double gate 14T and 10T full adder cell at 0.7V.
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4.3 DELAY Propagation delay is required by a digital signal to travel from that input of the circuit to the output. The propagation delay is inversely proportional to the speed of the architecture and hence it is important performance parameter. The basic equation of delay in presence of sleep transistor is shown in
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INTERNATIONAL CONFERENCE ON DEVELOPMENTS IN ENGINEERING RESEARCH, ICDER - 2014 [3] Lu Junming; Shu Yan; Lin Zhenghui; Wang Ling," A Novel IO-transistor Low-power High-speed Full adder cell", Proceedings of 6th International Conference on Solid-State and Integrated-Circuit Technology, vol-2, pp. 1155-1158,2001. [4] Dan Wang, Maofeng Yang, Wu Cheng, Xuguang Guan, Zhangming Zhu, Yintang Yang, "Novel Low Power Full Adder Cells in 180nm CMOS Technology", 4th IEEE Conference on Industrial Electronics and Applications, ICIEA 2009, pp 430-433. [5] Adarsh Kumar Agrawal, Shivshankar Mishra, and R K. Nagaria, "Proposing a Novel Low-Power High-Speed Mixed GDI Full Adder Topology", accepted in Proceeding of IEEE International Conference on Power, Control and Embedded System (ICPCES), 28 Nov.-1 Dec. 2010. [6] Shipra Mishra, Shelendra Singh Tomar and Shyam Akashe, “Design low power 10T full adder using process and circuit techniques”, 7th IEEE International Conference on Intelligent Systems and Control(ISCO) Coimbatore 2013, pp. 325-328. [7] Mohammad Hossein Moaiyeri and Reza Faghih Mirzaee, Keivan Navi, 'Two New Low-Power and High-Performance Full Adders", Journal Of Computers, Vol. 4,N o. 2,February 2009. [8] Mariano Aguirre-Hernandez and Monico Linares-Aranda, "CMOS Full Adders for Energy-Efficient Arithmetic Applications", IEEE Transactions On Very Large Scale Integration (Vlsi) Systems, Vol. 19, No. 4, April 2011. [9] G.Shyam Kishore, Associate.Prof, ECE dept, JITS, Karimnagar, Andhra Pradesh, India, "A Novel Full Adder with High Speed Low Area", Proceedings published in International Journal of Computer Applications® (UCA) , 2nd National Conference on Information and Communication Technology (NCICT) 2011.
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