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FPGA Implementation of Fault Tolerant Embedded RAM using BISR Technique Swathi Karumuri, Suresh Chowdary Kavuri Dept., of VLSI and Embedded systems, Dept., of Electronics and Communication Engineering, JNTU Hyderabad, India swathisubadra@gmail.com kavurisureshchowdary@gmail.com Abstract-- Embedded memories with fault tolerant capability can effectively increase the yield. The main aim of this project is to design a fault tolerant memory which is capable of detecting stuck at faults and to repair them automatically. It uses BISR with redundancy scheme in order to achieve this. The architecture consists of a multiplexer (MUX), memory (circuit under test-CUT), Built in self test (BIST) module, Built in self diagnosis (BISD) module. Besides adding spare rows and columns user can select normal words as redundancy to repair the faults. So, it reduces the area. High repairing speed is possible with one to one mapping between faults and redundancy locations. It provides test mode and access mode to the RAM users. Many repairing schemes were implemented where repairing is not possible if the redundancy locations have faults. This proposed architecture shows the number of redundant locations and depending on that it has the advantage of repairing faults in redundancy locations also. The proposed model is simulated and synthesized using Xilinx and tested using Spartan3E development board.
time-saving and less cost compared to the ones controlled by the external tester (ATE) [8]. However, BIST doesn’t repair the faults. BISR techniques tests embedded memories, saves the fault addresses and replaces them with redundancy. [5] Presents multiple redundancies scheme and [9] proposes BISR strategy applying two serial redundancy analysis (RA) stages. All the previous BISR techniques have the ability to repair memories, but they can not avoid storing fault addresses more than once. [10] proposes a solution to this but it cannot repair redundant location faults. This paper proposed an efficient strategy that can repair redundancy faults also. The rest of the paper is organized as follows. Section II briefs different fault models, March algorithms and BIST. Section III introduces the proposed BISR technique. Section IV shows the experimental results. Section V concludes this paper. Section VI gives the future work. II.
Keywords-- Built in self diagnosis (BISD), Built in self repair (BISR), Built in self test (BIST), FPGA, VHDL.
I.
FAULT MODELS, MARCH ALGORITHMS AND BIST
A fault model is a systematic and precise representation of physical faults in a form suitable for simulation and test generation [11]. Different RAM faults are as follows and can be referred in [12]. AF: Address Fault ADOF: Address Decoder Open Faults CF: Coupling Faults DRF: Data Retention Faults SAF: Stuck-at Faults SOF: Stuck Open Faults TF: Transition Faults Memory test algorithms are two types where traditional tests are either simple, fast but have poor fault coverage or have good fault coverage but complex and slow. Due to this imbalance conflicts, the these algorithms are losing popularity. The details of these algorithms and comparison can be referred in [13]-[14]. An Efficient memory test should provide the best fault coverage in the shortest test time. March tests are the most common in use. They have good fault coverage and short test time. In order to verify whether a given memory cell is good, it is necessary to conduct a sequence of write(w) and read(r) operations to the cell. The actual number of read/write operations and the order of the operations depend on the target fault model. March element is a finite sequence of read/write operations applied to a cell in memory before processing the next cell. The next cell address can be ascending or descending in order. The comparison of different march algorithms are tabulated in Table I [15]. MarchC- algorithm has better fault
INTRODUCTION
With improvement in VLSI technology, more and more components are fabricated onto a single chip. It is estimated that the percentage of area occupied by embedded memories on an SOC is more than 65% and will rise up to 70% by 2017[1]. The increasing use of large embedded memories in SOCs require automatic reconfiguration to improve yield and performance. Memory fabrication yield is limited to manufacturing defects, alignment defects, assembly faults, random generated defect patterns, random leakage defects and other faults and defects [2]. To detect defects in a memory, many fault models and test algorithms have been developed [3]. Most of these algorithms have been in use. To increase the yield and efficiency of embedded memories, many redundancy mechanisms have been proposed in [4]-[7]. In [5]-[6] both redundant rows and columns are incorporated into the memory array. Repairing the memory by adding spare words, rows and columns into the word oriented memory core as redundancy is proposed in [7]. All these redundancy mechanisms increase the area and complexity in designing of embedded memories. A new redundancy mechanism is proposed in this paper in order to solve the problem. Some normal words in embedded memories can be considered as redundancy instead of adding extra rows and columns. It is necessary to test the memory before using redundancy mechanisms to repair the faults. In 1970’s, circuit under test is tested by external equipments called ATEs. BIST controlled DFT circuitry is more efficient,
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INTERNATIONAL CONFERENCE ON CURRENT INNOVATIONS IN ENGINEERING AND TECHNOLOGY
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coverage, less operations and less test length. It has 6 elements and 10 operations. So it is used in this paper to test the memory. The steps in MarchC- algorithm are as follows” TABLE I MARCH ALGORITHMS AND FAULT COVERAGE
1 up - W0 2 up – (R0, W1) 3 up – (R1, W0) 4 down – (R0, W1) 5 down – (R1, W0) 6 down - R0 In above steps, W represents write, R represents read, “up” represents executing RAM addresses in ascending order while “down” in descending order. Write0(1) represents writing 0(1)into the memory, read 0(1) represents expected data(0 or 1) from the memory in read operation. The BIST module contains a test pattern generator and an output response analyzer (ORA). MarchC- algorithm is used to generate the test patterns and a comparator is used as an ORA. The output from the memory in read operation is compared with expected data in the corresponding March element and indicates whether there are any faults in memory or not. It can also indicate if the memory test is done by activating test_done to 1. III.
A.
Fig. 1 Proposed Redundancy mechanism in RAM
redundancy limit it activates overflow signal. It shows the number of faults in redundant locations. When repairing is activated, faulty addresses are replaced with redundant addresses. MUX module controls the access between test mode and access/user mode. In test mode (test_h=1) BIST generates the inputs to the memory and in access mode (test_h=0) the inputs are equal to the system inputs or user inputs.
PROPOSED BISR TECHNIQUE
Proposed Redundancy Mechanism
The proposed architecture is flexible. Some normal words in RAM can be selected as redundancy if it needs to repair itself. To distinguish them from the normal ones we name these words as Normal-Redundant words. We take a 64x4 RAM as shown in Fig.1 as an example. There are 58 normal words and 6 Normal-Redundant words. When repairing is not used, the Normal-Redundant words are accessed as normal ones. The Normal-Redundant words can be accessed, when there are faults in normal words. This kind of selectable redundancy architecture can increase efficiency and save area. B.
Proposed BISR Architecture The architecture of Proposed BISR is shown in Fig.2. It consists of 3 parts named as BIST module, MUX module, and BISD module. BIST module produces test inputs to the memory using MarchC- algorithm. It detects the failures in memory by comparing RAM output data with expected data of MarchC- algorithm. compare_q=1 for faulty addresses. It asserts test _done to 1 when testing is completed. BISD module stores the faulty address in Fault_A_Mem. It maintains a counter to count the number of faulty addresses. When the count exceeds the maximum
Fig. 2 Architecture of proposed BISR
C.
Built in Self Repair Procedure Fig. 3 shows the flowchart for testing and repairing mechanism used. The BISR starts by resetting the system initially (rst_l=0).After that the system should be tested to find the faults in the memory. In this phase BIST and BISD modules works in parallel. BIST detects the fault address and it will be sent to the BISD. It checks it with already stored addresses .If
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the faulty address has not been stored it stores in Fault_A_Mem and the counter increments. It will be ignore otherwise. After the test phase there will be two conditions. If there are no faults or there are too many faults that overflows the redundancy capacity, BISR goes into COMPLETE phase. If there are faults in memory but without overflows then BISR goes into REPAIR and TEST phase. As in TEST phase, BIST and BISD works in parallel. BISD replaces the fault addresses with redundant ones. It can repair the faults in redundancy locations also. BIST module tests the memory again. There will be two results, repair pass or fail. Fig. 4 shows the storing and repairing fault addresses.
ISBN: 378 - 26 - 138420 - 5
but the fault addresses should not be stored thrice. So, one to one mapping is proposed in BISD module. Second feature is, BISR is flexible. In access mode user can decide whether to use repairing or not. If BISR, i.e. repairing is activated redundant locations are used for repairing .Table II shows the operating modes of RAM. Third feature is, it’s repairing speed is high. With one-one mapping it can replace the faulty location’s address with corresponding redundant address very quickly. TABLE II OPERATING MODES OF RAM
E. Proposed Repairing Mechanism to Repair Faults in Redundant Locations In order to repair the faults, there should not be any faults in redundant locations. After test phase Fault_A_Mem contains all the faulty addresses. If it contains all normal location faults, then the mapping shown in Fig. 4 works good. If the Fault_A_Mem contains redundant location addresses then mapping faulty address with corresponding faulty redundant location results in faulty output again. To solve this problem the repairing mechanism is modified slightly and is shown in Fig. 5 where there is one redundant and four normal faults.
Fig. 3 Flow chart of testing and repairing mechanism
Fig. 5 Mapping procedure in presence of redundant fault
Fault-address 3 is mapped with redundant address 5 as redundant address 3 is in Fault_A_Mem. Fig. 6 shows the flow chart. If there are redundant faults then the resultant redundant address should be checked in Fault_A_Mem .If there are any unmapped redundant locations, then mapping is done to that redundant location, if the new redundant location is fault free. If it is faulty again then next unmapped redundant location is considered and checking continuous until the new redundant location is fault free. Otherwise repairing fails.
Fig. 4 Flow of storing fault addresses & repairing mechanism
D.
BISR Features The first feature is, BISR is efficient. Normal redundant words can be used when repairing is not activated. It saves chip area. The fault addresses are stored only once. March algorithm has 6 steps. The address will be read five times in one test. Some faulty addresses will be detected mpore than one time. Take stuck-at-1 fault, it will be detected in 2nd, 4th and 6th steps
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Fig.7 Output showing repairing of redundant location faults(rounded), normal faults REFERENCES [1] Fig. 6 Flow chart for repairing redundant and normal faults IV.
[2]
EXPERIMENTAL RESULTS
The proposed BISR is simulated and synthesized using Xilinx and is checked on Spartan 3E FPGA kit. A stuck-at-0 and stuck-at-1 faults are set into the memory to verify the function. It is observed that in presence of faults, the data written into and data read from the faulty location is not same if repairing is not activated. Repairing is activated and is observed that the locations are repaired. It is also verified that the faults in redundant locations are repaired. Fig. 7 shows the output when redundant and normal faults are repaired.
[3] [4]
[5]
[6]
[7]
V. CONCLUSION
A fault tolerant embedded RAM using BISR technique has been presented in this paper. It uses selectable redundancy and is designed flexible such that user can select the operating modes. BISD module avoids storing the fault addresses more than once. The mechanism for repairing redundant locations faults has been proposed and is observed that it efficiently repairs the redundant faults along with normal faults.
[8] [9]
[10]
VI. FUTURE WORK The proposed architecture is mainly focused on stuck-at-faults in the memory using MarchC- algorithm. There are many fault models such as address decoder faults, transition faults etc; and there are different test algorithms. Therefore a future work can improve the proposed architecture to repair the above mentioned faults in the memory using different test algorithms.
[11]
[12] [13] [14] [15]
Farzad Zarrinfa “Optimizing embedded memory for the latest ASIC and SOC design” (2012) -chip design tools, technologies and methodologies by Mentor Graphics. C. Stapper, A. Mclaren, and M. Dreckman, “Yield model for Productivity Optimization of VLSI Memory Chips with redundancy and partially good Product,” IBM Journal of Research and Development, Vol. 24, No. 3, pp. 398-409, May 1980. Ad J.van de Goor, “Testing Semiconductor memories: Theory and Practice”, 1999, ISBN 90-80 4276-1-6 . P. Mazumder and Y. S. Jih, “A new built-in self-repair approach toVLSI memory yield enhancement by using neural type circuits,” IEEE transactions on Computer Aided Design, vol. 12, No. 1, Jan, 1993. W. K. Huang, Y. H. shen, and F. lombrardi, “New approaches for repairs of memories with redundancy by row/column deletion for yield enhancement,” IEEE Transactions on Computer-Aided Design, vol. 9,No. 3, pp. 323-328, Mar. 1990. H. C. Kim, D. S. Yi, J. Y. Park, and C. H. Cho, “A BISR (built-in self repair) circuit for embedded memory with multiple redundancies,” VLSI and CAD 6th International Conference, pp. 602-605, Oct. 1999. Shyue-Kung Lu, Chun-Lin Yang, and Han-Wen Lin, “Efficient BISR Techniques for Word-Oriented Embedded Memories with Hierarchical Redundancy,” IEEE ICIS-COMSAR, pp. 355-360, 2006. C. Stroud, “A Designer’s Guide to Built-In Self-Test”, Kluwer Academic Publishers, 2002. I.Kang, W. Jeong, and S. Kang, “High-efficiency memory BISR with two serial RA stages using spare memories,” IET Electron. Lett. vol. 44, no. 8, pp. 515-517, Apr. 2008. Huamin Cao, Ming Liu, Hong Chen, Xiang Zheng, Cong Wang and Zhihua Wang,” Efficient Built-in Self-Repair Strategy for Embedded SRAM with Selectable Redundancy”, Consumer Electronics, Communications and Networks (CECNet), 2012 2nd International Conference . M. Sachdev, V. Zieren, and P. Janssen, “Defect detection with transient current testing and its potential for deep submicron CMOS ICs,” IEEE International Test Conference, pp. 204-213, Oct. 1998. Mentor Graphics,”MBIST Architect Process Guide”,Software Version 8.2009_3, Aug 2009, pp. 113-116. Pinaki Mazumder, Kanad Chakraborty,”Testing and Testable Design of High-Density Random-Access Memories”. Vonkyoung kim and Tom Chen,”Assessing SRAM Test Coverage for Sub–Micron CMOS Technologies”,VLSI test symposium,1997,15th IEEE. L.Dharma Teja,K. Kiruthika and V. Priyanka Brahmaiah,”Built in self repair for Embedded RAMS with efficient fault coverage using PMBIST”, International Journal of Advances in Engineering & Technology, Nov. 2013.
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