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Proc. of Int. Conf. on Control, Communication and Power Engineering 2010

The Silent Transistor: A New Topology for Low Power Memory Cell 1

Paramita Chowdhury1 and Amitava Das2 Electronics & Communication Engineering Department, NSEC, Kolkata, India Email: paramitamamon_aec@yahoo.com 2 Electrical Engineering Department, TI, Kolkata, India Email: amitavadas@ieee.org

Abstract— This paper proposes a new topology to low power approaches for very large scale integration (VLSI) design. Power dissipation is one of the major concerns when designing a VLSI system. Until recently, dynamic power was the only concern. However, as the technology feature size shrinks, static power, which was negligible before, becomes an issue as important as dynamic power. Since static power increases dramatically in nanoscale silicon VLSI technology, the importance of reducing leakage. This paper describes a novel low-leakage technique The silent transistor. The silent transistor technique is applied to memory cells, and achieve between two and three orders of magnitude leakage power reduction compared to the best prior state saving technique we could find (namely, the forced stack technique)power consumption cannot be overstressed.

A. Switching Power In digital CMOS circuits, switching power is dissipated when energy is drawn from power supply to charge up the output node capacitance. The switching power is given by:

PSwitching = pt CLVdd2 f

It is very clearly seen that lowering down the power supply reduce the switching power, but it increases the circuits delay as it is:

Td ∞

Vdd (Vdd − Vth )α

(2)

B. Short Circuit Power The switching power dissipation is purely due to energy required to charge up the parasitic load capacitance in the circuit, and the switching power is independent of the rise and e transistor fall times of the input signals.

Index Terms— sleepy stack, silent transistor, low leakage power dissipation, SRAM cell.

I. INTRODUCTION As MOSFETs are scaled to nanoscale technology nodes, variability and static power dissipation are becoming increasingly important design considerations. Because memory cells are constrained to near minimum feature size dimensions for area efficiency, they are more sensitive to the impact of intrinsic device variations Also, increasing leakage current in memory cells is becoming a critical problem with process scaling [4]. More specifically gate leakage in devices has increased exponentially as oxides have reached a thickness of 3-4 atomic layers. This very thin insulating layer increases the tunneling leakage from the gates to the sources of devices. Increased leakage presents a huge power dissipation issues. As the technology features scales down to nanoscale the increase of static power becomes the dominant factor to the designers. For this atmosphere we present a solution for low power memory cells the “silent transistor” which survive for high speed, ultra leakage reduction factor.

C. Leakage Power For nanoscale VLSI leakage current is due to mainly for subthreshold voltage. Although dynamic power is dominant for technologies at 0.18μ and above, leakage (static) power consumption becomes another dominant factor for 0.13μ and below. One of the main contributors to static power consumption in CMOS is subthreshold leakage current shown in Figure 1, i.e., the drain to source current when the gate voltage is smaller than the transistor threshold voltage. Since subthreshold current increases exponentially as the threshold voltage decreases, nanoscale technologies with scaled down threshold voltages will severely suffer from subthreshold leakage power consumption. Subthreshold leakage can be reduced by stacking transistors, i.e., taking advantage of the so-called “stack effect”. The stack effect occurs when two or more stacked transistors are turned off together; the result is reduced leakage power consumption.

II. MAIN FACTOR The main key factors in which the power consumption scenario is depends on are generally: (i) Switching Power (ii) Short Circuit Power (iii) Leakage Power

Fig 1: Subthreshold voltage of an nFFT

(1)

Proc. of Int. Conf. on Control, Communication and Power Engineering 2010

III. THE SILENT TRANSISTOR

immediately available to the low-VTH transistors connected to the gate output regardless of the status of each transistor in parallel to the sleep transistors. Furthermore, we can use high-VTH transistors (which are slow but 1000X or so less leaky), for the sleep transistors and the transistors parallel to the sleep transistors (Fig. 3) without incurring large delay increase. During silent mode (Fig. 3 (b)), S = 1 and S0 = 0 are asserted, and so both of the sleep transistors are turned off. Although the sleep transistors are turned off, the sleepy stack structure maintains exact logic state. The leakage reduction of the sleepy stack structure occurs in two ways. First, leakage power is suppressed by high-VTH transistors, which are applied to the sleep transistors and the transistors parallel to the sleep transistors. Second, two stacked and turned off transistors induce the stack effect, which also suppresses leakage power consumption. By combining these two effects, the silent transistor structure achieves ultra-low leakage power consumption during silent mode while retaining exact logic state.

The Silent transistor structure has a combined structure of the forced stack and the sleep transistor techniques. Fig.2 (a) depicts a forced stack inverter, and Fig.2 (b) depicts a sleep transistor inverter. The forced stack inverter breaks existing transistors into two transistors and forces a stack structure to take advantage of the stack effect; this is shown in Fig.2 (a). Meanwhile, the sleep transistor inverter shown in Fig. 2(b) isolates existing logic networks using sleep transistors. The stack structure in Fig. 2(b) saves leakage power consumption during sleep mode. This sleep transistor technique frequently uses high-Vth sleep transistors (the transistors controlled by S and S0) to achieve larger leakage power reduction.

IV. SIMULATION RESULTS & DISCUSSION We have done the simulation with 0.15Îź technology with the help of TSPICE for low cost, low power design with good PDP. The supply voltage applied is 1V.

Fig 2: (a) Forced inverter (b) Sleep transistor

The sleepy stack technique has a structure merging the forced stack technique and the sleep transistor technique. Figure 3 shows a silent transistor inverter. However, in this project we mainly focus on applying the sleepy stack structure with W2/2 sleep transistor widths to SRAM.

Fig 3: Silent transistor (a) Rise mode (b) Silent mode

A. Sleepy Stack Operation Now we explain how the silent transistor works during rise mode and during silent mode. Also, we explain leakage power saving using the silent transistor structure. The sleep transistors of the silent transistor operate similar to the sleep transistors used in the sleep transistor technique in which sleep transistors are turned on during rise mode and be silent during silent mode. Figure 3 depicts the silent transistor operation using a silent transistor inverter. During rise mode [Fig. 3(a)] S = 0 and S0 = 1 are asserted, and thus all sleep transistors are turned on. This silent transistor structure can potentially reduce circuit delay in two ways. First, since the sleep transistors are always on during rise mode, the SILENT TRANSISTOR structure achieves faster switching time than the forced stack structure; specifically, in Fig. 3(a), at each sleep transistor drain, the voltage value connected to the sleep transistor source is always ready and available at the sleep transistor drain, and thus current flow is

Fig 4:Circuit diagram of SRAM cell

The simulations have done in three ways: (a) First we measure the power with base case i.e. conventional 6-T SRAM cell. (b) We then compare the base case with high Vt technique where all transistors are in high Vt. (c) Then we apply forced stack technique to the SRAM cell by dividing each transistor into two half size of it. All transistors are low VTH. (d) Finally we apply sleepy stack technique and measure power. The simulation result shows that using Silent transistor technique the leakage reduction is maximized. It can reduce 30X power compared to the best previous state saving technique, forced stack. 166

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Proc. of Int. Conf. on Control, Communication and Power Engineering 2010 TABLE I. Sl No

Method

Power

Base Case

1419.6E-009

SRAM with high Vt

495.5E-009

SRAM with forced stack

25.204E-009

SRAM with Sleepy stack

8.90E-009

leakage current reduction between Isub0 and Isub1 (= Isub2). Simulation result shows that by base case, the SRAM power consumption is maximum. When we apply the same circuit by with high Vt forced stack technique can reduce power consumption of 25X. For silent transistor SRAM cell high Vt transistor can reduce 50X power reduction compared to best state saving that is forced stack technique. We can easily see from the Fig. 4 ,the power consumption scenario has gradually decreases as we go for forced stack technique. CONCLUSIONS In nanometer scale CMOS technology, sub threshold leakage power is compatible to dynamic power consumption, and thus handling leakage power is a great challenge. In this dissertation, we present a new circuit structure named “Silent transistor” to tackle the leakage problem. The “Silent transistor” has a combined structure of two well-known low-leakage techniques, which are the forced stack and sleep transistor techniques. However, unlike the forced stack technique, the “Silent transistor” technique can utilize high-Vth transistors without incurring large delay overhead. Also, unlike the sleep transistor technique, the sleepy stack technique can retain exact logic state while achieving similar leakage power savings. In short, our “Silent transistor” structure achieves ultra-low leakage power consumption while retaining state.

Fig 5: Simulation result

As we say before that leakage power can be reduced by stacking transistor, i.e., taking advantage of the socalled “stack effect”. The stack effect occurs when two or more stacked transistors are turned off together; the result is reduced leakage power consumption. To understand the simulation results shows in Fig. 4, let us illustrate the leakage reduction factor X. Let us assume that the two stacked transistors (M1 and M2) in Fig. 5 are turned off. We also assume that the transistor width of each of M1 and M2 is the same as the transistor width of M0 (WM0 = WM1 =WM2). Two leakage currents Isub1 of the transistor M1 and Isub2 of the transistor M2 can be expressed as follows: 1

(Vgs 1 −Vth 0 −γ Vsb1 +ηVds 1 )

I sub1 = Ae nVθ 1

I sub 2 = Ae nVθ 1

= Ae nVθ

(1 − e −Vds1 /Vθ )

(Vgs 2 −Vth 0 −γ Vsb 2 +ηVds 2 )

( −Vth 0 +ηVx )

Ae Ae

[1] AGARWAL, A., HAI, L., and ROY, K., “DRG-Cache: A Data Retention Gated- Ground Cache for Low Power,” Proceedings of the Design Automation Conference, pp. 473 – 478, June 2002. [2] AGARWAL, A., ROY, K., and VIJAYKUMAR, T. N., “Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology,” Proceedings of the Design, Automation and Test in Europe, pp. 778–783, March 2003. [3] AMRUTUR, B. S. and HOROWITZ, M. A., “Fast LowPower Decoders for RAMs,” IEEE Journal of Solid-State Circuits, vol. 36, no. 10, pp. 1506–1515, October 2001. [4] ARM Ltd. [Online]. Available http://www.arm.com. [5] AZIZI, N., MOSHOVOS, A., and NAJM, F., “LowLeakage Asymmetric-Cell SRAM,” Proceedings of the International Symposium on Low Power Electronics and design, pp. 48–51, August 2002. [6] Berkeley Predictive Technology Model (BPTM). [Online]. Available http://www.device.ecs.berkeley.edu/˜ptm/ [7] BOWMAN, K. A., AUSTIN, B. L., EBLE, J. C., TANG, X., and MEINDL, J. D., “A Physical Alpha- Power Law MOSFET Model,” IEEE Journal of Solid-State Circuits, vol. 34, no. 10, pp. 1410–1414, October 1999.

( −Vx −Vth 0 −γ Vx +η (Vdd −Vx

= Ae nVθ

I X = sub0 = Isub1

REFERENCES

(1 − e −Vds 2 /Vθ )

(1 − e −Vx /Vθ )

1 ( −Vth 0 +ηVdd ) nV0

1 (−Vx −Vth 0 −γVx +η (Vdd −Vx )) nVθ

Vx (1+λ +η ) nVθ

(3)

where Vx is the voltage at the node between M1 and M2, and we assume 1 >> e-Vds1/V.Now consider