64_ by ides editor

Proc. of Int. Conf. on Advances in Electrical & Electronics 2010

Novel Anti Punch doping in Recessed Source Drain UTB SGOI MOSFETs for Reduced Static Power Dissipation Kiran Bailey 1, K.S. Gurumurthy 2 1

Department of ECE, BMS college of Engineering, Bangalore, INDIA Email: kiranbailey@gmail.com 2 Department of ECE , UVCE, Bangalore University Bangalore, INDIA Email: drksgurumurthy@gmail.com

Abstract— An evaluation of the Recessed Source Drain Silicon-Germanium on Insulator (SGOI) MOSFETs is reported by implementing a 2D device design flow using a commercial Technology CAD (TCAD) tool within the context of optimizing the device design for low leakage and low static power dissipation in circuits. These devices have been explored with an aim to continue the trend of scaling and also to improve the device performance with respect to delay and power dissipation. In this paper, the improvement in static leakage in CMOS circuits achieved by introducing AntiPunch (AP) doping in conventional Recessed Source drain Silicon- Germanium on Insulator (SGOI) MOSFETs is presented. Device doping profiles have been optimized to obtain minimum leakage and minimum static power dissipation. Static leakage in devices with AP is suppressed (83% in both NMOS and PMOS devices) due to reduced short channel effects leading to reduced sub threshold leakage currents. This results in an average power savings of 67% in Ring Oscillator (RO) built using the newly proposed devices. However, the delay in the AP RO increases by 11% because of reduction in on current (11.9% in NMOS and 8% in PMOS).

source/drain series resistance increases, leading to reduced drive currents [7]-[8]. To counter this, the recessed sourcedrain structure is explored and the results have been presented. In this work, static leakage and performance evaluation of Anti-punch (AP) transistors have been compared at device and circuit level with the conventional Recessed Source Drain UTB SGOI MOSFETs. The Recessed Source Drain UTB SGOI transistors have been designed with a body thickness of 10 nm and recessed source drain depths of 50 nm. Two dimensional device and mixed mode circuit simulations have been performed using Synopsys Sentaurus device simulator. The Hydrodynamic carrier transport model for hetero junction simulation has been employed taking into account the Ge mole fraction, Bandgap narrowing effects, Schokley–Read-Hall (SRH) recombination and Auger recombination.

Index Terms— Recessed source drain SGOI MOSFETs, Leakage currents, TCAD, Static Power dissipation, Noise Margin.

I. INTRODUCTION

Fig 1. Device geometry and electrostatic potential contours in a 22 nm recessed source drain NMOSFET with anti punch doping.

Scaling of MOS transistors has been extensively studied to improve packaging density and also improve the performance of VLSI circuits. However, physical limits of scaling are fast approaching due to several processes and device limitations [1]-[2]. Gate oxide thickness cannot be scaled below a limit due to increased gate tunneling leakage current. Also, Vt can not be scaled to a large extent as off currents increase exponentially. Hence, in the Nanoscale CMOS devices Short Channel effects (SCE) are very dominant. To counter the SCEs, a high doping of the channel is employed which degrades the mobility of the carriers in the channel due to scattering. The reduced mobility affects the drive current thus taking away the advantage of scaling. Biaxially strained Silicon by the growth of Silicon on Silicon Germanium (SiGe) [3] results in improved mobility and the use of Silicon Germanium on Insulator (SGOI) improves SCEs [4]-[6]. The Ultra Thin body (UTB) SOI devices have very thin body thickness so the gate control of the channel may be good, but the

II. DEVICE DESIGN The basic device, on which modifications to doping profile is made, is a 22 nm channel length, Ultra thin body Silicon Germanium (Si0.85Ge0.15) on Insulator MOSFET with recessed source drain architecture [9] . Device geometry and Electrostatic potential contours in AP doped transistors are shown in Fig.1. The Recessed Source Drain UTB SGOI transistors have a body thickness of 10 nm with recessed source drain depths of 50 nm. The body thickness is 10 nm with source drain depth at 50 nm. The critical steps in the device design are i) The formation of SiGe channel of 10 nm over a buried oxide approximately 150 nm thick; ii) Thin Silicon cap layers (2nm thick) on either side of the channel to provide for better interface property with the oxide layer [10]; iii)Polysilicon gate formation with a thin layer of gate oxide(0.9 nm); iv)An Anti punch 52

Proc. of Int. Conf. on Advances in Electrical & Electronics 2010

current for both NMOS and PMOS reduces linearly due to the increase in threshold voltage, but at the same time the Leakage current reduces exponentially with the increase in AP doping concentration. Thus, the AP doping is limited by the power supply-to-threshold voltage ratio (Vdd/Vt). The optimal values of source and drain extension AP doping are 1018/cm3 for both source and drain sides. Fig 4. Shows the variation of threshold voltage with AP doping. It is seen that a very high AP doping tends to increase the Subthreshold Slope (SS) due to increase in Vt, while the Drain induced barrier lowering (DIBL) is found to improve with AP doping as seen in Fig.5. This is because of improved SCEs.

(AP) doping in the source drain extension regions to counter SCEs; v)Lightly doped drain (LDD)implants and nitride spacer formation; vi) Source/Drain Implants to a depth of 50 nm. Doping profiles have been optimized to obtain minimum leakage at a reasonable on current by varying the concentration of the Anti punch (AP) doping. The Anti punch doping is introduced in the source drain extension regions to limit the penetration of the depletion region into the channel thus improving short channel effects. By increasing the AP doping, the sub threshold leakage gets minimized but at the same time band to band tunneling current increases along with an increase in the threshold voltage. Also, decreasing the AP doping levels lead to the degradation of the SCEs. Therefore, a tradeoff between static power dissipation and delay is necessary. In this case, the AP doping concentration is optimized to obtain minimum leakage for Low Standby Power (LSTP) applications [11]. A. UTB SGOI MOSFETs without AP doping: The Recessed source drain architecture for the UTB SGOI MOSFETs includes a thin body over a buried oxide region approximately 100-150 nm thick. The source and drain regions have a depth of 50 nm. For an NMOS transistor in off state( Vgs=0, Vds=Vdd), the total leakage current includes Gate direct tunneling current (Igd), Sub threshold leakage current(Isub) and Band-to-band tunneling current(Ibtbt). The major component of the gate leakage in the off state is due to gate to drain overlap. The channel region is lightly doped at 1016/cm3. The source and drain regions have a doping of 1020/cm3 and the source drain extension regions have a doping of 1019/cm3 at a depth of 10 nm. A similar design approach has been adopted for the PMOS transistor. The Id-Vg curves for these devices are depicted in Fig.2.

Fig.2 Ids-Vgs characteristics for NMOS and PMOS devices with and without AP doping.

(a)

(b)

Fig 3. Saturation and Leakage currents in MOSFETs with and without AP doping(depicted as undoped) for various anti punch doping concentrations. (a) Ion (b) Sub threshold leakage current Ioff.

B. Anti punch doped UTB SGOI MOSFETs: An NMOS transistor with the same geometry as the undoped NMOSFET is optimized by varying the source drain extension Anti punch (AP) doping for minimum sub threshold leakage current. The aim is to control SCEs and thereby control leakage currents thus optimizing for minimum static power dissipation. Fig 3. shows the Ion and Ioff through the drain terminal for different AP doping concentrations. As can been seen, the Saturation drain Fig 4. Threshold voltage variation at different AP doping concentrations.

(a)

C. Comparison of Device characteristics: The Electrical characteristics for the transistors with and without AP doping are shown in Table I. It is seen that threshold voltage increases after introducing AP doping and hence the reduction in the Gate overdrive leads to the reduction in the drive current whereas the leakage current shows dramatic improvement due to its exponential dependence on the threshold voltage. It can be observed that AP doped MOSFETs require additional processing steps to introduce the source drain extension engineered Anti punch doping. This can be implemented before source drain formation by using

(b)

Fig 5. (a) Subthreshold slope variation (b) DIBL variation, with AP doping Concentration.

53 ÂŠ 2010 ACEEE DOI: 02.AEE.2010.01.64

Proc. of Int. Conf. on Advances in Electrical & Electronics 2010

disposable spacers over source drain regions and introducing AP doping by Ion Implantation. Therefore, AP doped MOSFETs can only be implemented in circuit styles where, at the design level, Power dissipation is of importance. TABLE I ELECTRICAL CHARACTERISTICS OF PROPOSED {NMOS ,PMOS} DEVICES Device parameter

Without doping

AP doped

LG TOX Anti punch doping Threshold Voltage Vt(V) Ion (uA/um) Ioff (nA/um) DIBL( mV/V) Subthreshold Slope(mV/dec)

22 nm 0.9 nm 1E16 0.51,-0.49

22 nm 0.9 nm 1E18 0.55,-0.54

2770, 516 40, 62 130, 180 103, 104.36

2440, 474 6.8, 10 122, 110 81.1, 102.9

Fig 7. RO.

A. Performance Analysis: The Gate input capacitance calculated using C-V curves is 1.2fF. Therefore, a constant lumped capacitance of 7.2fF (for 3 stage RO) is connected to the output of each stage. The stage delay for RO with AP doping is 4ps and 9ps compared to 3ps and 8ps for RO without AP doping for output rising edge and falling edge respectively simulated at a frequency of 500 MHz.

TABLE II STATIC POWER DISSIPATION IN AN INVERTER OF RO Input ‘0’

AP doped Without AP

B. Power Dissipation: The main leakage components in a transistor when it is off are the sub threshold leakage Isub, Gate leakage Igd, and the band-to-band tunneling leakage Ibtbt. When the transistor is on, is main leakage component is Igd. The Static power dissipation is given by

Input ‘1’

Ileak NMOS 2.8nA

Ileak PMOS 3nA

14nA

P static

6.38 nW 30.8 nW

Ileak, NMOS 8.6nA

Ileak PMOS 3nA

10nA

15nA

Pstati c

12.7 6n W 27.5 nW

Pstatic= (Isub + Igd + Ibtbt) Vdd.

Performance and Power consumption is analyzed for a 3stage Ring Oscillator (RO) circuit. Each stage of the RO is a CMOS inverter. The width ratio of PMOS to NMOS is 2:1 to obtain symmetrical characteristics. The voltage transfer characteristics along with the short circuit currents for the designed MOSFETs with and without AP are shown in Fig.6. The gain during switching is higher due to reduced sub threshold swing and DIBL. This results in higher peak short circuit current and better noise margin in the AP doped inverter. Fig. 7 shows the input and output waveforms of a single stage of RO at a frequency of 500 MHz.

C. Noise Margin: The Noise Margins for the inverter are obtained from the voltage transfer curves and are given by NMH=VOH-VSx

(2)

NML=VSy-VOL

(3)

The values of the NMH are 0.57 and NML are 0.58 respectively for Transistors with AP and 0.54 and 0.59 respectively for transistors without AP doping. Table III gives a brief comparison of various device and circuit parameters with ITRS and other references.

(b)

Fig 6. (a) Voltage transfer characteristics of CMOS inverter, (b) Short circuit current Vs input voltage in inverter.

(1)

Table II gives the leakage current components and total static powe dissipation for Inverters with and without AP doping. It is shown that inverters with AP doping have reduced subthreshold leakage, and static power dissipation in AP RO is 21% of the power dissipation of a RO without AP doping for input ‘0’and 46.4% for input ‘1’. These results in an average power saving of 67% in AP doped RO. At device level, the total static leakage in off state in AP doped NMOS and PMOS transistors are 83% less than that of transistors without AP doping.

III. PERFORMANCE AND POWER

(a)

Input and Output waveforms of a single stage of Inverter of

Proc. of Int. Conf. on Advances in Electrical & Electronics 2010

CONCLUSIONS

REFERENCES

In this paper Anti-punch doped Recessed source drain UTB SGOI MOSFETs have been designed, and studied. The effects of varying the Anti punch doping levels on the device and circuit parameters are analyzed and reported. The devices have been optimized to achieve minimum leakage and therefore AP doped transistors dissipate comparatively less static power in the circuits. It was found that the AP doping is crucial to improve SCEs. The main disadvantage is that they require more processing steps. The Noise margins show improvement due to reduced DIBL and Sub threshold slope. Thus, these devices are useful for high performance and Low power applications.

[1] Taur Y,”CMOS design near the limit of scaling”,IBM J Res Develop 2002;46(2/3):213–22. [2] Skotnicki T, Fenouillet-Beranger C, Gallon C, Boeuf F, Monfray S, Payet F, et al.“Innovative materials, devices, and CMOS technologies for low-power mobile multimedia.” IEEE Trans Electron Dev 2008;55(1):96–130. [3] M. Reiche, O. Moutanabbir, J. Hoentschel , U. Gösele, S. Flachowsky and M. Horstmann , “Strained Silicon Devices”, Solid State Phenomena Vols. 156-158 (2010) pp 61-68. [4] Suzuki E, Ishii K, Kanemaru S, Maeda T, Tsutsumi T, Sekigawa T, et al. “Highly suppressed short-channel effects in ultrathin SOI n-MOSFETs.”, IEEE Transactions Electron Dev 2000;47(2):354–9. [5] Hisamoto D. “FD/DG-SOI MOSFET – a viable approach to overcoming the device scaling limit.”, Int Electron Dev Meet 2001;1:429–32. [6] Trivedi VP, Fossum JG, “Scaling fully depleted SOI CMOS.”, IEEE Trans Electron Dev 2003;50(10):2095–103. [7] Choi CH, Goo JS, Yu Z, Dutton RW. “Shallow source/drain extension effects on external resistance in sub-0.1 lm MOSFETs”. IEEE Trans Electron Dev 2000;47(3):655–8. [8] Doris B, Ieong M, Kanarsky T, Zhang Y, Roy RA, Dokumaci O, et al. “Extreme scaling with ultrathin Si channel MOSFETs.”, Int Electron Dev Meet 2002;1:267–70. [9] Wei Ke, Xu Han, Dingyu Li, Xiaoyan Liu, Ruqi Han, and Shengdong Zhang ” Recessed Source/Drain for Scaling SOI MOSFET to the Limit”, 1-4244-0161- 5/06©2006 IEEE [10] .Yee Chia Yeo, Vivek Subramanian, Jakub Kedzierski, Peiqi Xuan, Tsu-Jae King, Jeffrey Bokor, and Chenming Hu, “Nanoscale Ultra-Thin-Body Silicon-on-Insulator PMOSFET with a SiGe/Si Heterostructure Channel” IEEE Electron device letters, vol. 21, no. 4, April 2000. [11] International Technology Roadmap for Semiconductors (ITRS) 2009 edition. [12] Muhammad Nawaz, Stefan Deckar, Luis-Felipe Giles, Wolfgang Molzer, Thomas Schulz, “ Evaluation of process parameter space of bulk FinFETs using 3D TCAD”, Microelectronic Engineering 85 (2008) 1529-1539. [13] Fu-Liang Yang, Haur-Ywh Chen, Fang-Cheng Chen, Yi-Lin Chan, Kuo-Nan Yang, Chih-Jian Chen, Hun-Jan Tao, YangKyu Choi, Mong-Song Liang and Chenming Hu, “ 35 nm CMOS FinFETs”, 2002 Symposium on VLSI Technology Digest of Technical papers. [14] Adidya Bansal, Kaushik Roy “Asymmetric Halo CMOSFETS to reduce static Power dissipation with improved performance”, 0-7803-8834-8/05 2005 IEEE.

ACKNOWLEDGMENT The authors wish to thank BMS college of Engineering for supporting this work by encouraging and also supplying the necessary tools. TABLE III COMPARISON WITH ITRS AND OTHER REFERENCES Transistor parameter

This work

ITRS HP

ITRS LSTP

Ref [12]

Ref [13]

Ref [14]

Lg(nm) Vdd(V) Tox(nm) Gate Electrode Ion (uA/um) Ioff(A/um)

22 1.1 0.9 PolyS i 2440

22 1.0 0.9 n.a

22 0.95 1 n.a

1513

506

30 1.5 2 PolyS i 187.4

35 1 2.4 N+ Poly 1240

25 0.9 n.a N+p oly n.a

6.8n

0.71u

50p

3.1u

n.a

DIBL(mV/ V) SS(mV/dec) Pstatic(avg)

120

n.a

81.1 6.38n W 9

n.a n.a

324.3 4 121 n.a

200 n n.a 78 n.a

n.a

92 76.3n W 35.6

Delay (ps)