Proc. of Int. Conf. on Recent Trends in Information, Telecommunication and Computing, ITC
Algorithms and Architectures for Reduced Complexity LDPC Decoding: A survey Monica V. Mankar1, G.M.Asutkar2 and P.K.Dakhole3 1
2
Yeshwantrao Chavan college of Engineering/Dept. Of Electronics Engg.,Nagpur,India Email:monica14mankar@gmail.com Priyadarshani Institute of Engg. And technology./Dept. Of Electronics and communication Engg., Nagpur, India Email: g_asutkar@yahoo.com 3 Yeshwantrao Chavan college of Engineering/Dept. Of Electronics Engg.,Nagpur,India Email:pravin_dakhole@yahoo.com
Abstract— Low-density parity-check (LDPC) code, have become most popular, promising near-optimal error correction code (ECC). Trade off between the performance and complexity of LDPC decoders is of paramount interest to communication engineers and researchers. The VLSI implementation of LDPC decoder is a big challenge. VLSI implementations has many difficulties to achieve as lower error floors, reduced interconnect complexities, small chip areas, lower power dissipation to support multiple code lengths and code rates. This Paper provides an overview of LDPC codes structure and different decoding algorithms. Index Terms— VLSI implementation, low complexity, LDPC, Min sum, etc.
I. INTRODUCTION Low-density parity-check (LDPC) codes are a class of linear block codes defined by a sparse parity-check matrix, first introduced by Gallager in his PhD. Thesis [1] [2]. LDPC codes were re-discovered by D. MacKay and R. Neal in1996. They show in their work that LDPC codes have very good coding gain performance. LDPC code supports some industrial standards, such as WLAN (802.11n), WiMAX (802.16e), DVB-S2, CMMB, and 10GBaseT (802.3an) systems [4]. LDPC codes are one of the most attractive error correction codes due to their high performance, high degree of parallelism and relatively low complexity as compare to the other Error correction codes (ECC). LDPC Prefers an iterative decoding method which shows parallelism in the decoding process results in a high decoding throughput. Most of the work on LDPC decoder design has been focused on achieving optimal tradeoffs between hardware complexity and decoding throughput . If number of iteration increases, it will decrease the throughput. Hence research is focused on high performance, low complexity, and low power LDPC error correction codes as per the need of wireless portable devices. A. Representations of LDPC Codes Basically LDPC codes can be represented by two ways. First they can be described via matrices and secondly a graphical representation. 1. Matrix Representation An LDPC code is a type of linear block code defined by a sparse MxN parity-check matrix H. The (n,k) DOI: 02.ITC.2014.5.97 © Association of Computer Electronics and Electrical Engineers, 2014
LDPC codes mean that a k bit message can be encoded to be n bit codeword[9]. The PCM H(n-k)xn consists of (n-k) rows and n columns and the corresponding code rate R is defined as k/n. If x=(x0,……..xn-1) is a codeword, it satisfies parity check equation: H. xT = 0 (1) A parity check matrix with dimension M ×N for a (8, 4) code in (1). Two numbers wr for the number of 1’s in each row and wc for number of 1’s in each columns describing this matrix. The matrix is called as lowdensity parity check if it satisfies the two conditions that are wc ≤ n and wr ≤ m.
0 1 0 1
1 1 0 0
0 1 1 0
1 0 0 1
1 0 0 1
0 1 1 0
0 0 1 1
1 0 1 0
(2)
2. Graphical Representation The graphical representation for LDPC codes was introduced by Tanner. Tanner Graphs show a complete representation of the LDPC code and also help to describe the decoding algorithm. These are also called as bipartite graphs. Bipartite means here the nodes of the graph are separated into two distinctive sets and edges are only connecting nodes of two different types. Tanner graph shows two types of nodes are called variable nodes and check nodes [3].Fig.1. shows a Tanner graph that represents the same code as the matrix in (2). It consists of m check nodes (the number of parity bits) and n variable nodes (the number of bits in a codeword). B. Types of LDPC codes Broadly there are LDPC block codes and LDPC convolutional codes. But the research is focused on LDPC block codes due to many practical considerations [4]. LDPC codes are regular or irregular. An LDPC code is called regular if the degree of any check node is a constant and the degree of any variable node is also a constant. Otherwise the code is called irregular. There are also structured LDPC codes. These codes include Quasi cyclic [5][6] and Shift LDPC codes[7][8]. Also Non-binary LDPC codes, is the class of LDPC codes. Quasi cyclic (QC)-LDPC codes are a type of block structured low density parity check codes. QC-LDPC is defined by very sparse base matrix. Quasi-cyclic means the code has the property that when a codeword is cyclically shifted by k positions another codeword is obtained [10].The encoder of a QC-LDPC code can be easily built with shift-registers [11] while random codes usually entail complex encoding circuitry to perform matrix and vector multiplications [12]. QC-LDPC codes facilitate efficient high-speed decoding due to the regularity of their parity check matrices. 3. Shift LDPC codes Shift-LDPC code was first presented by Sha et al in 2006 [8]. It is a class of implementation-oriented LDPC codes which have comparable decoding performance to compute generated random codes. In [8], [7] Sha et al proposed a specific high-speed decoder architecture targeting for multi-Gbps applications. 4. Non-binary LDPC codes Non-binary LDPC codes, which are extension of binary LDPC codes, were first presented by Davey and MacKay in 1998 [13]. The non-zero entries in the parity check matrix of a non-binary LDPC code are directly replaced by elements in a Galois field. The performance of non-binary LDPC codes has been shown to be better than binary LDPC codes under binary Gaussian channel.
Figure 1. Tanner graph corresponding to the parity check matrix in (2)
404
II. LDPC DECODER ARCHITECTURES LDPC decoders have mainly two types of architectures. Fully-parallel decoders and Partially-parallel decoders architectures. A. Fully-parallel decoders Fully-parallel decoders show highest throughput and they do not require large memory element such as SRAMs to store intermediate messages. Large circuit area and routing congestion are the drawbacks of Fullyparallel decoders due to the large number of processing units and very long global wires between them [20].In this architecture each row and each column of the parity check matrix is directly mapped to a different processing unit and all these processing units operate in parallel . B. Partially-parallel decoders In Partially-parallel decoders architecture the parity check matrix partition into row wise and column wise groupings such that a set of check node and variable node updates can be done per cycle. This is suitable for regular structured LDPC codes. The irregularity of random codes causes partitioning to be difficult due to the memory addressing problems inherent with the irregular placement of “ones” in the parity check matrix. III. DECODING ALGORITHMS FOR LDPC CODES LDPC code is usually decoded with an iterative decoding .Iterative decoding process results in the optimal decoding performance with low complexity. If the larger number of decoding iterations, the less decoding throughput and the longer decoding latency. For A high decoding date rate, a large number of computation units are required for an LDPC decoder, which leads to large chip area and high power consumption [4]. Thus the research on area and power efficient Very Large Scale Integration (VLSI) design for high-speed LDPC decoding is essential for practical applications The most common message passing algorithms are bit-flipping, the belief propagation algorithm, and the sum-product algorithm. LDPC decoding algorithms are based on either hard decision or soft- decision on the messages received from the noisy channel. In hard decision, the data received from the channel and then passed to the decoder, e.g. Bit-Flipping Algorithm (BFA). BFA algorithm has least decoding complexity, but suffers from poor performance. In soft-decision based algorithms uses probabilities represented in logarithmic ratio which is also known as log-likelihood ratio (LLR). e.g. Belief Propagation based algorithms uses soft LLR input for decoding [15]. BP is also called as the Sum-Product Algorithm (SPA) [14]. A soft decision based message passing algorithm shows best performance, but with high decoding complexity. MinSum Algorithm (MSA) is the modified version of SPA that has reduced implementation complexity along with a slight degradation in performance [17]. Decoding algorithms used to decode LDPC codes are message-passing algorithms as their operation can be explained by the passing of messages along the edges of a Tanner graph. The message-passing algorithms are also known as iterative decoding algorithms as the messages pass back and forward between the bit and check nodes iteratively until a result is achieved [3]. Different message-passing algorithms are named for the type of messages passed or for the type of operation performed at the nodes. A. Sum-Product Algorithm In Sum-Product algorithm for LDPC decoding requires intrinsic message for variable node operations In the decoding process, these LLRs are passed through the variable nodes. The variable nodes perform the ‘sum’ operations on the input LLRs, as in (3) .The computed extrinsic messages are passed along the connected edges to the check nodes [14]. Variable node operation: (3)
Vi LLRn Cj j i
Where n=1,2,………………Number of variable nodes i, j= degree of variable nodes
405
The operation performed by the check nodes shown in (4) . Check nodes output messages are passed to the respective variable nodes. The check nodes also perform the parity check operation [14]. We have to repeated this process until we reached the maximum iterations or the parity check is satisfied. Check node operation: V C k 2 ta n h 1 ta n h l 2 k 1
(4)
Where, l, k = 1, 2….degree of check node The Sum Product Algorithm has high computational complexity as it requires multiple nonlinear operations in the check node and also requires high precision extrinsic messages to be exchanged between the nodes. But decoding performance is very good [14]. B. Bit-Flipping Algorithm In BFA the messages passed between the check node and variable nodes are also single-bit hard-decision binary values. The variable node sends the bit information to the connected check nodes over the edges[16][17]. The check node performs a parity check operation on the bits received from the variable nodes as in(5) . It sends the message back to the respective variable nodes with a suggestion of the expected bit value for the parity check to be satisfied. Check node operation:
Ck V 1 V 2 ......... Vl
l 1
(5)
Where, l, k = 1,2,….degree of check node The variable node receives suggested bit values from the check nodes. Based on the majority of the suggested bit values, the variable node flips the current bit as in (6) or retains the original value[17]. This operation is repeated until the parity check is satisfied or maximum number of iterations is reached. Variable node operation:
0.....if , majority(Ci ) 0 Vn 1.....if , majority (Ci ) 1 Vn.....otherwise BFA is consists of simple check nodes and variable algorithm .But it has poor decoding performance.
(6)
operations hence it is very low complexity decoding
C. Min –Sum algorithm The modified version of the Sum-Product algorithm is Min-Sum algorithm (MSA).In MSA the check node operation is modified to reduce the complexity of the algorithm. Here the quantized intrinsic message i.e. Log-likelihood ratio (LLR) and the extrinsic messages (between variable and check nodes) are of equal length [18]. The variable node and check node operations are as shown in (7)and(8), respectively[19]. Variable node operation:
Vi LLRn Cj
(7)
j i
Where n=1,2,………………Number of variable nodes i, j= degree of variable nodes Check node operation:
Ck
s ig n (V l ) m in V l
lk
l k
Where l, k…….dc (degree of check node).
406
(8)
IV. CONCLUSION Recent research has focused on VLSI implementation of decoding algorithms of LDPC for the current applications. LDPC code can be decoded with iterative decoding which result in optimum decoding architectures along with different structures of the parity-check matrix. Due to trade off between complexity and performance, MSA (Min Sum algorithm) is the best solution which provides reduced implementation complexity with a slight degradation in performance. ACKNOWLEDGMENT The authors would like to thank Zhongfeng Wang, Zhiqiang Cui, and Jin Sha for different types of LDPC codes,Vikram ArkalgudChandrasetty , SyedMahfuzulAziz for study of decoding algorithms, Tinoosh Mohsenin and Bevan Baas for different architectures for LDPC codes. REFERENCES [1] R.G.Gallager, “Low density parity check codes.” IRE Trans. Info. Theory, vol. IT-8,pp.21-28,1962. [2] D.J.C.MacKay and R.M.Neal, “Near Shannon limit performance of low density parity check codes,” Electron Lett., vol.32, pp.1645-1646.1996. [3] LDPC Codes – a brief Tutorial by Bernhard M.J. Leiner, Stud.ID: 53418L, April 8, 2005. [4] Zhongfeng Wang, Zhiqiang Cui, and Jin Sha ,( 2011) ,“ VLSI Design for Low Density Parity Check Code Decoding,” IEEE CIRCUITS AND SYSTEMS MAGAZINE. [5] J. L. Fan, “Array codes as low-density parity-check codes,” in Proc. 2nd Int. Symp. Turbo Codes, Brest, France, Sept. 2000, pp. 545–546. [6] Z. Li and B. V. K. V. Kumar, “A class of good quasi-cyclic low-density parity check codes based on progressive edge growth graph,” in Proc.38th Asilomar Conf. Signals, Systems and Computers, 2004, vol. 2, pp. 1990-1994 [7] J. Sha, Z. Wang, M. Gao, and L. Li, “Multi-Gb/s LDPC code design and implementation,” IEEE Trans. VLSI Syst., vol. 17, no. 2, pp. 262–268, Feb. 2009. [8] J. Sha, M. Gao, Z. Zhang, L. Li, and Z. Wang, “Efficient decoder implementation for QC-LDPC codes,” in Proc. IEEE Int. Conf. Communications, Circuits and systems (ICCCAS), June 2006, vol. 4, pp. 2498–2502. [9] Yun Chen, Xiang Chen, Yifei Zhao and Jing Wang," Design and Implementation of Multi-mode QC-LDPC Decoder," IEEE Trans. Circuits and Syst.,vol. 6, pp. 204-212, March 2010. [10] Marc P.C.Fossorier, “Quasi-cyclic Low Density Parity-Check Codes from Circular Permutation Matrices”, IEEE Trans.,vol.50,No.8,August 2004. [11] Z. Li, L. Chen, L. Zeng, S. Lin, and W. Fong, “Efficient encoding of quasi-cyclic low-density parity check codes,” IEEE Trans. Commun., vol. 54, pp. 71–81, Jan. 2006. [12] D.-U. Lee, W. Luk, C. Wang, and C. Jones, “A flexible hardware encoder for low-density parity-check codes,” in Proc. IEEE Symp. FCCM’04, 2004, pp. 101–111. [13] M. Davey and D. J. C. Mackay, “Low-density parity check codes over GF(q),” IEEE Commun. Lett., vol. 2, no. 6, pp. 165–167, June 1998. [14] A. Anastasopoulos, "A comparison between the sum product and the min-sum iterative detection algorithms based on density evolution," Proceedings of the IEEE Global Telecommunications Conference, San Antonio, TX, pp. 1021-1025, 25-29 November 2001. [15] M.G. Luby, M. Amin Shokrolloahi, M. Mizenmacher, and D.A. Spielman, "Improved low-density parity-check codes using irregular graphs and belief propagation," Proceedings of the IEEE International Symposium on Information Theory, pp. 117. [16] Vikram Arkalgud Chandrasetty and Syed Mahfuzul Aziz, FPGA Implementation of a LDPC Decoder using a Reduced Complexity Message Passing Algorithm”, JOURNAL OF NETWORKS, VOL. 6, NO. 1, JANUARY 2011. [17] N. Miladinovic and M.P.C. Fossorier, "Improved bit flipping decoding of low-density parity-check codes," IEEE Transactions on Information Theory, vol. 51, no. 4, pp. 1594-1606, April 2005. [18] A. Darabiha, A.C. Carusone, F.R. Kschischang,” A bit-serial approximate min- sum LDPC decoder and FPGA implementation”, Proceedings of the IEEE International Symposium on Circuits and Systems, Island of Kos, Greece, pp. 149–152, 21–24 May 2006. [19] Vikram ArkalgudChandrasetty , SyedMahfuzulAziz,” An area efficient LDPC decoder using a reduced complexity min-sum algorithm”,Elsvier, INTEGRATION, the VLSI journal 45 (2012) 141–148 [20] Tinoosh Mohsenin and Bevan Baas,”Trends and Challenges in LDPC Hardware Decoders, 978-1-4244-58271/09/$26.00 ©2009 IEEE
407