International Journal of Advanced Engineering, Management and Science (IJAEMS)
[Vol-1, Issue-2, May- 2015] ISSN: 2454-1311
Overview of Testing Power Switches in VLSI Circuits Sami Venkatesh1, Uday B1, Sk Tabrace2, S Premkumar3 1,2
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Department of ECE, Saveetha University, CHENNAI Department of ECE, Assistant Professor , Saveetha University, CHENNAI
Abstract— This paper presents a comparative discover of power switches. Power switches are increasingly becoming dominant leakage power reduction technique. Hence, fast and efficient DFT resolution for examination and diagnosis of power switches is far demanded to enable faster identification of possible faults and their locations. By employing effective discharge route design, that eliminates the potential of false examination and hence considerably cutting the price and discharge times. We validated the effectiveness of our proposed solution across SPICE simulations. In this paper we are going to discover the Complete overview of power switches. Keywords— Power Gating, DFT(design for test), leakage power reduction, fault diagnosis, Multimode Switches. I. INTRODUCTION Power switches are utilized to cut power leakage in a mechanism, power gating is a design method to cut power leakage , whereas leakage plays a main act in finished power consumption. Across IDLE mode the power leakage can be decreased by employing power switches to power down the logic blocks[1]. The principle of power gating method is to add PMOS switch(header) or NMOS switch(footer) in routes , so it can be coiled into stand-by mode to cut leakage of power[3] . power switches can be requested in two probable kinds whichever “coarse-grain “design style or “fine-grain” design style. A fine-grain design contain a power switch alongside every single average logic cell related to a power gesture to switch ON and OFF, In coarse-gain the power switches are clubbed jointly to form a logic[1]. The DFT’s method have been gave to examination the power switches.by contrasting both sketches the crude grain is larger because it incorporates alongside a power switches[2]. There are two probable kinds of faults are stuck-short and stuck-open, stuck-open obligation ascertain after drain (or) basis is disconnected due to a obligation transistor deeds, stuck-short produces a leading trail amid the drain voltage(Vdd) and ground[1]. The main drawback is there is a probable to discriminate stay obligation provoked by power switches as well as logic gates. The discharge period is extremely colossal so the switches can be coiled off , to vanquish this setback a
discharge transistor alongside low power leakage is used[2]. The chip variations in voltage and temperature could be problematic due to several power supply voltages[4]. The main way for cutting vibrant power dissipation is to cut transistor threshold voltage due draininduced barrier effect[4]. The assessing of power switches in intermediate power-off modes is extremely tough due to their intermediate voltage levels at assorted power down modes. The multimode power switches are utilized to cut stand-by leakage power due to long eras of inactivity. In exceedingly competent multi-mode powergating design it converts the analog characteristics of power switches into a digital signature and examination alongside the crafted in circuits.
II.
OVERVIEW OF POWER SWITCHES
1. Power Gating: This method is competent for cutting power leakage . it temporarily shut down the route to cut the finished power leakage[1] . it can be completed in two methods they are “low power mode” or “inactive mode”. These two methods are switched appropriately to maximize the power presentation .the main aim of power gating method is to minimize power leakage by circumventing power to discerning blocks that are not required. It results the design design as contrasted alongside the timepiece gating. It increases period delays as power gated modes[2]. Shutting down the power blocks can be accomplished by employing whichever multimedia or hardware. The supplementary option is dedicated power association controller. Power gating uses low-leakage PMOS transistors as header switches to shut off power supplies to portions of a design in nap mode. NMOS footer switches can additionally be utilized as nap transistors. By Inserting the nap transistors splits the chip's power web into a perpetual power web related to the power supply and a adjacent power web that propels the cells and can be coiled off. Power gating can be requested employing cell- or cluster-based (or fine grain) ways or a distributed coarse-grained approach[1]. 2. Power Gating Parameters: 2.1. Power gate size: It have to be selected to grasp the number of switching present at each given Page | 7
International Journal of Advanced Engineering, Management and Science (IJAEMS)
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time. The gate have to be bigger and there is no measurable voltage drop due to gate. 2.2. Gate control slew rate: After the slew rate is colossal, it seizes extra period to switch off and switch-on the route and hence it can alter the power gating efficiency. Slew rate is manipulated across buffering the gate power signal. 2.3. Simultaneous switching capacitance: The colossal number of route switched simultaneously it aftermath “Rush current�,so it can be switched simultaneously lacking effecting the power web integrity. Types Of Power Gating: 3.1. Fine-grain power gating:
Fig. 1 Fine Grain Design Fine-grain power gating encircles the switching transistor as a portion of the average cell logic. Switching transistors are projected by whichever library IP vendor or average cell designer. The size of the gate power is projected alongside the worst case thought, that this route will switch across every single timepiece series emerging in huge impact[5]. this knowledge permits several Vt libraries, the custom of low Vt mechanisms is minimum in the design (20%), so that the encounter can be reduced. After employing power gates on the low Vt cells the output have to be remote if the subsequent period is a elevated Vt cell. Or else it cause the subsequent elevated Vt cell to have leakage after output goes to an undetermined state due to power gating. The gating transistor is projected as a elevated gating elevated Vt device[2]. 3.2. Coarse-grain power gating:
[Vol-1, Issue-2, May- 2015] ISSN: 2454-1311
Fig. 2 Coarse Grain Design The coarse gain can be requested in two methods they are[1] 3.2.1. Ring Based Methodology : The power gates are allocated concerning the perimeter of the module that is being switched-off as a ring. Distinct corner cells are utilized to coil the power signals concerning the corners. 3.2.2 .Column Based Methodology: The power gates are inserted inside the module alongside the cells abutted to every single supplementary in the form of columns. The globe power is the higher layers of metal, as the switched power is in the lower layers. Simultaneous switching capacitance is the main thought in a coarse-grain power gating implementation. In order to check simultaneous switching by shackling the gate power buffers, distinct counters are utilized to selectively coil on blocks of switches. 4. Multimode Power Switches :
Fig. 3 Multimode Power Switch Circuit The multi-mode power-switch design counseled in is shown in Figure . It consists of a colossal footer high- Vt transistor Mp and a couple of tiny transistors M0, M1 that are related amid the core and the earth rail. After Mp is "on", the core operates in the normal useful mode[4]. After Mp is "off" (i.e. inactive mode) and transistors M0 and M1 are additionally off, the adjacent earth rail (VGND) prices to a voltage level close to the power supply. Therefore, it suppresses the leakage currents of the transistors of the route due to the body effect. In this mode (which is shouted hereafter snort mode), the Page | 8
International Journal of Advanced Engineering, Management and Science (IJAEMS)
leakage present of the core, (ILcore = ILM0+ILM1+ILMP), ILcore, is equal to the aggregate leakage present flowing across transistors M0, M1, MP ,which is extremely tiny (note that M0, M1 are extremely tiny low-Vt transistors and MP is a colossal high-Vt transistor). Therefore the voltage level at adjacent earth rail VV-GND ways Vdd and the route consumes a negligible number of energy. In order to reinstate the voltage of the adjacent earth rail to its nominal worth after the route transitions from the poweroff mode to the alert mode, the parasitic capacitance at the VGND node has to be completely emitted across the power switch Mp. Though, this switch is not colossal plenty (due to span constraints) to swiftly reinstate the voltage level at the adjacent earth node. Therefore the wake-up period is normally long comparative to route timepiece period. Transistors M0 and M1, that selectively stay on across the short inactive eras, set the adjacent earth node to an intermediate voltage level and therefore proposal two intermediate power-off modes (M0 implements the dream mode and M1 implements the nap mode). Specifically, in the dream mode transistor M0 is on and transistors MP and M1 are off .Thus the static power consumed by the core increases contrasted to the snort mode, but the wakeup period drops. In order to become into the nap mode, transistor M1 is turnedon, and MP, M0 are coiled off Consequently, the voltage level at the V- gnd node is more decreased contrasted to the dream mode and therefore the wake-up period cuts the price of increased static power consumption. Note that in both nap and dream modes, static power consumptions far lower than that in the alert mode. Thus, there are momentous benefits if the core is locale into an intermediate mode for a short era instead of staying inactive in the alert mode. 4.1. Proposed Multimode Circuit: The assessing of each construction proposals intermediate poweroff modes can be completed by computing the adjacent earth voltage and by verifying that the wake-up period has not increased and that the aim of cutting static power at each power-off mode is achieved[4]. the resolution is to embed an analog-todigital converter (ADC) that though is extremely luxurious in words of span and is additionally extremely
[Vol-1, Issue-2, May- 2015] ISSN: 2454-1311
Fig. 4 Proposed Multimode Power Switch Circuit sensitive to procedure variations. In this work, we counsel a easy and exclusively digital built-in examination route, that can be embedded on-chip to precisely compute the adjacent earth voltage. Note that even nevertheless we focus on the power-off switches counseled in the counseled examination method is generic and it can be utilized to examination each comparable structure. The frank believed of the counseled examination construction is to change the voltage of the virtual-ground node to a frequency reading. Specifically, we use a voltage power oscillator (VCO) to change the voltage of V-GND into a gesture toggling alongside a frequency that depends on this voltage. Next we use this gesture to trigger a binary counter that provides a quantification of the frequency. By employing this method, the digital worth that is stored in the counter at the conclude of the assessing era is undeviatingly proportional to the voltage at V-GND. It consists of a shackle of inverters growing a ring oscillator and a number of D flip-flops growing a ripple counter. The VCO is crafted employing a ring of current-starved inverters. We utilized the construction of inverters shown in Fig as they furnish elevated resolution in the detection of voltage variations but each comparable construction can be additionally used. The adjacent earth is related to the VCO as the power voltage. The propagation stay of every single inverter depends on the power voltage. Thus, the frequency of the ring oscillator varies alongside the voltage at V-GND. After the voltage at V-GND is elevated, the emitting present across the tail NMOS transistor is large. Subsequently, the frequency of the ring oscillator is high. The opposite happens after the voltage at V-GND is low. The frequency of the ring oscillator increases monotonically as the power voltage increases beforehand the tail NMOS transistor goes into the saturation region. The frequency of the ring oscillator can be facilely computed employing a binary counter. In our design, a ripple counter was requested employing D flipflops (DFFs). The D input of every single DFF is related Page | 9
International Journal of Advanced Engineering, Management and Science (IJAEMS)
to its output Q.The output Q of every single DFF is related to the timepiece input of the flip flop at the subsequent period of the counter. At every single two consecutive toggles of every single flip flop, one toggle of the subsequent flip flop is activated, thereby bestowing binary counting. Therefore the worth of the binary counter at the conclude of the examination era is undeviatingly proportional to the frequency of the VCO. The output of the counter embodies a examination signature that embodies the voltage level at the adjacent earth node. The perish signature can be facilely transferred to the tester by employing design- fortestability constructions such as scan shackles and examination wrappers that are public in logic cores. In order to recognize flawed dies, the signature of every single tested perish have to be contrasted to a precomputed fault-free signature. Though, a solitary obligation free signature is not adequate to ascertain whether a perish is defective or obligation free. The reason is that the voltage at V-GND could deviate from the anticipated worth and be yet satisfactory endowed that the number of wake-up cycles limits of the core are not exceeded. Thus, it is extra realistic to accept that the power switches are defect free if the voltage at V-GND lies amid an higher attached and a lower attached, these bounds depend on the power-off mode. 5. Effective DFT Method: 5.1. Fine Grain :
Fig. 5 Fine Grain Design 5.2. Coarse Grain:
Fig. 6 Coarse Grain Design
[Vol-1, Issue-2, May- 2015] ISSN: 2454-1311
Power switches are normally requested in whichever “fine-grain” or “coarse-grain” design styles. A fine-grain style incorporates a power switch inside every single average logic cell alongside a power gesture to switch on/off the power supply of the cell. In the coarse-grain design style, a number of power switches are joined to feed a block of logic. After contrasting the two design styles, the fine-grain design simplifies the combination of power gating across continuing EDA instruments, but it has a higher span overhead and is extra vulnerable to voltage drop variations due to procedure, voltage, and temperature (PVT) variations . Domination switches are requested in two power modes, that provides a tradeoff amid leakage power saving and wake-up time. Designfor-test (DFT) resolutions for power switches alongside intermediate power-off mode have been presently proposed. Therefore, this paper focuses on power switches alongside a finished power-off mode. Diagnosis is a systematic method to exceptionally recognize the defect provoking malfunction in the route , Current scutiny has described a number of DFT resolutions to examination power switches after pondering the two probable kind of faults: stuck-open and stuck-short .Stuck-open obligation models a physical scenario whereas the drain or basis of a transistor is disconnected managing to a defective transistor behavior. Assessing such faults need two examination vectors. The early examination vector propels the output of a transistor to logic elevated or low, as the subsequent examination vector complements the output logic worth employing every single transistor in the pull-up or pull-down web .Stuck-short faults produce a leading trail amid Vdd and earth and could be noticed by a examination method shouted IDDQ assessing that monitors the present flow across a steady-state condition . this DFT resolution suffers from long discharge period after the power switches are coiled off. This leads to long examination period due to the necessity of requesting a slower examination timepiece and could lead to fake examination .This setback was addressed in across an competent DFT resolution, that added a low-leakage (high Vth) discharge transistor segment to the DFT. This is because the discharge transistor is switched off across normal procedure of the design, consequently elevated presentation and leaky (low Vth ) transistors are unnecessary. This is why a elevated Vth (low presentation ) nMOS transistor is utilized as a discharge transistor This DFT resolution is shown in the counseled DFT achieves fast examination period across balanced price and discharge periods and eliminates the potential of a fake examination The drawback of such a method is that it is not probable to find the precise cause of supplementary Page | 10
International Journal of Advanced Engineering, Management and Science (IJAEMS)
stay managing to IC timing violation, and consequently it is not probable to discriminate amid the stay obligation provoked by power switches, logic gates, or interconnects on the defective trails, thereby altering negatively the finished diagnosis accuracy. III.
RESULT ANALYSIS
1. Power Gating: In this serving, two models in that the manipulation switches can be utilized is experimentally analysed to find that ideal produces larger manipulation consumption abilities for a logic block. We have counseled a diagnosis that is competent in recognizing the attendance of defective manipulation switches in a route alongside the aid of a set of examination vectors. The manipulation switches are tear into segments that aftermath in elevated diagnosis accuracy. Validation is completed across TSPICE and the output is discovered to be exceedingly efficient. Every single segment is selected separately and the locale of obligation is tested out.
[Vol-1, Issue-2, May- 2015] ISSN: 2454-1311
a defective power switch stays undetected by the diagnosis algorithm. PFD mentions to the working point whereas, due to slower gesture transition (than at 1.0 V, 25 °C), it appears as if there is a flawed power switch in a segment nevertheless it is fault-free. The aftermath are generated employing three working voltages (0.9, 1.0, and 1.1 V; 10% variation of nominal Vdd) and, at every single working voltage, the stay is simulated at five working temperatures (−25 °C–125 °C), alongside a pace size of 25 °C) employing the C432 benchmark design ,Fall stay is simulated at the output of NAND gate employing HSPICE. that the plummet stay is minimum at (1.1 V, −25 °C) and maximum at (0.9 V, 125 °C). This is because the transistor stay reduces as the working voltage increases and it reduces more at lower temperatures . This way that, after working at 1.1 V and low temperatures, it is probable that obligation result is masked out by reduction in gesture transition stay, managing to what is shouted “diagnosis escape.” Similarly, after working at 0.9 V and elevated temperatures, it is probable that the diagnosis algorithm incorrectly diagnoses (“false diagnosis”) a design as defective after it is truly fault-free, due to sluggish gesture transition at this working point, after working at 1.0 V and 25 °C, after pondering both stuck-open and stuck-short faults. We led two sets of examinations to examine the result of PVT variations on the accuracy of counseled diagnosis algorithm.
3. Effective DFT Method: Fig. 7 Simulated Output
2. Multimode Power Switches: In this serving, we early examine the counseled diagnosis algorithm lacking pondering the result of procedure variation and next below the impact of procedure variation. In particular, we examine the result of two working points that can potentially lead to defeat of diagnosis accuracy, denoted to as possible diagnosis getaway (PDE) and possible fake diagnosis (PFD).
To validate the effectiveness of our counseled DFT resolution a number of examinations have been grasped out on assorted ISCAS benchmark routes employing ST 90nm procedure knowledge libraries[3]. First, the timing data corresponding to the turn-on actions of the power switches is described employing HSPICE.
Fig. 9 Simulated Output
Fig. 8 Simulated Output These two working points are shown in Fig ,PDE mentions to the working point whereas, due to faster gesture transition (than at 1.0 V, 25 °C), it is probable that
This data is next utilized for arranging the stay agents, that are consolidated in the route below examination alongside alongside the power switches.The examination periods of the DFT resolutions in analogy depend on the number of the segments m and the number of examination timepiece cycles needed for assessing the power switches. Page | 11
International Journal of Advanced Engineering, Management and Science (IJAEMS)
The number of examination clockcycles demanded by is (2 ∗ m + 1), as that for our DFT resolution is (2 _log2m_ + 3) [3]. The early column displays the disparate number of the segments, as the subsequent two columns display the examination period for assessing power switches employing both DFT solutions. The pursuing column displays the examination period savings of the counseled DFT resolution contrasted to and the last column indicates the speedup of the counseled DFT resolution .As can be perceived, as the examination period needed by increases linearly alongside the number of the segments in power switches, our counseled DFT gives exponential savings for the alike number of segments in power swithces. Moreover, after the mechanism is faultfree, our resolution completes assessing in 4 cycles even though of the number of segments. Though, in the DFT resolution ,all the segments have to be tested one by one even nevertheless the mechanism is fault-free and that will give the worst case stay of (2m + 1) examination cycles[7]. Assessing the assessing speeds amid the DFT resolutions, it can be perceived that our DFT resolution achieves a speedup of concerning three orders of magnitude for 6-segment power switches, counseling that the counseled DFT resolution is an appealing option for assessing power switches for SoCs alongside a colossal number of segments. Furthermore, our counseled DFT way efficiently identifies the locale of solitary faults across tear and vanquish established examination power. referred to in the text solely by a number enclosed in a round bracket (i.e., (3) reads as "equation 3"). Ensure that any miscellaneous numbering system you use in your paper cannot be confused with a reference [4] or an equation (3) designation.
[Vol-1, Issue-2, May- 2015] ISSN: 2454-1311
benchmarks synthesized alongside a 90-nm gate library. Experimental aftermath displayed that, below nominal working conditions (at 1.0 V, 25 °C, and lacking pondering procedure variation), it might accomplish nearly 100% accuracy. In case of VT variations, the worst case defeat of accuracy was less than 12%, and in the end below the impact of procedure variation, the worst case defeat of accuracy was less than 4.5%. REFERENCES [1] “Delay Test for Diagnosis of Power Switches”.Saqib Khursheed, Kan Shi, Bashir M. Al-Hashimi, Fellow, IEEE, Peter R. Wilson, Senior Member, IEEE, and Krishnendu Chakrabarty, Fellow, IEEEJ. [2] “Systematic Diagnosis of Power Switches”. D Ruth Anita Shirley ,M.E. VLSI Design ,SNS College of Technology ,Coimbatore, India ,ruthshirley06@gmail.com [3] “A Fast and Effective DFT for Test and Diagnosis of Power Switches in SoCs” Xiaoyu Huang, Jimson Mathew, Rishad A. Shafik, Subhasis Bhattacharjee, Dhiraj K. Pradhan, Department of Computer Science, University of Bristol, UK; E-mail: csxjm@bristol.ac.uk. [4] “Signature Analysis for Testing, Diagnosis, and Repair of Multi-Mode Power Switches”. Zhaobo Zhang1, Xrysovalantis Kavousianos1,2, Yan Luo1, Yiorgos Tsiatouhas2 and Krishnendu Chakrabarty1,Duke University, 27708 Durham, NC, USA , University of Ioannina, 45110 Ioannina, Greece [5] S. K. Goel, M. Meijer, and J. de Gyvez,“Testing and diagnosis of power switches in SOCs,” in Proc. Eur. Test Symp., May 2006, pp. 145–150 [6] Z. Zhang, X. Kavousianos, Y. Luo, Y. Tsiatouhas, and K. Chakrabarty,“Signature analysis for testing, diagnosis, and repair of multi-modepower switches,” in Proc. Eur. Test Symp., May 2011, pp. 13–18. [7] S. Khursheed et al., “Improved DFT for Testing Power Switches,” in Proc. of European Test Sympoisum (ETS), pp. 7-12, 2011.
IV. CONCLUSION We have counseled a diagnosis that is competent in recognizing the number of faults and the locale of the power switches. With the aid of a DFT, the power switches are tear into segments that aftermath in elevated diagnosis accuracy. Validation is completed across TSPICE and the output is discovered to be 96% efficient. Every single segment is selected separately and the locale of obligation is tested out reliant on the algorithm. We clarified an effectual diagnosis method to recognize the locale and number of defective power switches in a design. It utilizes an effectual DFT resolution for assessing power switches. The counseled method tear power switches into segments and uses the transition stay examination to accomplish extremely elevated diagnosis accuracy. The diagnosis method was validated across SPICE simulation employing a number of ISCAS Page | 12