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CONTENTS

UNIT 1

01-29

NUMBER SYSTEMS AND LOGIC GATES UNIT – II

30-38

SIMPLIFICATION OF LOGICAL EXPRESSIONS UNIT – III

39-57

COMBINATIONAL LOGIC SYSTEMS

UNIT IV

58-87

SEQUENTIAL LOGIC SYSTEMS UNIT – V

88-106

D/A AND A/D CONVERTERS

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UNIT I NUMBER SYSTEMS AND LOGIC GATES

There are four systems of arithmetic that are frequently used in digital systems

Decimal

Binary

Hexadecimal and

Octal

DECIMAL NUMBER SYSTEM

The decimal number system consists of ten symbols: 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9. Since it has ten symbols, its radix (or base) is said to be 10. The decimal number system is often called a ‘base 10’ system.

Note : Even though we call it a decimal (10) system, it does not a have a symbol 10. It is a combination of 1 and 0.

Using the ten symbols in the decimal system any number can be expressed using the method of ‘positional weighing’.

Consider the number 693. It can be split down as follows.

Hundreds 693

Tens

600

+90

6x10

+9 x 10

1 digit

2 digit

Units +3

+3x10° th

0 digit

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The digit 6 represents 600 because it is placed three positions to the left of the decimal point. The digit 9 represents 90 because it is positioned two positions to the left of decimal point. The digit 8 represents 8 units because of its placement one position to the left of decimal point. This is an example of place value in decimal number system.

The principle of positional weighing can be extended to any number system. Any number can be represented by the equation. n

Y = dn xr + dn-1 x r

n-1

+ ........ + d0 x r

Where Y is the value of the entire number, dn is the value of n digit from the point and r is the radix or base.

BINARY NUMBER SYSTEM The binary number system uses only two symbols 0 and 1. So it is called ‘base 2’ system. The radix or base is 2. The positions of these 0 and 1 are called ‘Bits’ (Contraction of the word binary digits). The binary number system also uses the idea of ‘place value’. The counting in binary system is similar to that in decimal counting. This is shown below in Table 1.1

Table 1.1

Decimal Symbol

Binary Symbol

100

101

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110

111

1000

1001

The binary equivalent of decimal 0 is a 0

The binary equivalent of decimal 1 is a 1

The next number in decimal is 2. The binary equivalent of decimal 2 is obtained by adding a 1 to the second column and resetting the first bit to 0. I.e. the binary equivalent of decimal 2 is 10. This is similar to the decimal system when counting proceeds from 9 to 10.

Consider the binary number 1011

Place value

Binary number

Decimal equivalent

+1=11

(There are one 8; zero 4; one 2 and one 1)

Decimal equivalent is obtained using the placement rule. 3

1 x 2 + 0 x 2 + 1 x 2 + 1x2 = 8 + 0 + 2 + 1 = 11

Using the above procedure a binary number can be converted into an equivalent decimal number.

The 4-Bit system and its equivalent decimal values are shown below in Table 1.2.

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Table 1.2 Binary

Number

Decimal equivalent

Number

Decimal equivalent

0000

1000

0001

1001

0010

1010

0011

1011

0100

1100

0101

1101

0110

1110

0111

1111

OCTAL NUMBER SYSTEM

The octal number system uses eight symbols 0, 1, 2, 3, 4, 5, 6, 7. [octal means eight]. Octal numbers are referred to ‘base 8’ numbers. This means the radix or base is 8. Octal number system can be written as

dn x R + ………….+d1 x R + d0 x R

dn x 8 + ………….+d1 x 8 + d0 x 8

Where the digits dn ……….. d0 are 0, 1, 2, 3, 4, 5, 6 or and R = 8 is the Consider the Octal number, (37)8

This is read as 37 to base 8

(37)8

3x8 +7x8

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3x8+7x1

24 + 7 = (31)10

Relation between octal, binary and decimal numbers

Table 1.3

OCTAL

BINARY

DECIMAL

000

001

010

011

100

101

110

111

001000

001001

Etc.

Consider (67)8 (Read it as 67 to base 8) Octal 6

equals 110 in binary

Octal 7

equals 111 in binary

Combining binary groups

(67)8

(110111)2

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HEXADECIMAL NUMBER SYSTEM The hexadecimal number system is a ‘base 16 number system’. It uses 16 symbols 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F. The decimal number and their equivalent hexadecimal numbers are given in Table 1.4.

Table 1.4

Hexa Deci.

Decimal

Binary

Hexa Deci.

Decimal

Binary

Number

Value

Number

Value

0000

1000

0001

1001

0010

1010

0011

1011

0100

1101

0101

1110

0110

1110

0111

1111

In hexadecimal system A stands for 10, B stands for 11 and so on. Finally F stands for 15.

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The positional values of hexadecimal numbers, from right to left are 16 , 16 , 16

Consider the hexadecimal values of hexadecimal number (24)16

(24)16

2 x 16 + 4 x 16

32 + 4

93610

CODE CONVERSIONS

DECIMAL-BINARY CONVERSIONS

1. Binary To Decimal

Conversion of binary to decimal requires adding the value for each position of the number having a binary digit 1.

Example : Find the decimal value of the binary number 101011

1 x 2 + 0 x 2 + 1 x 2 + 0 x 2 + 1 x 2 + 1 x 20

32 + 0 + 8 + 0 + 2 + 1 = 43

The following table will help to convert a binary number into decimal value.

Table 1.5 gives the value of places left of binary point and in powers of 2.

Table 1.5

512

256

128

Exercise : Convert the following binary numbers into equivalent Decimal values

a. 1011 b. 10110

c. 110111

d. 11001101

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Answer:

a. 11

b. 22

c. 55

d. 205

2. Decimal to Binary

Decimal to binary conversion is done by repeated division by 2 and using the ‘remainders’ as conversion value.

Example 1.1

Convert (26)10 into binary

1 -2

3 -2

0 with 1 MSD

1 with 1

3 -2

3 with 0

13 -2

26 -2

6 with 1

13 with 0 LSD

decimal number radix in binary

Quotient Remainder

The last remainder is the MSD (most significant digit) and the first remainder is the LSD (least significant digit).

The binary equivalent of (26)10 is 11010. Exercise :

Convert the following decimal numbers into binary numbers

a. 20010 =

11001000

b. 3710

100101

c. 4310

101011

OCTAL DECIMAL CONVERSIONS

1. Octal to Decimal

Using the positional value we can convert an octal number into decimal value.

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Example : Convert (3)8 into decimal number

(36)8

3x8 +6x8

3 x 8 + 6 x 1 = 24 = 6 = (30)10

2. Decimal to Octal

Decimal to octal conversion is performed by using the repeated division by 8 and using the remainders as conversion value.

Example 1.2

Convert (127)10 into binary

1 -8

15 --8

127 ---8

0 1 15 The conversion value is 177. with with with 1 7 7 i.e. (127)10 Exercise :

decimal number radix in binary

Quotient Remainder

(177)8

Convert the following decimal numbers into octal numbers

a. (255)10

(377)8

b. (498)10

(762)8

c. (63)10 =

(77)8

OCTAL â&#x20AC;&#x201C; BINARY CONVERSIONS

1. Octal to Binary

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This conversion is very simple. Each octal digit is converted into its 3 – Bit binary equivalent.

Example : convert (67)8 into binary.

Octal 6 is equal to 110

Octal 7 equals 111

Combining the binary groups we get

678

1101112

Exercise : (276)8 = (?)2 Answer : (010111110)2 2. Binary to Octal Conversion

Reversing the above process, we can convert a binary number into its octal value.

Example Convert (100001110)2 into octal

Answer : (416)8

DECIMAL – HEXADECIMAL CONVERSION

1. Decimal to Hexa Decimal

Conversion of a decimal number to a hexadecimal number is done by repeated division by 16. The remainders give the hexadecimal value.

Example 1.

Convert (152)10 into binary

9 ---16

152 ---16

decimal number radix in binary

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0 with 9

9 with 8

Quotient

Remainder

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Thus, (152)10 = (98)16 Exercise : Convert the following decimal numbers into hexadecimal numbers.

a. 42310 =

1A716

b. 95

5F16

c. 249

F916

2. Hexadecimal to Decimal

A hexadecimal number can be converted into a decimal number by positional weighing.

Example :

Convert (23016 into decimal number

(23)16

2 x 16 + 3 x 16

2 x 16 + 3 x 1

32 + 3

(35)10

Exercise : Convert the following hexadecimal numbers into decimal numbers.

a. B4A16

289010

b. 2416

3610

c. 1F16

3110

d. A216 =

16210

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HEXADECIMAL – BINARY CONVERSION

1. Binary to Hexadecimal The given binary number is grouped into ‘four bit’ groups. Each four bit is replaced by its hexadecimal equivalent. The grouping is done starting from right end.

Example : convert the binary number 1011101010010010 into hexadecimal value.

Thus (1011101010010010)2 = BA9216

101011010 = 0010, 1011, 1010

2BA16

2. Hexadecimal to Binary Conversion

Conversion of a hexadecimal number to binary number is performed by expressing each hexadecimal digit by four binary digits.

Example : Convert AE16 into binary

1010

1110

(AE)16 = (10101110)2

Exercise : Convert the hexadecimal numbers into binary

a. (F019)16

1111000000011001

b. A2C16

101000101100

BINARY CODES

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There are number of binary codes which can be classified into two groups

1. Weighted binary code and

2. Non-weighed binary code

Weighted Binary Code

Weighed binary codes obey the positional weighing principle.

The position of a

number represents a specific weight. The normal binary counting sequence is an example for this. Each column has a weight; 8, 4, 2 or 1. This code is called 8421 code. It is also called as BCD code. (Binary Coded Decimal).

Like the 8421 code, there are other weighed binary codes : 2421, 5211, X53. These binary codes are shown in Table 1.6.

Table 1.6 Binary Coded Decimal Numbers 9bCD numbers)

Decimal

8421 Code

2421 Code

5211 Code

X53 Code

0000

0011

0001

0100

0010

0011

0101

0011

0010

0101

0110

0100

0111

0101

1011

1000

0110

1100

1010

1001

0111

1101

1100

1010

1000

1110

1011

1001

1111

1100

Sequential code

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A sequential code is one in which each succeeding code is one number greater than the preceding code.

Example :

8421 and XS3 codes.

Reflective codes

A reflective code is one in which the code for 9 is the complement of code for 0 (also 8 for 1, 7 for 2, 6 for 3 and 5 for 4).

Example :

2421, 5211 XS3 codes.

Non-Weighed Codes

Non weighed binary codes are not positional weighed. Each position of a number is not given a specific values. Examples are XS3 code and Gray code. EXCESS – 3 CODE [XS3 CODE]

It is a non-weighed code. It is used to represent decimal numbers. It is given in table. A code in XS3 code is the corresponding 8421 code +0011(3). [There is an excess value of 3].

XS3 code = 8421 code + 0011

Thus the decimal 0 has a value 0000 in 8421 code. Its value in XS3 code is 0011. The value of 4 in 8421 code is 0100. In XS3, the value of 4 is 0111.

Addition of two XS3 numbers in performed by simply adding the binary numbers. If there is no ‘carry out’ from the additions, subtract 0011.

Example :

Add 2 + 4 in XS3

Decimal 2 in

XS3 is

0100

Decimal 4 in

XS3 is

0111

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1100 (No carry out) Subtract

0011 6=

1001

If the addition results in a carry out then add 0011

Example : Add 6 and 8 in XS3

Decimal 2 in

XS3 is

0100

1001

1011

Sum

10100

Add

0011

10111

Gray Code

In binary code when count proceeds from 1111 to 0000 (or 0111 to 1000) all bits charge simultaneously. If the change in any one bit is faster than the others, then error will come in. Gray code eliminates this error.

In Gray code only one bit will change each time the decimal number is incremented. The Gracy code is given in Table 1.7

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Table 1.7 â&#x20AC;&#x201C; Gray code

Decimal

Gray

Decimal

Gray

0000

0101

0001

0100

0011

1100

0110

1101

0110

1111

0111

In binary code, when count proceeds from 7 to 8 all the bits changes; 0111 to 1000, whereas in Gray one bit changes: 0100 to 1100.

Alphanumeric Code

A code used to represent both alphabetic and numeric characters is called alphanumeric code. There are number of alphanumeric codes of which ASCII code is very popular.

ASCII Code The word ASCII stands for American Standard Code (ASCII â&#x20AC;&#x201C; American Standard Code for Information Interchange) used by many Input/output devices. th

ASCII code is a 7-bit code. The 8 bit is generally used to represent parity. In this code, both lower and upper cases can be represented (like a and A). It also allows special characters like +, *, =.

There are over 30 commands or control operators (e.g. start of

message, end of message, carriage return, line feed etc).

The ASCII code for decimal digits, alphabetic characters, and a few special characters is given in Table.

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ASCII Code Table

MSB LSB 0

Hex Binary

000

001

010

100

101

110

111

NUL

DLE

SOH

DC1

STX

DC2

“

EXT

DC3

EOT

DC4

END

NAK

ACK

SYN

BEL

ETB

‘

0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111

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CAN

(

)

SUB

ESC

;

{

]

}

DEL

1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 Error Detecting Code

Digital system must be very accurate. There should not be error in any digit while transmitted. If error occurs the binary is ignored or transmitted again.

There are number of schemes to detect the error in data during transmission. One simple scheme is ‘Parity detection’.

PARITY

When a word (binary data) is transmitted, an extra bit is added. This bit is known as ‘parity bit’.

Odd parity For odd parity, the extra bit added is set to a ‘0’ or a ‘1’. So that the total number of 1s in the entire word is ‘odd’.

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Example :

Parity Bit

(7-bit Data)

Total 1s

1010110

1110011

0100001

0000000

In the above example, the total number of 1s, including the parity bit, is always odd. This 8 bit data (7 data bits +a parity bit) is transmitted.

At the receiving end, the parity is checked. If parity is even, then retransmission is requested.

Even parity Even parity can also be used. The ‘parity bit’ is set to a ‘o’ or a ‘1’, so that total number of bits in the entire word is even.

Example :

Parity Bit

(7-bit Data)

Total 1s

11010111

0000111

1010000

Note : In parity check-up method, if two errors occur, it can not be detected.

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CHECK SUMS To overcome the difficulty in parity check method, the ‘Check sum’ method is used. Each word is added to the previously transmitted word so that the sum is retained.

First word

10110011

Second word

00101001

Sum

11011100

BASIC LOGIC GATES

Logic gates are circuits that perform AND, OR, NOT operations. They are available in integrated circuit (IC) form. The logic symbol and truth tables of these gates are given.

AND Gate

Input

Output

A.B

A A.B B Fig. Logic Symbol of AND Gate

When any one input or both input low the output is ‘O’. The out put is a ‘1’ when A and B are both 1s.

OR Gate (Inclusive) (OR Gate)

A+B

A A+B

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Fig. Logic Symbol of O R Gate

When both inputs are ‘O’ the output is a ‘O’ when the input A or B is a ‘1’. It is ‘inclusive’ of one more operation that the output is a ‘1’ for both inputs at ‘1’.

NOT Gate (Inverter)

Input

Output

Fig. Logic Symbol of NOT Gate

A NOT gate complements the input i.e. it inverts.

XOR Gate (Exclusive OR Gate)

AB

A AB

Fig. Logic Symbol of XOR Gate

The last combination that both inputs at ‘1’ is exclusive (not allowed). So for this, output is ‘O’ (For NAND and NOR gates see Demorgan’s laws).

Boolean Theorems

There are tweleve theorems of Boolean Algebra. They are used to simplify complex relation between Boolean variables.

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Duality Theorem

Dual of a Boolean expression can be obtained by

(i)

Changing all ‘.’s into ‘+’s.

(ii)

Changing all ‘+’s into ‘.’s.

(iii) Changing all ‘1’s into ‘0’s. (iv) Changing all ‘0’s into ‘1’s.

(v)

Not complementing any literal

Boolean Theorems

Theorem 1(a)

Theorem 1(b)

0.A=0

1+A=1

0 . anything = 0

1 + anything = 1

Theorem 2(a)

Theorem 2(b)

1.A=A

0+A=A

1 . anything = anything

0 + anything = anything

Theorem 3(a)

Theorem 3(b)

A.A=A

A+A=A

Theorem 4(a)

Theorem 4(b)

A=0

A+

A =1

These first four theorems and their duals can be verified (proved) using the truth tables of AND and OR gates respectively.

Commulative Laws

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The positions of variables can be interchanged.

Theorem 5(a)

Theorem 5(b)

A . B = B.A

A+B=B+A

Associative Laws

A variable can be associated first with any variable.

Theorem 6(a)

Theorem 6(b)

A.B.C = A.(B.C) = (A.B).C

A+B+C=(A+B)+C=A+(B+C)

DEMORGAN’S LAWS

Theorem 7(a) First Law: The complement of a product is equal to sum of the complements.

AB  AB Proof: The law can be proved by the method of induction (i.e. substitution all possible values for the variables).

Cost i.

A = 0, B = 0

Then left hand side

Right hand side

0.0  0 1

0  B  1  1 1

0.1  0  1

Case ii. A = 0, B = 1

Then left hand side

Right hand side

0  1  1  0 1

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Case iii. A = 1, B = 0

Then left hand side

Right hand side

0.1  0  1

1  0  0  1 1

Case iv. A = 1, B = 1

Then left hand side Right hand side

1.1  1  0

= =

1  1  000

Since Left Hand Side is equal Right Hand Side the law is proved.

A.B

_ A _ B

A.B

Fig. Circuit for L.H.S.

Fig. Circuit for R.H.S.

In the circuit for L.H.S., the NOT gate follows the AND gate. This combination is called NAND gate. A A.B B

Fig. Symbol of NAND gate

7(b) Second Law : The complement of a sum is equal to product of the complements.

Proff :

Case i. A = 0, B = 0

Left Hand Side

Right Hand Side

00  0 1 =

0.0 = 1.1 = 1

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Case ii. A = 0, B = 1

Left Hand Side

Right Hand Side

0 1  1  0

0 . 1  1.0  0

Case iii. A = 1, B = 0

Left Hand Side

Right Hand Side

1 0  1  0

1 . 0  0.1  0

Case iv. A = 1, B = 1

Left Hand Side

Right Hand Side

11  1  0 1 . 1  0.0  0

Since all Left Hand Sides are equal to the Right Hand Sides the law is proved.

A.B

_ A _ B

A.B

Fig. Circuits of LHS

Fig. Circuits for RHS

In the circuit for LHS the NOT gate follows the OR gate. This combination is called NOR gate.

AB

Fig. NOR Gate

Note :

NAND and NOR gates are the outcomes of DeMorgan’s Laws. They are called ‘Universal Gates’. This means NAND and NOR gates can be used to perform

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the functions of other gates namely AND, OR, NOT and XOR.

Theorem 8(a)

Theorem 8(b)

Distributive Law A(B+C) = AB + AC

A+(B.C) = (A+B).(A+C)

Theorem 9(a)

Theorem 9(b)

AB + A. B =A

(A+B) . (A +

The variable which appears in constant (same) form in all terms will be the answer.

Theorem 10(a)

Theorem 10(b)

A + AB = A

A.(A+B) = A

If a smaller term appears in a larger term as such (same form) then the smaller term is the answer.

Theorem 11(a)

Theorem 11(b)

AB+ A C+BC =AB+ A C

(A+B) ( A +C)(B+C)=(A+B)( A +C)

Variable A is available in two forms in the first two terms. The third term which includeds the two coefficients of A (B and C) is redundant (i.e. varishes).

UNIVERSAL GATES

NAND and NOR gates are called universal gates. Using NANDs only or NORs only other logic functions AND, OR, NOT and XOR can be performed.

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NAND AS UNIVERSAL GATE

1. NAND as NOT gate

The two input terminals are connected together.

Fig. NAND as NOT gate

2. NAND as OR gate Ā

AB

Fig. NAND as OR gate

3. NAND as NOR gate

(In the above circuit and another NAND as NOT gate).

Ā A A+B

AB

_ B

Fig. NAND as NOR gate

4. NAND as AND gate

A.B A.B

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Fig. NAND as AND gate

5. NAND as XOR gate _____ A.A.B A

___ ___ A.B A.B

___ A.B

_____ B.A.B

Fig. NAND as XOR gate

NOR AS UNIVERSAL GATE

1. NOR as NOT gate

__ A

Fig. NO as NOT gate

2. NOR as OR gate A

A+B

Fig. NOR as OR gate

3. NOR as AND gate

A A A .B B B

Fig. NOR as AND gate

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4. NOR as NAND gate

(In the above circuit add a NOR as NOT gate)

___

_ A

A-B

_ B

Fig. NOR as NAND gate

NOR as XOR gate

____ A +B

A B

AB + AB A ____ A .B B

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UNIT – II

SIMPLIFICATION OF LOGICAL EXPRESSIONS

INTRODUCTION TO COMBINATIONAL LOGIC

Combinational logic system is a logic network in which the outputs are the direct result of inputs. The logic network consist of gates and other components. Some examples of combinational logic circuits are adders, subtracters, decoders, encoders, multiplexers, demultiplexers etc. Combinational circuits do not have a memory. In this they differ from sequential circuits.

SUM-OF-PRODUCT (SOP)

A direct way to get a logic expression is by reading the terms for which the output is a 1 in the truth table. This gives a logic expression that is a ‘Sum of Products’ form. It is an orderly way of expressing a logic function.

Consider the following truth Table 1.Truth Table 1

OUTPUT

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The sum of production (SOP) in the given table can be written for which the output is a ‘1’.

Output =

A . B . C  A . B. C  A . B . C  A . B . C

In the above logical expression for SOP each term is called a ‘minterm’. ‘Minterm’ means fundamental products. It is a kproduct (ANDing) of all the variables in the system.

Example 1 : Write down the SOP from the following table

Truth Table 2

Answer :

OUTPUT

A . B .C  A . B . C  A . B. C  A . B . C  A . B . C  ABC

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PRODUCT-OF-SUMs : (POS) A logical expression can also be written using ‘maxterms’ for which the output is a ‘O’.

Maxterm : Fundemental sum (ORing) of the inverted logic variable. Consider the Truch Table 3 given below.

Truth Table 3

OUTPUT

POS output = (A+B+C) . (A +

B  C ) . (A  B  C)

Example 2 : Write down the POS from Table 1.

Answer : POS output =

A  B  C . A  B  C . A  B  C

REDUCING BOOLEAN EXPRESSIONS USING BOOLEAN LAWS

A Boolean expression can be reduced by using Boolean laws (theorems). Simplification gives reduced form of Boolean expression. A stage will be reached when no

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further reduction is possible. For the reduced Boolean expression the logic circuit may be implemented. This means less number of gates and less cost.

Example 1. Reduce

Example 2. Simplify

Example 3 : Simplify

A . B + (B+C)

A.B+B+C

B.1+C

B+C

C(B + C) (A + B + C)

(BC + CC) (A + B + C)

(CB + C) (A + B + C)

C(B + 1) (A + B + C)

C(A + B + C)

C(A + B + 1)

A . B . C  A . B. C  A . B. C

A . B C  C  A . B . C

A . B. 1  A . B . C

A . B.  A . B . C

1 + anything = 1

KARNAUGH MAP

Karnaugh map method is a technique employed to reduce (simplify) Boolean expressions. This technique may be used to any number of variables, but in practice not more than six. The K’map method consists of the following steps.

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Construction of the map

Entering the map

Reading the map

TWO VARIABLE K MAP ConstructionThe number of ‘boxes’ or ‘cells’ in a K’ map is equal to the number of possible combinations of the variables. For two variables, there are four possible combinations of the variables. (Namely 00.01, 10 and 11, or in literals A = 1 and

A B, A B, A B and AB. Here A means

A means A = 0). The boxes can be arranged linearly (lengthwise) or squarly.

The boxes are arranged in a particular fashion. The boxes are numbered according to ‘reflected’ binary ordering’ or ‘Gray code ordering’ as shown below.

The boxes should be numbered only in this ordering so that only one variable changes at a time when we move from one box to the next.

Entering the map

Consider the Boolean expression AB + A

B . There are two terms AB and A B . Only two

boxes corresponding to these are to be entered. The first term represents A = 1 and B = 1. The second term represents A = 1 and B = 0. So the corresponding boxes are marked with a ‘1’. It means such a term is available in the Boolean expressions. The entered K map is shown in Figure.

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Reading the map

After the 1s are entered they are combined by means of one or more number of ‘loops’, following certain rules.

Rule 1

Only adjacent is should be combined inside a loop (if the two is are not adjacent, loop cannot be formed and the B’ expression can not be reduced).

The loop formed combining the two 1s is shown in figure

AB 00

Fig.

Rule 2 Only 2, 4, 8, 16…….. numbers of 1s should be put inside a loop. (3, 5, 6, 7……. Number of 1s cannot be put in a single loop).

Example

AB  AB . The entered map with loops formed is

Consider the B’ expression AB +

shown. For three 1s two loops are formed.

AB 00

Fig.

Rule 3 No ‘1’ should be left uncombined.

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The loops provide the reduced expression. The variable or variables, which remain constants in a loop, give the result. AB 00

AB 00

A (Answer)

B+A (B logical OR A)

Fig.

Rule 4

K map is foldable on either ends (i.e. K map can be folded such that left edge touches right edge or top edge touches the bottom edge).

If the two 1s are at the two corners they can be put inside a loop.

AB 00

Fig.

THREE VARIABLE K MAP

A three variable K map consists of 8 boxes to represent the eight possible combinations of the three variable. The boxes in a column are numbered according to the reflected binary ordering.

The two rows represent the two possible values of C.

construction of three variable K map is shown in figure AB 00 01

The

0 1

Fig.

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Rule 5

Since each loop gives an answer (reduced expression) the number of loops should be less.

Rule 6

Try to form the biggest loop possible, because the bigger the loop the smaller is the reduced expression.

Rule 7 The isolated ‘1’ should be put in a loop first.

AB 00

C 0 1

AB 00

C 0

Fig.

Fig.AC

AB C 0 1

Fig.

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FOUR VARIABLE K MAP

Since there are four variable there are sixteen possible combinations of them. Two variables (A and B) are represented along the columns and two variables (C and D) are represented along the rows.

The binary reflected ordering should be followed while

numbering the boxes in columns as well as rows.

Example 1. AB CD

Fig.

Answer = C

Fig.

(Answer is ‘C’ because, C is constant for all the eight boxes) Example 2. AB

AB CD

11 10

Fig.

00 01

00 1

Fig.

(Rule 7 is important and also rule 5)

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UNIT – III COMBINATIONAL LOGIC SYSTEMS Combinational logic systems is a logic network in which the outputs are the direct results of inputs.

The logic network consists of gates and other components.

Some

examples of combinational logic circuits are Adders, subtractors, decoders, encoders, muliplexers, demultiplexers etc. HALF ADDERAddition of two bits is called ‘half addition’.

The circuit employed for half

addition is called ‘half adder’.

Truth Table for Half adder

Input numbers Sum S

Carry C

XOR

AND

Above Table showns that when two input numbers A and B are given, the ‘Sum’ is obtained by XOR operation and the carry is obtained by AND operation. So using XOR and AND gates a half adder circuit can be built as shown below. A

S =A  B

Full Adder

A HA

C =A.B

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Addition of three bits is called ‘full addition’ Circuit used for this is called ‘full adder’. The three bits added are two bits of the binary numbers and the carry from previous addition.

The truth Table for full addition is shown in Table. A and B are the two bits to be added and Ci is the carry from previous addition (initial carry). S is the sum and C 0 is the output carry to be added with next higher digit.

Truth Table for Full adder.

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

Carry from previous digit C1 0 1 0 1 0 1 0 1

Sum S 0 1 1 0 1 0 0 1

Carry to next digit C0 0 0 0 1 0 1 1 1

Fig. Full adder

Two Half adders and an OR gate are used construct a full adder. HALF – SUBTRACTER

When two bits are involved in subtraction it is half subtraction Circuit used for this is called “half subtracter”.

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Truth Table of Half Subtracter

Inputs

Outputs

Minuend A

Subtrahend B

Difference D

Borrow B0

Difference is obtained from XOR operation and borrow from

A . B operation.

D=AB

B B = A. B

Fig. Half Subtracter

Fig. Symbol

FULL – SUBTRACTER

In a full subtracter, we have to take into account inputs A and B and the borrow in. The truth Table is shown.

Truth Table of Full Subtracter

Inputs

Outputs

Borrow In (c)

Difference

Borrow out

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From the Truth Table we can write Difference =

A B C  A B C  A B C  A BC

Borrow out =

A B C  A B C  A BC  A BC

The above Boolean expressions can be reduced and implemented using half subtracters.

HS D

A B B

Fig. Full Subtracter

ONE’S COMPLEMENT OF A NUMBER

In a binary number change all 1s into 0s and all 0s into 1s. The new binary number obtained is called ‘one’s complement’ of the original number

Example :

Find one’s complement of

i. 1011

ii. 101101

Answer

i. 0100

ii. 010010

TWO’S COMPLEMENT OF A NUMBER If a 1 is added to the one’s complement of a number we get the two’s complement of the original number.

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Example :

Find one’s complement of

101101

Binary number

010010

Add

Two’s complement

01010011

Find two’s complement of

10101100

Binary number

01010011

Add

Two’s complement

01010100

SUBTRACTION USING TWO’S COMPLEMENT ADDITION Binary subtraction of two numbers can be performed by adding the two’s complement of the subtrahend (number being subtracted)

0111

Minuend

-5

1011

Two’s complement of subtrahend (5)

10010

0101

1010

1011

Discard final carry Answer = 0010 = 2 in decimal

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Example :

1001

-4

1100

0101

2s of 4 Neglect final carry

0100

1011

1100

Answer : 0101 [5]10 Example :

110010

- 101101

010011 1000101

- 2s of 101101 ignore carry

Answer = 000101

ENCODERS

Information is usually handled within digital systems in coded form.

There are

number of codes available (BCD code, Gray code, binary code, octal code, hexadecimal code etc.) Often it is required to convert from one code to another code. The process of generating these codes is called ‘encoding’. The circuit used for this is called ‘encoder’.

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Decimal to BCD encoder

The input device of a digital system is a set of keys (switches). When a key is pressed it generates a logic 0 or 1 level. In decimal to BCD encoder, there are 10 keys, each one corresponding to a particular decimal number. Four NAND gates are used to produce the BCD output. Note : For a NAND gate if any one input is a logic ‘0’, the output is a 1.

S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Fig. Decimal to BCD encoder D (8)

C (4)

B (2)

A (1)

When a switch for a decimal number is pressed the corresponding line goes LOW. The NAND gates connected to that lines produces an output logic 1. For example when S 4 is pressed the BCD output produced is 0100. [only C output is HIGH].

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Switch

0000

0001

0010

0011

0100

0101

00110

0111

1000

1001

pressed Decimal Number BCD output

Similary when S3 is pressed, the output A and B are HIGH. The output is 0011.

For encoding two digit decimal numbers we require two such arrangements, one for the first digit and the other for next digit.

Ex :

0100

0101

+VCC

1 7

2 3 4

7 8

Fig. Practical IC : 74147

Hexadecimal to Binary encoder

GND

The circuit arrangement is similar to decimal to BCD encoder.

16 switches are used to represent the inputs 0 through F

4 NAND gates are used to produce the binary outputs.

Octal to binary encoder

7 switches are used to represent the octal numbers 0 ........ 7

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3 NAND gates are used to produce the binary outputs.

Priority Encoder

A priority encoder is not generally used for encoding. It produces a unique output code for each input. The various inputs are arranged in order of priority. When two or more keys are pressed, the input having highest priority (say bigger number) is considered and the output is produced. For example when switches 5 and 2 are pressed, 5 will have highest priority, and an output 0101 is produced.

Truth Table of priority Encoder 741471C

No. 0 1 2 3 4 5 6 7 8 9

0 0 x x x x x x x x x

1 1 0 x x x x x x x x

2 1 1 0 x x x x x x x

Active low decimal input 3 4 5 6 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 x 0 1 1 1 x x 0 1 1 x x x 0 1 x x x x 0 x x x x x x x x x x

8 1 1 1 1 1 1 1 1 0 x

9 1 1 1 1 1 1 1 1 1 0

Active low BCD output D C B A 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 1 0 1 0 0 1 1 0 0 0 0 1 1 1 0 1 1 0

X â&#x20AC;&#x201C; means donâ&#x20AC;&#x2122;t care. i.e. may be 0 or 1.

DECODERS

A decoder performs the reverse (complementary) function of an encoder.

In a

decoder the binary input is decoded into decimal (or octal) form. The decoded output is used to drive display devices.

Decoders have either active HIGH or active LOW outputs.

Binary to Octal Decoder (3-to-8 decoder)

The three binary inputs are decoded into eight outputs. Each output represents one possible combinations of the inputs.

The three inverters provide the complement of the

inputs. Each AND gate generates an output.

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B2 B1

Fig. Binary to Octal decoder

Truth Table

Binary Inputs

Octal

Output

The outputs are mutually exclusive. i.e. only one output can be produced.

BCD to seven segment Decoder/Driver

Seven segment display is the most popular display device used in digital systems. To use the display device, the data in BCD format is decoded in suitable form.

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The decoder/driver has four BCD inputs and seven outputs. These outputs drive the seven segment display. The decoder outputs ‘a’ through ‘g’ are to be connected to the seven segments ‘a’ through ‘g’ respectively.

The block diagram of a BCD to seven segment decoder and a seven segment display are shown in figures and respectively.

b B

Decoder / Drover

c d

Fig. Decoder/Driver

b c

b g

d e

e f

e f g

Fig. Display

The output of a decoder can be active HIGH or LOW. For active LOW outputs, the seven segment display must be of ‘common anode’ type.

For active HIGH outputs, the

display must be of ‘common cathode’ type.

The truth Table of BCD to seven segment decoder/driver is given in Table [EX 7447]

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(Active High) BCD inputs

Decoder outputs (active Low)

Display

0 means segment is ON

1 means segment is OFF

PARALLEL BINARY ADDERS

A full-adder is capable of adding two 1-bit binary numbers and a carry-in. When two n-bit binary numbers are to be added, the number of full-adders required will be equal to the number of bits n in each number. Of course, the addition of LSBs can be done by using either a half-adder or a full-adder with Cin terminal grounded. The carry-out of each full-adder is connected to the carry-in of the next higher order adder. In parallel adder is used to add two numbers in parallel form and to produce the sum bits as parallel outputs.

A block

diagram of a 4-bit parallel adder capable of adding two 4-bit numbers designated as A3A2A1A0 and B3B2B1B0 is shown in Fig. The resulting output sum bits are S3S2S1S0.

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For example, if A3A2A1A0 = 1101 and B3B2B1B0 = 0101, we have

A0 B0 Cin S0 Cout  1  1 0  0 1  Least significan t stage   A1 B1 Cin S1 Cout  0  0 1  1 0    A 2 B2 Cin S2 Cout  1  1  0  0 1    A3 B3 Cin S3 Cout   1  0  1  0 1  Most significan t stage  

S4 We see that S3S2S1S0 = 0010. Since the carry-out from the most significant stage is a 1, we have an overflow, i.e. the sum (10010) must be expressed in 5 bits.

Parallel inputs

B Cin FA3

B Cin FA2

B Cin FA1

B Cin FA0

Cout

Fig. A 4-bit parallel binary adder Parallel outputs

Cascading Parallel Adders

An 8-bit parallel adder can be constrcted by cascading two 4-bit parallel adders as shown in Fig. One 4-bit adder (the lower order adder) is used to add the 4 LSBs of the inputs

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and the other (the higher order) adder adds the 4 MSBs. The carry-out from the lower order adder is the carry-in to the least significant stage of the higher order adder. Additional adders can be cascaded to create parallel adders for any number of bits.

MULTIPLEXERS (DATA SELECTORS)

Multiplexing means sharing. There are two types of multiplexing-time multiplexing and frequency multiplexing.

A common example of multiplexing or sharing occurs when

several peripheral devices share a single transmission line or bus to communicate with a computer. To accomplish this sharing, each device in succession is allocated a brief time to send or receive data. At any given time, one and only one device is using the line. This is an example of time multiplexing, since each device is given specific time intervals to use the line. In frequency multiplexing, several devices share a common line by transmitting at different frequencies. In a large mainframe computer, numerous users are time-multiplexed to the computer in such a rapid succession that all appear to be using the computer simultaneously.

A multiplexer (MUX) or data selector is a logic circuit that accepts several data inputs and allows only one of them at a time to get through the output. The routing of the desired data input to the output is controlled by SELECT inputs (sometimes referred to as ADDRESS inputs). Figure shows the functional diagram of a general multiplexer. In this diagram, the inputs and outputs are drawn as large arrows to indicate that they may constitute one or more signal lines.

D0 D1 Output Z

Data inputs

Fig. Functional diagram of a digital multiplexer DN - 1 MUX Select inputs

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The multiplexer acts like a digitally controlled multi-position switch. The digital code applied to the SELECT inputs determines which data inputs will be switched to the output. For example, the output Z will equal the data input D0 for some particular input code; Z will equal D1 for another particular code, and so on. In other words, we can say that a multiplexer selects 1-out-of-N input data sources and transmits the selected data to a single output channel. This is called multiplexing.

Basic 2-input Multiplexer

Figure shows the logic circuitry and function table for a 2-input multiplexer with data inputs D0 and D1, and data select input S. The logic level applied to the S input determines which AND gate is enabled, so that its data input passes through the OR gate to the output.

The output, Z = SD0 + SD1. When S = 0, AND gate 1 is enabled and AND gate 2 is disabled. So,

When S = 1, AND gate 1 is disabled and AND gate 2 is enabled. So,

Z = D0.

Z = D1.

Select input S

Z = D0 S+D1S D1

2 Fig. The 2-input multiplexer

Select input S

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The 74157 Quadruple 2-input Data Selector/Multiplexer

The 74157 consists of four separate 2-input multiplexers on a single chip. Each of the four multiplexers share a common data select line and a common





E Enable line as

shown in Fig. Because there are only two inputs to be selected from each multiplexer, a single data select input is sufficient. A LOW on the pass through to the output. A HIGH on the

E input allows the selected input data to

E input prevents data from going through to the

output, i.e. it disables the multiplexers. The ANSI/EEE logic symbol for this device is shown in Fig.

Enable

Data (1) select

(2) (4)

(5) (7)

En G1

(2) (3) 1 1 1B (5) 2A (6) 2B (11) 3A (10) 3B (14) 4A (13) 4B 1A

(3)

(15)

MUX

(4)

(7)

(9)

Data inputs 3A

(11) (9) (10)

4B Data select Enable

(14) (12) (13)

(12) 4Y

(6)

(1) (15)

Fig. The 74157 quadruple 2-input data selector/multiplexer

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Note that the four multiplexers are indicated by the partitioned output line and that the inputs common to all the four multiplexers are indicated as inputs to the ‘notched’ block at the top, which is called the ‘common control block’. All the labels within the upper MUX block also apply to the other blocks below it.

Note the 1 and

1 labels in the MUX block and the G1 label in the common control

block. These indicate dependency notation. In this case, G1 indicates an AND relationship between the data select input and the data inputs with 1 or

1 labels. (The 1 means that the

AND relationship applies to the complement of the G1 input). In other words, when the data select input is HIGH, the B inputs of the multiplexers are selected, and when the data select input is LOW, the A inputs are selected. The G is always used to denote AND dependency.

The 4-input Multiplexer

Figure a shows the logic circuitry for a 4-input multiplexer with data inpouts D0, D1, D2, and D3, and data select inputs S0 and S1. The logic levels applied to the S0 and S1 inputs determine which AND gate is enabled, so that its data input passes through the OR gate to the output. The function table in Fig. gives the output for the input select codes as

S1 S0 D 0  S1S0 D1  S1 S0 D 2  S1S0 D3

The 2-4-8-16-input multiplexers are readily available in the TTL and CMOS families. These basic ICs can be combined for multiplexing a larger number of inputs. Some packages contain more than one multiplexer, for example, the 74157 quad 2-to-1 multiplexer (four 2-to1 multiplexers having the same data select inputs) and the 74153 dual 4-to-1 multiplexer. Some designs have 3-state outputs and others have open collector outputs.

Most have

enable inputs to facilitate cascading.

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Fig. The 4-input multiplexer

Select inputs S1 S0 0 0 0 1 1 0 1 1

Outputs Z D0 D1 D2 D3

Function table

DEMULTIPLEXERS (DATA DISTRIBUTORS)

A multiplexer takes several inputs and transmits one of them to the output.

demultiplexer performs the reverse operation; it takes a single input and distributes it over several outputs. So, a demultiplexer can be thought of as a ‘distributor’, since it transmits the same data to different destinations. Thus, whereas a multiplexer is an N-to-1 device, a n

demultiplexer is a 1-to-N (or 2 ) device.

Figure shows the functional diagram for a

demultiplexer (DEMUX). The large arrows for inputs and outputs can represent one or more lines.

The ‘select’ input code determines the output line to which the input data will be

transmitted. In other words, the demultiplexer takes one input data source and selectively distributes it to 1-of-N output channels just like a multi-position switch. O0 O1 . . .

Data inputs

. . .

ON - 1 DEMUX Select inputs

Fig. General demultiplexer

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1-Line to 4-Line Demultiplexer

Figure shows a 1-line to 4-line demultiplexer circuit. The input data line goes to all of the AND gates. The two select lines S0 and S1 enable only one gate at a time, and the data appearing on the input line will pass through the selected gate to the associated output line. Data input

Select input S1

Fig. Logic diagram of a 1-line to 4-line demultiplexer

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UNIT IV SEQUENTIAL LOGIC SYSTEMS INTRODUCTION

Sequential circuit is one whose output depends on the current inputs and also on the previous inputs. Sequential circuits use memory elements. The flip-flop is the basic memory element in a sequential circuit. In sequential circuit the output changes in a sequential way. Most widely used sequential circuits are ‘Registers’ and Counters’.

FILP-FLOPS

Filp-flop is a bistable circuit. It has two stable states. It remains in any one of the state until triggered.

FFs are built using NAND or NOR gates.

FFs form the heart of

sequential circuits.

R-S NAND FILP-FLOPS An R-S FF using NAND gates is shown in figure. It has two input terminals ‘S’ and ‘R’. S Stands for SET and R stands for RESET. There are two outputs Q and

Q , which are

complement to each other.

Fig. R-S NAND FF

When output Q = 1 (Q = 0), FF is in SET state.

When Q = 0 ( Q = 1), FF is in RESET state.

The control inputs S and R determine the state of the FF.

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S = 1, R = 1

The control inputs are both equal to 1. The state of the FF now depends on the other input levels.

Let

Q = 1.

The output of upper NAND gate is 0 i.e. Q = 0. This makes

Q = 1. The two outputs

are complementary.

R=1

S =1

Let

Fig.

Q = 0. The output of upper NAND gate is Q = 1. This makes Q =0.

So the FF can exist in any one of the states.

i.e. either in SET state with Q=1 and

or in RESET state with Q=0 and

Q =0

Q =1

Thus for S = 1 and R = 1, both states are possible.

S = 0, R = 1

Now the FF can remain only in RESET State. This can be verified as follows. Let = 1. The output of upper NAND is Q = 0. This makes the output of upper NAND is Q = 1. This makes the RESET state (Q = 0,

Q =1. On the other hand if Q = 0,

Q = 1 which in turn makes Q = 0. Thus only

Q = 1) alone is possible.

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R=1

Q=0

S=0

Q=1

Fig.

S = 1, R = 0

Under this condition the FF will exist only in SET state with Q = 1 and

Q = 0.

S = 0, R = 0

In this case both outputs will be at logic 1.

Since the two outputs are not

complementary, this is an illegal state. [Forbidden state].

R=0

Q=1

S = 0 Fig. Race Condition

Q=1

If both inputs are now changed, to S = R = 1, the state of the FF is ‘indeterminate’. Because with S = R = 1, both states are possible. There is a race between the two gates to see which one is faster. This situation is called ‘Race condition’. So the case S = R = 0 is not used. Truth Table of R – S NAND FF

Remarks

Race

Reset

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Set

No Change

CLOCKED FLIP FLOPS

Thousands of FFs are used in computers. To coordinate the overall action a square wave signal (  ) called ‘clock’ (CLK) is send to each FF. This signal changes the state of FF at the right time. The clock signal is actually a narrow pulse. During the application of the pulse, the FF changes state according to the input logic levels in S and R. These FFs are called ‘clocked FFs’. When the change occurs during high level of the clock, it is called ‘positive clocking’. Similarly if the change occurs during low level of clock, it is ‘negative clocking’.

CLOCKED R-S NAND FF The circuit is shown in figure. A pair of NAND gates called ‘input NAND’s drives the basic R-S FF. S and R are the inputs to this input NANDs. The controls inputs for the basic FF are marked S’ and R’.

S R’

CLK Fig. Clocked S’ R-S NAND FF

When CLK is LOW When the clock is LOW, the output of the two input NANDs are 1s. i.e. S’ = R’ = 1 in the basic FF. This means no change state. So when CLK is LOW, the FF is inactive. i.e. it remains in the same state.

When CLK is HIGH

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When CLK is HIGH, the input NANDs are enabled. The FF responds to inputs S and R. The FF works as described earlier. S = 1, R = 0 SETs the FF. S = 0, R = 1 RESETs the FF. When S = R = 0 (i.e. S’ = R’ = 1) represents ‘no change’ (NC) state. When both S = R = 1, then the output of both input NANDs are 0s (i.e. S’ = R’ = 0). This is ‘race condition’.

Truth Table of clocked R-S NAND FF

CLK

Remarks

LOW

No Change

HIGH

No Change

HIGH

RESET

HIGH

SET

HIGH

Race

(when CLK, S and R are all HIGH, it is race condition)

CLK

Q Fig. Symbol of clocked R-S FF

Negative clocking is similar. An inverter in connected between the clock pulse and the input NANDs. The FF changes state when CLK in LOW. For a HIGH CLK, the FF is in no change state.

S CLK R

Q FF Q

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Fig. Symbol of –ve clocked R-S FF

DATA FLIP FLOP [D FF]

R-S FF is susceptible to race condition.

It can be modified to eliminate race

condition. This results in a new kind of FF known as ‘Data Flip Flop’ or ‘D FF’. The circuit is shown in figure.

Undocked D FF

S Fig. Unclocked D FF

The data input D drives the S input directly. Because of the inverter ‘D drives the R input. So S and R can never be equal hence race condition is eliminated.

When D = 1, it makes S = 1 and R = 0. The FF is SET with Q = 1.

When D = 0, it makes S = 0 and R = 1. The FF is RESET with Q = 0.

Truth Table

In D FF, the output Q follows the data input D. i.e. Q = D.

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Q D FF Q

Fig. Symbol of D FF

CLOCKED D FF

The circuit of a clocked D FF is shown in figure. S

R’ Q

_ Q R

S’

Fig. Clocked D FF

Data input D drives S input directly. D is connected to R through an inverter. Since S and R cannot be equal, race condition is avoided.

A LOW CLK disables the input NANDs. The FF remains in no change state.

When CLK is HIGH D = S = Q. i.e. the FF is SET if D = 1, and RESET if D = 0.

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Truth Table

CLK

Q D FF

CLK

Fig. Symbol of clocked D FF

EDGE TRIGGERED DFF

Here the FF changes state during positive edge or negative edge of the clock pulse. There are more accurate and reliable.

D FF CLK

D FF Q

Fig. Positive edge triggered

CLK

Fig. Negative edge triggered

TOGGLE FLIP FLOP (T FF)

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The T FF has the unique property of ‘Toggling’. Its output changes on successive clock pulses. For every two input clock pulses the output produces one pulse. Since output frequency is half of the clock frequency, the circuit is often called as “divide by two” circuit.

CLK

Fig. Toggle FF

The Q output is connected to R input

Q output is connected to S input.

Let the FF be initially in reset state with Q = 0 (and Q = 1). So S = 1 and R = 0.

A LOW clock will produce no change condition.

When clock goes HIGH, the FF SETs. i.e. output changes, with Q = 1 and

Q = 0.

Now R = 1 and S = 0.

At the next pulse the FF RESETs, with Q = 0 and

Q = 0.

These changes occur on successive pulses also. i.e. the outpout toggles for every clock pulse.

Truth Table

CLK

Qn+1

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So whatever is the state of FF at the n pulse, it will go to complementary state at the th

(n+1) pulse. T FF is used in counters to count pulses.

J-K FLIP FLOP

J-K FF is most important type of FF. This is a very flexible FF. It can be easily converted into a D or T FF. J-K FF is used as ideal memory element. Race condition is also not present.

The FF has two inputs J and K the input J corresponds to S and K corresponds R in the R-S FF. But there is one important difference. When J and K are both HIGH, the FF toggles as T FF. The J-K is an improved version of R-S FF.

Fig. J-K Flip Flop S Q

The control inputs J and K decide the state of the FF, when a clock pulse is applied.

WORKING OF A J-K FF

When clock is LOW

Both NAND gate outputs are 1s. i.e. R=1, S=1. The basic R-S FF remains in no change state.

When clock is HIGH

J=0, K=0

Again both NAND gates are disabled. The FF remains in no change state.

J=1, K=0

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NAND gate N1 is enabled and N2 is disabled.

If Q = 0,

Q = 1, this gives a signal to SET the FF.

In case if the FF is originally in SET state with Q = 1,

Q = 0, both NAND gates are

disabled. The FF remains in SET state.

The with J=1 and K=0, ONLY SET state is possible.

J=0, K=1

Following similar argument, we can find the FF can exist ONLY in the RESET state.

J=1, K=1

If Q = 0,

Q = 1, only the NAND gate N1 is enabled. The FF changes to SET state,

when CLK is applied.

If Q = 1,

Q = 0, the lower NAND gate N2 is enabled. The FF changes to RESET

state when next CLK is applied.

The FF toggles for every clock pulse.

Truth Table

CLK

Remarks

No Change

Reset

Set

Toggle

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J-K FF as T FF

Truth Table of J-K FF shows when both J and K are HIGH, the FF toggles. So connect J and K together and make them HIGH. HIGH J

CLK

K Q T FF Fig. J-K FF as

J-K FF as D FF

In a D FF the two inputs are complementary. D input is directly connected to J input. D is connected to K through an inverter.

D J

Q Fig. J-K as DFF

REGISTERS

Register is a group of Flip Flops, used to store a binary number. One flip flop can store one bit of data (0 or 1). It is called a one â&#x20AC;&#x201C; bit register. To store a 3-bit binary number (data) three Flip Flops are needed. Using more Flip Flops more bits can be stored (one FF for each bit).

SHIFT REGISTERS

A shift register moves the stored word to the left or right. This shifting is essential for arithmetic and logical operation. Shift registers are constructed using clocked D FFs. For every clock pulse, the stored bits are shifted one position to the left or right.

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SHIFT LEFT REGISTERS

In this, the stored bits are shifted one position to the left, for every clock pulse.

The circuit of a 4-Bit Shift left register is shown in figure. It consists of four positive edge triggered. D Flip Flops. All are provided with a HIGH CLEAR (CLR). i.e. when CLR line goes HIGH all FFS are cleared (RESET).

FF3

D2 FF2

Q1 FF1

Din

FF0 CLK

Fig. Four bit shift-left register

CLR

The data input Din is applied to the D0 input of the first flip flop FF0, The output of Q0 FF is connected to D, input of next FF. Similarly Q1 to D2, Q2 to D3.

When CLR goes HIGH and then LOW, all FFS are cleared, The stored word (data) becomes.

Q = Q3Q2Q1Q0 = 0000 Consider Din is made HIGH i.e. Din = 1.

When the first clock pulse is applied Din = 1 is shifted to Q0. The stored word becomes

Q = 0001

Second pulse gives

Q = 0011

Third pulse gives

Q = 0111

Fourth pulse gives

Q = 1111

Now conside Din is made LOW i.e. Din = 0

Sixth pulse gives

Q = 1110

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Seventh pulse gives

Q = 1100

Eight pulse gives

Q = 1000

Nineth pulse gives

Q = 1000

and so on.

SHIFT-RIGHT REGISTER A 4 – Bit shift right register is shown in figure. Each Q output is connected to the D input of the proceeding flip flop.

Din

FF3

D2 FF2

Q1 FF1

Fig. Four Bit Shift – right register

D0 FF0 CLK CLR

Data input Din is applied to the left most flip flop FF3. Q 3 in connected to D2, Q2 to D1 and Q1 to D0. When CLR goes HIGH and then LOW, all flip flops are cleared.

Consider Din = 1 The first clock pulse gives

Q = 1000

Second gives

Q = 1100

Third gives

Q = 1110

Fourth gives

Q = 1111

Fifth gives

Q = 1111

Now make Din = 0 Sixth pulse gives

Q = 0111

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Seventh pulse gives

Q = 0011

Eight gives

Q = 0001

Nineth gives

Q = 0000

and so on Controlled Shift – Left Register A controlled shift – left register has control input, which determines the action of the register. The control is obtained by using combinational logic circuits. The circuit of a 4-Bit controlled shift – left register is shown in figure. The two AND gates 3 and an OR gate form the combinational logic for each flip flop. SHL is the control line.

SHL SHL Din

D3 FF3

D2 FF2

Q1 FF1

D0 FF0 CLK CLR

Fig. Controlled Shift-left Register

When SHL Line is High

All A1 gates are enabled and all A2 gates are disabled.

Din can reach D0 input Q0 can reach D1 input

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Q1 can reach D2 input and

Q2 can reach D3 input. When clock pulses are applied, the bits move one position to the left for every clock pulse. The circuit works as a shift â&#x20AC;&#x201C; left register.

When SHL Line is Low

All A2 gates are enabled and A1 gates are disabled.

The output Q0 is returned to D0 input.

Q1 is returned to D1 Q2 is returned to D2

Q3 is returned to D3

i.e. the output of each FF is fed back its input.

When clock pulses are applied the stored bits are circulated in the same FF. I.e. the bits are retained in the same FF (not shifted).

Applications of Shift Registers

Delay line

Serial to parallel converter

Parallel to serial converter

Ring counter

Twisted ring counter

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COUNTERS

A circuit used for counting pulses in known as a counter. A counter is an useful and important sub-system in a digital system. There are two types of counters.

Asynchronous counter (Ripple counter)

Synchronous counter

In asynchronous counter, the flip flops are not clocked simultaneously. Each flip flop receives the clock from the output of the previous flip flop. These counters have a cumulative setting time. i.e. asynchronous counters are slower.

In synchronous counters all the flip flops are clocked simultaneously. I.e. clocking is synchronous.

ASYNCHRONOUS COUNTER (RIPPLE COUNTER)

(Up Counter) A 4 â&#x20AC;&#x201C; Bit ripple counter can be constructed using four J-K flip flops. All the flip flops are negative edge triggered. Q0 output is connected to the clock input of the next flip flop FF 1. Similarly Q1 is connected to clock input of FF2, and Q2 to that of FF3.

HIGH Q3

J3 FF3

J0 FF0

FF1

FF2 K3

CLK CLR

Fig. Four bit Ripple counter

In all FFs the J and K inputs are tied together and held HIGH. This means all FFs will toggle whenever they receive a negative edge of clock pulse.

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When CLR line goes LOW and then HIGH all FFs are cleared. The initial count word is

The clock pulse (CLK) is directly applied to the flip flop FF0. So FF0 toggles for every negative edge of CLK.

When first pulse is applied FF0 toggles from 0 to (i.e. Q0 = 1)

At the second pulse FF0 toggles 1 to 0 (i.e. Q0 = 0). This is a negative edge. So at the second pulse FF1 also toggles.

Similarly at the fourth pulse Q1 changes from 1 to 0. This negative edge makes FF 2 to toggle at the fourth pulse. Thus, FF0 toggles for every clock pulse. FF1 toggles for every two pulses

FF2 toggles for every four pulses FF3 toggles for every eight pulses and so on.

This can be summarized as shown in count sequence Table.

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Count Sequence

Pulse Applied

Counter output Q3

1 2

Count value

4 5 6 7 8 9

In ripple counters Q0 FF must toggle (1.0) before Q1 FF, Q1 FF must toggle before Q2 FF and so on Worst case occurs when count changes from 0111 to 1000 and from 1111 to 0000. So ripple counters are slower. This problem is overcome in synchronous counters.

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SYNCHRONOUS COUNTER

(UP COUNTER)

Synchronous counters are built with positive edge triggered J-K flip flops. pulses are applied to all FFs simultaneously (i.e. clocking is synchronous).

Clock

Because of

simultaneous clocking, the correct count word appears with one propagation delay time.

HIGH

J3 FF3

FF2 FF2 Four Bit Synchronous Fig. counter K3

J0 FF0

CLK K0

The J0 and K0 inputs of flip flop FF0 are permanently held HIGH. So FF0 toggles for CLR

every positive edge of the CLK.

The other FFs responds to the CLK under certain conditions.

FF1 toggles when Q0 = 1

FF2 toggles when Q0 AND Q1 are 1s.

FF3 toggles when Q0 AND Q1 AND Q2 are 1s.

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Working

When CLR goes low and then HIGH all FFS are cleared.

Initial counter word is Q = 0000

First CLK pulse set Q0 FF

Counter word becomes Q = 0001

Since Q0 = 1, FF1 will also at the next pulse.

The second pulse gives Q = 0010

At the third pulse FF0 gives Q = 0011 Since Q0 AND Q1 are 1s, FF2 will toggle at the fourth pulse

Fourth pulse gives, Q = 0100

And so on. The count proceeds upto 1111. At the next CLK pulse the counter is RESET (Q = 0000) and the cycle repeats.

Count Sequence

The count sequence is the same as given for ripple counter (Table).

Advantage

Synchronous counter is faster than ripple counter. There is no worst case. It takes only one propagation delay time for any counter word.

RING COUNTER

A ring counter uses binary words that have atleast one bit HIGH. It is not used to count binary numbers. It produces binary words in desired sequence. Ring counters are built with positive edge triggered D FFs. The circuit of a 4 â&#x20AC;&#x201C; bit ring counter is in shown figure.

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FF3

D2 FF2

FF2

D0 FF0 CLK

CLR

Fig. Four bit ring counter

Q0 output is connected to D1 input Q1 output is connected to D2 input

Q2 output is connected to D3 input

Q3 output is connected to D0 input A ring counter works more than a shift register. The bits are shifted one position to the left for every CLK pulse. The final output is fed back to the input of first FF i.e. the bits are shifted left and also rotated. This kind of action is called Rotate – left. The PRESET (PR) terminal of FF0 and RESET  terminals of all other FFS are connected to

CLR terminal.

When

CLR goes LOW and then HIGH, the first flip flop FF0 is PRESET, all other

FFs are RESET.

The counter word is Q = 0001

When the first CLK pulse arrives the bits are shifted one position to left.

Counter word is

Q = 0010

Second pulse gives

Q = 0100

Third pulse gives

Q = 1000

Fourth pulse gives

Q = 0001

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i.e. counter returns to initial condition at the fourth pulse. In order that ring counters to work there must be at least a ‘1’ or a ‘0’ in the binary word. If all bits are 1s or all are 0s the counter will not work.

Down Counter A down counter from a HIGH to a LOW binary word (i.e. from 11…..1 to 00……0). So a four bit down counter counts from 1111 to 0000. A PRESET signal can set all the FFS to gives the initial output word 1111. A 4 – bit down ripple counter circuit is shown in figure. PRE HIGH J3

FF3 Q3

J0 FF0

FF2

FF2 K3

CLK

Fig. Four Bit down ripple counter

When PRE goes HIGH and the LOW all FFS are preset. They are ready for action. The J and K inputs of all FFs are held HIGH. So they toggle whenever they receive a negative edge of a clock pulse. This means a FF toggles whenever its preceeding FF’s complement of the output (i.e.

Q ) changes from 1 to 0. [1 to 0 is the negative edge]

Thus,

FF1 toggles whenever

Q 0 goes from 1 to 0

FF2 toggles whenever

Q1 goes from 1 to 0

And so on.

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When PRE signal is applied, initial output word is

The first negative edge produces a toggling in FF0. The output is

Q = 1110 Now

Q 0 is a 1…… The second pulse results in Q 0 going from 1 to 0. This negative

edge makes FF1 to toggle. The output word is

Q = 1101 The third pulse produces Q = 1100 This process continues, and the counter is now counting from 1111 (15 10) to 0000 (010). The final output word is, Q = 0000 At the next pulse the cycle repeats,

Down count sequence

Count 15 14 13 12 13 12 11 10 9 8 7 6 5 4 3 2 1

Q3 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0

Q2 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0

Q1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0

Q0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

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DECADE COUNTER A decade counter counts from 0 to 9. It is mod – 10 counter. The difference between the two is that, a mod – 10 counter can be preset to count to 10 pulses starting from 0 or any other number. The decade counter starts counting from 0. The decade counter is used in BCD applications, like frequency counters, digital voltmeters, electronic watches etc. A decade counter requires four flip – flops. The count starts from 0000, and counts upto 1001. At the tenth pulse the counter is reset to 0000. (the six omitted states are 1010 through 1111).

Using Karnaugh map method the logical levels needed for the various J and K inputs can be found. These are shown below.

Results from Karnaugh maps :

J0 = 1, K0 = 1

J1 = Q0 Q3, K1 = Q0

J2 = Q1 Q0 K2 = Q1 Q0 J3 = Q2 Q1 Q0 K3 = Q0

As per the results, the four flip flops are interconnected to give the decade counter.

HIGH Q3

FF3 Q3

J0 FF0

FF2

FF2 K3

K0 CLK CLR

Fig. Decade counter

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When CLR goes LOW and then HIGH, all FFs are reset. The output is,

Q = Q3 Q2 Q1 Q0 = 0000 As J0 = K0 = 1, FF0 toggles at every negative edge of the clock pulse. So at the end of the first pulse,

Q = 0001

Now, Q0 = 1 and Q3 = 1, so that J1 = 1 and K1 = 1. So the FF1 is now ready to toggle at the second pulse. This gives

Q = 0010

As Q0 in now = 0, J1 = 0 and K1 = 0 The FF1 remains latched, while FF0 alone toggle at the third pulse.

Q = 0011

Since Q0 and Q1 are 1s the inputs J2 = K2 = 1. So FF2 toggles at next pulse. The fourth pulse gives,

Q = 0100

This process countinues and at the end of the ninth pulse, Q = 1001. As K3 is now = 1, FF3 will reset at the next pulse. The tenth pulse resets all FFs giving, Q = 0000

Then the cycle repeats. The timing diagram is shown in figure.

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CLK

Fig. Timing diagram of decade counter

The count sequence is shown in Table

Count Sequence

FF Outputs Count Q3

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MASTER – SLAVE FLIP-FLOP

To eliminate problems which arise with the latch type of flip-flop, more complicated flip-flop designs are used. The most popular uses edge triggering from the clock to initiate changes in the flip-flop’s output and is based on the use of two single or latch flip-flop to form a single edge-triggered flip-flop.

The basic flip-flop design is shown in Fig. Figure shows that an edge-triggering RS flip-flop consists of two flip-flops plus some gating. The two flip-flops are called the master and slave. An expanded logic diagram for Fig. is shown in Fig in which the master flip-flop is composed of the leftmost NAND gates and the slave flip-flop of the rightmost NAND gates. The expanded diagram in Fig can be used to explain the flip-flop’s operation. The flip-flop’s output changes on the negative-going edge of the clock pulse. The basic timing is shown in Fig. First, on the positive-going edge and during the positive section of the clock pulse, the master flip-flop is loaded by the two leftmost NAND gates.

Then, during the

negative-going edge of the clock signal, the two rightmost NAND gates load the contents of the master flip-flop into the slave flip-flop just after the two-input NAND gates are disabled. This means that the master flip-flop will not change in value while the clock is low (0); so the slave remains attached to a stable flip-flop, with a value taken during the positive section of the clock pulse.

A more detailed account of the action of the flip-flop is as follows : If the clock signal is low, the two-input NAND gates both have 1 outputs; so the master flip-flop does not change states since it is a NAND gate flip-flop and can be set or cleared only by 0 inputs.

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S R

Master

Slave

Q Q

Clock S

Q output

Clock R

Master flip-flop

Q output

Slave flip-flop

INPUTS

STATE OF FLIP-FLOP AFTER CLOCK

Unchanged

Not used

At the same time, as long as the clock signal is low (a 0), the inverter causes the inputs to the E and F NAND gates to force the value of the master flip-flop into the slave flip-flop. The situation is stable. The master cannot change, and the output flip-flop is “slaved’ to the master.

When the clock starts positive, however, the E and F NAND gates are disabled, and the NAND gates A and B to the master flip-flop are then enabled.

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When the input clock signal is a 1, then the master flip-flop will accept information from the S and R inputs, and the slave flip-flop is now isolated from the master and will not change states regardless of changes in the master.

The operation of the master flip-flop is according to the following rules when the clock level is a 1 :

If both S and R are at 0 levels, the two input NAND gates will have 1 outputs and the master flip-flop will not change values.

If the S input is a 1 and the R input a 0, the master flip-flop will go to its 0 state, with the upper NAND gate having a 1 output.

If the S input is a 0 and the R input a 1, the master flip-flop will go to its 0 state, with the upper NAND gate having a 0 output.

If both R and S are 1s, the final state is indeterminate.

When the clock signal goes negative to its 0 level, first the input NAND gates to the master flip-flop are disabled, that is, each output goes to a 1; then the E and F NAND gates are enabled (by the inverted clock signal). This causes the state of the master flip-flop to be transferred into the slave flip-flop.

The effects of all this are shown in the next-state table in Fig, which indicates that the flip-flop is an RS flip-flop activated by a negative-going clock signal.

An edge-triggering flip-flop which triggers on positive edges can be made by adding an inverter at the CL input.

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UNIT – V D/A AND A/D CONVERTERS D/A CONVERTERS

Weighed Resistor Method

The basic problem in converting a digital input into an equivalent analog voltage is to change N digital voltage levels into an equivalent analog voltage. This can be more easily accomplished by designing a resistive network. It will change each of the digital level into an equivalent binary weighed voltage.

Consider the truth table for 3-bit binary signal. The smallest digital input is 000. Let us make this 0v, the largest number is 111. Let us make this equal to 7v. Thus between 000 and 111, there are 7 discrete levels. Therefore it will be convenient to divide analog output into seven levels.

Digital input Analog output volts 2

2 0 0 0 0 1 1 1 1

2 0 0 1 1 0 0 1 1

2 0 1 0 1 0 1 0 1

Analog Output volts 0 1 2 3 4 5 6 7 (max)

The smallest incremental change in the digital signal is represented by the LSB 2°. This bit should cause a change in analog voltage, which is equal to 1/7

full-scale analog

output voltage. The resistive divider will be designed such that a 1 in the 2° positive will cause

1 x 7  1v . 7

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Since 2 = 2 and 2° = 1. It can be seen that 2 bit represents the number which is 1

twice the size of 2°. A 1 in the 2 bit position must cause a change in analog output voltage which is twice that of the LSB. A resistive divider must then be constructed such that a 1 in 1

the 2 position should cause a change of

2 x 7  2v . 7

Similarly, 2 = 4 = 2 x 2 = 4 x 2 , which shows that the 2 bit must cause a change in 2

the output voltage which is 4 times that of LSB. For the 2 bit the output voltage change is

4 x 7  4v . 7 WEIGHED RESISTANCE DAC (RESISTIVE DIVIDER)

Consider a resistive divider having 3 digital input and one analog o/p as shown in fig. For every possible digital i/p the corresponding analog o/p is giver in the truth table.

22 21

DAC

Fig. Block Diagram of 3-input DAC

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Truth table

Digital input Analog Output VA 2

To convert the digital input into analog o/p the DAC must do two things.

The 2째 bit must be changed into IV; the 2 bit must be changed into 2v; 2 bit must be changed into 4 volts.

These 3 voltages representeding the digital inputs must be summed together to form the analog output voltage.

A resistive divider circuit is shown in fig. The Resistors R 0, R1, R2 form the divider network. RL represents the load resistance where RL > R0.

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Fig. Resistive divider circuit

Assume a digital input signal 001 is applied to the network. Further let logic 0=0v and logic 1=7v.

The equivalent circuit is shown in fig. 22

Ro 4

Ro 2

Fig. The analog output voltage can be easily found by using Millmann’s Theorem. This theorem states that, “the voltage appearing at any node in a resistive network is equal to the summation of the currents entering the node divided by the summation of the conductances connected at the point.”

Voltage at any node

Summation of currents Summation of conduc tan ces

V V  1  2 R0 R1 R2 1  1  1 R0 R1 R2

V V  1  2 R0 R0 2 R0 4 1  1  1 R0 R1 R2

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Substituting for V0, V1, V2 =

V0 7

R0 R0

7/7

In the same way the equivalent circuit for other 7 combinations of the inputs can be drawn and Milmanns theorem is used to obtained the output.

The resistive divider should have the following criteria :

For every digital input there should be a resistor.

Beginning with LSB each following resistor value is one half the size of previous resistance.

The LSB has binary equivalent weight of

1 where ‘n’ is the number of 2 1 n

digital inputs.

The analog output voltage VA can be found for any digital input signal by using following modified form of Millmann’s theorem,

VA 

V0 2 0  V1 21  V2 2 2  ........... 2n  1

Where V0, V1, V2, ………….. are digital i/p voltages and ‘n’ is the number of bits. Typical weighed resistance DAC using op-Amp as summing network is shown in the figure R1 - Ro

Ro/4

Ro/2

Fig. Resistive divider with OP AMP as buffer

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O/P

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The resistive divider has two serious drawbacks.

Since the resistors used are high precission resistors, the cost is high.

The resistance used in MSB is required to handle a much greater current than the LSB.

For these reasons binary ladder network is preferred to the resistive divider.

BINARY LADDER METHOD

[R-2R Method]

The binary ladder is a resistive network whose output voltage is a properly weighed A 4 â&#x20AC;&#x201C; bit binary ladder arrangements is shown in fig.

sum of the digital inputs.

It is

constructed with resistors having two values only.

LSB

R A

Fig. R-2R Network R

R C

Each digital input is applied to a separate resistance 2R. The nodes A, B, C, D of the ladder are interconnected using R the left end of the ladder is connected to ground through a terminating resistor of value 2R. The resistive property can be analysed as follows.

For simplicity let us assume that all the digital inputs are at ground (0000). The equivalent circuit for this input is shown in figure.

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R A

R B

R C

Fig. Equivalent Circuit for input (0000) For the node â&#x20AC;&#x2DC;Aâ&#x20AC;&#x2122; the total resistance terminating at ground is 2R. The resistance 0

toward input 2 is also 2R. The combination of these two will give an equivalent resistance of R. So the modified circuit is shown below in figure.

Fig. A

R B

Moving to the point B we find a total resistance of 2R towards left end and another resistance 1

of 2R towards the 2 input. Combining these resistances we get an equivalent resistor R to the left of B.

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Fig.

From the point C, there is a resistor of 2R towards the left and another resistor 2R 2

towards the 2 . These two are combined together to give a resistor of R.

R C

R Vo

Fig.

Finally from the circuit in fig. we find that a total resistance of 2R on the left of D and another 3

resistance 2R towards the input 2 . These two are combined to give an equivalent resistance of R to the left of D.

R C

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From this we conclude that the total resistance looking from any node towards the terminating end is always 2R. The suitation is true regardless digital inputs are at ground or at V volts.

Now let us consider a digital inputs 1000 is applied to the ladder input. The circuit arrangement is shown in figure (a).

Since there is no voltage to the left of node D, the entire circuit can be redrawn as in +V

fig (b). 23

R A

R C

Fig. (a)

V a

Fig. (b)

From the equivalent circuit the analog output voltage is,

  V V VA    .2R  2  2R  R  R  Next let us assume the digital input 0100. The binary ladder for this input is shown in figure (c).

R A

R B

Fig. (c)

R C

V D

Since there are no voltage to the left of ‘C’ the circuit is redrawn as shown in fig. (

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The potential at the point C is V/2.

Then applying Thevenin’s equivalent circuit

theorem to the left of the circuit denoted by dotted line can be modified. The circuit is shown in next figure (e).

V 2

R Fig. (e) C

The output voltage is given by,

V . 2R V 2 VA   R  R  2R 4 This process can be continued and it can be shown that the next MSB provides an output voltage of V/8 and next one v/16 and so on. The output voltage for N inputs is given by.

VA 

V V V V    ......  N 2 4 8 2

This can be further modified and analog voltage is given by.

V02  V11  V22 VA  2N Where V0, V1, V2 are potentials applied at respective digital inputs and ‘N’ is the number if digital input levels.

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A/D CONVERTERS

SUCCESSIVE APPROXIMATION METHOD

The principle of successive approximation method can be explained by the following example. Consider an object of unknown weight in the range of 1 kg. Suppose that a balance and a set of unknown weights of ½, ¼ and 1/8 kg are available. These weights are to be used in a succession of trails to determine the weight of the body.

Fig. Principle of successive approximation ADC The unknown weight ‘W’ is placed on one side of the balance and the ½ kg weight on the other side. The decision is taken in the following way.

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If W  ½ kg, retain the ½ kg weight on the balance and add ¼ kg. Also write a 1 as MSB. If W  ½ kg remove ½ kg weight and place ¼ kg on the scale. Now put a 0 in MSB and 1 in next lower MSB. In this way the weights are successively tried smaller by a factor of 2. If a weight is retained, it is represented by a 1 and if removed then it is represented by a 0. The complete process is illustrated figure.

In this pervious example, let us consider the weight of the body is slightly less than ½ kg. From figure we find the successive approximation method gives a binary output of ‘011’, which represents 3/8 kg. To reduce this error it is necessary to ‘OFFSET’ the scale (i.e) to tilt the scale in favour of the unknown weight. The magnitude of the offset must be equal to one half of the smallest weight (i.e.) 1/16kg in this case.

Circuit

Offset Voltage Va

DAC Vi +

MSB

Comparator

LSB Programmer

Fig. A/D converter circuit

CLK

The successive approximation A/D converter is shown in fig. The comparator serves the function of the scale. The output of the comparator is used for setting (or) resetting the bits of the programmer. The programmer output is converted into equivalent analog voltage from which the offset voltage is subtracted and then applied to the inverting input terminal of the comparator. It should be noted that of the offset weight was added on the side of the unknown weight. Therefore it is to be subtracted from the known weight side for getting the equivalent effect.

The programmer consists of a number of flip flops and some gates. One set of FFs performs the function of a ring counter and the other set acts as a register. The output of the

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100

programmer will change only when the CLK pulse is present.

To start conversion the

programmer sets the MSB to 1 and all other bits to 0. This is converted into analog signal by the D/A converter and the comparator compares it with the analog input voltage. If the analog input voltage Va ď&#x201A;ł Vi the output of the comparator (V0) is HIGH which sets the next bit also.

On the other hand if Va < Vi then V0 is LOW which resets the MSB and sets the next bit.

Thus a 1 is tried in each bit of the D/A converter until the binary equivalent of the analog input voltage is obtained.

For a N-bit converter, the number of CLK pulses required would be N and hence it is slower than the parallel comparator A/D converter. However it is faster than the conventional N

counter type converter where nearly 2 counts would by needed.

COUNTING TYPE A/D CONVERTER

A high resolution ADC using only one comparator can be constructed if a suitable reference voltage is available. Consider simple N bit binary counter where N is the desired number of bits. Let the output of the counter is connected to a standard DAC (Binary ladder). If a CLK pulse is now applied to input of the counter, then the output of the binary ladder is a stair case waveform, as shown in figure.

The waveform is the reference voltage to the

comparator.

Fig. Staircase wave form

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101

The block diagram of counter type ADC is shown in figure. START

Pulse Generator

GATE

Counter

Comp

Level Amp.

VA Fig. Block diagram of ADC

DAC

The counter is RESET to all zeroes. Then a start signal is applied to the gate. The gate opens and the CLK pulses reach the binary counter. The counter advance through normal binary count sequence. This binary output is converted into analog form by a ladder DAC. A stair case waveform is generated at the output of DAC. This waveform is applied as the reference voltage at the non-inverting input of a comparator.

The analog voltage to be digitized is applied to inverting input of the comparator. When the reference voltage equals or exceeds the analog input voltage the comparator output goes high which closes the gate. The counter stops and conversion is complete. Now the number stored in the binary counter is the digital equivalent of analog input. This is shown in figure.

VA Count Stop

V ref

Fig. Stair-case wave form and analog vollage

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102

The counter is RESET to all zeroes. Then a start signal is applied to the gate. The gate opens and the CLK pulses reach the binary counter. The counter advances through normal binary count sequence. This binary output is converted into analog form by a ladder DAC. A stair case waveform is generated at the output of DAC. This waveform is applied as the reference voltage at the non-inverting input of a comparator.

The counter type ADC provides a very good method for digitizing to a high resolution. This method is much simpler to simultaneous method because only one comparator is required. But the conversion time is longer.

Since the count always starts from 0 and advances to normal binary sequence, it may N

require as many as 2 counts before the conversion is complete. The count advances one count for each CLK pulse. In the CLK frequency is 1 MHz, then for 10 bit counting the time period is 1024msec. Conversion time also depends on the magnitude of analog voltage and therefore it is not a constant.

One method of decreasing the conversion time is to divide the counter into sections. For this reason 10 bit counter is divided into two sections of 5 bit each. At the start of conversion the LSB section is PRESET to 1 and the counts are inserted in MSB section. When the comparator indicates that the DAC o/p has reached the analog voltage the LSB section is cleared and the pulses are inserted into it, until the correct value is reached. 5

The maximum number of steps required to complete the conversion is 2 for LSB and 5

another 2 for MSB. This gives a total of 2 + 2 = 2 = 64 counts. Whereas a normal 10 bit counter has the maximum count of 1024. The section counting technique is often used in

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103

digital voltmeter. Where the o/p is to be in decimal notation, each section of the counter then represents a decimal digit.

For varying analog signal input the digital conversion takes place by sampling the analog voltage at district intervals.

Resolution of DAC V

Analog input

DAC Output

Sampling interval

Fig.

For the counter type ADC the resolution depends on single voltage step. With large number of counter stages number of steps increases and the resolution also increases. In N

general percentage of resolution is 1/2 x 100 where â&#x20AC;&#x2DC;Nâ&#x20AC;&#x2122; is the number of bits.

Dual Slope A/D Converter

Another popular method of converting analog voltage into digital form is dual slope ADC. This converter is used in voltmeters because of its speed of conversion, accuracy and low cost.

The block diagram of Dual slope ADC is shown in figure.

It consists of an

integrator, a comparator, a binary counter and a control logic.

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104

|| C VA A - Vr

R V0

Control Logic

Comparator

Integrator 1 Q

Binary Counter AND

2N-1

CLX

2

Fig. Dual slope ADC

At time t = 0 the conversion begins with switch in position A. The analog voltage V A to be digitized is applied to the input of the integrator. The output of the integrator is,

V0 

1 VA . dt RC 0

V0 

t . VA 

 - is the time constant = CR

This negative voltage is applied to the inverting input of the comparator. The other I/P of the comparator is at ground potential. This makes Vc, HIGH which enables the AND gate. The CLK pulses are allowed through the AND gate and reach the binary counter. The count proceeds from 00…….0 to 11………1, when 2

N-1

counts is RESET. The MSB going

from 1 to 0 sets the FF which controls the switch. The switch is moved to position B at time t = T1. NOW – Vr is applied to the integrator. The o/p V0 starts moving in the +ve direction. The counter counts until V0 reaches 0. As soon as V0 moves above ‘0’ Ve goes low disabling the AND gate. The CLK pulses cannot reach the counter and the count stops. The wave forms of V0 and Vc are shown in fig

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105 V0

0 

t VA r



T1 VA r

1 0

Fig. Waveforms of Vc and Vo

The time T1 is a fixed time given by, N

T1 = 2 . Tc, where Tc is the period of the CLK pulse. When the switch is in position B the integrator o/p is given by,

V0 

t  T1  T1 . VA  . Vr  

At t = T2 we have V0 = 0

T2  T1  0  

VA . T1 Vr

T1 T  T1 . VA  2 . Vr  

T2  T1 



VA N . 2 Tc Vr

Let ‘n’ be the number of counts recorded in the counter at T 2. Thus (T2 – T1) = n.Tc

 n . Tc 

n 

VA N 2 . Tc or Vr

VA N 2 Vr

n  VA N

Thus the o/p of the counter is proportional to analog voltage. Further we take 2 = Vr then the count recorded will be numerically equal to the analog voltage. How the count varies with different analog voltage is shown in fig.

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106 Fixed time T1

Varying slope (-ve)

Varying time T2 T2 T2

Fixed Slope (+Ve)

Fig. Dual slopes for different analog inputs

The time T1 is fixed time interval. During this time the slope of V0 changes as the analog VA changes. Since the integrator o/p has both +Ve and –Ve slopes this converter is called ‘Dual slope converter’.

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