Fast & Power savvy ALU with Modified Radix 4 Booth Multiplier using Block Enable Abu R Chowdhury, Purushottam Sigdel, Md Farhadur Reza, Salim Farah & Advisor – DR. BAYOUMI, MAGDY, DR. WU, HONG-YI
The Center for Advanced Computer Studies (CACS), University of Louisiana at Lafayette Introduction
Methodology
• In modern days of computer systems one necessary task is to perform a large number of mathematical calculations in a very less time in less power.
• At first step, we selected Arithmetic Logical Unit as the logical circuit; we wanted to do this with 8 bits and to support the basic operation.
• Since in performing mathematical calculations (especially multiply) the computer spends a considerable amount of its processing time, an improvement in the speed of a math coprocessor for performing addition, subtraction and multiplication will increase the overall speed and low power of the computer. • Arithmetic Logic Unit (ALU) and Hardware multipliers are the integral component of every computer system, cellular phone and most digital audio/video etc. • With battery-powered devices and hand-held devices being used in almost all fields now, addressing faster computation and less power are very much critical and essential. • In our proposed study we tried to introduce block enabled ALU where we use only one unit at a time with the help of Transmission (TX) gates and considerably minimize the dynamic power.
Objective
Overall Implementation & Layout
• The We tested for various input patterns of A and B. And we have tested all the individual components (adder/subtractor, multiplier, AND, etc.) separately. Here we are showing all the functions result in a single simulation.
• The Basic operations are divided in three categories: the Arithmetic operation, the Logical Operations and the Multiplier. The Arithmetic operations are Addition and Subtraction. The Logical operations are AND, OR, NOT, and XOR. • We also enhanced our design with Radix-4 modified booth Multiplier which is also incorporated in the circuit.
Input A
A7 0
A6 1
A5 1
A4 1
A3 1
A2 1
A1 1
A0 1
Input B
B7 0
B6 1
B5 0
B4 1
B3 0
B2 1
B1 0
B0 1
Table 2: Input A and B
• We introduce block enable through Transmission (TX) gate to save power consumption and minimize to only one operation in each activity. • Moreover, while reviewing the literature about different designs and implementations of the ALUs, we used design procedures from two paper that proposes a way to design the fastest Carry Look Ahead adders with minimizing power and area and for faster multiplication using Modified Booth Radix – 4.
Testing & Simulation
Figure 4: Logical Unit Layout a) AND b) OR c) NOT and d) XOR (Clockwise)
S2
S1
S0
Function
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
“Not used” Multiplication Subtraction Addition Exclusive OR (XOR) OR AND NOT
Table 3: Simulation Control Signal
Gradual Improvements of Design
Multiplication: Here we multiply two 8-bit numbers using modified booth multiplier. Addition: Here we used modified CLA adder to add two 8-bit numbers. Subtraction: Here we used modified CLA adder to do the subtraction of two 8-bit numbers. Exclusive OR (XOR): XOR of two 8-bit numbers OR: OR of two 8-bit numbers AND: AND of two 8-bit numbers. NOT: NOT function of one 8-bit number
• To design and Implement logical circuit and construct ALU and Multiplier layout using Logisim, Magic software and Spice simulation that could be further implemented on a chip. • Designing ALU with Booth Multiplier and to meet faster calculation and less power consumption at architectural level is the goal of this project. Figure 5: Arithmetic Unit Layout
Used Tools • Logisim is a free educational tool for designing and simulating digital logic circuits. With its simple toolbar interface and simulation of circuits as you build them, it is simple enough to facilitate learning the most basic concepts related to logic circuits.
Figure 1: a) Initial Logisim Design b) Developed Logisim Design
• Magic is a free VLSI layout tool, written in the 1980's at Berkeley by John Ousterhout, now famous primarily for writing the scripting interpreter language Tcl. Due largely in part to its liberal Berkeley open-source license; magic has remained popular with universities and small companies. The open-source license has allowed VLSI engineers with a bent toward programming to implement clever ideas and help magic stay abreast of fabrication technology. • Hspice is used to accomplish transient simulations of the circuits. Hspice is an accurate circuit simulation tools which offers foundrycertified MOS device models with state-of-the-art simulation and analysis algorithms. HSpice is developed in Synopsis, a world leader in electronic design automation (EDA), supplying the global electronics market with the software, IP and services used in semiconductor design and manufacturing.
Control Bits • Three bit control signal is used to select one of the seven function and only selected functional unit will execute at that interval. This approach saves power because only one functional units is running at any time. Decoder Input 000 001 010 011 100 101 110 111
Functional unit INV/NOT AND OR XOR ADD SUB MUL --
Table 1: Control Signal of Functional Units. TEMPLATE DESIGN © 2008
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Figure 8: Simulation Result Function Carry Out/Last 8 bit of MUL Multiplication Subtraction Addition Exclusive OR (XOR) OR AND NOT
Figure 2: a) Booth Multiplier Unit b) 4 bit and 12 bit Carry Lookahead Adder Design with Modified Full adder and nand gates fast calculation
Transmission Gate
Out3
Out2
Out1
Out0
00101010 0 0 0
0 0 1 0
0 0 1 0
1 1 0 1
0 0 1 0
1 1 0 1
0 0 1 0
1 1 0 1
1 0 0 0
0 0 0
0 0 0
1 1 0
1 0 0
1 1 0
1 0 0
1 1 0
1 0 0
1 1 0
Table 4: Output of Simulation Result
Future Enhancement - Conclusion Figure 6: Multiplier Unit Layout
• It is the definitive stage in ALU that propagates the desired output corresponding to the operation performed. Transmission gates is used to make sure only one module is working at a time and in that way it would save lot of dynamic power. We changed throughout our project implementation to have a good combination of fast and power saving Tx gates, multiplexer and decoder units to implement our control signal.
Figure 3: TX Gate
Output Out7 Out6 Out5 Out4
Figure 7: TX Unit Layout
• Since the main goal of the study was to implement a faster ALU design, other kind of techniques can be included to provide even faster output. Also we can always add more function such as Barrel shifter, Divisor, etc to make our ALU more diverse. • In the whole ALU design a massive 4933 transistors have been used which span in area of 49 micro meter sq. [(11416 λ X 5300 λ) where λ = 90 nm] and Average power consumption is 0.00073 watt. • The power consumption compare to with and with out block enable in 8-bit Booth multiplier was found 1000 fold better. • Although using block enabled helped us to save lot of dynamic Power, we really need to compare with other ALUs in the future and come up with substantial result to show our design is superior in number of aspect. For this we are hoping to publish few papers combining future simulation.