What is Package on Package Assembly? What is package on package? Package on package assembly or POP is an integrated circuit packaging method by which a BGA and a vertically discreet logic are combined. Packages are effectively placed on top of each other. It takes a form of a stack through which signals are passed. POP ensures a component density which is more than normal and can be utilised in devices such as digital camera and smart phones. Benefits of POP: The PoP method is beneficial because it merges the benefits of die stacking and traditional packaging at the same time. The POP saves a lot of space in the mother board. The PCB area used by PoP is way less as compared to other methods. It has electrical advantages too. For instance, it reduces the track length between memory chip and controller chip. Due to the propagation of faster signal, better electrical performance of a device can be achieved. The PoP also cut down noise and outside interference. How is Package on package assembly better than chip stacking? The financial advantage is the decoupling of logic device and memory device. There are several other advantages mentioned below:
Separate testing of logic and memory packages are possible In case of a memory or logic damage, the whole set need not be rejected. The packages which are functioning properly can be used for the project Memory from different portion can be used at convenient time without changing the logic sequence. This effectively means the user is capable of controlling the logistics. Any package which has the possibility of mating mechanically can be used Logic suppliers need not source memory because the memory only come into the picture during final assembly
What are the design considerations for package on package assembly?
The packages at the top and the bottom are of similar size Both the packages should be under filled simultaneously to ensure reliability The fluid should reach the gap of the second level for simultaneous under fill of the both the layers Since the thermal delta varies between two levels, the bottom layer under fill is slower as compared to top layer under fill
Challenges of PoP: There are some technical challenges involved in the PoP assembly process:
Solder balls can dislodge or migrate due to errors in the reflow profile Too much warpage leads to slumping of solder, pillow defects, head defects, bridging of ball etc. Control and matching the warpage of top and bottom side is a challenge. The later accounts for majority of the assembly problems. To minimize the warpage, it is essentially a trade-off between time, temperature control and materials As the material becomes thinner, the degree of warpage increases
Next generation package on package assembly: The next generation PoP has fast integration, increased performance, high miniaturization and steep collaboration. There is more control on warpage and more number of pins is available. The power efficiency of next gen pop is way better compared to the old ones. The bottlenecks are removed with the help of TMV and the ratio of package to die is increased up to 30 percent.