Narasinga Rao Miniskar IMEC, Kapeldreef 75, Heverlee 3001, Belgium. http://www.miniskar.co.cc
Email : narasinga.rao@gmail.com Phone : +32-487-161-473
Career Objective Looking for a competitive and challenging full-time position in the field of embedded system design research and product development. Industry Experience • Research Scholar, imec, Leuven, Belgium. Oct’06 - present Working as a research scholar in imec (SSET/DC) in the area of Heterogeneous Multiprocessors Dynamic Application Mapping in an energy efficient way. Scenarios have been used to handle the dynamic applications mapping on uni-processor. In this research, we have proposed a systematic methodology for System Scenarios Identification and Detection to handle the dynamic applications mapping on heterogeneous multiprocessors. We have also proposed extensions for the Task Concurrency management methodology, to perform the design-time co-exploration and more energy efficient pareto-based run-time management. In this research, we have studied dynamic applications from Graphics, Multimedia and Wireless domains. We have implemented our proof-of-concept tools, which can be seen in projects. • Senior Software Engineer, Agere Systems, Bengalore, India. Aug’04 - Oct’06 Worked as a developer and validation engineer for Software Traffic Generator, Traffic Analyzer and QA test framework: TAZO for Agere Network processors. I was the key contributor for the development of regression test harness environment for simulation based performance analysis tools of Agere network processors. Areas Of Interest • • • • •
Embedded Systems, Digital Image Processing, Computer Architecture, Digital Electronics System software development, Software Synthesis for Embedded Processors and Platforms Specification Models, Methodologies, & Tools for System Level Design Automation Computer Networks, Compilers (Both front-end and back-end) Algorithms, Data Structures and Data base management system
Software Skills Expertise in Good Exposure to assemblies Good Exposure to Tools
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C, C++, GeCode, SystemC, JAVA, VHDL, XML 8085, 8086, SPARC, Srijan-VLIW GNU BinUtils, newlibc, DDD, IMPACT Trimaran MD, ML-Yacc, ML-Lex, Flex, Bison, MPI, Scripting Languages : PERL, PhP, BASH, CSH, JavaScript, CGI Databases and Packages : SQL, PL-SQL, MS-Access, Visual Basic Strong skills in software design, programming, algorithms, data structures & debugging
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Educational Background Degree Doctor of Philosophy(PhD), M.Tech, Computer Science & Engineering B.Tech, Computer Science & Engineering Diploma, Computer Science & Engineering SSC
Year University/Institute 2007-present K.U.Leuven Electrical Engineering 2002-2004 IIT Delhi
%/CGPA 8.32 (CGPA)
1998-2002
JNTU, Hyderabad
82.11%
1995-1998
GIPDCE&T, Tirupati
79.45%
1994-1995
Board of Secondary Education, Andhra Pradesh
79.33%
Achievements • Received prestigious Agere Systems performance recognition award: SPOT • Ranked with Outstanding performance appraisal in Agere Systems, India • Secured 99.61 percentile with All India Rank 72 in GATE 2002 • Received Silver medal from the Vice chancellor, JNT University, Hyderabad, for achieving the top rank and percentile in our Engg College • Got Second prize in software contest conducted in IEEE Annual Technical Symposium and Exhibition-2002, IIT-Roorkee • Got Third position in B-Tech in the class of 60 students • Secured 28th rank in Engineering entrance testECET 1998 • Got Second position in Diploma in the class of 40 students • Received fellowship from CISCO Systems for my M.Tech Course in IIT Delhi Course Work • CAD of Digital Systems, High level Design and Modeling, Architecture of Large systems, Digital Systems, Computer Architecture, Micro Processors, Compiler Design, Design of Electronic Systems • Data structures, Discrete mathematics, Design and Analysis of Algorithms, Theory of Computation, Operating Systems, Databases and Distributed Databases, Introduction to Logic and Functional Programming • Computer Networks, Advanced Computer Networks, Network Security, Digital Image Processing Selected Projects (details on request) • Heterogeneous MPSoC Mapping Framework • IWT-OptiMMA: Optimization of MP-SoC Middleware for Event-driven Applications • Design-time Co-Exploration and Run-Time Management for Heterogeneous MPSoC applications mapping • Systematic System Scenarios Identification and Detection for dynamic applications mapping on Heterogeneous MPSoCs • System Scenario methodology on H264 decoder and Scalable 3D Graphics game engine applications mapping on Heterogeneous MPSoC 2
• Task Concurrency Management mapping exploration on Medical Imaging Cavity Detector, Scalable 3D Graphics game engine, and H264 decoder applications • Heterogeneous MPSoC virtual platform functional simulator using SystemC TLM • Retargetable Software Synthesis for Heterogeneous Multiprocessor SoC • System Software for Process Networks • Modeling of Mobile IP using SystemC • Cycle Accurate RTL Model of 8085, with pipelining feature • Filter Bank based Finger Print matching • Designing of Text Editor with all editing features for C programming language • IRDS Bank Management Some Course Work Projects • • • • • • • • • • • • •
DSP optimizations on Medical Imaging Cavity Detector, JPEG encoder and decoder Digital Image processing filters, enhancements, morphing and transformations JPEG image Compression and Decompression Implementation Compiler and Interpreter for P3 language Ping and Trace-router implemented in C Secure Chat with RSA A client-server model for a multi party chat system in C++ A multi-player board game (Conquest) in JAVA A UDP ping server and client pair using C++ Parallel matrix Multiplication using MPI in C language Ad-Hoc network setup, configuration, AODV routing and UPNP service discovery protocol Image Steganography Implementation of List SchedulingTool
Publications & Talks • [Paper] Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study. SAMOS 2009 • [Paper] PinComm: Characterizing Intra-application Communication for the Many-Core Era. ICPADS 2010 • [Paper] Pareto based run-time manager for overlapped resource sharing, ACES 2009 • [In Journal Submission] Pareto based run-time manager for overlapped resource sharing • [In Journal Submission] Design-Time Co-Exploration of Processing, Communication and Memory for Heterogeneous MPSoCs • [In Journal Submission] Systematic System Scenarios Identification for Heterogeneous Multiprocessor Mapping • [In Journal Submission] Systematic System Scenarios Detection for Heterogeneous Multiprocessor Mapping • [Poster] Pareto Based Run-Time Resource Manager With Overlapped Resource Sharing Strategy, ACES 2009 3
• [Poster] Resource Management of Processing Elements in Heterogeneous Multiprocessor SoCs, DATE 2009 • [Poster] OptiMMA: Optimization of MP-SoC Middleware for Event-driven Applications, DATE University Booth, 2011 • [Talk] Several talks given in OptiMMA project User Group Meetings • [Talk] Several talks given in Scenarios Cluster Group Meetings Mentoring Experience • Main contributor and mentor for the IWT-OptiMMA project in Belgium • Main contributor in System Scenarios Research group • Guided 10 student groups, worked on DSP optimizations for Crypto and Speech codecs projects on TI C64X+ DSP • Guided 3 master thesis students in IMEC from ALaRI and Lund Universities Teaching Assistantship • Architecture for multimedia systems & Architecture synthesis and compilation course in K.U.Leuven for 3 years. • Data Transfer and Storage Exploration course in K.U.Leuven for 3 years • Numerical and Scientific Computing, Introduction to Computers and Programming courses in IIT-Delhi Extracurricular Activities and Hobbies • Programming stands first in the list of my hobbies • Active Volunteer for ROSE vzw social organization • Worked as webmaster for ROSE vzw and ISAL organizations • Administrator for Agere IDC CVS and weekly script & web interface • Playing chess and Chinese checker, Reading books and Surfing net • Always trying to learn new things and new technology from available resources • Very much interested to explore challenging problems • Class representative at school and college level • Worked as a volunteer for Intel and MCL laboratories in IIT-Delhi CSE department Personal Profile Full Name : Miniskar Narasinga Rao Father Name : Miniskar Subba Rao Nationality : Indian Sex : Male Marital status : Married Date of Birth : 24-12-1979. Language Proficiency : English, Telugu, Hindi and Marathi. References Prof. Francky Catthoor, SSET/DT, IMEC, Heverlee, Belgium - 3001 catthoor@imec.be
Prof. Roel Wuyts, SSET/DT, IMEC, Heverlee, Belgium - 3001 wuytsr@imec.be
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Sankaran Chandramouleeswaran, Technical Director, Agere Systems (Now LSI), Bengalore, India mouli.sankaran@lsi.com