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3-D TSV: Insight On Critical Issues And Market Analysis
Published on July 2014
Report Summary TSV is a vertical electrical connection that passes completely through a silicon wafer or chip to create 3D ICs or packages. The drivers for market adoption of 3D ICs are increased performance, reduced form factor and cost reduction. This report analyzes the market for TSV ICs, equipment, and materials. A critical element in enabling 3D integration is the Through-Silicon Via (TSV); a large, metal-filled conduit passing through the silicon substrate. TSV provides the high-bandwidth interconnection between stacked chips. The TSV process, which is more complex than initially anticipated, is now beginning to enter production. A $900 million equipment market in 2015
Table of Content TABLE OF CONTENTS Chapter 1 Introduction 1-1 Chapter 2 Insight Into Critical Issues 2-1 2.1 Driving Forces In 3-D TSV 2-1 2.2 Benefits of 3-D ICs With TSVs 2-2 2.3 Requirements For A Cost Effective 3-D Die Stacking Technology 2-3 2.4 TSV Technology Challenges 2-4 2.5 TSV Supply Chain Challenge 2-13 2.6 Limitations of 3-D Packaging Technology 2-14 2.6.1 Thermal Management 2-14 2.6.2 Cost 2-16 2.6.3 Design Complexity 2-16 2.6.4 Time to Delivery 2-17 Chapter 3 Cost Structure 3-1 3.1 Cost Structure of 3-D chip Stacks 3-1 3.2 Cost of Ownership 3-5 Chapter 4 Critical Processing Technologies 4-1 4.1 Introduction 4-1
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>> Get this Report Now by email! 4.2 Cu Plating 4-3 4.3 Lithography 4-5 4.3.1 Optical Lithography 4-5 4.3.2 Imprint Lithography 4-6 4.3.3 Resist Coat 4-7 4.4 Plasma Etch Technology 4-8 4.5 Stripping/Cleaning 4-12 4.6 Thin Wafer Bonding 4-14 4.7 Wafer Thinning/CMP 4-19 4.8 Stacking 4-20 4.9 Metrology/Inspection 4-22 Chapter 5 Evaluation Of Critical Development Segments 5-1 5.1 Introduction 5-1 5.2 Via-first 5-3 5.2.1 Equipment Requirements 5-5 5.2.2 Material Requirements 5-7 5.3 Via-Middle 5-8 5.3.1 Equipment Requirements 5-10 5.3.2 Material Requirements 5-11 5.4 Via-Last 5-14 5.4.1 Equipment Requirements 5-14 5.4.2 Material Requirements 5-15 5.5 Interposers 5-17 Chapter 6 Profiles Of Participants 6-1 6.1 Chip Manufacturers/Packaging Houses/Services 6-1 ASE ALLVIA Amkor ams AG s BeSang Dai Nippon Printing Elpida Memory Freescale Fujikura GlobalFoundries IBM Infineon Intel Invensas Micron Technology NEC Oki Electric
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>> Get this Report Now by email! Renesas Samsung Silex Microsystems SMIC SK Hynix STATS ChipPAC STMicroelectronics Tezzaron Toshiba ThruChip Communications TSMC UMC Xilinx Ziptronix 6.2 Equipment Suppliers 6-18 Applied Materials Datacon EVG Lam Research PVA TePLA Rudolph Technologies Spectra Physics Suss MicroTec Tokyo Electron Ltd. Ultratech 6.3 Material Suppliers 6-24 3M Adeka Alchimer Atotech AZ Brewer Science Cabot Microelectronics Dow Chemical DuPont Electronics Enthone Thin Materials AG 6.4 R&D 6-30 3D Alliance A*STAR CEA-Leti Fraunhofer IZM KAIST Sematech Chapter 7 Market Analysis 7-1 7.1 TSV Device Roadmap 7-1
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LIST OF TABLES 1.1 3-D Mass Memory Volume Comparison Between Other Technologies And TI's 3-D Technology 1-8 1.2 3-D Mass Memory Weight Comparison Between Other Technologies And TI's 3-D Technology 1-9 3.1 Cost Of Ownership Comparison 3-15 4.1 Via Middle Metrology/Inspection Requirements 4-24 4.2 Via Last Metrology/Inspection Requirements 4-26 7.1 Forecast Of TSV Devices By Units 7-4 7.2 Forecast Of TSV Devices By Wafers 7-6 7.3 Forecast Of TSV Equipment by Type 7-9
LIST OF FIGURES 1.1 3-D Technology On Dram Density 1-2 1.2 3-D Through-Silicon Via (TSV) 1-6 1.3 Graphical Illustration Of The Silicon Efficiency Between MCMs And 3-D Technology 1-10 1.4 Silicon Efficiency Comparison Between 3-D Packaging Technology and Other Conventional Packaging Technologies 1-11 2.1 TSV Fabrication Process Challenges 2-6 2.2 TSV Fabrication Process Challenge ' Cu Protrusion 2-7 2.3 TSV Reliability Challenges 2-10 2.4 Via Middle Process Integration Challenges 2-11 2.5 Via Middle Process Integration Challenges 2-12 3.1 Cost Structure of D2W and W2W 3-2 3.2 Assembly Cost Analysis 3-4 3.2 Cost Structure Of Different Vias And Tools 3-4 3.3 Cost Of Ownership For 5 X 50 TSV VIA Middle 3-6 3.4 Cost Of CMP For TSV VIA Middle Process 3-7 3.5 Cost Of Ownership For 10 X 100 TSV Via Middle 3-8 3.6 Cost Structure Of TSVs 5 X 50 µm 3-10 3.7 Interposer TSV: Upscaling To 10 X 100 µm 3-11 3.8 TSV Downscaling To 3×50 µm 3-12 3.9 Cost Structure Of Different Vias And Tools 3-14 3.10 Via First Cost Of Ownership 3-16 3.11 Via First Cost Of Ownership Front And Back Side 3-18 3.12 Via First Process Flow 3-19 3.13 iTSV Versus pTSV Cost Of Ownership 3-21 3.14 Effect Of TSV Depth And Diameter On Cost 3-22 4.1 Illustration Of Bosch Process 4-10
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>> Get this Report Now by email! 4.2 Key Via Middle TSV Process Steps 4-23 4.3 Key Last TSC Process Steps 4-25 5.1 VIA First, Middle, And Last Process Flows 5-2 5,2 VIA First TSV Process Flow 5-4 5.3 VIA Middle TSV Process Flow 5-9 5.4 Soft Reveal Process 5-13 5.5 VIA Last TSV Process Flow 5-15 5.6 Comparison Between 2.5D And 3D 5-18 5.7 TSV Interposer Cross Sectional Schematic With RDL Layer 5-20 5.8 Process Flow For RDL And UBM 5-21 7.1 Leading Edge TSV Roadmap 7-2 7.2 Forecast Of TSV Devices By Units 7-5 7.3 Forecast Of TSV Devices By Wafers 7-7 7.4 Forecast Of TSV Equipment by Type 7-10 7.5 Forecast Of TSV Materials 7-12
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