Me lab manual 2014 by Sax Sam

ESD-1 LAB MANUAL

M.E.APPLIED ELECTRONICS

SYSTEM DESIGN USING PIC MICROCONTROLLER Ex NO:1 Date: AIM To write a program for Transmission and Reception, LCD, Seven Segment display using PIC microcontroller. APPARATUS REQUIRED  PIC 16f877 kit  Power Cable  Serial Cable  PC PROCEDURE       

Double click on MP Lab Open project,create a new project and give file name and save Open new file,type the program and save with c extension Include the source file and enable port by “+pe”. Run compiler and close the window Open PIC LSP by clicking on PIC LSP icon Download file to pic kit to execute the output.

THEORY Serial Transmission and reception Serial communication is one of the simplest ways of communication between a microcontroller and PC or vice versa. It requires only single wire for transmission of a data and another for receiving.This communication can be used for controlling the robot from a PC manually or the computer program controls it. The serial port on your PC is a full-duplex device meaning that it can send and receive data at the same time. Once the start bit has been sent, the transmitter sends the actual data bits. There may either be 5, 6, 7, or 8 data bits, depending on the number you have selected. Both receiver and the transmitter must agree on the number of data bits, as well as the baud rate. Almost all devices transmit data using either 7 or 8 databits.

ESD-1 LAB MANUAL

M.E.APPLIED ELECTRONICS

LCD A liquid crystal display (LCD) is a flat panel display, electronic visual display, or video display that uses the light modulating properties of liquid crystals. Liquid crystals do not emit light directly.LCDs are available to display arbitrary images (as in a general-purpose computer display) or fixed images which can be displayed or hidden, such as preset words, digits, and 7-segment displays as in a digital clock. They use the same basic technology, except that arbitrary images are made up of a large number of small pixels, while other displays have larger elements. LCDs are used in a wide range of applications including computer monitors, televisions, instrument panels, aircraft cockpit displays, and signage. They are common in consumer devices such as video players, gaming devices, clocks, watches, calculators, and telephones, and have replaced cathode ray tube (CRT) displays in most applications. They are available in a wider range of screen sizes than CRT and plasma displays, and since they do not use phosphors, they do not suffer image burn-in. LCDs are, however, susceptible to image persistence. Seven segment display A seven-segment display (SSD), or seven-segment indicator, is a form of electronic display device for displaying decimal numerals that is an alternative to the more complex dot-matrix displays. Seven-segment displays are widely used in digital clocks, electronic meters, and other electronic devices for displaying numerical information In most applications, the seven segments are of nearly uniform shape and size (usually elongated hexagons, though trapezoids and rectangles can also be used), though in the case of adding machines, the vertical segments are longer and more oddly shaped at the ends in an effort to further enhance readability. The numerals 0,1,6, 7 and 9 may be represented by two or more different glyphs on seven-segment displays.The seven segments are arranged as a rectangle of two vertical segments on each side with one horizontal segment on the top, middle, and bottom. Additionally, the seventh segment bisects the rectangle horizontally. There are also fourteen-segment displays and sixteen-segment displays (for full alphanumerics); however, these have mostly been replaced by dot-matrix displays.The segments of a 7-segment display are referred to by the letters A to G, where the optional DP decimal point (an "eighth segment") is used for the display of non-integer numbers.

ESD-1 LAB MANUAL

M.E.APPLIED ELECTRONICS

PROGRAM 1a.TRANSMISSON & RECEPTION #include<16f877.h> #use delay(clock=20000000) #use rs232(baud=19200,xmit=pin_c6,rcv=pin_c7) void main() { printf("\n\r Program for Serial Reception and Transmission"); printf("\n\r Press Any Key On the Keyboard"); printf("\n\r"); while(1) { putc(getc()); } }

ESD-1 LAB MANUAL

M.E.APPLIED ELECTRONICS

1b.LCD #include<16F877.h> #use delay(clock=20000000) #use rs232(baud=19200, xmit=PIN_C6, rcv=PIN_C7) void busycheck(); unsigned int array[13]={"DEPT. OF ECE"}; unsigned char array1[] = {"ME_AE"}; unsigned char array2[] = {"ESD LAB"}; unsigned char a,i,b; void main() { output_low(PIN_B3); output_high(PIN_B1); busycheck(); output_d(0x38); output_high(PIN_B3); output_low(PIN_B3); busycheck(); output_d(0x06); output_high(PIN_B3); output_low(PIN_B3); busycheck(); output_d(0x01); output_high(PIN_B3); output_low(PIN_B3); busycheck(); output_d(0x0c); output_high(PIN_B3); output_low(PIN_B3); busycheck(); output_d(0x82); output_high(PIN_B3); output_low(PIN_B3); for (i=0;i<12;i++) { busycheck(); output_d(0x01); output_low(PIN_B1); output_high(PIN_B1); b=array[i]; output_d(b); output_high(PIN_B3); output_low(PIN_B3); 4

ESD-1 LAB MANUAL

M.E.APPLIED ELECTRONICS

} busycheck(); output_d(0xc6); output_high(PIN_B3); output_low(PIN_B3); for (i=0;i<5;i++) { busycheck(); output_d(0x01); output_low(PIN_B1); output_high(PIN_B1); b=array1[i]; output_d(b); output_high(PIN_B3); output_low(PIN_B3); } busycheck(); output_d(0x96); output_high(PIN_B3); output_low(PIN_B3); for (i=0;i<7;i++) { busycheck(); output_d(0x01); output_low(PIN_B1); output_high(PIN_B1); b=array2[i]; output_d(b); output_high(PIN_B3); output_low(PIN_B3); } busycheck(); output_d(0xd4); output_high(PIN_B3); output_low(PIN_B3); for (i=0;i<20;i++) { busycheck(); output_d(0x01); output_low(PIN_B1); output_high(PIN_B1); 5

ESD-1 LAB MANUAL

M.E.APPLIED ELECTRONICS

output_d('-'); output_high(PIN_B3); output_low(PIN_B3); } stop: goto stop; } void busycheck() { output_d(0x02); output_low(PIN_B1); output_high(PIN_B1); delay_ms(2); busy: output_high(PIN_B3); output_low(PIN_B3); a=input_d(); if ((a&0x80)==0x80) goto busy; output_d(0x0); output_low(PIN_B1); output_high(PIN_B1); delay_us(10); }

ESD-1 LAB MANUAL

M.E.APPLIED ELECTRONICS

1c.SEVENSEGMENT #include <16F877.h> #use delay(clock=20000000) #use I2C(MASTER,sda=PIN_C4,scl=PIN_C3) void IC_Config(); unsigned long int c; void main() { IC_Config(); while(1) { delay_ms(5); i2c_start(); i2c_write(0x44); i2c_write(0x00); i2c_write(0x77); i2c_write(0xfe); i2c_stop(); delay_ms(5); i2c_start(); i2c_write(0x44); i2c_write(0x00); i2c_write(0x7f); i2c_write(0xfd); i2c_stop(); delay_ms(5); i2c_start(); i2c_write(0x44); i2c_write(0x00); i2c_write(0x39); i2c_write(0xfb); i2c_stop(); delay_ms(5); i2c_start(); i2c_write(0x44); i2c_write(0x00); i2c_write(0x3f); i2c_write(0xf7); i2c_stop(); } } void IC_Config() { 7

ESD-1 LAB MANUAL

M.E.APPLIED ELECTRONICS

delay_us(1000); i2c_start(); i2c_write(0x44); i2c_write(0x04); //GPIO Register i2c_write(0x00); i2c_write(0x00); i2c_stop(); delay_us(1000); i2c_start(); i2c_write(0x44); i2c_write(0x06); //GPIO Register i2c_write(0x00); i2c_write(0x00); i2c_stop(); delay_us(1000); i2c_start(); i2c_write(0x44); i2c_write(0x0a); //GPIO Register i2c_write(0x01); i2c_write(0x01); i2c_stop(); delay_us(1000); }

RESULT Thus, the system design for Transmission & Reception,LCD,Seven Segment display are executed using PIC Microcontroller and its output are verified. 8

ESD-1 LAB MANUAL

M.E.APPLIED ELECTRONICS

SYSTEM DESIGN USING DSP Ex. No:2 Date: AIM To write a program for adaptive filter, periodogram and multistage multirate system using DSP processor SOFTWARE/APPARATUS REQUIRED  TMS 320C6713  CCS studio 3.1, vsk 6713software  Serial Cable  PC  Function generator  CRO PROCEDURE  Double click on CCS studio  Open project,create a new project and give file name and save  Open new file,type the program and save with c extension  Include the source file  Run compiler and close the window  Open vsk 6713 by clicking on vsk 6713 icon  Download file to DSP processor kit to execute the output.  Give inputs from function generator and check the executed output in the CRO. THEORY Periodogram The periodogram is based on the definition of the power spectral density (PSD) . Let random process window) contains

denote a windowed segment of samples from a , where the window function (classically the rectangular nonzero samples. Then the periodogram is defined as the

squared-magnitude DTFT of

divided by

(7.23)

ESD-1 LAB MANUAL

M.E.APPLIED ELECTRONICS

In the limit as goes to infinity, the expected value of the periodogram equals the true power spectral density of the noise process . This is expressed by writing

Adaptive filter Digital signal processing (DSP) has been a major player in the current technical advancements such as noise filtering, system identification, and voice prediction. Standard DSP techniques, however, are not enough to solve these problems quickly and obtain acceptable results. Adaptive filtering techniques must be implemented to promote accurate solutions and a timely convergence to that solution. Adaptive Filtering System Configurations There are four major types of adaptive filtering configurations; adaptive system identification, adaptive noise cancellation, adaptive linear prediction, and adaptive inverse system. All of the above systems are similar in the implementation of the algorithm, but different in system configuration. All 4 systems have the same general parts; an input x(n), a desired result d(n), an output y(n), an adaptive transfer function w(n), and an error signal e(n) which is the difference between the desired output u(n) and the actual output y(n). In addition to these parts, the system identification and the inverse system configurations have an unknown linear system u(n) that can receive an input and give a linear output to the given input. Adaptive System Identification Configuration The adaptive system identification is primarily responsible for determining a discrete estimation of the transfer function for an unknown digital or analog system. The same input x(n) is applied to both the adaptive filter and the unknown system from which the outputs are compared (see figure 1). The output of the adaptive filter y(n) is subtracted from the output of the unknown system resulting in a desired signal d(n). The resulting difference is an error signal e(n) used to manipulate the filter coefficients of the adaptive system trending towards an error signal of zero.

ESD-1 LAB MANUAL

M.E.APPLIED ELECTRONICS

PROGRAM 2.a Adaptive Filter typedef unsigned int Uint32; typedef int Int32; typedef short Int16; typedef unsigned short Uint16; int main(void) { Int16 outCh1; Int16 outCh2; Int16 *origSig; Int16 *noiseSig; Int16 alteredSig; Int16 noiseEst; double *kern; Int16 errorSig; Int32 outValue; Int32 filtCount; Uint32 *socValue; Uint32 socRead; Uint32 *adcValue; Uint32 *dacCh1; Uint16 *dacCh2; Uint16 adcOut; socValue = (Uint32 *)0x9004000c; adcValue = (Uint32 *)0x90040008; dacCh1 = (Uint32 *)0x90040008; dacCh2 = (Uint16 *)0x9004000a; origSig = (Int16 *)0x00013000; noiseSig = (Int16 *)0x00014000; kern = (double *)0x00016000; for(filtCount = 0; filtCount < 32; filtCount++) { *(noiseSig + filtCount) = 0x00000000; *(kern + filtCount) = 0x00000000; } while(1) { socRead = *socValue; adcOut = *adcValue; adcOut &= 0x0fff; //adcOut ^= 0x0800; *origSig = adcOut; 11

ESD-1 LAB MANUAL

M.E.APPLIED ELECTRONICS

adcOut = *adcValue; adcOut &= 0x0fff; adcOut ^= 0x0800; *noiseSig = adcOut; alteredSig = *origSig + *noiseSig; outValue = 0; for(filtCount = 0; filtCount < 32; filtCount++) outValue += *(noiseSig + filtCount) * *(kern + filtCount); noiseEst = outValue >> 12; errorSig = alteredSig - noiseEst; for(filtCount = 31; filtCount >= 0; filtCount--) { *(kern + filtCount) = *(kern + filtCount) + (2 * 0.0000001 * errorSig) * *(noiseSig + filtCount); *(noiseSig + filtCount + 1) = *(noiseSig + filtCount); } outCh1 = alteredSig; //*dacCh1 = adcOut; *dacCh1 = outCh1; outCh2 = errorSig; //*dacCh2 = adcOut; *dacCh2 = outCh2; } return 0; } 2.b PERIODOGRAM

#include "math.h" #define ORDER 128 #define M_PI 3.1415926535897932384626433832795 #define no_of_samples 8 void square__calc(int *w,int *o); void root(int *o_out,int *o_output); void auto_corr(int *,int *,unsigned int); void normalize(int *a1_input,int *n_a_output,unsigned int num_of_points); unsigned int max_find(int *a_input);

ESD-1 LAB MANUAL

M.E.APPLIED ELECTRONICS

//int in[25] = {1,4,3,23,2,55,8,8,44,32,68,2,99,5,1,58,45}; //int in[25] = {1,7,3,4,2,6,12,8}; //int in[32] = {1024,1223,1415,1592,1747,1874,1969,2027,2047,2027,1969,1874,1747,1592,1415, 1223,1024,825,633,456,301,174,79,21,1,21,79,174,301,456,633,825, //}; //int in[32] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19, //20,21,22,23,24,25,26,27,28,29,30,31,32}; //int in[8]={ //100,200,300,400,500,600,700,800, //}; /*int in[8]={ 100,700,300,400,200,600,1200,800, };*/ int in[8]={ 1,27,73,4,65,86,87,8, }; /* int in[32]={ 100,200,300,400,500,600,700,800,900,1000, 1100,1200,1300,1400,1500,1600,1700,1800,1900,2000, 2100,2200,2300,2400,2500,2600,2700,2800,2900,3000, 3100,3200 }; */ unsigned int num_of_points,max_th; main() { int *x,temp,N,N2,inv=0,*output,*input,*a_input,*out,*n_a_input; int ir,ii,tr,ti,ar,ai,br,bi; int i,j,k,l,le1,p,m; int twid[900]; max_th = 0; input = (int *)0x80000000; a_input = (int *)0x80004000; n_a_input = (int *)0x80005000; x = (int *)0x80001000; out = (int *)0x80002000; output = (int *)0x80003000; for(i=0;i<no_of_samples;i++){ *input++ = in[i]; } for(i=no_of_samples;i<ORDER/2;i++) *input++ = 0; input = (int *)0x80000000; auto_corr(input,a_input,64); a_input = (int *)0x80004000; max_th = max_find(a_input); 13

ESD-1 LAB MANUAL

M.E.APPLIED ELECTRONICS

if(max_th==1){ normalize(a_input,n_a_input,ORDER); n_a_input = (int *)0x80005000; for(i=0;i<128;i++){ *x++ = *n_a_input++; *x++ = 0;} } else{ a_input = (int *)0x80005000; for(i=0;i<128;i++){ *x++ = *a_input++; *x++ = 0;} } x = (int *)0x80001000; N = 128; N2 = (N << 1); twid[0] = 0x100; twid[1] = 0x0; twid[2] = 0x100; twid[3] = 0x0; twid[4] = 0x100; twid[5] = 0x0; twid[6] = 0x100; twid[7] = 0x0; twid[8] = 0x100; twid[9] = 0x0; twid[10] = 0x100; twid[11] = 0x0; twid[12] = 0x100; twid[13] = 0x0; twid[14] = 0x100; twid[15] = 0x0; twid[16] = 0x100; twid[17] = 0x0; twid[18] = 0x100; twid[19] = 0x0; twid[20] = 0x100; twid[21] = 0x0; twid[22] = 0x100; twid[23] = 0x0; twid[24] = 0x100; twid[25] = 0x0; twid[26] = 0x100; twid[27] = 0x0; twid[28] = 0x100; twid[29] = 0x0; twid[30] = 0x100; twid[31] = 0x0; twid[32] = 0x100; twid[33] = 0x0; 14

ESD-1 LAB MANUAL

twid[34] twid[35] twid[36] twid[37] twid[38] twid[39] twid[40] twid[41] twid[42] twid[43] twid[44] twid[45] twid[46] twid[47] twid[48] twid[49] twid[50] twid[51] twid[52] twid[53] twid[54] twid[55] twid[56] twid[57] twid[58] twid[59] twid[60] twid[61] twid[62] twid[63] twid[64] twid[65] twid[66] twid[67] twid[68] twid[69] twid[70] twid[71] twid[72] twid[73] twid[74] twid[75] twid[76] twid[77] twid[78] twid[79] twid[80] twid[81] twid[82] twid[83]

M.E.APPLIED ELECTRONICS

= 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; 15

ESD-1 LAB MANUAL

M.E.APPLIED ELECTRONICS

twid[84] = 0x100; twid[85] = 0x0; twid[86] = 0x100; twid[87] = 0x0; twid[88] = 0x100; twid[89] = 0x0; twid[90] = 0x100; twid[91] = 0x0; twid[92] = 0x100; twid[93] = 0x0; twid[94] = 0x100; twid[95] = 0x0; twid[96] = 0x100; twid[97] = 0x0; twid[98] = 0x100; twid[99] = 0x0; twid[100] = 0x100; twid[101] = 0x0; twid[102] = 0x100; twid[103] = 0x0; twid[104] = 0x100; twid[105] = 0x0; twid[106] = 0x100; twid[107] = 0x0; twid[108] = 0x100; twid[109] = 0x0; twid[110] = 0x100; twid[111] = 0x0; twid[112] = 0x100; twid[113] = 0x0; twid[114] = 0x100; twid[115] = 0x0; twid[116] = 0x100; twid[117] = 0x0; twid[118] = 0x100; twid[119] = 0x0; twid[120] = 0x100; twid[121] = 0x0; twid[122] = 0x100; twid[123] = 0x0; twid[124] = 0x100; twid[125] = 0x0; twid[126] = 0x100; twid[127] = 0x0; twid[128] = 0x100; twid[129] = 0x0; twid[130] = 0x100; twid[131] = 0x0; twid[132] = 0x100; twid[133] = 0x0; 16

ESD-1 LAB MANUAL

twid[134] twid[135] twid[136] twid[137] twid[138] twid[139] twid[140] twid[141] twid[142] twid[143] twid[144] twid[145] twid[146] twid[147] twid[148] twid[149] twid[150] twid[151] twid[152] twid[153] twid[154] twid[155] twid[156] twid[157] twid[158] twid[159] twid[160] twid[161] twid[162] twid[163] twid[164] twid[165] twid[166] twid[167] twid[168] twid[169] twid[170] twid[171] twid[172] twid[173] twid[174] twid[175] twid[176] twid[177] twid[178] twid[179] twid[180] twid[181] twid[182] twid[183]

M.E.APPLIED ELECTRONICS

ESD-1 LAB MANUAL

twid[184] twid[185] twid[186] twid[187] twid[188] twid[189] twid[190] twid[191] twid[192] twid[193] twid[194] twid[195] twid[196] twid[197] twid[198] twid[199] twid[200] twid[201] twid[202] twid[203] twid[204] twid[205] twid[206] twid[207] twid[208] twid[209] twid[210] twid[211] twid[212] twid[213] twid[214] twid[215] twid[216] twid[217] twid[218] twid[219] twid[220] twid[221] twid[222] twid[223] twid[224] twid[225] twid[226] twid[227] twid[228] twid[229] twid[230] twid[231] twid[232] twid[233]

M.E.APPLIED ELECTRONICS

= 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; 18

ESD-1 LAB MANUAL

twid[234] twid[235] twid[236] twid[237] twid[238] twid[239] twid[240] twid[241] twid[242] twid[243] twid[244] twid[245] twid[246] twid[247] twid[248] twid[249] twid[250] twid[251] twid[252] twid[253] twid[254] twid[255] twid[256] twid[257] twid[258] twid[259] twid[260] twid[261] twid[262] twid[263] twid[264] twid[265] twid[266] twid[267] twid[268] twid[269] twid[270] twid[271] twid[272] twid[273] twid[274] twid[275] twid[276] twid[277] twid[278] twid[279] twid[280] twid[281] twid[282] twid[283]

M.E.APPLIED ELECTRONICS

= 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; 19

ESD-1 LAB MANUAL

twid[284] twid[285] twid[286] twid[287] twid[288] twid[289] twid[290] twid[291] twid[292] twid[293] twid[294] twid[295] twid[296] twid[297] twid[298] twid[299] twid[300] twid[301] twid[302] twid[303] twid[304] twid[305] twid[306] twid[307] twid[308] twid[309] twid[310] twid[311] twid[312] twid[313] twid[314] twid[315] twid[316] twid[317] twid[318] twid[319] twid[320] twid[321] twid[322] twid[323] twid[324] twid[325] twid[326] twid[327] twid[328] twid[329] twid[330] twid[331] twid[332] twid[333]

M.E.APPLIED ELECTRONICS

= 0x100; = 0x0; = 0x100; = 0x0; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; 20

ESD-1 LAB MANUAL

twid[334] twid[335] twid[336] twid[337] twid[338] twid[339] twid[340] twid[341] twid[342] twid[343] twid[344] twid[345] twid[346] twid[347] twid[348] twid[349] twid[350] twid[351] twid[352] twid[353] twid[354] twid[355] twid[356] twid[357] twid[358] twid[359] twid[360] twid[361] twid[362] twid[363] twid[364] twid[365] twid[366] twid[367] twid[368] twid[369] twid[370] twid[371] twid[372] twid[373] twid[374] twid[375] twid[376] twid[377] twid[378] twid[379] twid[380] twid[381] twid[382] twid[383]

M.E.APPLIED ELECTRONICS

= 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; 21

ESD-1 LAB MANUAL

twid[384] twid[385] twid[386] twid[387] twid[388] twid[389] twid[390] twid[391] twid[392] twid[393] twid[394] twid[395] twid[396] twid[397] twid[398] twid[399] twid[400] twid[401] twid[402] twid[403] twid[404] twid[405] twid[406] twid[407] twid[408] twid[409] twid[410] twid[411] twid[412] twid[413] twid[414] twid[415] twid[416] twid[417] twid[418] twid[419] twid[420] twid[421] twid[422] twid[423] twid[424] twid[425] twid[426] twid[427] twid[428] twid[429] twid[430] twid[431] twid[432] twid[433]

M.E.APPLIED ELECTRONICS

= 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0xec; = 0xffffff9f; = 0xec; = 0xffffff9f; = 0xec; = 0xffffff9f; = 0xec; = 0xffffff9f; = 0xec; = 0xffffff9f; = 0xec; = 0xffffff9f; = 0xec; = 0xffffff9f; = 0xec; = 0xffffff9f; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0x61; = 0xffffff14; 22

ESD-1 LAB MANUAL

twid[434] twid[435] twid[436] twid[437] twid[438] twid[439] twid[440] twid[441] twid[442] twid[443] twid[444] twid[445] twid[446] twid[447] twid[448] twid[449] twid[450] twid[451] twid[452] twid[453] twid[454] twid[455] twid[456] twid[457] twid[458] twid[459] twid[460] twid[461] twid[462] twid[463] twid[464] twid[465] twid[466] twid[467] twid[468] twid[469] twid[470] twid[471] twid[472] twid[473] twid[474] twid[475] twid[476] twid[477] twid[478] twid[479] twid[480] twid[481] twid[482] twid[483]

M.E.APPLIED ELECTRONICS

= 0x61; = 0xffffff14; = 0x61; = 0xffffff14; = 0x61; = 0xffffff14; = 0x61; = 0xffffff14; = 0x61; = 0xffffff14; = 0x61; = 0xffffff14; = 0x61; = 0xffffff14; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0xffffff9f; = 0xffffff14; = 0xffffff9f; = 0xffffff14; = 0xffffff9f; = 0xffffff14; = 0xffffff9f; = 0xffffff14; = 0xffffff9f; = 0xffffff14; = 0xffffff9f; = 0xffffff14; = 0xffffff9f; = 0xffffff14; = 0xffffff9f; = 0xffffff14; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; 23

ESD-1 LAB MANUAL

twid[484] twid[485] twid[486] twid[487] twid[488] twid[489] twid[490] twid[491] twid[492] twid[493] twid[494] twid[495] twid[496] twid[497] twid[498] twid[499] twid[500] twid[501] twid[502] twid[503] twid[504] twid[505] twid[506] twid[507] twid[508] twid[509] twid[510] twid[511] twid[512] twid[513] twid[514] twid[515] twid[516] twid[517] twid[518] twid[519] twid[520] twid[521] twid[522] twid[523] twid[524] twid[525] twid[526] twid[527] twid[528] twid[529] twid[530] twid[531] twid[532] twid[533]

M.E.APPLIED ELECTRONICS

= 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff14; = 0xffffff9f; = 0xffffff14; = 0xffffff9f; = 0xffffff14; = 0xffffff9f; = 0xffffff14; = 0xffffff9f; = 0xffffff14; = 0xffffff9f; = 0xffffff14; = 0xffffff9f; = 0xffffff14; = 0xffffff9f; = 0xffffff14; = 0xffffff9f; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0x100; = 0x0; = 0xfb; = 0xffffffcf; = 0xfb; = 0xffffffcf; = 0xfb; = 0xffffffcf; = 0xfb; = 0xffffffcf; = 0xec; = 0xffffff9f; = 0xec; = 0xffffff9f; = 0xec; = 0xffffff9f; 24

ESD-1 LAB MANUAL

twid[534] twid[535] twid[536] twid[537] twid[538] twid[539] twid[540] twid[541] twid[542] twid[543] twid[544] twid[545] twid[546] twid[547] twid[548] twid[549] twid[550] twid[551] twid[552] twid[553] twid[554] twid[555] twid[556] twid[557] twid[558] twid[559] twid[560] twid[561] twid[562] twid[563] twid[564] twid[565] twid[566] twid[567] twid[568] twid[569] twid[570] twid[571] twid[572] twid[573] twid[574] twid[575] twid[576] twid[577] twid[578] twid[579] twid[580] twid[581] twid[582] twid[583]

M.E.APPLIED ELECTRONICS

= 0xec; = 0xffffff9f; = 0xd4; = 0xffffff72; = 0xd4; = 0xffffff72; = 0xd4; = 0xffffff72; = 0xd4; = 0xffffff72; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0x8e; = 0xffffff2c; = 0x8e; = 0xffffff2c; = 0x8e; = 0xffffff2c; = 0x8e; = 0xffffff2c; = 0x61; = 0xffffff14; = 0x61; = 0xffffff14; = 0x61; = 0xffffff14; = 0x61; = 0xffffff14; = 0x31; = 0xffffff05; = 0x31; = 0xffffff05; = 0x31; = 0xffffff05; = 0x31; = 0xffffff05; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; 25

ESD-1 LAB MANUAL

twid[584] twid[585] twid[586] twid[587] twid[588] twid[589] twid[590] twid[591] twid[592] twid[593] twid[594] twid[595] twid[596] twid[597] twid[598] twid[599] twid[600] twid[601] twid[602] twid[603] twid[604] twid[605] twid[606] twid[607] twid[608] twid[609] twid[610] twid[611] twid[612] twid[613] twid[614] twid[615] twid[616] twid[617] twid[618] twid[619] twid[620] twid[621] twid[622] twid[623] twid[624] twid[625] twid[626] twid[627] twid[628] twid[629] twid[630] twid[631] twid[632] twid[633]

M.E.APPLIED ELECTRONICS

= 0xffffffcf; = 0xffffff05; = 0xffffffcf; = 0xffffff05; = 0xffffffcf; = 0xffffff05; = 0xffffffcf; = 0xffffff05; = 0xffffff9f; = 0xffffff14; = 0xffffff9f; = 0xffffff14; = 0xffffff9f; = 0xffffff14; = 0xffffff9f; = 0xffffff14; = 0xffffff72; = 0xffffff2c; = 0xffffff72; = 0xffffff2c; = 0xffffff72; = 0xffffff2c; = 0xffffff72; = 0xffffff2c; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff2c; = 0xffffff72; = 0xffffff2c; = 0xffffff72; = 0xffffff2c; = 0xffffff72; = 0xffffff2c; = 0xffffff72; = 0xffffff14; = 0xffffff9f; = 0xffffff14; = 0xffffff9f; = 0xffffff14; = 0xffffff9f; = 0xffffff14; = 0xffffff9f; = 0xffffff05; = 0xffffffcf; 26

ESD-1 LAB MANUAL

twid[634] twid[635] twid[636] twid[637] twid[638] twid[639] twid[640] twid[641] twid[642] twid[643] twid[644] twid[645] twid[646] twid[647] twid[648] twid[649] twid[650] twid[651] twid[652] twid[653] twid[654] twid[655] twid[656] twid[657] twid[658] twid[659] twid[660] twid[661] twid[662] twid[663] twid[664] twid[665] twid[666] twid[667] twid[668] twid[669] twid[670] twid[671] twid[672] twid[673] twid[674] twid[675] twid[676] twid[677] twid[678] twid[679] twid[680] twid[681] twid[682] twid[683]

M.E.APPLIED ELECTRONICS

= 0xffffff05; = 0xffffffcf; = 0xffffff05; = 0xffffffcf; = 0xffffff05; = 0xffffffcf; = 0x100; = 0x0; = 0x100; = 0x0; = 0xfe; = 0xffffffe7; = 0xfe; = 0xffffffe7; = 0xfb; = 0xffffffcf; = 0xfb; = 0xffffffcf; = 0xf4; = 0xffffffb6; = 0xf4; = 0xffffffb6; = 0xec; = 0xffffff9f; = 0xec; = 0xffffff9f; = 0xe1; = 0xffffff88; = 0xe1; = 0xffffff88; = 0xd4; = 0xffffff72; = 0xd4; = 0xffffff72; = 0xc5; = 0xffffff5e; = 0xc5; = 0xffffff5e; = 0xb5; = 0xffffff4b; = 0xb5; = 0xffffff4b; = 0xa2; = 0xffffff3b; = 0xa2; = 0xffffff3b; = 0x8e; = 0xffffff2c; = 0x8e; = 0xffffff2c; 27

ESD-1 LAB MANUAL

twid[684] twid[685] twid[686] twid[687] twid[688] twid[689] twid[690] twid[691] twid[692] twid[693] twid[694] twid[695] twid[696] twid[697] twid[698] twid[699] twid[700] twid[701] twid[702] twid[703] twid[704] twid[705] twid[706] twid[707] twid[708] twid[709] twid[710] twid[711] twid[712] twid[713] twid[714] twid[715] twid[716] twid[717] twid[718] twid[719] twid[720] twid[721] twid[722] twid[723] twid[724] twid[725] twid[726] twid[727] twid[728] twid[729] twid[730] twid[731] twid[732] twid[733]

M.E.APPLIED ELECTRONICS

= 0x78; = 0xffffff1f; = 0x78; = 0xffffff1f; = 0x61; = 0xffffff14; = 0x61; = 0xffffff14; = 0x4a; = 0xffffff0c; = 0x4a; = 0xffffff0c; = 0x31; = 0xffffff05; = 0x31; = 0xffffff05; = 0x19; = 0xffffff02; = 0x19; = 0xffffff02; = 0x0; = 0xffffff00; = 0x0; = 0xffffff00; = 0xffffffe7; = 0xffffff02; = 0xffffffe7; = 0xffffff02; = 0xffffffcf; = 0xffffff05; = 0xffffffcf; = 0xffffff05; = 0xffffffb6; = 0xffffff0c; = 0xffffffb6; = 0xffffff0c; = 0xffffff9f; = 0xffffff14; = 0xffffff9f; = 0xffffff14; = 0xffffff88; = 0xffffff1f; = 0xffffff88; = 0xffffff1f; = 0xffffff72; = 0xffffff2c; = 0xffffff72; = 0xffffff2c; = 0xffffff5e; = 0xffffff3b; 28

ESD-1 LAB MANUAL

twid[734] twid[735] twid[736] twid[737] twid[738] twid[739] twid[740] twid[741] twid[742] twid[743] twid[744] twid[745] twid[746] twid[747] twid[748] twid[749] twid[750] twid[751] twid[752] twid[753] twid[754] twid[755] twid[756] twid[757] twid[758] twid[759] twid[760] twid[761] twid[762] twid[763] twid[764] twid[765] twid[766] twid[767] twid[768] twid[769] twid[770] twid[771] twid[772] twid[773] twid[774] twid[775] twid[776] twid[777] twid[778] twid[779] twid[780] twid[781] twid[782] twid[783]

M.E.APPLIED ELECTRONICS

= 0xffffff5e; = 0xffffff3b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff4b; = 0xffffff3b; = 0xffffff5e; = 0xffffff3b; = 0xffffff5e; = 0xffffff2c; = 0xffffff72; = 0xffffff2c; = 0xffffff72; = 0xffffff1f; = 0xffffff88; = 0xffffff1f; = 0xffffff88; = 0xffffff14; = 0xffffff9f; = 0xffffff14; = 0xffffff9f; = 0xffffff0c; = 0xffffffb6; = 0xffffff0c; = 0xffffffb6; = 0xffffff05; = 0xffffffcf; = 0xffffff05; = 0xffffffcf; = 0xffffff02; = 0xffffffe7; = 0xffffff02; = 0xffffffe7; = 0x100; = 0x0; = 0xff; = 0xfffffff4; = 0xfe; = 0xffffffe7; = 0xfd; = 0xffffffdb; = 0xfb; = 0xffffffcf; = 0xf8; = 0xffffffc2; = 0xf4; = 0xffffffb6; = 0xf1; = 0xffffffaa; 29

ESD-1 LAB MANUAL

twid[784] twid[785] twid[786] twid[787] twid[788] twid[789] twid[790] twid[791] twid[792] twid[793] twid[794] twid[795] twid[796] twid[797] twid[798] twid[799] twid[800] twid[801] twid[802] twid[803] twid[804] twid[805] twid[806] twid[807] twid[808] twid[809] twid[810] twid[811] twid[812] twid[813] twid[814] twid[815] twid[816] twid[817] twid[818] twid[819] twid[820] twid[821] twid[822] twid[823] twid[824] twid[825] twid[826] twid[827] twid[828] twid[829] twid[830] twid[831] twid[832] twid[833]

M.E.APPLIED ELECTRONICS

= 0xec; = 0xffffff9f; = 0xe7; = 0xffffff93; = 0xe1; = 0xffffff88; = 0xdb; = 0xffffff7d; = 0xd4; = 0xffffff72; = 0xcd; = 0xffffff68; = 0xc5; = 0xffffff5e; = 0xbd; = 0xffffff55; = 0xb5; = 0xffffff4b; = 0xab; = 0xffffff43; = 0xa2; = 0xffffff3b; = 0x98; = 0xffffff33; = 0x8e; = 0xffffff2c; = 0x83; = 0xffffff25; = 0x78; = 0xffffff1f; = 0x6d; = 0xffffff19; = 0x61; = 0xffffff14; = 0x56; = 0xffffff0f; = 0x4a; = 0xffffff0c; = 0x3e; = 0xffffff08; = 0x31; = 0xffffff05; = 0x25; = 0xffffff03; = 0x19; = 0xffffff02; = 0xc; = 0xffffff01; = 0x0; = 0xffffff00; 30

ESD-1 LAB MANUAL

twid[834] twid[835] twid[836] twid[837] twid[838] twid[839] twid[840] twid[841] twid[842] twid[843] twid[844] twid[845] twid[846] twid[847] twid[848] twid[849] twid[850] twid[851] twid[852] twid[853] twid[854] twid[855] twid[856] twid[857] twid[858] twid[859] twid[860] twid[861] twid[862] twid[863] twid[864] twid[865] twid[866] twid[867] twid[868] twid[869] twid[870] twid[871] twid[872] twid[873] twid[874] twid[875] twid[876] twid[877] twid[878] twid[879] twid[880] twid[881] twid[882] twid[883]

M.E.APPLIED ELECTRONICS

= 0xfffffff4; = 0xffffff01; = 0xffffffe7; = 0xffffff02; = 0xffffffdb; = 0xffffff03; = 0xffffffcf; = 0xffffff05; = 0xffffffc2; = 0xffffff08; = 0xffffffb6; = 0xffffff0c; = 0xffffffaa; = 0xffffff0f; = 0xffffff9f; = 0xffffff14; = 0xffffff93; = 0xffffff19; = 0xffffff88; = 0xffffff1f; = 0xffffff7d; = 0xffffff25; = 0xffffff72; = 0xffffff2c; = 0xffffff68; = 0xffffff33; = 0xffffff5e; = 0xffffff3b; = 0xffffff55; = 0xffffff43; = 0xffffff4b; = 0xffffff4b; = 0xffffff43; = 0xffffff55; = 0xffffff3b; = 0xffffff5e; = 0xffffff33; = 0xffffff68; = 0xffffff2c; = 0xffffff72; = 0xffffff25; = 0xffffff7d; = 0xffffff1f; = 0xffffff88; = 0xffffff19; = 0xffffff93; = 0xffffff14; = 0xffffff9f; = 0xffffff0f; = 0xffffffaa; 31

ESD-1 LAB MANUAL

twid[884] twid[885] twid[886] twid[887] twid[888] twid[889] twid[890] twid[891] twid[892] twid[893] twid[894] twid[895]

M.E.APPLIED ELECTRONICS

= 0xffffff0c; = 0xffffffb6; = 0xffffff08; = 0xffffffc2; = 0xffffff05; = 0xffffffcf; = 0xffffff03; = 0xffffffdb; = 0xffffff02; = 0xffffffe7; = 0xffffff01; = 0xfffffff4;

if(inv == 1) { for(i=0;i<180;i++) { if((i%2) != 0) { twid[i] = (-1)*twid[i]; } } } j = 1; for(i=1;i<N2;i+=2) { if(j>i) { {temp=x[j];x[j]=x[i];x[i]=temp;} {temp=x[j-1];x[j-1]=x[i-1];x[i-1]=temp;} } m = N2>>1; while(m >= 2 && j>m) { j-=m; m>>=1; } j+=m; } k = 0; for(l=2;l<=N;l=l<<1) { le1 = 2*l; for(p=0;p<l;p+=2) { i = p; while(i<N2) { 32

ESD-1 LAB MANUAL

M.E.APPLIED ELECTRONICS

j = i + l; ir = x[j]; ii = x[j+1]; tr = twid[k++]; ti = twid[k++]; x[j] = (ir*tr) - (ii*ti); x[j+1] = (ir*ti) + (ii*tr); x[j] = x[j] >> 8; x[j+1] = x[j+1] >> 8; ar = x[i]; ai = x[i+1]; br = x[j]; bi = x[j+1]; x[i] = ar + br; x[i+1] = ai + bi; x[j] = ar - br; x[j+1] = ai - bi; i = i + le1; } } } if(inv == 1) { for(i=0;i<N2;i++) x[i] = x[i]/N; } x = (int *)0x80001000; out = (int *)0x80002000;

square__calc(x,out); while(1); }

void square__calc(int *w,int *o){ long t1,t2,t3,t4,c; for(c=0;c<ORDER;c++){ t1 = *w++; t2 = *w++; t1 = t1 * t1; t2 = t2 * t2; t3 = t1 + t2; t4 = sqrt(t3); *o++ = (int)t4; } return; } 33

ESD-1 LAB MANUAL

M.E.APPLIED ELECTRONICS

void auto_corr(int *x_in,int *x_in_xx,unsigned int ac_n){ unsigned int ac_local,ac_index,ac_count,i,index; int sum,temp,*xx; //

xx = (float *)malloc(2*ac_n); xx = (int *)0x80090000; ac_count = ac_n-1; for(ac_index=0;ac_index<ac_count;ac_index++){ xx[ac_index] = 0; xx[ac_index+ac_n+ac_count] = 0;}

ac_local = 0; for(ac_index=0;ac_index<ac_n;ac_index++){ xx[ac_index+ac_count] = x_in[ac_index]; }

for(index=0;index<(2*ac_n)-1;index++){ sum=0; for(ac_index=0;ac_index<ac_n;ac_index++){ temp = x_in[ac_index] * xx[ac_index]; sum = sum + temp; x_in_xx[index] = sum; } for(i=0;i<(2*ac_count)+ac_n;i++) xx[i] = xx[i+1]; } // for make 2n-1 + 1 x_in_xx[index] = 0; return; } void normalize(int *nor_a_input,int *n_a_output,unsigned int nor_n){ unsigned int nor_i; for(nor_i=0;nor_i<nor_n;nor_i++){ n_a_output[nor_i] = nor_a_input[nor_i]/128; } return; }

ESD-1 LAB MANUAL

M.E.APPLIED ELECTRONICS

unsigned int max_find(int *a_input){ unsigned int mf_i,mf_threshold = 5000,ret_val=0; for(mf_i=0;mf_i<ORDER;mf_i++){ if(a_input[mf_i]>mf_threshold){ ret_val = 1; break;} } return(ret_val); }

2.c MULTIRATE MULTIFILTER #include "deci3.h" #include "deci4.h" #include <stdio.h> /* Specifications for the filters used: fs = 8 KHz, fp1 = fp2 = 700 Hz, fs1 = 3000 Hz, fs2 = 1000 Hz, dp1 = dp2 = 0.005, ds1 = ds2 = 0.001, N1 = 8, N2 = 37, M1 = M2 = L2 = L1 = 2. For every 4 samples read from the adc the following approximate times apply without using any additional delays: samples 1 and 3: 16 us, sample 2: 28 us, sample 4: 0.1 ms sample 1 = indexSamp 1 sample 2 = indexSamp 2 sample 3 = indexSamp 3 sample 4 = indexSamp 0 This means that without using additional delays the samples are not read at the 8 Khz rate. Therefore appropriate delays are added for samples 1, 2, 3 and 4 so that each sample would be read at a rate close to 8 KHz (0.125 ms). */ typedef unsigned int Uint32; typedef int Int32; typedef short Int16; typedef unsigned short Uint16; typedef unsigned char Uchar; 35

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Uint32 *inDeciM1; Uint32 *inDeciM2; Uint32 *inInterpL2; Uint32 *inInterpL1; Uint32 *storeL1; Uint32 *outL1; Int16 *fInterpL2; Int16 *fInterpL1; Uint16 adcOut; Uint32 valueL1; Int32 outValue; Int32 filtCount; Uchar indexL2; Uchar indexL1; Uchar indexInit; Uchar indexSamp; int deciM1(void); int deciM2(void); int interpL2(void); int interpL1(void); int main(void) { Uint32 *socValue; Uint32 *adcValue; Uint32 *dacValue; Uint32 socRead; Uchar *led; Int32 tCount; Uint32 countM1; Uint32 countM2; Uint32 countL1; Uint32 countL2; Uint32 *inTest; socValue = (Uint32 *)0x9004000c; adcValue = (Uint32 *)0x90040008; dacValue = (Uint32 *)0x90040008;

fInterpL2 = (Int16 *)0x0000a000; fInterpL1 = (Int16 *)0x0000b000;

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inDeciM1 = (Uint32 *)0x00011000; inDeciM2 = (Uint32 *)0x00012000; inInterpL2 = (Uint32 *)0x00013000; inInterpL1 = (Uint32 *)0x00014000; storeL1= (Uint32 *)0x00016000; outL1 = (Uint32 *)0x00017000; led = (Uchar *)0x90040016; inTest = (Uint32 *)0x00015000; for(filtCount = 0; filtCount < 50; filtCount++) *(inTest + filtCount) = filtCount + 0x300; for(filtCount = 0; filtCount < 37; filtCount++) *(fInterpL2 + filtCount) = *(fDeciM2 + filtCount) * 2; for(filtCount = 0; filtCount < 8; filtCount++) *(fInterpL1 + filtCount) = *(fDeciM1 + filtCount) * 2; for(filtCount = 0; filtCount < 200; filtCount++) { *(inDeciM1 + filtCount) = 0; *(inDeciM2 + filtCount) = 0; *(inInterpL2 + filtCount) = 0; *(inInterpL1 + filtCount) = 0; } indexL2 = 1; indexL1 = 1; countM1 = 1; countM2 = 0; countL2 = 0; countL1 = 0; indexSamp = 1; while(1) {

if(indexSamp == 0) for(tCount = 0; tCount < 200; tCount++); else if ((indexSamp == 1) || (indexSamp == 3)) for(tCount = 0; tCount < 900; tCount++); else if (indexSamp == 2) for(tCount = 0; tCount < 700; tCount++);

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socRead = *socValue; adcOut = *adcValue; adcOut &= 0x0fff; adcOut ^= 0x0800; *inDeciM1 = adcOut; if(countM1 == 2) { deciM1(); countM1 = 0; countM2++; } if(countM2 == 2) { deciM2(); countM2 = 0; } if((countM1 == 0) && (countM2 == 0)) { while(countL2 < 2) { interpL2(); for(filtCount = 36; filtCount >= 0; filtCount--) *(inInterpL2 + filtCount + 1) = *(inInterpL2 + filtCount); indexInit = 1; countL2++; } } storeL1= (Uint32 *)0x00016000; if((countM1 == 0) && (countM2 == 0) && (countL2 == 2)) { while(countL1 < 4) { if(countL1 == 0) { valueL1 = *storeL1; *inInterpL1 = valueL1; } else if(countL1 == 2) 38

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{ valueL1 = *(storeL1 + 1); *inInterpL1 = valueL1; } interpL1(); for(filtCount = 7; filtCount >= 0; filtCount--) *(inInterpL1 + filtCount + 1) = *(inInterpL1 + filtCount); countL1++; } } outL1 = (Uint32 *)0x00017000; if(indexInit == 0) outValue = 0x800; else outValue = *(outL1 + indexSamp);

*dacValue = outValue; indexSamp++;

countL1 = 0; countL2 = 0; for(filtCount = 7; filtCount >= 0; filtCount--) *(inDeciM1 + filtCount + 1) = *(inDeciM1 + filtCount); countM1++; if(indexSamp == 4) indexSamp = 0; } return 0; } int deciM1(void) { for(filtCount = 36; filtCount >= 0; filtCount--) *(inDeciM2 + filtCount + 1) = *(inDeciM2 + filtCount); outValue = 0; 39

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for(filtCount = 0; filtCount < 8; filtCount++) outValue += *(inDeciM1 + filtCount) * *(fDeciM1 + filtCount); outValue >>= 14; *inDeciM2 = outValue; return 0; } int deciM2(void) { outValue = 0; for(filtCount = 0; filtCount < 37; filtCount++) outValue += *(inDeciM2 + filtCount) * *(fDeciM2 + filtCount); outValue >>= 14; *inInterpL2 = outValue; return 0; } int interpL2(void) { indexL2 ^= 0x01; if(indexL2 == 0) filtCount = 0; else filtCount = 1; outValue = 0; while(filtCount < 37) { outValue += *(inInterpL2 + filtCount) * *(fInterpL2 + filtCount); filtCount += 2; } outValue >>= 16; *storeL1++ = outValue; return 0; } int interpL1(void) {

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indexL1 ^= 0x01; if(indexL1 == 0) filtCount = 0; else filtCount = 1; outValue = 0; while(filtCount < 8) { outValue += *(inInterpL1 + filtCount) * *(fInterpL1 + filtCount); filtCount += 2; } outValue >>= 16; *outL1++ = outValue; return 0; }

RESULT: Thus a program for adaptive filter, periodogram and multistage multirate system using DSP processor are executed. 41

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SIMULATION OF QMF USING SIMULATION PACKAGE Ex.No:3a Date: AIM To design a QMF using simulation package(Matlab) SOFTWARE REQUIRED PC, MATLAB ALGORITHM  Start the program.  Get the denominator coefficient.  Get the input sequence.  Get the intial condition vector.  Calculate first all pass, second all pass and time reversed output of cascade.  Stop the program. THEORY In digital signal processing, a quadrature mirror filter is a filter most commonly used to implement a filter bank that splits an input signal into two bands. The resulting high-pass and low-pass signals are often reduced by a factor of 2, giving a critically sampled two-channel representation of the original signal. Multirate filter banks are so named because they effectively alter the sampling rate of a digital system, as indicated by the decimators (downsamplers) following the analysis filters, A0 and A1, and the expanders (upsamplers) preceding the synthesis filters, S0 and S1. Properly designed analysis and synthesis filters combined with the properties of decimation and expansion allow filter banks to partition a wideband input signal into multiple frequency bands (often called subbands or channels) and to recombine these subband signals back into the original signal. In the case of Figure a, the analysis filters, A 0 and A1, are typically complementary lowpass and highpass filters that mirror each other about the digital freque one fourth the sampling frequency. 42

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Figure. (a) Block diagram of a simple two-channel multirate system, and (b) approximate magnitude responses of analysis filters, A0 and A1

PROGRAM clear all; a=input('Enter the denominator coefficient:'); N=length(a)-1; k=[0:N]; b(1+k)=a(1+N-k); x1=input('Enter the input seq:'); M=length(x1); zi=input('Enter the intial condition vector:'); N=length(zi); [yf1,zf1]=filter(b,a,x1,zi); zf2=fliplr(zf1); x2=fliplr(yf1); yf2=filter(b,a,x2,zf2); yf3=fliplr(yf2); disp('Input='); disp(x1); disp('Output of first all pass='); disp(yf1); disp('Output of second all pass='); disp(yf2); disp('Time reversed output of cascade='); disp(yf3); 43

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OUTPUT Enter the denominator coefficient:[1 3 5 7] Enter the input seq:[4 6 8 0] Enter the intial condition vector:[20 40 60] Input= 4 6 8 0 Output of first all pass= 48 -42 44 -196 Output of second all pass= -680 2048 -2034 Time reversed output 684

684 -2034

2048

-680

RESULT: Thus the QMF was designed using simulation package and its output is verified.

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SIMULATION OF DECIMATION AND INTERPOLATION USING MATLAB Ex.No:3b Date: AIM To simulate decimation and interpolation by using simulation package(Matlab). SOFTWARE REQUIRED MATLAB THEORY Digital Interpolation by a Factor of L Consider a band-limited discrete-time signal x(m) with a base-band spectrum X(f) as shown in Figure 1. The sampling rate can be increased by a factor of L through interpolation of L–1 samples between every two samples of x(m). In the following it is shown that digital interpolation by a factor of L can be achieved through a twostage process of: (a) Insertion of L–1 zeros in between every two samples and (b) Low-pass filtering of the zero-inserted signal by a filter with a cutoff frequency of Fs/2L, where Fs is the sampling rate.

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Digital Decimation by a Factor of L Consider a band-limited discrete-time signal x(m) with a base-band spectrum X(f). The sampling rate can be decreased by a factor of L through discarding of Lâ&#x20AC;&#x201C;1 samples for every L samples of x(m). In the following it is shown that digital decimation by a factor of L can be achieved through a two-stage process of: (a) Low-pass filtering of the zero-inserted signal by a filter with a cutoff frequency of Fs/2L, where Fs is the sampling rate. This is the antialisaing process. (b) Discarding of Lâ&#x20AC;&#x201C;1 samples for every L samples.

PROGRAM f=1; n=0:1/30:1; x=10*sin(2*pi*f*n); subplot(3,1,1); stem(x),title('sine wave'); xlabel('n--->'); ylabel('amp---->'); y=interp(x,2); subplot(3,1,2); stem(y); title('interpolated wave'); xlabel('n------>'); ylabel('amp---->'); y1=decimate(x,2); subplot(3,1,3); stem(y1); title('decimated wave'); xlabel('n--->'); ylabel('amp--->');

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OUTPUT sine wave

amp---->

10 0 -10

20 n---> interpolated wave

amp---->

10 0 -10

40 n------> decimated wave

amp--->

10 0 -10

8 n--->

RESULT Thus the decimation and interpolation was designed using simulation package and its output is verified.

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MODELING OF SEQUENTIAL DIGITAL SYSTEM USING VERILOG Ex:No:4 Date: AIM To design the following sequential circuits and to verify its input & output characteristics using verilog(Xilinx). a )SR Flipflop b) JK Flipflop c) D-flipflop, d) T-flipflop, e) Register f) Shift Register g) PIPO shift register h)synchronous counter i)asynchoronous counter j) up counter k) Down counter l) Up doun counter m) ring counter SOFTWARE REQUIRED

 Xilinx

PROCEDURE                 

Open project navigator. Go to the file and click the new project Type the project name The “property wizard” is open to check all properties such as product, categories, family, device etc. then click next Create new source, the wizard appears then click next Project summary is displayed then click next Go to the project and click “new source” Then type the full name “XXXX” as well as select verilog module then click next “Define module window” here we assign the input and output clicks next and click finish Type the program and save it Make sure that the source is in “BEHAVIOUR” Synthesize the program and check for errors. Creation of test bench waveform Open project new source, then select test bench waveform and give a file name click next. Then click the ISE simulator and view the signal window Force the input data corresponding circuit. Simulate the program using ISE simulator.

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THEORY SR Flipflop

Its inputs, Set and Reset, provide the means for changing the state, Q, of the circuit. When both inputs, R and S, are equal to 0 the latch maintains its existing state. This state may be either Qa = 0 and Qb = 1, or Qa = 1and Qb = 0, which is indicated in the truth table by stating that the Qa and Qb outputs have values 0/1 and 1/0, respectively. Observe that Qa and Qb are complements of each other in this case. When R = 0 and S = 1, the latch is set into a state where Qa = 1 and Qb = 0.When R = 1 and S = 0, the latch is reset into a state where Qa = 0 and Qb = 1. The fourth possibility is to have R = S = 1. In this case both Qa and Qb will be 0. D Flipflop It has a single data input, called D, and it stores the value on this input, under the control of a clock signal. It is called a gated D latch. shows the circuit for a gated D latch. It is based on the gated SR latch, but instead of using the S and R inputs separately, it has just one data input, 49

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D. For convenience we have labeled the points in the circuit that are equivalent to the S and R inputs. If D = 1, then S = 1 and R = 0, which forces the latch into the state Q = 1. If D = 0, then S = 0 and R = 1, which causes Q = 0. Of course, the changes in state occur only when Clk = 1. It is important to observe that in this circuit it is impossible to have the troublesome situation where S = R = 1. In the gated D latch, the output Q merely tracks the value of the input D while Clk = 1. As soon as Clk goes to 0, the state of the latch is frozen until the next time the clock signal goes to 1. Therefore, the gated D latch stores the value of the D input seen at the time the clock changes from 1 to 0.

T Flipflop

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By including some simple logic circuitry to drive its input, the D flip-flop may appear to be a different type of storage element. An interesting modification is presented in Figure . This circuit uses a positive-edge-triggered D flip-flop.The feedback connections make the input signal D equal to either the value of Q or Q under the control of the signal that is labeled T. On each positive edge of the clock, the flip-flop may change its state Q(t). If T = 0, then D = Q and the state will remain the same, that is, Q(t + 1) = Q(t). But if T = 1, then D = Q and the new state will be Q(t + 1) = Q(t). Therefore, the overall operation of the circuit is that it retains its present state if T = 0, and it reverses its present state if T = 1. The operation of the circuit is specified in the form of a truth table in Figure Any circuit that implements this truth table is called a T flip-flop. The name T flip-flopderives from the behavior of the circuit, which â&#x20AC;&#x153;togglesâ&#x20AC;? its state when T = 1. The togglefeature makes the T flip-flop a useful element for building counter circuits JK Flipflop

Instead of using a single control input, T, we can use two inputs, J and K, as indicated in Figure. For this circuit the input D is defined as D = JQ + KQ 51

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A corresponding truth table is given in Figure. The circuit is called a JK flip-flop. It combines the behaviors of SR and T flip-flops in a useful way. It behaves as the SR flip-flop, where J = S and K = R, for all input values except J = K = 1. For the latter case, which has to be avoided in the SR flip-flop, the JK flip-flop toggles its state like the T flip-flop. The JK flip-flop is a versatile circuit. It can be used for straight storage purposes, just like the D and SR flip-flops. But it can also serve as a T flip-flop by connecting the J and K inputs together. Registers A flip-flop stores one bit of information. When a set of n flip-flops is used to store n bits of information, such as an n-bit number, we refer to these flip-flops as a register. A common clock is used for each flip-flop in a register. he term register is merely a convenience for referring to n-bit structures consisting of flip-flops. Shift Register

Fig. shows a four-bit shift register that is used to shift its contents one bitposition to the right. The data bits are loaded into the shift register in a serial fashion using the In input. The contents of each flip-flop are transferred to the next flip-flop at each positive edge of the clock.

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Counters Design circuits that can increment or decrement a count by 1. Counter circuits are used in digital systems for many purposes. They may count the number of occurrences of certain events, generate timing intervals for control of various tasks in a system, keep track of time elapsed between specific events, and so on. counter circuits can be designed using T and D flip-flops. Asynchronous counters Only the first flip-flop is clocked by an external clock. All subsequent flip-flops are clocked by the output of the preceding flipflop.Asynchronous counters are slower than synchronous counters because of the delay in the transmission of the pulses from flip-flop to flip-flop.Asynchronous counters are also called ripple-counters because of the way the clock pulse ripples it way through the flip-flops.

Synchronous Counters The asynchronous counters are simple, but not very fast. If a counter with a larger number of bits is constructed in this manner, then the delays caused by the cascaded clocking scheme may become too long to meet the desired performance requirements. We can build a faster counter by clocking all flip-flops at the same time, using the approach described below. A 4-bit synchronous counter built from D-flipflops with carry-input (count-enable) and carry-output. In this circuit, the single clock signal is directly connected to all flipflops, so that all flipflops change state at the same time. Ex: Ring counter It is possible to devise a counterlike circuit in which each flip-flop reaches the state Qi = 1 for exactly one count, while for all other counts Qi = 0. Then Qi indicates directly an occurrence of the corresponding count. Actually, since this does not represent binary numbers, it is better to say that the 53

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outputs of the flips-flops represent a code. Such a circuit can be constructed from a simple shift register, as indicated in Figure. The Q output of the last stage in the shift register is fed back as the input to the first stage, which creates a ring like structure. If a single 1 is injected into the ring, this 1 will be shifted through the ring at successive clock cycles. For example, in a four-bit structure, the possible codes Q0Q1Q2Q3 will be 1000, 0100, 0010, and 0001

UP COUNTER A synchronous binary counter counts from 0 to 2N-1, where N is the number of bits/flip-flops in the counter. Each flip-flop is used to represent one bit. The flip-flop in the lowest-order position is complemented/toggled with every clock pulse and a flip-flop in any other position is complemented on the next clock pulse provided all the bits in the lower-order positions are equal to 1. Take for example A4 A3 A2 A1 = 0011. On the next count, A4 A3 A2 A1 = 0100. A1, the lowest-order bit, is always complemented. A2 is complemented because all the lower-order positions (A1 only in this case) are 1's. A3 is also complemented because all the lower-order positions, A2 and A1 are 1's. But A4 is not complemented the lower-order positions, A3 A2 A1 = 011, do not give an all 1 condition. To implment a synchronous counter, we need a flip-flop for every bit and an AND gate for every bit except the first and the last bit. The diagram below shows the implementation of a 4-bit synchronous up-counter.

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In a binary up counter, a particular bit, except for the first bit, toggles if all the lower-order bits are 1's. The opposite is true for binary down counters. That is, a particular bit toggles if all the lower-order bits are 0's and the first bit toggles on every pulse. Taking an example, A4 A3 A2 A1 = 0100. On the next count, A4 A3 A2 A1 = 0011. A1, the lowest-order bit, is always complemented. A2 is complemented because all the lower-order positions (A1 only in this case) are 0's. A3 is also complemented because all the lower-order positions, A2 and A1 are 0's. But A4 is not complemented the lower-order positions, A3 A2 A1 = 011, do not give an all 0 condition. Down Counter The implementation of a synchronous binary down counter is exactly the same as that of a synchronous binary up counter except that the inverted output from each flip-flop is used. All the methods used improve a binary up counter can be similarly applied here. 55

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Up/down counter A counter that can change state in either direction, under the control of an up/down selector input, is known as an up/down counter. When the selector is in the up state, the counter increments its value. When the selector is in the down state, the counter decrements the count.

3-bit Synchronous Binary Up/Down Counter From the diagram, we can see that COUNT-UP and COUNT-DOWN are used as control inputs to determine whether the normal flip-flop outputs or the inverted ones are fed into the J-K inputs of the following flip-flops. If neither is at logic level 1, the counter doesn't count and if both are at logic level 1, all the bits of the counter toggle at every clock pulse. The OR gate allows either of the two outputs which have been enabled to be fed into the next flip-flop. As with the binary up and binary down counter, the speed up techniques apply.

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PROGRAM 4.a SR Flipflop module srff(q,q1,r,s,clk); output q,q1; input r,s,clk; reg q,q1; initial begin q=1'b0; q1=1'b1; end always @(posedge clk) begin case({s,r}) {1'b0,1'b0}: begin q=q; q1=q1; end {1'b0,1'b1}: begin q=1'b0; q1=1'b1; end {1'b1,1'b0}: begin q=1'b1; q1=1'b0; end {1'b1,1'b1}: begin q=1'bx; q=1'bx; end endcase end endmodule

4.b.JK Flipflop module jk(q,q1,j,k,c); output q,q1; input j,k,c; reg q,q1; initial begin q=1'b0; q1=1'b1; end always @ (posedge c) begin case({j,k}) {1'b0,1'b0}:begin q=q; q1=q1; end {1'b0,1'b1}: begin q=1'b0; q1=1'b1; end {1'b1,1'b0}:begin q=1'b1; q1=1'b0; end {1'b1,1'b1}: begin q=~q; q1=~q1; end endcase 57

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end endmodule

4.c.D Flipflop module dff(d, clk, q, qbar); input d; input clk; output q; output qbar; reg q,qbar; always@(posedge clk) begin q=d; qbar=~d; end endmodule

4.d.T Flipflop module tff(reset, clk, t, qn1); input reset; input clk; input t; output qn1; reg qn1; always@(posedge clk or posedge reset) begin if(reset) begin qn1=0; end else begin 58

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qn1=~t; end end endmodule

4.f.4-bit Shift Register module shift4(R, L, w, Clock, Q); input [3:0] R; input L, w, Clock; output [3:0] Q; reg [3:0] Q; always @(posedge Clock) if (L) Q <= R; else begin Q[0] <= Q[1]; Q[1] <= Q[2]; Q[2] <= Q[3]; Q[3] <= w; end endmodule

4.g.PIPO shift register module pipo(din,clk,rst,dout); input [3:0] din; input clk,rst; output [3:0] dout; reg [3:0] dout; always @(posedge clk or negedge rst) begin if(!rst) 59

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begin dout <= 4'b0; end else begin dout <= din; end end endmodule

4.h.Synchronous counter-2 bit module Count2Bit(Clock, Clear, out); input Clock; input Clear; output [1:0] out; reg [1:0]out; always@(posedge Clock, negedge Clear) if((~Clear) || (out>=4))out=2'b00; else out=out+1; endmodule

4.i. Asynchronous Counter module Ripple_Counter(Count,RST,A0,A1,A2,A3); output A0,A1,A2,A3; input Count,RST; //add d0, d1, d2, d3 as instance for each D_FF: D_FF d0(~A0,A0,Count,RST); D_FF d1(~A1,A1,A0,RST); D_FF d2(~A2,A2,A1,RST); D_FF d3(~A3,A3,A2,RST); endmodule 60

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module D_FF(D,Q,CLK,RST); output Q; input D,CLK,RST; reg Q; always @ (posedge CLK or negedge RST) if(~RST) Q=1'b0; else Q=D; endmodule

4.j. Up Counter module upcounter(count,clk,n); output [3:0] count; input clk; input [3:0] n; reg [3:0] count; initial count=4'b0000; always @(negedge clk) count=(count==n)? 4'b0000:count+1'b1; endmodule

4.k.Down Counter module downcounter(count,clk,n); output [3:0] count; input clk; input [3:0] n; reg [3:0] count; initial count=4'b0000; always @(negedge clk) 61

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count=(count==4'b0000)? n:count-1'b1; endmodule

4.l. Updown Counter module up_dn(clk, u_d, n, a); input clk; input u_d; input [3:0] n; output [3:0] a; reg [3:0] a; initial a=4'b0000; always @(negedge clk) a=(u_d)?((a==n)?4'b0000:a+1'b1):((a==4'b0000)?n:a-1'b1); endmodule

4.m.Ring Counter module dff(q,d,c); output q; input d,c; reg q; initial q=1'b1; always @ (posedge c) q=d; endmodule module dff1(q,d,clk); output q; input d,clk; reg q; initial q=1'b0; 62

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always @ (posedge clk) q=d; endmodule module ring(q,clk); inout [3:0]q; input clk; dff u1(q[0],q[3],clk); dff1 u2(q[1],q[0],clk); dff1 u3(q[2],q[1],clk); dff1 u4(q[3],q[2],clk); endmodule

RESULT Thus the sequential circuits are designed using verilog and its output are verified.

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MODELING OF SEQUENTIAL DIGITAL SYSTEM USING VHDL Ex:No:5 Date: AIM:To design the following sequential circuits and to verify its input & output characteristics using verilog(Xilinx). a )SR Flipflop b) JK Flipflop c) D-flipflop d) Tflipflop SOFTWARE REQUIRED:-

 Xilinx

PROCEDURE  Open project navigator.  Go to the file and click the new project  Type the project name  The “property wizard” is open to check all properties such as product, categories, family, device etc. then click next  Create new source, the wizard appears then click next  Project summary is displayed then click next  Go to the project and click “new source”  Then type the full name “XXXX” as well as select vhdl module then click next  “Define module window” here we assign the input and output clicks next and click finish  Type the program and save it  Make sure that the source is in “BEHAVIOUR”  Synthesize the program and check for errors.  Creation of test bench waveform  Open project new source, then select test bench waveform and give a file name click next.  Then click the ISE simulator and view the signal window  Force the input data corresponding circuit.  Simulate the program using ISE simulator.

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SR Flipflop

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forces the latch into the state Q = 1. If D = 0, then S = 0 and R = 1, which causes Q = 0. Of course, the changes in state occur only when Clk = 1. It is important to observe that in this circuit it is impossible to have the troublesome situation where S = R = 1. In the gated D latch, the output Q merely tracks the value of the input D while Clk = 1. As soon as Clk goes to 0, the state of the latch is frozen until the next time the clock signal goes to 1. Therefore, the gated D latch stores the value of the D input seen at the time the clock changes from 1 to 0.

T Flipflop

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Instead of using a single control input, T, we can use two inputs, J and K, as indicated in Figure. For this circuit the input D is defined as D = JQ + KQ A corresponding truth table is given in Figure. The circuit is called a JK flip-flop. It

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combines the behaviors of SR and T flip-flops in a useful way. It behaves as the SR flip-flop, where J = S and K = R, for all input values except J = K = 1. For the latter case, which has to be avoided in the SR flip-flop, the JK flip-flop toggles its state like the T flip-flop. The JK flip-flop is a versatile circuit. It can be used for straight storage purposes, just like the D and SR flip-flops. But it can also serve as a T flip-flop by connecting the J and K inputs together. PROGRAM 5.aSR Flipflop library ieee; use ieee.std_logic_1164.all; entity RS_FF is port (clk,rst,R,S:in std_logic; Q, Qbar:inout std_logic); end RS_FF; ---------------------------------------------------architecture arch_RS_FF of RS_FF is Begin process(R,S,clk,rst) begin if(rst='1')then Q<='Z'; Qbar<='Z'; elsif(clk'event and clk='1')then if(S='0' and R='0')then Q<=Q; Qbar<=not Q; elsif(S='0' and R='1')then Q<='0'; Qbar<='1'; elsif(S='1' and R='0')then Q<='1'; Qbar<='0'; elsif(S='1' and R='1')then Q<='Z'; Qbar<='Z'; end if; end if; end process; end arch_RS_FF;

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5.b.JK Flipflop library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity JK_FF is port (clk,rst,J,K:in std_logic; Q, Qbar:inout std_logic); end JK_FF; ---------------------------------------------------architecture arch_JK_FF of JK_FF is Begin process(J,K,clk,rst) begin if(rst='1')then Q<='Z'; Qbar<='Z'; elsif(clk'event and clk='1')then if(J='0' and K='0')then Q<=Q; Qbar<=not Q; elsif(J='0' and K='1')then Q<='0'; Qbar<='1'; elsif(J='1' and K='0')then Q<='1'; Qbar<='0'; elsif(J='1' and K='1')then Q<=not Q; Qbar<=Q; end if; end if; end process; end arch_JK_FF;

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5.c.D Flipflop library ieee; use ieee.std_logic_1164.all; ----------------------------------------------entity dff is port (clk,reset,d:in std_logic; q:out std_logic); end dff; ----------------------------------------------architecture arch_dff of dff is begin process (d,clk,reset) begin if(reset='1') then q<='0'; elsif(clk'event and clk='1') then q<=d; end if; end process; end arch_dff;

5.d.T Flipflop library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity tff is port (clk,reset,t:in std_logic; q:out std_logic); end tff; architecture arch_tff of tff is 70

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begin process (t,clk,reset) begin if (reset='1') then q<='0'; elsif (clk'event and clk='1') then q<=not t; end if; end process; end arch_tff;

RESULT Thus the sequential circuits are designed using vhdl and its output are verified.

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DESIGN AND IMPEMENTATION OF ALU USING FPGA Ex:No:6 Date: AIM To design and implement ALU verify its input & output characteristics using FPGA(Xilinx).

APPARATUS/SOFTWARE REQUIRED  Xilinx Software  FPGA Kit  PC THEORY Arithmetic and Logic Unit (ALU) is a digital circuit that performs arithmetic and logical operations. The ALU is a fundamental building block of the central processing unit of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers. The processors found inside modern CPUs and graphics processing units (GPUs) accommodate very powerful and very complex ALUs; a single component may contain a number of ALUs. PROCEDURE          

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 Select the synthesis implementation.It has to process if we have no error.  Assign pin packages from user constraint.  Generate programming file.  Dowload the program to FPGA Kit and execute.

PROGRAM 6.b 2 bit-ALU module alu(a, b, f, c); input [1:0] a; input [1:0] b; input [1:0] f; output [1:0] c; reg [1:0] c; always@(a or b or f) begin case(f) 2'b00: c=a+b; 2'b01: c=a-b; 2'b10: c=a&b; 2'b11: c=a|b; endcase end endmodule

6.b 3-bit ALU module alu(a, b, c, sel); input a; input b; input [2:0]sel; output c; reg c; always @(a or b or sel) case (sel) 3'b000 : begin c=a+b; end 3'b001 : begin c=a-b; end 73

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3'b010 : begin c=a*b; end 3'b011 : begin c=a&b; end 3'b100 : begin c=a|b; end 3'b101 : begin c=a^b; end 3'b110 : begin c=~b; end 3'b111 : begin c=1'b0; end endcase endmodule

RESULT Thus ALU was designed using Verilog(Xilinx) and implemented using FPGA its and output is verified. 74

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SIMULATION OF NMOS, PMOS & CMOS CITCUITS USING SPICE ExNo:7 Date:

AIM

To design a NMOS,PMOS,CMOS inverter circuit and obtain its waveform using pspice APPARATUS /SOFTWARE REQUIRED  PSPICE software  PC THEORY NMOS Transistors

N-type metal-oxide-semiconductor logic uses n-type metal-oxidesemiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. NMOS transistors have four modes of operation: cut-off (or sub-threshold), triode, saturation (sometimes called active), and velocity saturation. The n-type MOSFETs are arranged in a so-called "pull-down network" (PDN) between the logic gate output and negative supply voltage, while a resistor is placed between the logic gate output and the positive supply voltage. The circuit is designed such that if the desired output is low, then the PDN will be active, creating a current path between the negative supply and the output. PMOS Transistors P-type metal-oxide-semiconductor logic uses p-type metal-oxidesemiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. PMOS transistors have four modes of operation: cut-off (or subthreshold), triode, saturation (sometimes called 75

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active), and velocity saturation.The p-type MOSFETs are arranged in a so-called "pull-up network" (PUN) between the logic gate output and positive supply voltage, while a resistor is placed between the logic gate output and the negative supply voltage. The circuit is designed such that if the desired output is high, then the PUN will be active, creating a current path between the positive supply and the output.

While PMOS logic is easy to design and manufacture (a MOSFET can be made to operate as a resistor, so the whole circuit can be made with PMOS FETs), it has several shortcomings as well. The worst problem is that a DC current flows through a PMOS logic gate when the PUN is active, that is whenever the output is high. This leads to static power dissipation even when the circuit sits idle. Also, PMOS circuits are slow to transition from high to low. When transitioning from low to high, the transistors provide low resistance, and the capacitative charge at the output accumulates very quickly (similar to charging a capacitor through a very low resistor). But the resistance between the output and the negative supply rail is much greater, so the high to low transition takes longer (similar to discharge a capacitor through a high resistor value). Using a resistor of lower value will speed up the process but also increases static power dissipation. Additionally, the asymmetric input logic levels make PMOS circuits susceptible to noise. Though initially easier to manufacture, PMOS logic was later supplanted by NMOS logic because NMOS is faster than PMOS. Modern fabs use CMOS, which uses both PMOS and NMOS transistors together. Static CMOS logic leverages the advantages of both by using NMOS and PMOS together in the wafer. CMOS Inverter Complementary metalâ&#x20AC;&#x201C;oxideâ&#x20AC;&#x201C;semiconductor (CMOS) is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic 76

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circuits. CMOS technology is also used for several analog circuits such as image sensors (CMOS sensor), data converters, and highly integrated transceivers for many types of communication. CMOS is also sometimes referred to as complementary-symmetry metal–oxide–semiconductor (or COS-MOS). The words "complementary-symmetry" refer to the fact that the typical digital design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions.

Two important characteristics of CMOS devices are high noise immunity and low static power consumption. Since one transistor of the pair is always off, the series combination draws significant power only momentarily during switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic, which normally have some standing current even when not changing state. CMOS also allows a high density of logic functions on a chip. It was primarily for this reason that CMOS became the most used technology to be implemented in VLSI chips. The phrase "metal–oxide– semiconductor" is a reference to the physical structure of certain fieldeffect transistors, having a metal gate electrode placed on top of an oxide insulator, which in turn is on top of a semiconductor material. PROCEDURE 1)Launch “PSpice Schematic Student” by left-clicking your mouse on “Start—PSpice Student—Schematics”. 2) Click on menu File—New, a new blank schematic sheet will appear as below. Now you can design your circuit schematic on it.click on menu File—Savetype it in “File name” row. Then click “Save”.

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1. Design your circuit in schematics. This can be divided into following substeps. 1.click on menu “Draw—Get new part” or click on the small shortcut icon of “Get New Part” Type the part name click “Place and Close” VDC simple analog voltage source, R Resistor, GND_ANALOGanalog ground

“Mbreak”: indicating it’s a MOS transistor, “N”: indicating it’s NMOS, “P” indicationg it’s a PMOS “3” or “4”: indicating it’s 3 terminal or 4 terminal. “3” terminal symbol is actually a 4-terminal symbol with its bulk (B) shorted to source (S). “D”: indicating it’s depleted device (threshold voltage Vth<0). If “D” is not specified, it’s an enhanced NMOS device (threshold voltage Vth>0). Generally we use enhanced instead of depleted devices. 2). First insert all the parts without considering their values (for example, place a resistor without considering the resistance value of it, etc.). 3). Make the necessary rotations for the parts, and move the parts to appropriate locations. 4). Make all the necessary wire connections.Please click on the small “Draw Wire” Icon press the “ESC” button on your keyboard to exit wire mode, and then click to selected the wrong wire and press “delete” button on your keyboard to delete it. Eg: Md,Ms,Mg in the transistor and click OK 5). Mark the nodes you are interested in with labels. Eg: Md,Ms,Mg in the transistor and click OK 78

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6). Set the values for all the parts, for example, the resistance values of resistors, the width (W) and length (L) of transistor, etc. 7)click to select the part, and then click menu “Edit—Attributes”, you would be able to get the popup window. Give the value and click “OK” 2. Define the SPICE parameter for NMOS and PMOS transistors. 1. click the NMOS transistor M1 so that its color turns to red. Then click menu “Edit—Model”, a popup window appear as follow. 2. click “Edit Instance Model (ModelEditor)” to open the model editor window please delete the line of: .model MbreakN-X NMOS and replace it with: .MODEL MbreakN-X NMOS LEVEL = 3 + TOX = 200E-10 NSUB = 1E17 GAMMA = 0.5 + PHI = 0.7 VTO = 0.8 DELTA = 3.0 + UO = 650 ETA = 3.0E-6 THETA = 0.1 + KP = 120E-6 VMAX = 1E5 KAPPA = 0.3 + RSH = 0 NFS = 1E12 TPG = 1 + XJ = 500E-9 LD = 100E-9 + CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10 + CJ = 400E-6 PB = 1 MJ = 0.5 + CJSW = 300E-12 MJSW = 0.5

for PMOS transistor .MODEL MbreakP-X PMOS LEVEL = 3 + TOX = 200E-10 NSUB = 1E17 GAMMA = 0.6 + PHI = 0.7 VTO = -0.9 DELTA = 0.1 + UO = 250 ETA = 0 THETA = 0.1 + KP = 40E-6 VMAX = 5E4 KAPPA = 1 + RSH = 0 NFS = 1E12 TPG = -1 + XJ = 500E-9 LD = 100E-9 + CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10 + CJ = 400E-6 PB = 1 MJ = 0.5 + CJSW = 300E-12 MJSW = 0.5 3)click menu of ModelEditor window: “File—Save as” to save it as a model library file in the same directory as your schematic file. Note: Please ensure that you click on menu “File—Save as” instead of “File—Save”, otherwise you will see following error. Please don’t click “File—Save”, instead, please click on “File—Saveas”. 4)Click on menu “File—Exit”, you will close the ModelEditor window. 79

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3. Setup analysis 1)click menu“Analysis—Setup”, a new popup window appears as below. Since we need to perform transient analysis, please check “Transient”,DC sweep,etc 2)change the “Print Step” to 0.1ms, the “Final Time” to 10ms.Now click “OK” and click “Close” to close both popup windows. 4. Run the simulation. click menu “Analysis—Simulate”. PSPICE will perform the transient simulation and open an “OrCAD PSPICE A/D Student Demo” window. 5. Observe the simulation results (traces of signals) in OrCAD PSpice A/D Demo. 1) click menu “Trace—Add Traces” in OrCAD PSpice A/D Demo. click “OK”, and you will see the waveform window To find VDS VDS=V(Md)-V(Ms), Md and Ms are the node labels we marked before. 1)Click menu “Plot—Add Plot to Window”, a new blank plot will appear in the window. 2)The “SEL>>” sign beside the blank plot indicates it’s the active plot, that is, newly added signal trace will be displayed in thisplot. 3) Now click menu “Trace—Add trace”, in the popup window, click “V(Md)” in left column,and then click “-“ sign in the right column (Analog Operations and Functions column), then againclick V(Ms) in the left column, you will see expression “V(Md)-V(Ms)” shows up in the “TraceExpression” line. 6. observe the values of voltage or current of each node directly in schematic window.Please click on the windows task bar of “Pspice Schematics” to come back to our schematicswindow, and click on the “V” and “I” icons,

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NMOS

OUTPUT

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PMOS

OUTPUT

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CMOS

RESULT

Thus the NMOS,PMOS, CMOSinverter circuits are designed and its output waveforms are obtained using PSPICE. 83

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SYSTEM DESIGN USING 16-BIT MICROPROCESSOR Ex.NO:8 Date: AIM To write a program to interface STEPPER MOTOR, TRAFFIC LIGHT CONTROLLER with 16-bit microprocessor. APPARATUS REQUIRED  8086 kit  Stepper motor  Traffic light kit  Keyboard and power cables. THEORY STEPPER MOTOR INTERFACE A motor in which the rotor is able to assume only discrete stationary angular position is a stepper motor. The basic twophase motor has two pairs of stator poles with its own windings. The excitation of any one winding generates a northand South Pole gets induced at the diametrically opposite sides.T h e s t a t o r f r a m e i s continuous and magnetic field passes through t h e cylindrical annular ring. The rotor magnetic system has two end faces. The leftface is magnetized permanently as south pole and right face as north pole. North pole structure is twisted with respect to south pole structure such that south polecomes in between two north poles.Step angle is the minimum degree of rotationassociated with single step. Revolution is the number of steps needed to completeone rotation or 360 degree. Traffic light controller Traffic light controller interface module is designed to simulate the function of four way traffic light controller. Combinations of red, amber and green LED’s are provided to indicate Halt, Wait and Go signals for vehicles. Combination of red and green LED’s are provided for pedestrian crossing. 36 LED’s are arranged in the form of an intersection.

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A typical junction is represented on the PCB with comprehensive legend printing. At the left corner of each road, a group of five LED’s (red, amber and 3 green) are arranged in the form of a T-section to control the traffic of that road. Each road is named North (N), South(S), East (E) and West (W). LED’s L1, L10, L19 & L28 (Red) are for the stop signal for the vehicles on the road N, S, W, & E respectively. L2, L11, L20 & L29 (Amber) indicates wait state for vehicles on the road N, S, W, & E respectively. L3, L4 & L5 (Green) are for left, strait and right turn for the vehicles on road S. similarly L12-L13-L14, L23-L22-L21 & L32L31-L30 simulates same function for the roads E, N, W respectively. A total of 16 LED’s (2 Red & 2 Green at each road) are provided for pedestrian crossing. L7-L9.L16-L18, L25-L27 & L34-L36 (Green) when on allows pedestrians to cross and L6-L8, L15-L17, L24-L26 & L33-L35 (Red) when on alarms the pedestrians to wait. To minimize the hardware pedestrian’s indicator LED’s (both red and green are connected to same port lines (PC4 to PC7) with red inverted. Red LED’s L10 & L28 are connected to port lines PC2 & PC3 while L1 & L19 are connected to lines PC0 & PC1 after inversion. All other LED’s (amber and green) are connected to port A & B. PROCEDURE STEPPER MOTOR  Start the program  Get the counter value and stop the program.  Get the stepping rotation vale for clockwise direction  Similarly process for anti-clockwise direction.  Stop the program. TRAFFIC LIGHT CONTROLLER  Start the program  Assign starting port controls  Execute the kit after entering program  Introduce delay for every signal operation  Stop the program after completing the verification of all directions.

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PROGRAM ADDRESS 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 100A 100B 100C 100D 100E 100F 1010 1011 1012 1013 1014 1015 1016 1017

8.a.STEPPER MOTOR INTERFACE LABEL MNEMONICS OPCODE COMMENTS START MVI DI, C7 Mov data from table TABLE to DI C7 10 18 MOV CL, 04 C6 Mov data 04 to CL CL 04 LOOP 1 MOV AL,[DI] 8A Mov data [DI] to AL reg 05 OUT C0, AL E6 O/P the AL reg data to C0 C0 MOV DX, C7 Mov data 1010 to 1010 DX C2 10 10 DELAY DEC DX 4A Decrement the DX reg JNZ DELAY 75 Jump on no zero FD INC DI 47 Increment DI reg LOOP LOOP1 E2 F2 JMP START E9 Jump to start address E8 FF

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8b.TRAFFIC LIGHT CONTROLLER ADDRESS 1000 1003 1005 1009 100D 1010 1012 1014 1017 1018 1019 101C 101E 1020 1023 1024 1025 1028 102A 102C 102F 1030 1031 1034 1036 1038 1039 103B 103D 1040 1043 1045 1047 1048 104A 104C 104D

LABEL START REPEAT

MNEMONICS MOV AL,80H OUT CNTRL,AL MOV BX, LOOKUP MOV SI, LABEL CALL OUT MOV AL,[SI] OUT PORTA, AL CALL DELAY1 INC SI INC BX CALL OUT MOV AL,[SI] OUT PORTB, AL CALL DELAY1 INC SI INC BX CALL OUT MOV AL,[SI] OUT PORTC, AL CALL DELAY1 INC SI INC BX CALL OUT MOV AL,[SI] OUT PORTC, AL INC SI MOV AL,[SI] OUTPORTA,AL CALL DELAY 1 JMP REPAEAT MOV AL,[BX] OUT PORTC,AL INC BX MOV AL,[BX] OUT PORTB,AL INC BX MOV AL,[BX] 87

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104F 1051 1054 1055 1059 105D 105E 1060 1064 1068 106C 106D 106F 1070 1072

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DELAY 1 B0: B1:

OUT PORTA,AL CALL DELAY1 RET MOV DI, 0004 MOV DX,FFFF DEC DX JNZ AI DEC DI MOV DI,00015H MOV DX,0FFFFH DEC DX JNZ BI DEC DI JNZ BI RET

RESULT Thus program to perform stepper motor interface,traffic light controller interface with 8086 was executed and verified. 88

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