lct2715_hd SERVICE MANUAL by Sherry Robbins

SERVICE MANUAL Model: LCT2715

Safety Instructions Production specification. Block Diagram Circuit Diagram Disassembly Pin Descriptions LCD Panel specification Exploded View Diagram Spare parts list V-chip password and software upgrade

This manual is the latest at the time of printing, and does not include the modification which may be made after the printing, by the constant improvement of product.

I. Safety Instructions The l ig h tn i ng fla sh w i th arro wh e ad symb ol , within an equilatera l triangle, is intended to alert the user to the presence of uninsulated “ dangerous voltage” within the prod uct’ s enclosure that may be of sufficie nt mag nitud e to consti tute a risk of electric shock to persons.

CAUTION RISK O F ELECT RIC SHO CK DO NO T O PEN

The excla mati on po i nt wi thi n a n e q ui l ate ra l tri a n gl e is i nte n de d to a le rt th e u se r to th e presence of important operating and maintenance (s e rv i ci n g ) i n str u ct i o n s i n th e l i te r a tu re accompanying the appliance.

CAUTION: TO REDUCE THE RISK OF ELECTRIC SHOCK, DO NOT REMOVE COVER (OR BACK). NO USER-SERVICEABLE PARTSINSIDE. REFER SERVICING TO QUALIFIED SERVICE PERSONNEL ONLY.

PRECAUTIONS DURING SERVICING

WARNING:

1. In a ddition to safe ty, othe r parts and assemblies are speci fied for conformance with such regulatio ns as those applyi ng to sp urious radiation . These must also be replace d only with specifie d replacements. Exampl es: RF converters, tun er units, a ntenna selection switches, RF cables, noise-blo cking capacitors, noise-bl ocking filters, etc. 2. Use sp ecified inte rnal Wiring . Note especially: 1) Wires covered with PVC tubing 2) Do uble insulated w ires 3) Hig h voltage leads 3. Use specified i nsulating material s for haza rdous live pa rts. Note espe cially: 1) In sulating Tape 2) PVC tubing 3) Spa cers (insu lating barriers) 4) Insula ting sheets for transistors 5) Plastic screws for fixing micro switches 4. When replacing AC primary side compo nents (tran sformers, power cords, n oise blo cking capacitors, e tc.), wra p ends o f wires securely about the te rminals be fore solde ring.

Before servicing this TV receiver, read the X-RAY RADIATION PRECAUTION, SAFETY INSTRUCTION and PRODUCT SAFETY NOTICE.

X-RAY RADIATION PRECAUTION 1. Excessively high can prod uce potentially hazardous X-RAY RADIATION. To avoid such hazards, the high volta ge must no t exceed the speci fied limit. The normal va lue of the high voltage of this TV receiver is 2 7 KV at zero b ean current (mi nimum b rightne ss). The high voltage must no t exceed 30 KV u nder any circu mstances. Each time when a re ceiver req uires servici ng, the high voltage sho uld be checked. The readi ng of the high voltage is re commended to be reco rded as a part o f the service record, It is important to u se an accurate and reliable high voltage meter. 2. The only source of X-RAY RADIATION in this TV receiver is the picture tube. For con tinued X-RAY RADIATION protectio n, the repla cement tube must be exactly the sa me type as specified in th e parts list. 3. Some parts in this TV receiver have special safety related characteristics fo r X-RADIATION protection. For continued safety, the parts rep lacement should be under taken only afte r referring the PRODUCT SAFETY NOTICE.

5. Make sure that w ires do no t contact heat generating parts (he at sin ks, oxide me tal fi lm resistors, fusi ble resistors, etc.) 6. Check if replace d wires do not conta ct sharply edged or po inted pa rts. 7. Make sure that foreign objects (screws, solder drop lets, etc.) do not remain insi de the set.

SAFETY INSTRUCTION The se rvice shoul d not be attempted by anyone unfamiliar with the ne cessary i nstructio ns on th is TV receiver. The fo llowing are the necessary instru ctions to be ob served before se rvicing. 1. An isolation transformer shoul d be con nected i n the power li ne between the receiver and the AC line when a service is performed o n the primary of the conve rter tra nsformer of the set. 2. Comply wi th all caution an d safety related provided on th e back of the cabi net, inside the cabinet, o n the chassis or p icture tube. 3. To avo id a shock hazard, alw ays discharge the pictu re tube's anode to the chassis g round be fore removi ng the anod e cap.

MAKE YOUR CONTRIBUTION TO PROTECT THE ENVIRONMENT Used batte ries wi th the ISO symbol for recycling a s well as small accumu lators (re chargeable batteries), mini-batteries (cell s) and starter b atteries should not be thrown into the garbage can. Please leave the m at an ap propriate depot.

-2-

PRODUCT SAFETY NOTICE

4. Completely discharge the high pote ntial voltage of the picture tube before handli ng. The pi cture tube is a vacuum and if bro ken, the gl ass will explode. 5. When rep lacing a MAIN PC B in the cabinet, always be certai n that all protective are installed properly such as co ntrol knobs, adjustment co vers o r shie lds, barri ers, iso lation resistor networks etc. 6. When se rvicing is re quired, observe the origin al lead dressing. Extra precau tion sho uld be gi ven to a ssure correct lead dressing in the high voltage area. 7. Keep wires away from high voltage or high te mpera ture compone nts. 8. Befo re returning the set to the customer, al ways perform an AC leaka ge current check on the exposed meta llic parts of th e cabine t, such as anten nas, termin als, screw heads, meta l overlay, control shafts, etc., to be sure the set i s safe to operate without danger of electrica l shock. Plu g the AC lin e cord directly to the AC outlet (do not use a line iso lation transformer d uring th is check). Use an AC voltmeter havin g 5K ohms volt sen sitivity or more i n the following manner. Conne ct a 1.5 K ohm 10 watt resistor pa ralleled by a 0.15ÂľF AC type capacito r, between a go od earth ground (water pipe, conductor etc.,) and the exposed metallic parts, one a t a ti me. Measure the AC vol tage across the combination of the 1 .5K ohm resistor and 0.15 uF capacitor. Re verse the AC p lug at the AC o utlet and repea t the AC volta ge measurements fo r each exposed metallic part. The me asured voltage must not exceed 0.3 V RMS. This correspo nds to 0.5mA AC. Any val ue exceeding this limit co nstitute s a poten tial sho ck hazard and must be corrected immedia tely. The resista nce me asureme nt shou ld be done betwe en accessi ble exposed metal parts and power cord plug prong s with th e power switch "ON". The resi stance should be mo re tha n 6M o hms.

Many e lectrical an d mechanica l parts in this TV receiver have special safety-related characteristics. These characteri stics are offer passed unnoticed by visual spection and the protecti on afforded by them cannot necessari ly be obta ined by using replacement compon ents rates for a hig her voltag e, wattage , etc. The replacemen t parts w hich have these sp ecial safety characteristics are identifie d by marks on the schematic diag ram and on the parts l ist. Before replacin g any of these compo nents, rea d the parts list in thi s manua l care fully. The use of substitute re placemen t parts which do not have the same safety chara cteristics as speci fied in the p arts list may cre ate shock, fire, X-RAY RADIATION or other h azards.

AC VOLTMETER

Goo d ea rth grou nd su ch as th e wat er p ip e , c o n du c t or , etc.

Pl ace this pro be on eac h e x p os ed me t al li c part

AC Leak age Curr ent Check

-3-

KAWA ELECTRONIC RESEARCH & DEVELOPMENT CENTRE

Product Specification Reference No. Revision Date Page

: LC27HAB002 :0 : 2005.08.1 : P.1 of 8

Model No. Customer Model No. Design Code

: LC27HAB : LCT2715 : LC27HABCUSXM1-A01

BOM No.

: LC27HABCUSXM1-A01

Artwork Ass'y No.

: 580-L26ABHM-TU02L

Description

: AKAL LCD TV 26â&#x20AC;? NTSC AC100V-240 V AC USA

Checked By:

Electronic Engineer Mechanical Engineer

Approved By:

Engineering Manager

Approved By:

PM Department Head

DOC Rev NO. 0

The Latest Revision Details Initial Release

DATE

KAWA ELECTRONIC RESEARCH & DEVELOPMENT CENTRE Reference No Revision Date Page

: LC27HAB001 :0 : 2005.8.1 : P. 2 of 8

General Description 1. Main features

Production Description Panel Supplier and Model Chips Solution Market

AKAL LCD TV 27” NTSC AC100V-240VAC USA CHIMEI V270B1-L01 MK8205 USA

1.1 VIDEO SECTION

Display size Display Resolution Pixel Pitch Peak Brightness Contract Ratio View Angle Color Deeps PC Resolution Supporting HDTV Compatible Progressive Scanning Film Mode Pull Down “GAMMA” Correction Color Temperature Control Comb Filter Second De-interlace for Sub picture Wide Mode TV System Dual Tuner System AV Input Color System PIP

27”/16:9 1366 X 768 0.1460mm×0.4365mm 550(nits) 1000:1, Typical (1/100 White Window, Dark Room) Hor. And Vert. ≥170 degree 16.7M Color (R / G/ B each 256 Scales) VGA, SVGA, XGA,WXGA 480p / 720p / 1080i Yes Yes Yes Yes Yes No Full,Fill Aspect Ratio,Nonliner,LB to 16:9, LB subtitles to 16:9 or Anamorphic NTSC M No PAL /NTSC Basic mode (video on graphic mode,resolution≥1024×768)

1.2 AUDIO SECTION Audio Output Power Sound Effect Tone Control 1.3 Input Terminals

1.4 Output Terminals 1.5 Others Closed Caption / V-Chip Teletext OSD Language

6W×2 Max.(8 ohm) NO Yes D-Sub 15 Pin Type(Analog-RGB Input ) ×1 D-Sub 9 Pin (RS-233 Input ) ×1 Component Video-YPbPr/YCbCr ×2 RCA Terminals S-Video Input (Mini Din 4Pin) ×1 Video Input RCA Terminals Y / Pb / Pr, Y / Cb / Cr (RCA Type) ×2 Stereo Audio Input for YPbPr / YCbCr x 2 (3.5mm Phone Type) ×1 Audio Output (RCA ; L&R Type) ×1 Yes No English, FranÇais, Español

KAWA ELECTRONIC RESEARCH & DEVELOPMENT CENTRE Reference No Revision Date Page Stereo Decode

MTS with SAP

Power Rating Power Consumption

AC 100-240V, 50/60Hz 200W

1.6 Support the Signal Mode This machine can support the different from VGA signal mode in 19 kinds No Resolution Horizontal Vertical Frequency(Hz) Frequency(KHz) 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) 12) 13) 14) 15) 16) 17)

640×480 640×480 640×480 640×480 720×400 800×600 800×600 800×600 800×600 832×624 1024×768 1024×768 1024×768 1152×864 1152×864 1280×960 1280×1024

31.50 35.00 37.50 37.86 31.47 35.16 37.90 46.90 48.08 49.00 48.40 56.50 60.00 63.86 67.52 60.02 64.00

60.00 67.00 75.00 72.81 70.08 56.25 60.32 75.00 72.19 75.00 60.00 70.00 75.00 70.02 75.02 60.02 60.01

: LC27HAB001 :0 : 2005.8.1 : P. 3 of 8

Dot Clock Frequency(MHz) 25.18 30.24 31.50 31.50 28.32 36.00 40.00 49.50 50.00 57.27 65.00 75.00 78.75 94.51 108.03 108.04 108.00

1.7 HDTV Mode (YPbPr) No 1) 2) 3) 4) 5) 6)

Resolution 480i 480p(720×480) 576p(720×576) 720p(1280×720) 720p(1280×720) 1080i(1920×1080)

Horizontal Frequency(KHz) 15.734 31.468 31.25 37.50 45.00 33.75

Vertical Frequency(Hz) 59.94 59.94 50.00 50.00 60.00 60.00

Dot Clock Frequency(MHz) 13.50 27.00 27.00 74.25 74.25 74.25

KAWA ELECTRONIC RESEARCH & DEVELOPMENT CENTRE Reference No Revision Date Page

: LC27HAB001 :0 : 2005.8.1 : P. 4 of 8

2. LCD local control button

Main power : push switch Channel +/- volume up/down menu input. standby : soft touch

3. Led indicators :

Power on: Green Standby: Red English, FranÇais, Español Full on screen display

4. OSD language 5. OSD 6. Remote control unit Customer Remote Code: 609F(NEC) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

POWER button MUTE button 0-9 DIGITAL button PIP button SOURCE button PIP SIZE button PIP POS button VOL +/- button CH +/- button MTS button UP/DOWN,LEFT/RIGHT ENTER buttons SYSTEM button MENU button V-CHIP button CCD button FREEZE button DISPLAY buttons FAVORITE button ADD/ERASE buttons SOUND button PIC SIZE button P.MODE button ZOOM button RECALL button SLEEP button

E7501-051001

7. Safety standard 8. EMC standard 9. Performance standard 10. Accessories

UL/FCC/cUL 15 Parts of the FCC rules,CLASS B LCD-TV Standard Battery 2pcs User Manual 1pcs AC Cable 1pcs Remote Control 1pcs The Accessories box 1pcs

KAWA ELECTRONIC RESEARCH & DEVELOPMENT CENTRE Reference No Revision Date Page

: LC27HAB001 :0 : 2005.8.1 : P. 5 of 8

Technical Data 1. Chassis 2. Power supply

CATV

MICO AC 100-240 V, 50/60Hz Battery 3V (UM-4/R03/AAA×2) NTSC M PAL/NTSC 3.58/NTSC 4.43 VHF-L : 2~6CH VHF-H : 7~13CH UHF : 14~69CH 1~125CH

Picture

45.75MHz

Horizontal (Hz) Vertical (Hz)

Internal

15625/15750 50/60 UL Plug V270B1-L01 8 ohm 10W (max) ×2

Fulfill all specifications

15°C ~ 30°C

TV Remote controller 3. TV system RF input Video input 4. Receiving channels TV

5. Intermediate frequencies 6 . Scanning 7 . AC plug

8. Panel 9. Speaker 10.Operating temperature

Accept picture/sound reproduction 11. Operating relative Fulfill all specifications humidity Accept picture/sound reproduction 12. Electrical & optical specification 13. Circuit diagram drawing No. 15. Cabinet 16. Cabinet color 17. Packing

5°C ~ 33°C 45% ~ 75% 20% ~ 80% See the attachment 1.

LC26HAB

1 set per

18. Container stuffing method 19. Dimension (mm) LCD-TV (No packing) Remote control unit 20. Net weight LCD-TV Remote controller

RD/05/P/LC26HAB/CSI/02 REV: 01

21. Cell Defect

Subject to Panel supplier specification

883(W) × 468(H) × 110(D)mm (w/o Stand) 883(W) × 523(H) × 250(D)mm (with Stand) 183(L) × 53(W) ×28(T)mm 14.1Kg (with Stand) approx. 70g (approx.)

KAWA ELECTRONIC RESEARCH & DEVELOPMENT CENTRE Reference No Revision Date Page

: LC27HAB001 :0 : 2005.8.1 : P. 6 of 8

Attachment 1：Electrical & Optical Specification No.

Items

Instruction

Typical

Limit

Unit

Video sensitivity

For 30dB S/N

≤51

dBuV

FM sound sensitivity

For 30dB S/N

≤35

dBuV

Color sensitivity

For RF transmission

≤40

dBuV

CCD sensitivity

TV screen refreshes 40 times number of mistakes≤8

≤50

dBuV

Minimum NICAM threshold

Without crackline noise

N/A

dBuV

Stereo Channel Separation

BTSC.

≥15

AGC static characteristic

Accept. Picture/Sound repr.

≥90

dBuV

Selectivity

Adjacent sound carrier

≥28

Below adjacent sound carrier

≥30

Adjacent picture carrier

≥40

Up adjacent picture carrier

≥30

≥45

VHF

≥45

UHF

≥40

IF rejection

Image rejection

AFT pull-in range

±1.0

≥⏐±1.0⏐

MHz

Chroma sync pull-in range

±500

≥⏐±200⏐

Color killer function

-11

≤-10

Resolution

PAL

300

≥300

Lines

NTSC

260

≥240

Lines

PAL

410

≥400

Lines

NTSC

320

≥300

Lines

Horizontal

450

≥450

Lines

Vertical

400

≥400

Lines

Horizontal Vertical

Video

15 16

Color Coordination View Angle(Lo/3)

White

Full Pattern

YW Horizontal

0.295

0.295±0.02

0.300 170

0.300±0.02 ≥170

Degree

Vertical

Overscan

Cross hatch signal

94~98

Picture position

In all direction

±2

≤⏐±3⏐

H sync pull-in range

±400

≥⏐±200⏐

V sync pull-in range

≥6

Audio frequency response

0.15~12

0.2~12

KHz

±3dB ref. to 1KHz

KAWA ELECTRONIC RESEARCH & DEVELOPMENT CENTRE Reference No Revision Date Page

: LC27HAB001 :0 : 2005.8.1 : P. 7 of 8

7×2

≥5.0×2

1KHz 10% THD

6×2

≥4.0×2

THD

Po=0.5W

0.5

≤3

Signal to buzz ratio

coeighting

≥30

Minimum volume hum

coeighting

≤10

mVrms

Maximum woofer output power

N/A

Woofer audio frequency response

±3dB ref. to 15Hz AV mode

N/A

Tone low frequency

100Hz ref. to 1KHz AV mode

±8

≥⏐±3⏐

Tone high frequency

10KHz ref. to 1KHz AV mode

±8

≥⏐±3⏐

Balance

Center

≤⏐±2⏐

Max.

Min.

-35

≤-30

Max Audio Output Power

Audio output power 10% THD

Video input level

1.0

1±0.3

Vpp

Audio input level*（1）

1.0 *

0.5±0.3

Vrms

Video output level

N/A

Vrms

Audio output level*（2）

0.3 *

0.5±0.3

Vrms

AV Audio input max. level

≤2

Vrms

AV Audio output L/R Separation

≥30

Power consumpution

Operating

200

≤200

Stand by

≤5

0 Degree 5m

≥6

≥45

Degree

≥15

Degree

≤10

mArms

IR receiving distance

IR receiving angle

left/right Up/down

Dielectric strength

DC 3KV

1min.

The vibration noise from The distance between electromagnetic devices in LCD- the tester and the TV set LCD-TV set is four times as many as the screen height

No obvious vibration noise can be heard

KAWA ELECTRONIC RESEARCH & DEVELOPMENT CENTRE Reference No Revision Date Page

: LC27HAB001 :0 : 2005.8.1 : P. 8of 8

Test Condition All tests shall be performed under the following conditions unless otherwise specified 1

Picture Modulation

87.5%

Sound Modulation

27KHz Dev. For DK/I/BG 15KHz Dev. For M/N

Picture to Sound Ratio

10dB

8 ohm

Sound Artificial Load Resistor Video signal

Audio signal

1KHz sine wave 0.5Vrms

Other conditions: A. Switch LCD-TV on and let it warm up for more than 30 minutes. Viewing distance: 3H (H: Panel High) in front of LCD, about 2M. Ambient light: â&#x2030;¤0.1 cd/ m2 B. Brightness, Contrast, Saturation, Tint, sharpness set at normal. C. Connect RMS volt meter to speaker terminals and adjust the LCD volume to get 500mW RMS power at each terminals. D. With image sticking protection of LCD module. The luminance will descend by time on a same still screen and rapidly go down in 5 minutes, when measuring the color tracking and luminance of a same still screen, be sure to accomplish the measurement in one minute to ensure its accuracy. E. Due to the structure of LCD module. The extra-high-bright same screen should not hold over 5 minutes for fear of branding on the panel. F. RF test point: Video output.

Note: *(1) Now this project cannot fit the limited spec. the typical audio input level is 1.0 Vrms, *(2) The audio out level is controlled by the volume level, the range is from 0 to 0.5Vrms.

Stair and Special

Flash

LVDS SIGNAL

IR Keypad TV

LVDS SIGNAL LVDS PANEL

Tuner

AV1 S_Video Y1PbPr Y2PbPr

MT8205 YPbPr

MUX

VGA

GPIO GPIO

Backlight COD_VOUTR

AOSDATA1 DACBCLK DACMCLK DACLRC DOUT

WM8776

Audio Board

Speaker

COD_VOUTL

VGA_L/R S1_AV1_L/R Y1PbPr_L/R Y2PbPr_L/R

DDR1

DDR2

MT8205P1V3.2

Rev

MT8205E (PBGA388) LCDTV BOARD 4 LAYERS

History

V0.1

1.FIRST VERSION

V0.2

1. 2.5V use 5VSB conversion. All 0402 change to 0603

Date 2004/11/29 2005/03/09

2. LED_RED/GRN CIRCUIT CHANGE 3. Change Power on/off circuit(ORO7 CTRL PIN)

4. WM8776 DVDD Needed 5. Del the Si9936 LVDS Parts 4

6. Del DVI&AD9883 PARTS

VCC

5VSB

J24

+12V

R359 10k

J6 5 4 3 2 1

ORO7 High :POWER OFF ORO7 LOW :POWER ON

SYS_PWR

5VSB

Q14 2

1 2 3 4 5 6 7 8

TXD RXD

R364 ORO7

TXD RXD

3 3

SCL SDA

6,9,11,13 6,9,11,13

DIP8/P2.0 5x1 W/HOUSING DIP5/W/H/P2.0

1. INDEX 2. LDO 3. MT8205E PBGA388 4. MT8205 ANALOG DECOUPLING 5. MT8205 DIGITAL DECOUPLING 6. ICE I/F 7. DDR MEMORY & FLASH 8. DVI INPUT 9. AD9883 10. VGA IN & PC AUDIO IN 11. VIDEO IN & TUNER I/O 12. AUDIO / VIDEO IN CIRCUIT 13. WM8776 AUDIO CODEC 14. LVDS / CRT / TTL OUT 15 BACK LIGHT / KEYPAD 16. READER CARD I/F

SOT23/SMD 2N3904

SCL SDA

4.7k

TO Power BD 5VSB 24V INVERTER_PWR

1 2 3 4 5 6

PWR_GND

UP3_0 BLACKLIGHT ON/OFF MUTE<-->UP1_5

TUNER_12V

CE16 220uF/16v C220UF16V/D6H11

ORO7

MUTE

8x1 W/HOUSING DIP8/W/H/P2.54

+12V 2

TUNER_12V

ORO7

UP1_5

HOLE/GND

H1 9 8 7 6

+12V

J108

9 8 7 6

2 3 4 5

DV33A

For Tuner

+12V 2

9 8 7 6

HOLE/GND

H2 9 8 7 6

L14 R51 10k

2 3 4 5

TUNER_12V

R52 10k

J2 FB BEAD/SMD/0805

CE17 47uF/16v

FOR Tuner

CB11 0.1uF

CE93 220uF/16v C220UF16V/D6H11

1 2 3 4

RxD TxD

RS-232 HOLE/GND

H3 9 8 7 6

2 3 4 5

9 8 7 6

2 3 4 5

5VSB P5 CONNECTOR DB9 1 6 2 7 3 8 4 9 5

2 3 4 5

9 8 7 6

2 3 4 5

SYSTEM EEPROM U6

RSTXD

HOLE/GND

5VSB RSRXD

2 3 4 5

0.1uF

13 8 11 10

R1IN R2IN T1IN T2IN

1 3 4 5 2 6

C+ C1C2+ C2V+ V-

R1OUT R2OUT T1OUT T2OUT

12 9 14 7

VCC

5VSB

0.1uF TXD

GND

RXD

TXD

R53 10k

U13

CB75 1 2 3 4

NC NC NC GND

VCC WP SCL SDA

8 7 6 5

R54 10k

SCL SDA

RXD EEPROM 24C16 SOP8/SMD

C8 0.1uF

MAX232A

9 8 7 6 1

9 8 7 6

2 3 4 5

1 HOLE/GND

HOLE/GND

H5 9 8 7 6

2 3 4 5 1

9 8 7 6

4x1 W/HOUSING DIP4/W/H/P2.0

Title

LCD TV - MediaTek MT8205 Solution AUIO IN/OUT GND

ANALOG INPUT GND

DIGITAL GND

Size C Date:

Doc Number

Rev V0.1

INDEX Tuesday, May 10, 2005

Sheet E

Power ON alive source

VCC

ADJ/GND

CM1117-3.3V

DV33

L8 3

FB BEAD/SMD/0805 +

CE4 220uF/16v

OUT

2 FB BEAD/SMD/0805

CE6 + +

CB4 0.1uF

DV33

OUT

U35 M1117-3.3V

5VSB

ADJ/GND

Vout

CE5 220uF/16v

SOT223/SMD

CB5 0.1uF

CB200 0.1uF

220uF/16v

CE118 220uF/16v

SOT223/SMD

CB201 0.1uF

DV33A

Vout ADJ/GND

CM1117-3.3V

OUT

FB BEAD/SMD/0805

FB BEAD/SMD/0805 +

CE10 220uF/16v

C5 10uF/10v

CE11 100uF/16v

+ CB7 0.1uF

CB6 0.1uF

CE12 220uF/16v

SOT223/SMD

CB8 0.1uF

1.25x(1+300/680)=1.8V

SOT223/SMD

1.25x(1+180/110)=3.3V

DV18A DV18A

AV33

OUT

CM1117-1.8V L6

AV33

L11

ADJ/GND

DV33A

5VSB

CE128 220uF/16v

CE129 220uF/16v

CB212 0.1uF

CB213 0.1uF

CB214 0.1uF

CB215 3300pF

CB216 3300pF

CB217 3300pF

5V ==> +12v

VCC

+12V

L9 L107 R3 FB

CE8 100uF/16v C100UF16V/D6H11

L10

R325

DIODE SMD 1N4148/SMD

+12V

R0805/SMD

+ CE107 CHOKE-100uH L18W10H18 L/CHOKE/DIP/1810

R6 13k

10 R0805/SMD U2 8 7 6 5

DRC Ipk VCC CII

SOIC8

+ SWC SWE TC GND

1 2 3 4

100uF/25v/NC C2 270pF

CE7 100uF/16v

R8 1.5k

AZ34063A-PWM C4 100pF

Title

LCD TV - MediaTek MT8205 Solution Size C Date: A

Doc Number

Rev V0.1

LDO Tuesday, May 10, 2005

Sheet E

VI[0..23] 4 4

APLLVDD

VPLLVDD

ADCPLLVDD1

ADCPLLVDD

AUXTOP AUXBOTTOM REXTA APLL_CAP

PWM2VREF

ADCVDD0

AVCM VOCM VICM

VREFP4 VREFN4 DACFS DACVREF DACVDD

LVDDA

VPLLVDD

ADCPLLVDD1

ADCPLLVDD

AUXTOP AUXBOTTOM

4 4

REXTA

APLL_CAP

PWM2VREF

ADCVDD0

AVCM

VOCM VICM

4 4

VREFP4 VREFN4

4 4

DACFS

DACVREF

DACVDD

LVDDA

ADCVDD0 ADCVDD0 MPX1 MPX2 GND VREFP4 VREFN4 GND

C3 D3 C1 C2 L11 D1 D2 F2 D4 E1 E2 E3 E4 ADCVDD F1 PWM2VREF F4 AUXTOP F3 AUXBOTTOM G3 GND J3 VPLLVDD G4 VPLLVDD H3 GND K3 GND K4 REXTA J4 VPLLVDD H4 LVDDA L3 AP7 G2 AN7 G1 CLK2+ H2 CLK2H1 GND M12 AP6 J2 AN6 J1 AP5 K2 AN5 K1 LVDDA L4 AP4 L2 AN4 L1 AP3 M2 AN3 M1 GND M11 CLK1+ N2 CLK1N1 AP2 P2 AN2 P1 LVDDA M3 AP1 R2 AN1 R1 AP0 T2 AN0 T1 GND N12 DACVDD N3 DACVREF M4 DACFS N4 GND N11 SVM T4 DACVDD P3 GND R3 DACVDD P4 G U4 GND R4 B U3 R V4 T3 VSYNC U1 HSYNC U2 V1 V2 V3 W1 W2 DV33A AC9 W3 W4 Y1 Y2 Y3 GND P11 Y4 AA1 AA2 AA3 AA4 AB1 AB2 AB3 AB4 AC1 DV18A AC18 AC2 AC3 AC4 GND R11 AD1 AD2 OBO7 AD3 OBO6 AD4 OBO5 AE1

ANALOGVDD XTALO XTALI GND APLL_CAP GND APLLVDD ANALOGVDD GND VI0 VI1 VI2 VI3 VI4 VI5 VI6 DV18A VI7 VI8 VI9 VI10 VI11 GND VI12 VI13 VI14 VI15 GND VI16 VI17 VI18 VI19 VI20 VI21 VI22 VI23 DVIODCK

VGAVSYNC# VGAHSYNC# GND DV18A GND ADCPLLVDD1 ADCPLLVDD GND GND ANALOGVDD

ADCVDD0 REDRED+ GREENGREEN+ VGASOG BLUEBLUE+ GND

MT8205

C24 D24 A24 Y24 A25 A26 B26 F23 B25 B24 C26 C25 E24 N15 G26 G25 F26 F24 F25 E26 N16 E25 G24 D26 D25 H25 H26 P14 J25 J26 K25 P16 K26 L25 AA24 L26 H24 M25 M26 N25 J23 R16 J24 K23 K24 L23 R14 L24 M23 N26 H23 P26 P25 P15 M24 N23 N24 R26 P24 P23 U23 AA23 R24 R23 T24 R15 T23 U24 W26 V25 V26 V23 U25 T13 U26 T25 T15 T26 R25 W25 W23 Y23 G23 T16 Y26 Y25 AA26 V24 AA25 AB26 T14 AB25 AC26 W24 AC25 AD26 AD25

DE_DVI VSYNC_DVI HSYNC_DVI DVDD18 AOSDATA0 AOSDATA1 AOSDATA2 DVDD3I AOSDATA3 LIN AOBCK AOLRCK AOMCLK DVSS3 DQ24 DQ25 DQ26 DVDD2 DQ27 DQ28 DVSS2 DQ29 DVDD2 DQ30 DQ31 DQS3 DQM1 DVSS18 DQS2 DQ23 DQ22 DVSS2 DQ21 DQ20 DVDD18 DQ19 DVDD2 DQ18 DQ17 DQ16 RA4 DVSS2 RA5 RA6 RA7 RA8 DVSS18 RA9 RA11 CKE DVDD2 RCLK RCLKB DVSS2 RA3 RA2 RA1 RA0 RA10 BA1 DVDD2I DVDD18 BA0 RCS# RAS# DVSS2 CAS# RWE# DQ8 DQ9 DQ10 DVDD2 DQ11 DVSS18 DQ12 DQ13 DVSS2 DQ14 DQ15 DQS1 AVSS18 AVDD18 RVREF DVSS18 DQM0 DQS0 DQ7 DVDD2 DQ6 DQ5 DVSS2 DQ4 DQ3 DVDD2 DQ2 DQ1 DQ0

DVIDE DVIVSYNC DVIHSYNC DV18A AOSDATA0 AOSDATA1 AOSDATA2 DV33A AOSDATA3 DOUT DACBCLK DACLRC DACMCLK GND A_DQ24 A_DQ25 A_DQ26 SDV25 A_DQ27 A_DQ28 GND A_DQ29 SDV25 A_DQ30 A_DQ31 A_DQS3 A_DQM1 GND A_DQS2 A_DQ23 A_DQ22 GND A_DQ21 A_DQ20 DV18A A_DQ19 SDV25 A_DQ18 A_DQ17 A_DQ16 A_RA4 GND A_RA5 A_RA6 A_RA7 A_RA8 GND A_RA9 A_RA11 A_CKE SDV25 A_CLK A_CLK# GND A_RA3 A_RA2 A_RA1 A_RA0 A_RA10 A_BA1 SDV25 DV18A A_BA0 A_CS# A_RAS# GND A_CAS# A_WE# A_DQ8 A_DQ9 A_DQ10 SDV25 A_DQ11 GND A_DQ12 A_DQ13 GND A_DQ14 A_DQ15 A_DQS1 GND DV18A VREF GND A_DQM0 A_DQS0 A_DQ7 SDV25 A_DQ6 A_DQ5 GND A_DQ4 A_DQ3 SDV25 A_DQ2 A_DQ1 A_DQ0

4 3

8,9 8,9

DVIHSYNC DVIVSYNC DVISCL DVISDA

8,9 8,9 8 8

IOWR# IOCE#

FCLK FCMD FDAT

R365 47k

6,15 7 7 7 7 7 7 7 7 7 7 7 7 7 7

16 16 16

8205UP1_[2..7]

F_A[8..21] F_D[0..7]

6,7 6,7

F_OE#

8205UP3_0 8205UP3_1 ICE

6 6 6

MPX1 MPX2

12 12

8205UP3_0 8205UP3_1 ICE

6 6

FCLK FCMD FDAT

8205UP1_[2..7]

DV33A

DACBCLK MPX1 MPX2 ORO[0..7] OGO[0..7]

ORO[0..7] OGO[0..7]

11,13,16 8,11

OBO[0..7]

VSYNC HSYNC

14 14

VGASDA VGASCL

10 10

RED+ REDGREEN+ GREENBLUE+ BLUE-

12 12 12 12 12 12

VGASOG

VGAHSYNC# VGAVSYNC#

HWSCL HWSDA

HWSCL

HWSDA

TXD RXD

1 1

IOA[0..7]

8205UP3_5

8205UP3_4

8205UP3_5

CVBS0+ CVBS0SY+ SYSC+ SCY+ YCB+ CBCR+ CR-

12 12 12 12 12 12 12 12 12 12 12 12

AP[0..7] AN[0..7]

14 14

CLK1+ CLK1CLK2+ CLK2-

14 14 14 14

SCL SDA

1,6,9,11,13 1,6,9,11,13

DACBCLK DACMCLK DACLRC AOSDATA3 DOUT

6,13 13 13 6,13 13

AOSDATA0 AOSDATA1 AOSDATA2 SOY

6,13 6,13 6,13 11

CVBS1+ CVBS1CVBS2+ CVBS2-

12 12 12 12

R G B GPIO PWM0 PWM1

SVM

R G B

14 14 14

GPIO PWM0 PWM1

14 13 13

DV18A Title

DV33A

LCD TV - MediaTek MT8205 Solution

DV18A Size C Date:

Doc Number

Rev V0.1

MT5205BGA388 Tuesday, May 10, 2005

Sheet E

VGAHSYNC# 10 VGAVSYNC# 10

CVBS0+ CVBS0SY+ SYSC+ SCY+ YCB+ CBCR+ CR-

SVM

8205UP1_2 8205UP1_3 8205UP1_4 DV18A 8205UP1_5 8205UP1_6 8205UP1_7 8205UP3_0 8205UP3_1 GND URST# 8205UP3_4 8205UP3_5 FCLK FCMD FDAT GPIO PWM0 PWM1 IR RxD TxD GND ICE HWSCL HWSDA VGASCL VGASDA DVISCL DVISDA

DV33A

F_OE# IOWR# IOCE#

OBO4 OBO3 OBO2 OBO1 OBO0 OGO7 OGO6 OGO5 GND OGO4 OGO3 OGO2 OGO1 DV33A OGO0 ORO7 ORO6 ORO5 ORO4 DV18A ORO3 ORO2 ORO1 ORO0 F_A15 GND F_A14 F_A13 F_A12 F_A11 F_A10 F_A9 F_A8 F_D0 F_D1 DV18A F_D2 F_D3 F_D4 GND F_D5 F_D6 F_D7 IOA0 IOA1 IOA2 IOA3 IOA4 IOA5 IOA6 IOA7 F_A16 DV33A F_A17 F_A18 F_A19 F_A20 GND F_A21 DV33A

DVIODCK DVIDE

URST# A_DQS[0..3] A_RA[0..11] A_BA[0..1] A_DQM[0..1] A_DQ[0..31] A_CLK A_CLK# A_CKE A_CS# A_RAS# A_CAS# A_WE# SDV25 VREF

IOWR# IOCE#

IOA[0..7]

BGA388/SOCKET MT8205

VI[0..23]

URST# A_DQS[0..3] A_RA[0..11] A_BA[0..1] A_DQM[0..1] A_DQ[0..31] A_CLK A_CLK# A_CKE A_CS# A_RAS# A_CAS# A_WE# SDV25 VREF

GND

8205UP3_4

CE21 10uF/25v

SW4P/DIP/FLAT

TXD RXD

AE2 OBO4 AF1 OBO3 AF2 OBO2 AE3 OBO1 AF3 OBO0 AE4 OGO7 AF4 OGO6 AC5 OGO5 T11 DVSS18 AD5 OGO4 AE5 OGO3 AF5 OGO2 AC6 OGO1 AD9 DVDD3 AD6 OGO0 AE6 ORO7 AF6 ORO6 AC7 ORO5 AD7 ORO4 AD18DVDD18 AE7 ORO3 AF7 ORO2 AC8 ORO1 AD8 ORO0 AF8 HIGHA7 P12 DVSS18 AE9 HIGHA6 AF9 HIGHA5 AE10 HIGHA4 AF10 HIGHA3 AC11HIGHA2 AD11HIGHA1 AF12 HIGHA0 AE15 AD0 AD15AD1 AC19DVDD18 AC15AD2 AF16 AD3 AE16 AD4 R12 DVSS3 AD16AD5 AC16AD6 AF17 AD7 AD17IOA0 AD14IOA1 AE14 IOA2 AF14 IOA3 AF13 IOA4 AE13 IOA5 AD13IOA6 AC13IOA7 AE8 A16 AC10DVDD3I AC17A17 AE12 IOA18 AD12IOA19 AE11 IOA20 T12 DVSS18 AF11 IOA21 AE17 IOALE AF15 IOOE# AC12IOWR# AC14IOCS# AF18 WR# AE18 RD# AD10DVDD3 AF19 INT0# AE19 UP12 AF20 UP13 AE20 UP14 AD19DVDD18 AD20UP15 AC20UP16 AF21 UP17 AE21 UP30 AD21UP31 P13 DVSS18 AC21PRST# AD22UP34 AC22UP35 AF22 FCICLK AE22 FCICMD AF23 FCIDAT AE23 GPIO0 AD23PWM0 AC23PWM1 AF24 IR AE24 RXD AD24TXD R13 DVSS3 AC24ICE AF25 SCL AE25 SDA AF26 SCL0 AE26 SDA0 AB23 SCL1 AB24 SDA1

APLLVDD

ADCVDD0 VOCM GND VICM ADCVDD0 CRCR+ CBCB+ YY+ SOY GND

SW1 2 1

2=4

1=3

ADCVDD

DVIHSYNC DVIVSYNC DVISCL DVISDA

R18 10k

URST#

VFEVSS1 AVCM ADCVDD0 CVBS2N CVBS2P CVBS1N CVBS1P CVBS0N CVBS0P ADCVSS0 REFP0 REFN0 ADCVDD1 SCN SCP SYN SYP ADCVSS1 REFP1 REFN1 VFEVDD0 VOCM VFEVSS0 VICM ADCVDD2 CRN CRP CBN CBP YN YP SOY ADCVSS2 REFP2 REFN2 MON0 MON1 ADCVDD3 RN RP GN GP SOG BN BP ADCVSS3 REFP3 REFN3 VSYNC HSYNC DVSS DVDD ADCPLLVSS1 ADCPLLVDD1 ADCPLLVDD ADCPLLVSS SYSPLLVSS SYSPLLVDD TESTP TESTN XTALVDD XTALO XTALI XTALVSS APLL_CAP APLLVSS APLLVDD DMPLLVDD DMPLLVSS VI0 VI1 VI2 VI3 VI4 VI5 VI6 DVDD18 VI7 VI8 VI9 VI10 VI11 DVSS3 VI12 VI13 VI14 VI15 DVSS18 VI16 VI17 VI18 VI19 VI20 VI21 VI22 VI23 VCLK_DVI

ANALOGVDD

ADCVDD

D5 1N4148/SMD

L12 D5 C4 B1 A1 B2 A2 B3 A3 L13 B4 A4 C5 B5 A5 B6 A6 M13 D6 C6 D7 B7 N13 A7 C7 B8 A8 B9 A9 B10 A10 C8 D10 D9 C9 D11 C11 D8 B11 A11 B12 A12 D13 B13 A13 C10 D12 C12 C13 C14 N14 D14 L14 D15 C15 M14 L15 D16 B14 A14 C16 B15 A15 M15 A16 D18 D17 C17 C18 B16 A17 B17 A18 B18 C19 D19 E23 A19 B19 C20 D20 A20 L16 B20 C21 D21 A21 M16 B21 C22 D22 A22 B22 C23 D23 A23 B23

U7 ANALOGVDD

DVIODCK DVIDE

DV33A

ADCVDD0 SCSC+ SYSY+ GND

XTALI XTALO

GND AVCM ADCVDD0 CVBS2CVBS2+ CVBS1CVBS1+ CVBS0CVBS0+ GND

XTALI XTALO

MT8205 ANALOG DECOUPLING R20 DACVREF DACFS

DACVREF

DACFS

DV18A

100k DACVREF

L17 DV18A

DACFS

ADCPLLVDD1

Y1 4

ADCPLLVDD1

FOR DACVDD ADCPLLVDD

ADCPLLVDD

C10 0.1uF/NC C0603/SMD

FB BEAD/SMD/0603

XTALO

C9 4.7uF C0603/SMD

CB14 0.1uF C0603/SMD

GND

27MHz GND

GND

XTALI

R21 560

C11 33pF

C12 33pF

DEL

AV33 APLLVDD

APLLVDD

DV33A

L18 AV33 CB17

+ ANALOGVDD

ANALOGVDD

VPLLVDD

LVDDA

ADCVDD

DACVDD

C13 4.7uF C0603/SMD

CE24 +

0.1uF

10uF/25v

L19

GND

DACVDD FB BEAD/SMD/0603

CE23

ANALOGVDD FB BEAD/SMD/0603 C15 0.1uF

CB15 0.1uF C0603/SMD GND

C14 4.7uF C0603/SMD

CB16 0.1uF C0603/SMD

GND R22

10uF/25v

ADCPLLVDD

DACVDD VPLLVDD LVDDA

C16 4.7uF C0603/SMD

CB18 0.1uF C0603/SMD GND

C18 4.7uF C0603/SMD

CB20 0.1uF C0603/SMD GND

33 +

CE25 22uF/25v

C17 4.7uF C0603/SMD

CB19 0.1uF C0603/SMD

GND DACVDD ADCVDD DACVDD

APLL_CAP

ANALOGVDD

AVCM VOCM VICM 3

FOR ADCVDD AVCM

VOCM VICM

3 3

C19 4.7uF C0603/SMD

CE78 47uF/16v

+ C20 1500pF C0603/SMD

GND

GND R23

Note for Fix or Adj Regulator

APLLVDD 3

ADJ/GND

CM1117-3.3V

3 VREFP4 VREFN4

ADCVDD0

PWM2VREF

AUXTOP AUXBOTTOM

ADCVDD0

PWM2VREF

AUXTOP AUXBOTTOM

OUT

AZ1117

3 3

CB25 +

CB27 0.1uF

Rdown

AV33

C22 4.7uF C0603/SMD

L29 AV33

LVDDA

CB23 0.1uF C0603/SMD

GND FB BEAD/SMD/0805

CE27 100uF/16v

CB22 0.1uF C0603/SMD

ANALOGVDD ADC_VDD ADC_VDD

3 3 +

C21 4.7uF C0603/SMD

GND

L28 VREFP4 VREFN4

CE26 22uF/25v

Vout

VCC

CB21 0.1uF C0603/SMD

CE28 220uF/16v

CE29 10uF/25v

FB BEAD/SMD/0603

CB26

0.1uF

GND

SOT223/SMD

C23 0.1uF

Rup

CB24 0.1uF C0603/SMD

CE30

AV33

47uF/16v

GND

L30

LVDDA AV33

Fix regulator

0 ohm

OFF

1.25x(1+Rdown/Rup)

Adj regulator

180 1%

110 1%

1.25x(1+180/110)=3.3V

CB28 0.1uF C0603/SMD

VPLLVDD FB BEAD/SMD/0603

C24 4.7uF C0603/SMD

GND LVDDA

CB29 0.1uF C0603/SMD

GND C25 0.1uF

CE31 47uF/16v

VPLLVDD REXTA APLL_CAP XTALI XTALO

REXTA

APLL_CAP

XTALI XTALO

3 3

CB30 0.1uF C0603/SMD

C26 4.7uF C0603/SMD

GND

CB31 0.1uF C0603/SMD

GND VPLLVDD

ADC_VDD C27 4.7uF C0603/SMD

L32 ADC_VDD

ADCVDD0

CB32 0.1uF C0603/SMD

GND

AVCM FB BEAD/SMD/0805

CB34 0.1uF C0603/SMD GND

R27 CB36 4.7uF C0603/SMD

ADCVDD0 CB38 0.1uF C0603/SMD GND

GND

REXTA 3.3k

GND

ADCVDD0

L37 VOCM

CB39 0.1uF C0603/SMD GND

ADCVDD

ADCVDD0 FB

CB44 0.1uF C0603/SMD

ADCVDD0

CB41 0.1uF

TP3 C28 4.7uF C0603/SMD

CB42 0.1uF C0603/SMD

GND

L38

AUXTOP

GND

CB45 0.1uF C0603/SMD GND

R31 LVDDA

TP4

PWM2VREF

R34 AUXBOTTOM

ADCVDD0

CB48 0.1uF C0603/SMD GND

CB47 0.1uF C0603/SMD

CE32 47uF/16v

VICM

GND

CB50 0.1uF C0603/SMD

ADCVDD0 CB52 0.1uF C0603/SMD GND

GND

ADCVDD0 CB54 0.1uF C0603/SMD GND

VREFP4

Title

LCD TV - MediaTek MT8205 Solution CB56 4.7uF C0603/SMD GND B

CB58 4.7uF C C0603/SMD

VREFN4

Size C Date: D

CB60 4.7uF C0603/SMD

Doc Number

Rev V0.1

MT8205 DECOUPOMG--ANALOG Tuesday, May 10, 2005

Sheet E

MT8205 DIGITAL POWER & DECOUPLING 4

DV33A

0603 PUT ON NEARLY BGA

DV18A DV18A

0603 PUT ON NEARLY BGA

0603 CB62 PUT ON NEARLY BGA

CB61 0.1uF

CB69 0.1uF C0603/SMD

0.1uF

CB70 0.1uF C0603/SMD

CB71 0.1uF C0603/SMD

CB72 0.1uF C0603/SMD

CB68 0.1uF C0603/SMD

C29 0.01uF C0603/SMD

C30 3300pF C0603/SMD

C31 3300pF C0603/SMD

C32 3300pF C0603/SMD

C33 3300pF C0603/SMD

C34 3300pF C0603/SMD

Title

LCD TV - MediaTek MT8205 Solution Size B Date: A

Doc Number

Rev V0.1

MT8205 DECOUPOMG--DIGITAL Tuesday, May 10, 2005

Sheet E

ICE

SCL SDA

R311 1k

1,9,11,13 1,9,11,13

RN38 IOA[0..7] ICE

IOA[0..7]

ICE

IOA0 IOA1 IOA2 IOA3

7 5 3 1

8 6 4 2

A0 A1 A2 A3

8 6 4 2

A4 A5 A6 A7

0x4 RN39

IOWR# 3

IOCE# PWR#

IOWR#

IOCE#

IOA4 IOA5 IOA6 IOA7

7 5 3 1

0x4

PWR#

R314 IOWR#

PCE#

A[0..7]

PWR# 0 R315

IOCE# A[0..7] F_A[8..21]

F_A[8..21]

PCE# 0

3,7 RN40

UP1_2 UP1_6 UP1_3 UP3_1 2

UP1_4

UP1_2 UP1_6 UP1_3

15 11 11

UP3_1

UP1_4

UP1_5 UP3_0 HWSCL

8205UP3_0 8205UP3_1 8205UP3_4 8205UP3_5

UP3_0

HWSCL

HWSDA

8 6 4 2

UP3_0 UP3_1 UP3_4 UP3_5

8 6 4 2

UP1_2 UP1_3 UP1_4 UP1_5

0x4 RN41

UP1_5

7 5 3 1

8205UP1_2 8205UP1_3 8205UP1_4 8205UP1_5

7 5 3 1

MUTE

0x4 R313

HWSDA

8205UP1_6

UP1_6 0

8205UP3_0 8205UP3_1 8205UP1_[2..7] 8205UP3_4 8205UP3_5 1

8205UP3_0

8205UP3_1

REMOVE WHENR312 USE ICE MODE 8205UP1_7 0 DEL

TEST POINT DIP1.0 TP/DIP/D1.0

8205UP1_[2..7] 3 8205UP3_4

UP3_4 FOR S/W SCL

8205UP3_5

UP3_5 FOR S/W SDA

TP28

UP1_7

HWSDA HWSCL

R300 R301

R R

UP3_5 UP3_4

R302 R303

0 0

SDA SCL Title

LCD TV - MediaTek MT8205 Solution Size B Date: A

Doc Number

Rev V0.1

MT8205 DECOUPOMG--DIGITAL Tuesday, May 10, 2005

Sheet E

SDV25

A_DQS[0..3] A_RA[0..11] A_BA[0..1] A_DQM[0..1] A_DQ[0..31]

3 3 3 3 3

A_CLK A_CLK# A_CKE A_CS# A_RAS# A_CAS# A_WE#

3 3 3 3 3 3 3

SDV25 VREF

RN2 7 5 3 1 22x4

A_RA4 A_RA5 A_RA6 A_RA7

RN4 7 5 3 1 RN6 7 5 3 1

22x4

A_RA8 A_RA9 A_RA11

8 6 4 2

D_RA3 D_RA2 D_RA1 D_RA0

8 6 4 2

D_RA4 D_RA5 D_RA6 D_RA7

D_DQ3 D_DQ4

8 6 4 2

D_RA8 D_RA9 D_RA11

D_DQ7

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

D_DQ0 D_DQ1 D_DQ2

D_DQ5 D_DQ6

D_DQS0

22x4 22

D_RA10

A_DQ0 A_DQ1 A_DQ2 A_DQ3

RN8 7 5 3 1

8 6 4 2

D_DQ0 D_DQ1 D_DQ2 D_DQ3

A_DQ4 A_DQ5 A_DQ6 A_DQ7

RN10 47x4 7 5 3 1

8 6 4 2

D_DQ4 D_DQ5 D_DQ6 D_DQ7

A_DQ8 A_DQ9 A_DQ10 A_DQ11

RN11 47x4 7 5 3 1

8 6 4 2

D_DQ8 D_DQ9 D_DQ10 D_DQ11

A_DQ12 A_DQ13 A_DQ14 A_DQ15

RN13 47x4 7 5 3 1

8 6 4 2

D_DQ12 D_DQ13 D_DQ14 D_DQ15

U14

SDV25 U15

A_RA3 A_RA2 A_RA1 A_RA0

A_RA10 R59

3 3

D_DQM0 D_WE# D_CAS# D_RAS# D_CS# D_BA0 D_BA1 D_RA10 D_RA0 D_RA1 D_RA2 D_RA3

A1 A2 A3 A4 A5 A6 A7 F_A8 F_A9 F_A10 F_A11 F_A12 F_A13 F_A14 F_A15 F_A16 F_A17 F_A18

D1V25

VDD VSS DQ0 DQ15 VDDQ VSSQ DQ1 DQ14 DQ2 DQ13 VSSQ VDDQ DQ3 DQ12 DQ4 DQ11 VDDQ VSSQ DQ5 DQ10 DQ6 DQ9 VSSQ VDDQ DQ7 DQ8 NC NC VDDQ VSSQ LDQS UDQS NC NC VDD VREF DNU VSS LDM UDM WE CK CAS CK CKE RAS CS NC NC A12 BA0 A11 BA1 A9 A10/AP A8 A0 A7 A1 A6 A2 8M x 16 A5 DDR A3 A4 VDD VSS

66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34

D_DQ15 D_DQ14 D_DQ13

D_RA0 D_RA1 D_RA2 D_RA3

RN3 7 5 3 1

D_RA4 D_RA5 D_RA6 D_RA7

RN5 8 6 4 2

D_DQ12 D_DQ11

8 6 4 2 75x4

D_DQ10 D_DQ9 D_DQ8

7 5 3 1

DV33A

75x4 RN7 2 4 6 8

D_DQS1 VREF

D_RA11 D_RA9 D_RA8

CB76

D_DQM0 D_CLK# D_CLK D_CKE

1 3 5 7

R58

F_A20 F_A21 PCE# F_OE#

10k 75x4

PWR#

25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 15 9 10 26 28 11

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 RY/BY A19 A20 CE TSOP OE WE

RESET

0.1uF

D_RA11 D_RA9 D_RA8 D_RA7 D_RA6 D_RA5 D_RA4

D_RA10 R60

D_DQ0 D_DQ1 D_DQ2 D_DQ3

RN9 7 5 3 1

8 6 4 2

D_DQ4 D_DQ5 D_DQ6 D_DQ7

RN12 7 5 3 1

D_DQ8 D_DQ9 D_DQ10 D_DQ11

RN14 7 5 3 1

DV33A

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A18 NC WP/ACC BYTE VCC 48 pin GND1 GND2

F_D0 F_D1 F_D2 F_D3 F_D4 F_D5 F_D6 F_D7

29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 16 13 14 47

DV33A DV33A

5VSB

R55 A0 F_A19 R56 0

10k

R57 R

FLASHVCC

37 27 46

CB77 0.1uF

MX29LV160BT D1V25 D1V25 75x4

M13L128168 8Mx16-6

8 6 4 2

CB78 0.1uF

CB79 0.1uF

CB80 0.1uF

CB81 0.1uF

CB82 0.1uF

CB83 0.1uF

CB84 0.1uF

CB85 0.1uF

CB87 0.1uF

CB88 0.1uF

CB89 0.1uF

CB90 0.1uF

CB91 0.1uF

CB92 0.1uF

CB93 0.1uF

CB95 0.1uF

CB96 0.1uF

CB97 0.1uF

CB98 0.1uF

CB99 0.1uF

CB100 0.1uF

CB101 0.1uF

75x4 8 6 4 2

D1V25 3

47x4 SDV25

RWR#

PWR#

PCE#

A[0..7] F_D[0..7]

F_OE#

F_A[8..21]

6 3,6

SDV25

A_DQ16 A_DQ17 A_DQ18 A_DQ19

RN16 7 5 3 1

A_DQ20 A_DQ21 A_DQ22 A_DQ23

RN17 47x4 7 5 3 1

A_DQ24 A_DQ25 A_DQ26 A_DQ27

RN19 47x4 7 5 3 1

A_DQ28 A_DQ29 A_DQ30 A_DQ31

RN21 47x4 7 5 3 1

8 6 4 2

D_DQ16 D_DQ17 D_DQ18 D_DQ19

8 6 4 2

D_DQ20 D_DQ21 D_DQ22 D_DQ23

D_DQ17 D_DQ18 D_DQ19 D_DQ20 D_DQ21 D_DQ22

D_DQ24 D_DQ25 D_DQ26 D_DQ27

8 6 4 2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

D_DQ16

D_DQ23 D_DQS2

3,6 8 6 4 2

D_DQ28 D_DQ29 D_DQ30 D_DQ31

D_DQM1 D_WE# D_CAS# D_RAS# D_CS#

Change to 47 ohm 47x4

A_DQS0

R61

D_DQS0

A_DQS1

R62

D_DQS1

A_DQS2

R63

D_DQS2

A_DQS3

R64

D_DQS3

D_BA0 D_BA1 D_RA10 D_RA0 D_RA1 D_RA2 D_RA3

VDD VSS DQ0 DQ15 VDDQ VSSQ DQ1 DQ14 DQ2 DQ13 VSSQ VDDQ DQ3 DQ12 DQ4 DQ11 VDDQ VSSQ DQ5 DQ10 DQ6 DQ9 VSSQ VDDQ DQ7 DQ8 NC NC VDDQ VSSQ LDQS UDQS NC NC VDD VREF DNU VSS LDM UDM WE CK CAS CK RAS CKE CS NC NC A12 BA0 A11 BA1 A9 A10/AP A8 A0 A7 A1 A6 8M x 16 A2 A5 DDR A3 A4 VDD VSS

66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34

D_DQ31 D_DQ30 D_DQ29

8 6 4 2

D_DQ26 D_DQ25

A_BA1

R66 R68

A_DQM0 A_DQM1 A_CKE

R71

RN20 D_DQ20 2 D_DQ21 4 D_DQ22 6 D_DQ23 8

D_DQ24 D_DQS3

R73 R75

D_BA1

D_BA0 D_DQM0

R69

1 2 3 4

D1V25 VREF

D_CKE

A_CLK#

R77 R79

D_CLK

CB102 0.1uF

CB103 0.1uF

CB104 0.1uF

D1V25

75x4 CB105

D_DQM1 D_CLK# D_CLK D_CKE

RN22 D_DQ27 1 D_DQ26 3 D_DQ25 5 D_DQ24 7

0.1uF

D_RA11 D_RA9 D_RA8 D_RA7 D_RA6 D_RA5 D_RA4

C40 3300pF 2 4 6 8

C41 3300pF

C42 3300pF

C43 3300pF

C44 3300pF

C45 3300pF

C46 3300pF

C47 3300pF

D1V25

75x4 RN23 D_DQ31 1 D_DQ30 3 D_DQ29 5 D_DQ28 7

+ 2 4 6 8

CE33

+ CE34

270uF/16v OS-CON/NC C270UF16V/D10H12

220uF/16v

75x4

SDV25

RN24 7 5 3 1

D_RAS# D_CS# D_BA0 D_BA1

8 6 4 2

SDV25

CB106 0.1uF

D_DQS2

R65

D_DQS3

R67

D_CAS#

R70

D_WE#

R72

D_DQM1

R74

D_DQS1

R76

D_DQS0

R78

D_DQM0

R80

CB107 0.1uF

CB108 0.1uF

CB109 0.1uF

CB110 0.1uF

CB111 0.1uF

CB112 0.1uF

CB113 0.1uF

DEL

4.7k U17

D1V25

TP10 A_CLK

1 3 5 7

75x4

D_DQM1

CB94 0.1uF

VREF

D_CS# D_RAS# D_CAS# D_WE#

D1V25 1 3 5 7

75x4

22x4 A_BA0

NEW ADD

75x4

RN25 7 5 3 1

8 6 4 2

RN18 D_DQ16 2 D_DQ17 4 D_DQ18 6 D_DQ19 8

D_DQ28 D_DQ27

M13L128168 8Mx16-6/NC FOR ENTRY

A_CS# A_RAS# A_CAS# A_WE#

CB86 0.1uF

75x4 RN15 D_DQ12 7 D_DQ13 5 D_DQ14 3 D_DQ15 1

U16

SDV25

GND VTT PVIN SD VSENSE AVIN VREF VDDQ

8 7 6 5

IC LP2996 DDR Termination SOP8

CE35 47uF/16v

0402 PUT ON NEARLY BGACB120 CB118 CB119 CB114 0.1uF

CB115 0.1uF

CB116 0.1uF

CB117 0.1uF

C48 3300pF

C49 3300pF

C50 3300pF

CB125 0.1uF

CB126 0.1uF

CB127 0.1uF

CB121

0.1uF C0603/SMD

C51 3300pF

C52 3300pF

C53 3300pF

C54 3300pF C0603/SMD

C55 3300pF C0603/SMD

CB128 0.1uF

CB129 0.1uF

CB130 0.1uF

CB131 0.1uF

CB124 0.1uF

D_CLK#

CB122

CB123

0.1uF

CE36 220uF/16v

SDV25

SDV25 ADJ/GND

SDV25 1

0.1uF

CB136 0.1uF

5VSB

CM1117-2.5V

SDV25

CB132 CB133 CB134 CB135 VREF DECOUPLING

VREF VREF

OUT

SDV25

VREF + CE38 + CE37 VREF SOT223/SMD

+ CE41 CB137

CB138

CB139

CB140

CB141

220uF/16v

+ CE39 220uF/16v

+ CE40 220uF/16v

Title

220uF/16v

LCD TV - MediaTek MT8205 Solution

220uF/16v

Size C

0.1uF

0.1uF A

0.1uF

Date: B

Doc Number

Rev V0.1

DDR MEMORY&FLASH Tuesday, May 10, 2005

Sheet E

VCC

D6 VGA_PLUGPWR

DIODE SMD 1N4148/SMD

D19 VGA_PLUGPWR

VGA_PWR

VGA_PLUGPWR

VGA_PLUGPWR DIODE SMD 1N4148/SMD

CB157

R115 10k

U22 1 2 3 4

0.1uF

NC NC NC GND

VCC WP SCL SDA

8 7 6 5

R116 10k VGA_IN_L

VGASCL VGASDA

VGA_IN_R

EEPROM 24C02

VGA_IN_L

VGA_IN_R

VGASDA

VGASCL

GND

P4 3

CE100

VGA_L

CE101

10uF/25v

R323

10k

VGA_IN_R

10uF/25v

R324

10k

VGA_IN_L

VGASDA VGASCL

HSYNC_VGA

K1 K2 K3 K4 K5

PHONEJACK/DIP

VGA_R

L PHONEJACK STEREO

1 2 3 4 G

VSYNC_VGA

VGASDA

R110

100 VGA_SDA

VGASCL

R111

100 VGA_SCL

RED_GND GRN_GND BLU_GND

RED

GREEN BLUE

VGA_SDA HSYNC#

VSYNC#

14 VGA_SCL

RED_GND

GRN_GND

BLU_GND

RED

GREEN

BLUE

VSYNC_VGA FB BEAD/SMD/0603

R298 2.2k

C157 5pF

L99

VGA_PWR HSYNC#

HSYNC_VGA FB BEAD/SMD/0603

VSYNC# RED RED_GND GREEN GRN_GND BLUE BLU_GND

1 6 2 7 3 8 4 9 5 10

VGAVSYNC#

L98

D-SUB15 FEMALE DSUB15/DIP/F 11

VGAHSYNC#

R299 2.2k

C158 5pF

Title

LCD TV - MediaTek MT8205 Solution Size B Date: A

Doc Number

Rev V0.1

VGA IN&PC AUDIO IN Tuesday, May 10, 2005

Sheet E

CVBS0---TUNER1 CVBS1---FRONT BD AV_IN CVBS2---AV BD (AV/S-V) IN R40 Y_GND CB 4

CB_GND CR CR_GND SOY SY SY_GND SC SC_GND TV TV_GND CVBS1 CVBS1_GND

Y_GND

CB_GND

CR_GND

SOY

SY_IN

AV , TUNER I/O

TUNER_12V

1 JP1 CON\SVHS

TU_VCC SC_IN

J4 TU_12V

1 2 3 4 5 6 7 8 9 10 11 12

SDA SCL SIF1_OUT AF1_OUT

SY_GND

SC_GND

CVBS0

ORO7 FOR TUNER SIF SELECT SWITCH IO-1

CVBS0_GND

OGO0 FOR TUNER SIF SELECT SWITCH IO-2

CVBS1

CVBS1_GND

TV_GND TV

1000uF/16v

AF1_OUT

SY_GND

2 1

3 SY_IN 4

R45

R47

SC_GND

FB6 0

FOR AV SWITCH IO-1 FB5 0

UP1_2 FOR POWER ON/OFF ORO7 FOR SYS_PWR

OGO5 FOR AUDIO 1st SWITCH IO-2

CE97

OGO6 FOR AUDIO 2nd SWITCH IO-1

SIF1_OUT

R46 75

ORO6 FOR AUDIO 1st SWITCH IO-1

TU_VCC

R43

CON12 DIP12/P2.0 OGO3

L102

SC_IN

OGO1 FOR TUNER BOARD PAL/NTSC SWITCH

VCC

R44

TU VCC FOR TUNER POWER USE

R41 R42 75

CB197 0.1uF

RESERVER

OGO2 FOR AUDIO 2nd SWITCH IO-2 OGO4 FOR AUDIO 2nd SWITCH IO-2

SIF1_OUT

AF1_OUT

12 R17 TP27

TP25

TP24

TP21

TP20

TP9

OGO6

OGO5

OGO4

OGO3

OGO2

R29 OGO1

TUNER_12V

TP8

SOY1 TP7

1,6,9,13

OGO0

SDA

ORO7

1,6,9,13

ORO6

SDA

SCL

TP6

SCL

YPBPR

R30

R33

Y_GND

R32 75

L103

OGO4 OGO5 OGO6 ORO6 ORO7 S1_AV1_L S1_AV1_R YPBPR1_L YPBPR1_R

OGO2

OGO3

OGO4

R11 0

FB2 0 2 YPBPR1_L

TP5

OGO5

OGO6

ORO6

ORO7

1 2

AV1_IN

S1_AV1_L

3 4

CE9 10uF/25v

S1_AV1_L

S1_AV1_R

5 6

CE13

S1_AV1_R

YPBPR1_R

YPBPR1_L YPBPR1_R

11 11

CE14 10uF/25v

OGO3

OGO1

CB198 0.1uF

OGO2

OGO1 2

OGO0

HP_SENSE

TU_12V + CE98 1000uF/16v

CE15 8 10uF/25v

1 3 6 4

R35

R19

R25

R28

CB_GND

0 CVBS1 FB3

18 R15 56

R16

0 CVBS1_GND

R24

10uF/25v

RCA1X3 RCA3/6P/DIP

R37 75

9 7

RCA1X3 RCA5/9P/Y

R36 0

FB1

0 R26 75

CR_GND

S1_AV1_R S1_AV1_L YPBPR1_R YPBPR1_L

FB4 0

Title

LCD TV - MediaTek MT8205 Solution

R39 R38 R48 R49 100K 100K 100K 100K

Size A3 Date:

Doc Number

Rev V0.1

VIDEO IN & TUNER IO Tuesday, May 10, 2005

Sheet E

VGASOG RED+ RED4

VGASOG

RED+

RED-

R338

R348 R166

CVBS0

C94

R160

C88

Y+

CVBS0+ 100 22

GREEN+ GREENBLUE+ BLUE-

GREEN+

GREEN-

BLUE+

BLUE-

CB+

47nF 47nF

R161

C168 330pF

R349

NC R339 C96

C90 Y-

Y_GND

CVBS0_GND

CVBS0100 47nF

0 47nF R340

CB+ CBCR+ CRY+ Y-

CB-

CR+

CR-

Y+

Y-

SY+

SY-

C162 30pF

R168

R350 CVBS1

R170

R164

C91

CB+

C98

CVBS1+

100 47nF

R165

C163 10pF

47nF R172 NC

NC C169 330pF

R351

R341

C93 CB-

CB_GND C100 CVBS1-

CVBS1_GND

100 47nF

0 SY+ SY-

47nF R342 CR R352

SC+ SC-

SC+

SC-

R162

CVBS2

R167

CR+ 100

47nF

CVBS2+ R169

C164 10pF

22 47nF

R163 CVBS0+ CVBS03

CVBS1+ CVBS1-

CVBS0+

CVBS0-

CVBS1+

CVBS1-

CVBS2+

CVBS2-

C95

C89

R343 C170 330pF

R353

C97 CR-

CR_GND C92

100 3

47nF

CVBS2-

CVBS2_GND 0

R354

47nF SY

R171

C99

SY+ 22

CVBS2-

47nF

FROM Tuner

CVBS2+

R173 NC

C171 330pF

R355

C101

SY_GND

OUTPUT MPX1 MPX2

MPX1

MPX2

SY-

CE116

0 47nF R356

47uF/16v /NC SC

R174

C102

SC+

C104 SIF1_OUT

R176

R344

MPX1

47nF R175 47nF Y_GND CB CB_GND CR CR_GND 2

SOY

Y_GND

CB_GND

CR_GND

SOY

3,11

C106 15pF/NC

C165 15pF/NC

AF Path C166

SY_GND

C103 SC-

0 47nF

47nF/NC CE62 AF1_OUT

R333

39k

R332

39k

L55

MPX2

C105

RED C160 15pF

RED_IN FB BEAD/SMD/0603

47uF/16v SY

C172 330pF

R357

SC_GND +

C161 15pF

R178

100

RED+

R179 47nF C107 5pF

C108 SC SC_GND

SC_GND

R180

RED_GND

100

RED47nF

L104 FB

C109 R183

VGASOG 4.7nF

CVBS0 CVBS0_GND CVBS1 CVBS1_GND

CVBS0

CVBS0_GND

CVBS1

CVBS1_GND

L57 GREEN

C111 GREEN_IN

R185

100

GREEN+

FB BEAD/SMD/0603

47nF R186

C112 5pF

75 C113

CVBS2 CVBS2_GND SIF1_OUT AF1_OUT

CVBS2

CVBS2_GND

GRN_GND

R187

100

GREEN-

L106

47nF

FB SIF1_OUT

AF1_OUT

RED

GREEN

L59 RED 1

GREEN BLUE

INPUT RED_GND GRN_GND BLU_GND

BLUE

RED_GND

GRN_GND

BLU_GND

C114 BLUE_IN

BLUE

R191

100

BLUE+ 1

FB BEAD/SMD/0603

47nF R195

C115 5pF

75 C116 R199

BLU_GND L105

100

BLUE-

Title

LCD TV - MediaTek MT8205 Solution Size C Date:

47nF

Doc Number

Rev V0.1

AUDIO/VIDEO IN CIRCUIT Tuesday, May 10, 2005

Sheet E

Del Parts

VCC

L61 HPVDD

C117

S1_AV1_R

S1_AV1_L

S1_AV1_R

R212

DVI_L

R214

CB161 0.1uF

SCL

R213

100 SCL14

SDA

R215

100 SDA14

10uF/25v 4

S1_AV1_L

DVI_R

TP18 4

VGA_IN_R

FB TP17 5k

VGA_IN_R

R216

VGA_IN_L

R217

CE108

10uF/25v R218

10k

S1_AV1_L

CE109

10uF/25v R221

10k

HPVDD

ORO3

ORO4 ORO5

3 3

UP1_5

1,6

ORO3

TP30

ORO4

TP31

Del Parts TP16

YPBPR1_R

CE110

10uF/25v

R222

10k

TP15

YPBPR1_L

CE111

10uF/25v

R223

10k

TP13

10uF/25v

R224

10k

S2_AV2_L CE113

10uF/25v

R225

10k

DACBCLK DACMCLK DOUT

GND

PWM1

DACLRC

ADCREFP

ADCREFP VMIDADC

CE64

10uF/25v

CE66

10uF/25v

TP23

CE65 10uF/25v

TP22 +

CE67 10uF/25v

CB165 0.1uF

CB166 0.1uF

VMIDDAC COD_VOUTR COD_VOUTL +

CE68 10uF/25v

CB167 0.1uF

3,6 3,6 3,6 3,6

HPVDD VMIDADC AUXL AUXR HPVDD

HPVDD

AOSDATA0 AOSDATA1 AOSDATA2 AOSDATA3

SDA14 SCL14

AOSDATA0 AOSDATA1 AOSDATA2 AOSDATA3

ADCLRC DGND DVDD MODE CE DI CL HPOUTL HPGND HPVDD HPOUTR NC

13 14 15 16 17 18 19 20 21 22 23 24

DOUT

36 35 34 33 32 31 30 29 28 27 26 25

AVDD ADCREFP ADCREFGND VMIDADC AUXL AUXR DACREFP DACREFN VMIDDAC VOUTR VOUTL NC

AIN2L AIN1R AIN1L DACBCLK DACMCLK DIN DACLRC ZFLAGR ZFLAGL ADCBCLK ADCMCLK DOUT

DVDD

DACBCLK DACMCLK AOSDATA1 DACLRC

3,6 3 3

DOUT

1 2 3 4 5 6 7 8 9 10 11 12

TP2

DACLRC

DACBCLK DACMCLK DACLRC

S2_AV2_R CE112

CB163 0.1uF

DACBCLK DACMCLK DACLRC

CE63 10uF/25v

ORO5 TP32

MUTE

+ U28

ORO4 ORO5

1,6,9,11 1,6,9,11

ORO3

SCL SDA

AIN2R AIN3L AIN3R AIN4L AIN4R AIN5L AIN5R AINOPL AINVGL AINOPR AINVGR AGND

48 47 46 45 44 43 42 41 40 39 38 37

S1_AV1_R

R220

VGA_IN_R

VGA_IN_L

R219

VGA_IN_L

WM8776 CE69

R226 1k

DV33 L63

COD_VOUTR

DVDD DVDD

10k

DV33

AUSPR R227

10uF/25V CODHPOUTR

FB PWM0

PWM0

TWO WIRE SERIAL CONTROL DEVICE ADDRESS 0x34h CODHPOUTL

CE74 47uF/16v

CB170 0.1uF

TP29

CE71

PWM1 COD_VOUTL

AUSPL R229

10uF/25v

10k WMVDD

VCC VCC

L62 WMVDD FB + J3

CE70 47uF/16v

CB168 0.1uF

R228 WMVREFP

WMVDD

AUSPR AUSPL

1 2 3 MUST USE SHIELD CABLE MUTE 4

CODHPOUTR +

CE115 220uF/16v

CB169 0.1uF

HPOUTR R230

220uF/16v

47k

CE73

560

4x1 W/HOUSING TO AUDIO BD DIP4/W/H/P2.0 GND CE75

HPOUTL

5 WMVDD

R233

AVDD

220uF/16v DVDD

DVDD

CODHPOUTL

47k

U29

AOSDATA0 AOSDATA3 AOSDATA2

33 33 33

SACLK SBCLK SLRCK

2 3 4

MCLK BCLK LRCLK

33 33 33

7 8 9

DATA0 DATA1 DATA2

R362 R363 R361

ML MC MD

R238 0

DNC

11 12 13

ML/I2S MC/IWL MD/DM

MUTE

MODE

1 15

R240 R

R241 C173 0.1uF

R242 R243 0

MODE

ORO3

VREFN

VOUT1L VOUT1R

21 22

AUAVL AUAVR

VOUT2L VOUT2R

23 24

AULS AULR

VOUT3L VOUT3R

25 26

AUCEN AUSUB

DGND

DVDD

WMVREFP

VREFP

AGND

R231 R232 R234

VMID

NC NC

TP14 TP12 TP11 TP19 TP26 TP42

VMID

DACMCLK DACBCLK DACLRC

CE77 10uF/25v

+ 20 19

CB171 0.1uF

PCM/DSD Wolfson-WM8766/8796 ADAC SSOP28/SMD

Title

LCD TV - MediaTek MT8205 Solution

Hardware Mode -> 24-bit Right Justified. Size C Date:

Doc Number

Rev V0.1

WM8776/WM8766/AUDIO CODEC Tuesday, May 10, 2005

Sheet E

LVDS OUT J8 4

AN0 AP0 AN1 AP1 AN2 AP2 CLK1CLK1+ AN3 AP3 AN4 AP4 AN5 AP5

+12V

AN6 AP6 CLK2CLK2+ AN7 AP7

VCC

JP2

1 3

2 4 2x2 JP2X2/DIP/P2.54

LVDS FB BEAD/SMD/0805

LVDSVDD 4A/?v FUSE/DIP/P10.0

LVDSVDD

CE87 220uF/16v

CE88 220uF/16v

CB185 0.1uF

L75 R

RED_OUT R278

CLK2+ CLK2-

CLK1+ CLK1-

3 3

CLK2+ CLK2-

3 3

AP[0..7] AN[0..7]

75 1%

0.082uH L/IND/SMD/0603 C149

C150

33pF

J9 GND

3 3

R G B SVM VSYNC HSYNC

3 3 3 3 3 3

SVM HSYNC VSYNC R366 GRN_OUT

1 2 3 4 5 6 7 8

RED_OUT GRN_OUT BLU_OUT

L76 R G B SVM VSYNC HSYNC

CB186 0.1uF

CRT OUT

GPIO

FI-SE30P-HF LVDS/30P/P1.25/S

CE86 330uF/25v C330UF25V/D8H14

R277

CLK1+ CLK1-

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

75 R279

0.082uH L/IND/SMD/0603

75 1%

C151

GND C152

33pF

8x1 W/HOUSING DIP8/W/H/P2.54

33pF GND

GPIO

L78 B

BLU_OUT R281 75 1%

0.082uH L/IND/SMD/0603 C154

C155

33pF

Title

LCD TV - MediaTek MT8205 Solution Size B

GND

Date: A

Doc Number

Rev V0.1

LVDS/CRT OUT Tuesday, May 10, 2005

Sheet E

PANEL INVERTER POWER UP1_2 UP3_1

OBO1 OBO2 OBO3 URST#

3,6

OBO4 OBO5

6,8

OBO0

OBO1

OBO2

OBO3

OBO0

URST#

UP3_1

OBO6 OBO7

OBO4

OBO5

OBO6

OBO7

Inverter_PWR

CE1 470uF/50v

CE2 470uF/50v

CE3 470uF/50v

CB1 0.1uF

FOR CHI-MEI INVERTER CONNECTOR

CB2 0.1uF PWR_GND

VCC J10 Inverter_PWR R336

UP3_0

PWM0

6 R285 10k

TP1 3

PWM0

UP3_0

1 2 3 4 5 6 7 8 9 10 11 12

R286 Dimming

R288 PWM0

VCC

SELECT Hi For External SELECT Low For Internal

100k 1

Q12 Back 2N3904Light circuit

CB190 0.1uF

VCC

R289 R

12x1 W/HOUSING R.A DIP12/WH/P2.0/R

R50 0

SOT23/SMD 4.7k R291 10k

SELECT 3

KEYPAD - MAX 8-KEYS

R. ANGLE

UP1_2

R290 0

BL_ON/OFF R293 1 4.7k

Q13 2N3904 SOT23/SMD

J12 OBO0 OBO1 OBO2 POWER OBO3 ON/OFF OBO4 OBO5

5VSB

510 LED_RED LED_GRN UP1_2

R2 R13 10K R0603/SMD 4.7K

OBO6

1 R10

OBO7

4.7K

510

R4 3

R14 10K R0603/SMD

L81 L82 L83 L84 L85 L86

R81

DV33A

FB FB FB FB FB FB

TV/AV MENU VOLVOL+ CHCH+ IR

J11

1 2 3 4 5 6 7 8 9 10 11 12

Inverter_PWR

1 2 3 4 5 6 7 8 9 10

0 PWR_GND 10x1 W/HOUSING R.A. DIP10/WH/P2.0/R

12x1 W/HOUSING DIP12/W/H/P2.0

Q1 2N3906 1

Q2 2N3906

R. ANGLE

UP3_0

0 IR & POWER ON LED

R57

5VSB

DV33A

L89 FB

L90 FB

BEAD/SMD/1206

Title

LCD TV - MediaTek MT8205 Solution Size C Date: A

Doc Number

Rev V0.1

BACK_LIGHT/KEYPAD Tuesday, May 10, 2005

Sheet E

TUNER1 IN

Date

ADDRESS

TUNER1

FQ1236 /

TUNER

: NTSC TV

AV , TUNER I/O

TU1

FQ1236-MK3

TU_VCC 1J1

GND3 GND4

SDA SCL SIF1_OUT

2 18

1R21

AF1_OUT

1R3

TV_GND

1R41

GNDS

CON12 M1 FB1

GNDS

9 8 7 6

FB2

VCC

TV_GND

2 3 4 5

9 8 7 6

2 3 4 5

TU_SCL

9 8 7 6

12 13 14

TH3 TH4

TH1 TH2 1 2 3 4 5 6 7 8 9 10 11

1R1 TU_CVBS

1 2 3 4 5 6 7 8 9 10 11 12

CVBS VS_IF AF /MPX

GND1 GND2 NC NC VS_TUNER SCL SDA AS NC NC AF-R AF-L 2nd SIF OUT

TU_12V

GND HOLE

1 SIF1_IN

GND HOLE

GNDS

TU_SDA TU_CVBS

GNDS AF1_IN

GNDS

TUNER1 SIF1 BPF NTSC 4.5MHz PAL 6MHz 1

SDA

1R7

1R8

1.8K

1C5

22pF/27pF

1L2

47uH/22uH

1C6

SIF1

1Q1 2N3904

1L3

1C8

1L4

820pF/560pF

1.5uH/1.2uH

820pF/560pF

1.5uH/1.2uH

TU_VCC 1R10

1R11

220

VCC 1L5

1 1

1C7

1 2

10nF

CE3 100uF/16V

1C9

71.5

CE6

CB3 0.1uF

100uF/16V

1R12

GND V

CB4 0.1uF 100uF/16V

GNDS GNDS

2 GND V

GND V

CB5 0.1uF

10uF/25v

GND V

CE5

+ 2

CE4

GND V

1R9

10nF

1C4 SIF1_IN

47pF

1C3

47pF

1C1

1C2

SCL

100

2 1R6

TU_SDA

1R5

TU_SCL

SIF_12V

GND V

B TU_12V

SIF_12V FB

2 +

CB6 0.1uF

1R14 1

SIF1

1R15 1

SIF1_IN

1R16 1

0/NC 2

AF1_OUT

SIF1_OUT

GNDS TU_12V

TU_12V

TU_VCC

CB7 0.1uF

2 AF1

CE9 220uF/16V

CE8 100uF/16V

SIF_12V

TU_12V

33uF/16V

2 AF1 1

CE7 1

1L6 AF1_IN

GND V

SIF1_OUT

GNDV

GND V AUDIO GROUND

GNDS

GNDS VIDEO GROUND

1 22pF

NPO

5% R1

10K

NIN

10K 5%

1 5

X5R

C11

MBRS130LTR

470NF

C15 2.2UF

47K

10K

R15

22pF

C24

2 2

1UF

MUTEC

2 1000UF/25V

ATA-120

AGND

100K

VPP

C17

6.2V

390PF

C16

C 100NF 1

C55 1n

AGND

C38

10uH

X5R

1 RC4558

FILM

X7R

PGND

C54 1n

1UF

X7R

R12

4K7 5%

2 R67

4K7 5%

1 C3

100NF

100UF/25V

1UF

R66

1K8 5%

X5R

R47

+ C7

4.7uF NPO

+ OUT

C20 2

100K 4.7nF

10UF

100UF/25V

U2A

AUSPL

1 C10

C12 100NF

22UF/16V

2 100K

10K

1 2

R11 R10 C14

+24V R2

+24V

82K

X7R

NPO

C21

1 22pF

NPO

5% R14 82K

+24V R16

+24V

R39

22 1UF

RC4558

C52 1n

1 2 3 4

R19 100K

C53 1n

AGND EN

1 1

SW VPP BS

R21

AGND

2 2

R23

470NF

10K

MBRS130LTR

FILM

R20 C33

R22

10K 22pF

2 1000UF/25V

X5R

1 C34

47K

C32

C41

C36

6.2V

390PF

R38 5%

10 5%

1UF

ATA-120 MUTEC

NIN

1 10K

X5R

10K 5%

4K7 5%

C39

10uH

C35 100NF

R46

4K7 5%

R45

1K8 5%

PGND

R33

X7R

OUT C40 10UF

R18

100UF/25V

X7R

C31

C25

1UF

100NF

C30

C28

X5R

4.7nF

U2B

AUSPR

+ C29

4.7uF NPO

C27

100K

22UF/16V

100K

R17

10K

R36 R37 C19

1 5%

X7R

NPO A

A Title Size

Number

Revision

B Date: File: 1

2-Sep-2005 Sheet of D:\正在进行的项目\LCD TV\LCD TV.DdbDrawn By: 6

R24 3K

MUTEC

5% R25 5%

C37

10K

2 Q1 2N3906

D D6

R40 10K

X5R

Q2 2N3904

D R29

MUTE

1UF

+24V

1N4148

5% +

R41

2N3904

10K

C42

100UF/25V R42

AGND

D10 NC

LOUT

1N4148

4.7V

AGND

R34 1K

Q5 2N3904

1 5%

R43 0R

Q4 2N3906

AGND

MUTEB

+ C18

ROUT

NC R28 1k

AGND

R35 1K

2 5%

R30

Q6 2N3904

22k

+ C51

AGND

220UF/25V

1N4148

C22

10K

+24V

22U/16V

10UF X5R

4K7

R51

R53

2 1 C26

OUT

10K

R13 1K

C45

1 5%

10U/16V

R65

C49

1 R52

R27 NC

47K

RC4558

C46

100K

MUTE

22K

22P

2 AGND

R50

4K7

R49

AUSPL

C60

1k8

100N

B R48

AGND Q7 NC

C13

100U/35V U5A

R55

10K

R54

AGND

R62

J10

LOUT

AGND

ROUT

10K

R63

10K

rca2

+24V

C44 U5B

10UF X5R

R58

C43

+ OUT

10K

R26 1K

C47

1 5%

10U/16V

R61 47K

RC4558

C48

1 R64

R59

R60 100K

4K7

Title

4K7

R57

C59

AUSPR

1k8

R56

22U/16V

22K

C50

2 AGND

22P

AGND Size

Date: File: 1

Number

Revision

2-Sep-2005 Sheet of D:\正在进行的项目\LCD TV\LCD TV.DdbDrawn By: 6

C11

1KV 470P

STTH3L06

MULT

10R

10NF

8.2K

100K R12

R10

0.33R

R18 C7

+24V4A

20R

R30

R26

BC327

STP12NK80

SYNC

C29

GND

1KV 470P

C26

8.2N

0.47R 3W

C24

220PF

R28

R46 30K

0.1UF

22K

TL431

C28

R43

R45 2.7K

75K R38 100R 2W

R31 C22

C21 0.1UF

R44 33.2K

1KV 470P

15K

0.1U

C34

R41

R35

R34 0.47R 3W

4A 1A (Standby 5V) 2A 4A 1A

C36

U3B

3.3N

470R/1W

1.2K

C25

5.6K

C35

R40

R29

LCD-TV 200W SMPS SPEC:

R42

C27 OPEN

R39 6.8K

35V 470U

35V 1000U

C30 C31 C32 C33

VCC

R33

ISEN

R37 100R 2W

OPEN

10R

M1 COMP

DIS

R32

OUT

1N4148

$0.45

VFB

14 Q3

L5991

SGND

VREF

PGND

DCL

STBY

C20

50V 22UF

RCT

R27 5.6K

10UH

+12V

+24V1A

R36

22R R24

R22 100R 2W

8 9

5 6

PQ3220

10K

1KV 470P

+12V

STTH310

R25

BC337

470R/1W

C13

10 11

TR2 ??

0.1U

1 2

10N

1. +5V 2. +5VS 3. +12V 4.+24V 5. +24VA

20K

1.6K

+24V1A

TR1 ??

PQ3220

25V 470U

R17

35V 470U

L6562 C3 100NF

R11

C19

C23

4.7K

50V 2.2U

3.3NF

C46

R52 1K D11 C38

1KV 470P

BC327 L8

R54 43K

C40

R51

CY3 250V 2200P

R53

50V 4.7U

120K

10NF

1A C50

C51 0.1U

C49

C47 C48

1N4148

10UH

R60 100R 2W

SHORT CIRCUIT PROTECTION

+24VA

D8 ??

U3A PC817

25V 470U

20K

Q1 1N4148 7

R23

R62 25V 470U

68K R19

VCC

1KV 470P

25V 470U

CY2 250V1000P

C18

C12

8 9

25V 1000U

CY1 250V1000P

$0.28 C2

C14 C15 C16 C17

+12V 5 6

10UH

+24V

10 11

C10

450V 100UF

BD1 STBR608

+24V4A

1 2

450V 100UF

R16

750K

1.8M

R14

36K

25V 1U C5 680NF

1.6M

0.33

1.6M

68K

INV

C1 CX2

ZCD

0.33U

R2 1.6M R1

35V 22U

CX1

STP20NM50

250VAC 5A

1.8M

750K

1.6M

GND COMP

10mH

1UF 630V

10mH

R15

R20 100R 2W

35V 1000U

STTH8R06

25V 470U

R21 100R 2W

V_BUKE V_BUKE

2.5R R13

25V 1000U

NTC1

PQ32-20 4

1KV 4700P

400UH

25V 1000U

D3 1

25V 1000U

470R/1W

AGND

130K

AGND

B J1 1 2 3 4 5 6 7 8

R59 V_BUKE

D10 FER107

R48

1 2 3 4 5

30K

R66 10K C52

U5 6 5

22NF

R65 10K

R49 10R

R67 10R

D14

D12 ??

FER104

10 9 8

16V 2200U

R56 0.01R +5VS

Drain NC

C45 25V 470U

16V 2200U

ZD3 22V

C54 35V 47U

EC28卧式

GND

D13

4.7K

+5V

Q12

C58 100N

C57 16V 470U

Vcc

R68 1K

R69 1.2K

R80

47K

R73 R74

470R/1W

1N4148

Q13

Q9 STP22NF0

BC337

R77 4.7K 10K R76

R79

C59

4.7K

100N +12V

4.7K

C55 0.1U

R70 1.2K

R71 5.6K

Q10

BC337

C56 47nF

STBY

U7 TL431

Q11

PH2.0

R72 5.6K

R75 4.7K

ON/OFF

BC337 Title Size

LCD-TV 200W SMPS Sch Number

Revision

Ver1.0

Orcad C Date: File: 1

4.7K

1K ZD1 27V

R57 0.01R

$0.60

Vfb

R64

R63

+24V

BC337

PC817B

1 2 3 4

10UH

25V 2200U C43 C44

R78

U4A PC817 +24VA +24VA GND GND

C41

56K

FER104 6

Vstr

J4 A

1KV 472P C42 10R 2W

U4B PC817

R58

R55

14 13 12

FSDM0565

PH2.5

TR3

C53 35V 47U

J3 1 2 3 4 5 6

BC327

PH2.0

C39 10nF

47K/1W

MMBT3906

C37 1000V 10nF

ZD2 BZX79C12RL

+12V

MMBT3904

30K

+24V +24V +24V GND GND GND

4.7K 1

R47

PH-2.0

+5VS +5VS GND GND ON/OFF

R61

2.0K R50

+5V +5V +5V GND GND GND +12V +12V

3-Jun-2005

Sheet of 6

1/1

Basic Operations & Circuit Description Main Electric Components (1). MODULE: There are 1 pc. panel and 2 pcs. PCB including 1 pc. INVERTER board(L), 1 pc. T-CONTROL board,

(2).SIGNAL PROCESS There are 4 pcs. PCBs including 1 pc. Audio&Tuner board, 1 pc. Main digital board, 1 pc. Keypad board, 1 pc. Remote Control Receiver board,

(3).POWER There are 1 pc. PCB for power.

PCB function 1. Power: (1). Input voltage: AC 100V~240V, 47Hz~63Hz. Input range: AC 90V(Min)~264V(Max) auto regulation. (2). To provide power for PCBs. a). +24V for Inverter. b). +5Vsb for standby, c). +5V for signal power, d). +24V for Audio Amp power and converter to e). +12V for Tuner power.

2. Main (Video InterFace) board: (1).Decoder the video signal (TV,CVBS,S-VIDEO) from analog to digital signal. (2).Converter the Video signals( TV,CVBS,S-VIDEO ) and graphics signal (VGA,YPbPr) from internace to progressive, (3). Converter the Digital to fit the panel display mode and output the LVDS signal to Panel.

3. Tuner & Audio Board: (1)Convert TV RF signal to video and audio signal to Main board. (2 ). Decoder the TV SIF signal to audio signal, (3 ). Converter the audio to audio Ampifile and out put to the speaker.

4. KEYBOARD To get the main button control on LCD_TV as SOURCE,MENU, CHANEL +,CHANEL -, VOL +,VOL-, STANDBY functions.

5. Remote control board Receive the remote signal and active for the control.

6. T-CONTROL board Converter the LVDS signal to the digital signal for fitting the PANEL.

7. INVERTER board Converter the low DC voltage +24V to high AC voltage to drive the backlight.

PCB failure analysis 1. CONTROL: a. Abnormal noise on screen. b. No picture.

2. MAIN (VIDEO): a. Lacking color, Bad color scale. b. No voice. c. No picture but with signals output, OSD and back light. d. Abnormal noise on screen.

3. POWER: No picture, no power output.

Basic operation of LCD-TV 1. After turning on power switch, power board sends 5Vst-by Volt to Micro Processor IC waiting for ON signals from Key Switch or Remote Receiver. 2. When the ON signal from Key Switch or Remote Receiver is detected, Micro Processor will send ON Control signals to Power. Then Power sends (5Vsc, 12Vsc, 24V and RLY ON, Vs ON) to PCBs working. This time VIF will send signals to display back light, OSD on the panel and start to search available signal sources. If the audio signals input, them will be amplified by Audio AMP and transmitted to Speakers. 3. If some abnormal signals are detected (for example: over volts, over current, over temperature and under volts), the system will be shut down by Power off.

LCD basic display theory. When an electrical field is applied to the LC planes, the LC molecules re-align themselves so that they are parallel to the electrical field. This electrical process is known as twisted nematic field effect or TNFE. In this alignment, polarized light is not twisted as it passes through the LC material (see Diagram 3A and 3B). If the front polarizer is oriented perpendicular to the rear polarizer, light will pass through the energized display but will be blocked by the rear polarizer. An LCD in this form is acting as a light shutter. Displays with variable characters are created by selectively etching away the conductive surface that was originally deposited on the glass. Etched areas become the display’s background; unetched areas become the display’s characters.

Diagram 3A. The “off” state of a TN LCD-the LC molecules form a twist and therefore cause polarized light to twist as it passes through.

Diagram 3B. The “on” state-the electrical field re-aligns the LC molecules so they do not twist the polarized light.

Disassembly In case of trouble, etc., Necessitating disassemble, please disassemble in the order shown in the illustrations. Reassemble in the reverse order. 1. Removal of the Back Cover

2. Removal of the MAIN PCB a. Remove the screws. b . Slide out the LCD chassis slightly; pull up the connector of AC cord from PCB; pull up the LCD PCB from LCD. c . Remove the Anode cap from Thepicture tube. To avaid a shock hazard, be sure to discharge d . Take out the LCD chassis.

IC DESCRIPTION

-MT8205G -AT24C02 -MX29LV160BBTC -LP2996 -AZ1117/H -WM8776 -MX232A -ISAV330

OBO4 OBO3 OBO2 OBO1 OBO0 OGO7 OGO6 OGO5 DVSS18 OGO4 OGO3 OGO2 OGO1 DVDD3 OGO0 ORO7 ORO6 ORO5 ORO4 DVDD18 ORO3 ORO2 ORO1 ORO0 HIGHA7 DVSS18 HIGHA6 HIGHA5 HIGHA4 HIGHA3 HIGHA2 HIGHA1 HIGHA0 AD0 AD1 DVDD18 AD2 AD3 AD4 DVSS3 AD5 AD6 AD7 IOA0 IOA1 IOA2 IOA3 IOA4 IOA5 IOA6 IOA7 A16 DVDD3I A17 IOA18 IOA19 IOA20 DVSS18 IOA21 IOALE IOOE# IOWR# IOCS# WR# RD# DVDD3 INT0# UP12 UP13 UP14 DVDD18 UP15 UP16 UP17 UP30 UP31 DVSS18 PRST# UP34 UP35 FCICLK FCICMD FCIDAT GPIO0 PWM0 PWM1 IR RXD TXD DVSS3 ICE SCL SDA SCL0 SDA0 SCL1 SDA1

C3 D3 C1 C2 L11 D1 D2 F2 D4 E1 E2 E3 E4 F1 F4 F3 G3 J3 G4 H3 K3 K4 J4 H4 L3 G2 G1 H2 H1 M12 J2 J1 K2 K1 L4 L2 L1 M2 M1 M11 N2 N1 P2 P1 M3 R2 R1 T2 T1 N12 N3 M4 N4 N11 T4 P3 R3 P4 U4 R4 U3 V4 T3 U1 U2 V1 V2 V3 W1 W2 AC9 W3 W4 Y1 Y2 Y3 P11 Y4 AA1 AA2 AA3 AA4 AB1 AB2 AB3 AB4 AC1 AC18 AC2 AC3 AC4 R11 AD1 AD2 AD3 AD4 AE1

AE2 AF1 AF2 AE3 AF3 AE4 AF4 AC5 T11 AD5 AE5 AF5 AC6 AD9 AD6 AE6 AF6 AC7 AD7 AD18 AE7 AF7 AC8 AD8 AF8 P12 AE9 AF9 AE10 AF10 AC11 AD11 AF12 AE15 AD15 AC19 AC15 AF16 AE16 R12 AD16 AC16 AF17 AD17 AD14 AE14 AF14 AF13 AE13 AD13 AC13 AE8 AC10 AC17 AE12 AD12 AE11 T12 AF11 AE17 AF15 AC12 AC14 AF18 AE18 AD10 AF19 AE19 AF20 AE20 AD19 AD20 AC20 AF21 AE21 AD21 P13 AC21 AD22 AC22 AF22 AE22 AF23 AE23 AD23 AC23 AF24 AE24 AD24 R13 AC24 AF25 AE25 AF26 AE26 AB23 AB24

VFEVDD1 ADCVDD4 SIF AF ADCVSS4 REFP4 REFN4 ADCVSS ADIN4 ADIN3 ADIN2 ADIN1 ADIN0 ADCVDD PWM2VREF AUXVTOP AUXVBOTTOM VPLLVSS VPLLVDD DLLVDD DLLVSS BGVSS REXTA BGVDD LVDDA A7P A7N CLK2P U? CLK2N LVSSA A6P A6N A5P A5N LVDDB A4P A4N A3P A3N LVSSB CLK1P CLK1N A2P A2N LVDDC A1P A1N A0P A0N LVSSC DACVDDC VREF FS DACVSSC SVM DACVDDB DACVSSB DACVDDA G DACVSSA B R DE VSY NCO HSYNCO VCLK EBO7 EBO6 EBO5 EBO4 DVDD3I EBO3 EBO2 EBO1 EBO0 EGO7 DVSS18 EGO6 EGO5 EGO4 EGO3 EGO2 EGO1 EGO0 ERO7 ERO6 ERO5 DVDD18 ERO4 ERO3 ERO2 DVSS3 ERO1 ERO0 OBO7 OBO6 OBO5 VFEVSS1 AVCM ADCVDD0 CVBS2N CVBS2P CVBS1N CVBS1P CVBS0N CVBS0P ADCVSS0 REFP0 REFN0 ADCVDD1 SCN SCP SYN SYP ADCVSS1 REFP1 REFN1 VFEVDD0 VOCM VFEVSS0 VICM ADCVDD2 CRN CRP CBN CBP YN YP SOY ADCVSS2 REFP2 REFN2 MON0 MON1 ADCVDD3 RN RP GN GP SOG BN BP ADCVSS3 REFP3 REFN3 VSYNC HSYNC DVSS DVDD ADCPLLVSS1 ADCPLLVDD1 ADCPLLVDD ADCPLLVSS SYSPLLVSS SYSPLLVDD TESTP TESTN XTALVDD XTALO XTALI XTALVSS APLL_CAP APLLVSS APLLVDD DMPLLVDD DMPLLVSS VI0 VI1 VI2 VI3 VI4 VI5 VI6 DVDD18 VI7 VI8 VI9 VI10 VI11 DVSS3 VI12 VI13 VI14 VI15 DVSS18 VI16 VI17 VI18 VI19 VI20 VI21 VI22 VI23 VCLK_DVI

Pinout information

MT8205

BGA388/SOCKET MT8205

Pin Descriptions 2.3 Pin Descriptions Table 2-1 provides detail video/audio port pin descriptions. Table 2-1 video/audio port pin descriptions. Pin E24 C25 C26 A25 A26 B26 B25 B24 A3 A2 A1 C1 C2

Symbol AOMCLK AOLRCK AOBCK AOSDATA0 AOSDATA1 AOSDATA2 AOSDATA3 LIN CVBS0P CVBS1P CVBS2P SIF AF

Type

Description

Audio out master clock

Audio out left-right clock

Audio out bit clock

Audio out data line 0

Audio out data line 1

Audio out data line 2

Audio out data line 3

Audio line in

Composite Video input 0

Composite Video input 1

Composite Video input 2

Tuner Sound

SIF

Tuner Sound

AT24C01A/02/04/08/16 Features

•

• • • • • • • • • • •

Low Voltage and Standard Voltage Operation 5.0 (VCC = 4.5V to 5.5V) 2.7 (VCC = 2.7V to 5.5V) 2.5 (VCC = 2.5V to 5.5V) 1.8 (VCC = 1.8V to 5.5V) Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K) or 2048 x 8 (16K) 2-Wire Serial Interface Bidirectional Data Transfer Protocol 100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility Write Protect Pin for Hardware Data Protection 8-Byte Page (1K, 2K), 16-Byte Page (4K, 8K, 16K) Write Modes Partial Page Writes Are Allowed Self-Timed Write Cycle (10 ms max) High Reliability Endurance: 1 Million Cycles Data Retention: 100 Years Automotive Grade and Extended Temperature Devices Available 8-Pin and 14-Pin JEDEC SOIC and 8-Pin PDIP Packages

2-Wire Serial CMOS E2PROM 1K (128 x 8) 2K (256 x 8) 4K (512 x 8)

Description The AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C01A/02/04/08/16 is available in space saving 8-pin PDIP, 8-pin and 14-pin SOIC packages and is accessed via a 2-wire serial interface. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions.

8K (1024 x 8) 16K (2048 x 8)

AT24C01A/2/4/8/16

Pin Configurations Pin Name

Function

A0 to A2

Address Inputs

SDA

Serial Data

SCL

Serial Clock Input

Write Protect

No Connect

8-Pin PDIP

14-Pin SOIC 8-Pin SOIC

0180C

2-25

Absolute Maximum Ratings* Operating Temperature................... -55°C to +125°C Storage Temperature...................... -65°C to +150°C Voltage on Any Pin with Respect to Ground ..................... -0.1V to +7.0V

*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Maximum Operating Voltage ........................... 6.25V DC Output Current ......................................... 5.0 mA

Block Diagram

Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each E2PROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the AT24C01A and the AT24C02. As many as eight 1K/2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). 2-26

AT24C01A/02/04/08/16

The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no connect. The AT24C08 only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no connects. The AT24C16 does not use the device address pins which limits the number of devices on a single bus to one. The A0, A1 and A2 pins are no connects. (continued)

MX29LV160BT/BB

16M-BIT [2Mx8/1Mx16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY FEATURES erase operation completion. • Ready/Busy pin (RY/BY) - Provides a hardware method of detecting program or erase operation completion. • Sector protection - Hardware method to disable any combination of sectors from program or erase operations - Temporary sector unprotect allows code changes in previously locked sectors. • CFI (Common Flash Interface) compliant - Flash device parameters stored on the device and provide the host system to access • 100,000 minimum erase/program cycles • Latch-up protected to 100mA from -1V to VCC+1V • Boot Sector Architecture - T = Top Boot Sector - B = Bottom Boot Sector • Low VCC write inhibit is equal to or less than 1.4V • Package type: - 44-pin SOP - 48-pin TSOP - 48-ball CSP • Compatibility with JEDEC standard - Pinout and software compatible with single-power supply Flash • 10 years data retention

• Extended single - supply voltage range 2.7V to 3.6V • 2,097,152 x 8/1,048,576 x 16 switchable • Single power supply operation - 3.0V only operation for read, erase and program operation • Fully compatible with MX29LV160A device • Fast access time: 70/90ns • Low power consumption - 30mA maximum active current - 0.2uA typical standby current • Command register architecture - Byte/word Programming (9us/11us typical) - Sector Erase (Sector structure 16K-Bytex1, 8K-Bytex2, 32K-Bytex1, and 64K-Byte x31) • Auto Erase (chip & sector) and Auto Program - Automatically erase any combination of sectors with Erase Suspend capability. - Automatically program and verify data at specified address • Erase Suspend/Erase Resume - Suspends sector erase operation to read data from, or program data to, any sector that is not being erased, then resumes the erase. • Status Reply - Data polling & Toggle bit for detection of program and

GENERAL DESCRIPTION 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility.

The MX29LV160BT/BB is a 16-mega bit Flash memory organized as 2M bytes of 8 bits or 1M words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29LV160BT/BB is packaged in 44-pin SOP, 48-pin TSOP and 48-ball CSP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers.

MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cycling. The MX29LV160BT/BB uses a 2.7V~3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms.

The standard MX29LV160BT/BB offers access time as fast as 70ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29LV160BT/BB has separate chip enable (CE) and output enable (OE) controls.

The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.

MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29LV160BT/BB uses a command register to manage this functionality. The command register allows for

P/N:PM1041

REV. 1.2, JUL. 01, 2004

LP2996 DDR Termination Regulator General Description

Features

The LP2996 linear regulator is designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2996 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

n n n n n n n n

An additional feature found on the LP2996 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

Source and sink current Low output voltage offset No external resistors required Linear topology Suspend to Ram (STR) functionality Low external component count Thermal Shutdown Available in SO-8, PSOP-8 or LLP-16 packages

Applications n DDR-I and DDR-II Termination Voltage n SSTL-2 and SSTL-3 Termination n HSTL Termination

Typical Application Circuit

20057518

ÂŠ 2003 National Semiconductor Corporation

DS200575

www.national.com

LP2996 DDR Termination Regulator

November 2003

SCDS164A â&#x20AC;&#x201C; MAY 2004 â&#x2C6;&#x2019; REVISED MAY 2004

D Low Differential Gain and Phase

D D D

VCC EN S1D S2D DD S1C S2C DC

RGY PACKAGE (TOP VIEW)

S1A S2A DA S1B S2B DB

VCC

16 15 EN 14 S2D

2 3

13 S2D 12 DD

4 5 6 7 8

11 S1C 10 S2C

D D D

IN S1A S2A DA S1B S2B DB GND

GND

D D D

D, DBQ, OR PW PACKAGE (TOP VIEW)

(DG = 0.64%, DP = 0.1 Degrees Typ) Wide Bandwidth (BW = 300 MHz Min) Low Crosstalk (XTALK = â&#x2C6;&#x2019;63 dB Typ) Low Power Consumption (ICC = 3 ÂľA Max) Bidirectional Data Flow, With Near-Zero Propagation Delay Low ON-State Resistance (ron = 3 â&#x201E;Ś Typ) VCC Operating Range From 4.5 V to 5.5 V Ioff Supports Partial-Power-Down Mode Operation Data and Control Inputs Provide Undershoot Clamp Diode Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 â&#x2C6;&#x2019; 2000-V Human-Body Model (A114-B, Class II) â&#x2C6;&#x2019; 1000-V Charged-Device Model (C101) Suitable for Both RGB and Composite-Video Switching

description/ordering information The TI TS5V330 video switch is a 4-bit 1-of-2 multiplexer/demultiplexer with a single switch-enable (EN) input. When EN is low, the switch is enabled and the D port is connected to the S port. When EN is high, the switch is disabled and the high-impedance state exists between the D and S ports. The select (IN) input controls the data path of the multiplexer/demultiplexer. ORDERING INFORMATION

QFN â&#x2C6;&#x2019; RGY SOIC â&#x2C6;&#x2019; D â&#x2C6;&#x2019;40Â°C to 85Â°C

ORDERABLE PART NUMBER

PACKAGEâ&#x20AC;

SSOP (QSOP) â&#x2C6;&#x2019; DBQ TSSOP â&#x2C6;&#x2019; PW

Tape and reel

TS5V330RGYR

Tube

TS5V330D

Tape and reel

TS5V330DR

Tape and reel

TS5V330DBQR

Tube

TS5V330PW

Tape and reel

TS5V330PWR

TOP-SIDE MARKING TE330 TS5V330 TE330 TE330

â&#x20AC; Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright ďŁŠ 2004, Texas Instruments Incorporated

!" # $"%& ! ' #( '"! ! $#! ! $# )# # #* " # ' ' + ,( '"! $ !# - ' # #!# &, !&"'# # - && $ # # (

POST OFFICE BOX 655303

â&#x20AC;˘ DALLAS, TEXAS 75265

19-0175; Rev 3; 5/96

±15kV ESD-Protected, +5V RS-232 Transceivers ____________________________Features ♦ ESD Protection for RS-232 I/O Pins: ±15kV—Human Body Model ±8kV—IEC1000-4-2, Contact Discharge ±15kV—IEC1000-4-2, Air-Gap Discharge ♦ Latchup Free (unlike bipolar equivalents) ♦ Guaranteed 120kbps Data Rate—LapLink™ Compatible ♦ Guaranteed 3V/µs Min Slew Rate ♦ Operate from a Single +5V Power Supply

_________________Pin Configurations TOP VIEW C1+ 1

16 VCC

V+ 2

15 GND

C1- 3 C2+ 4 C2- 5

________________________Applications

14 T1OUT

MAX202E MAX232E

12 R1OUT

V- 6

11 T1IN

T2OUT 7

10 T2IN 9

R2IN 8

Notebook, Subnotebook, and Palmtop Computers Battery-Powered Equipment Hand-Held Equipment

13 R1IN

R2OUT

DIP/SO Pin Configurations and Typical Operating Circuits continued at end of data sheet.

Ordering Information appears at end of data sheet.

_____________________________________________________________Selection Guide PART

No. of RS-232 DRIVERS

No. of RS-232 RECEIVERS

RECEIVERS ACTIVE IN SHUTDOWN

No. of EXTERNAL CAPACITORS

LOW-POWER SHUTDOWN

TTL THREESTATE

MAX202E

4 (0.1µF)

MAX203E

None

MAX205E

None

Yes

MAX206E

4 (0.1µF)

Yes

MAX207E

4 (0.1µF)

MAX208E

4 (0.1µF)

MAX211E

4 (0.1µF)

Yes

MAX213E

4 (0.1µF)

Yes

MAX232E

4 (1µF)

MAX241E

4 (1µF)

Yes

LapLink is a registered trademark of Traveling Software, Inc. ________________________________________________________________ Maxim Integrated Products

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

MAX202E–MAX213E, MAX232E/MAX241E

_______________General Description The MAX202E–MAX213E, MAX232E/MAX241E line drivers/receivers are designed for RS-232 and V.28 communications in harsh environments. Each transmitter output and receiver input is protected against ±15kV electrostatic discharge (ESD) shocks, without latchup. The various combinations of features are outlined in the Selection Guide. The drivers and receivers for all ten devices meet all EIA/TIA-232E and CCITT V.28 specifications at data rates up to 120kbps, when loaded in accordance with the EIA/TIA-232E specification. The MAX211E/MAX213E/MAX241E are available in 28pin SO packages, as well as a 28-pin SSOP that uses 60% less board space. The MAX202E/MAX232E come in 16-pin narrow SO, wide SO, and DIP packages. The MAX203E comes in a 20-pin DIP/SO package, and needs no external charge-pump capacitors. The MAX205E comes in a 24-pin wide DIP package, and also eliminates external charge-pump capacitors. The MAX206E/MAX207E/MAX208E come in 24-pin SO, SSOP, and narrow DIP packages. The MAX232E/ MAX241E operate with four 1µF capacitors, while the MAX202E/MAX206E/MAX207E/MAX208E/MAX211E/ MAX213E operate with four 0.1µF capacitors, further reducing cost and board space.

MAX202E–MAX213E, MAX232E/MAX241E

±15kV ESD-Protected, +5V RS-232 Transceivers Table 3. DB9 Cable Connections Commonly Used for EIA/TIAE-232E and V.24 Asynchronous Interfaces PIN

CONNECTION

Received Line Signal Detector (sometimes called Carrier Detect, DCD)

Handshake from DCE

Receive Data (RD)

Data from DCE

Transmit Data (TD)

Data from DTE

Data Terminal Ready

Handshake from DTE

Signal Ground

Reference point for signals

Data Set Ready (DSR)

Handshake from DCE

Request to Send (RTS)

Handshake from DTE

Clear to Send (CTS)

Handshake from DCE

Ring Indicator

Handshake from DCE

____________Pin Configurations and Typical Operating Circuits (continued) +5V INPUT

TOP VIEW

0.1µF* 6.3V

0.1µF 16 1 0.1µF* 6.3V

3 4

C1+ 1

16 VCC

V+ 2

15 GND

C1- 3 C2+ 4 C2- 5

0.1µF* 16V

C1+

VCC

V+

+5V TO +10V C1- VOLTAGE DOUBLER C2+ +10V TO -10V C2- VOLTAGE INVERTER

V-

+10V

-10V 0.1µF* 16V

14 T1OUT

MAX202E MAX232E

13 R1IN 12 R1OUT

V- 6

11 T1IN

T2OUT 7

10 T2IN

R2IN 8

T1IN

T1OUT 14

TTL/CMOS INPUTS

R2OUT

DIP/SO

RS-232 OUTPUTS 10

T2IN

R1OUT

T2OUT

5k R2OUT

R2IN

R2 5k

PIN NUMBERS ON TYPICAL OPERATING CIRCUIT REFER TO DIP/SO PACKAGE, NOT LCC. * 1.0µF CAPACITORS, MAX232E ONLY.

R1IN 13

TTL/CMOS OUTPUTS 9

GND 15

______________________________________________________________________________________

RS-232 INPUTS

TFT LCD Preliminary Specification

MODEL NO.: V270B1 - L01

LCD TV Head Division AVP QRA Dept.

郭振隆

Approval

DDIII Approval

陳永一

李汪洋

TVHD / PDD DDII Approval 藍文錦

DDI Approval 林文聰

LCD TV Marketing and Product Management Division Product Manager

陳立宜

謝芳宜

- CONTENTS REVISION HISTORY

-------------------------------------------------------

1. GENERAL DESCRIPTION

-------------------------------------------------------

2. ABSOLUTE MAXIMUM RATINGS

-------------------------------------------------------

------------------------------------------------------3.1 TFT LCD MODULE 3.2 BACKLIGHT INVERTER UNIT 3.2.1 CCFL(Cold Cathode Fluorescent Lamp) CHARACTERISTICS 3.2.2 INVERTER CHARACTERISTICS 3.2.3 INVERTER INTERTFACE CHARACTERISTICS

1.1 OVERVIEW 1.2 FEATURES 1.3 APPLICATION 1.4 GENERAL SPECIFICATIONS 1.5 MECHANICAL SPECIFICATIONS 2.1 ABSOLUTE RATINGS OF ENVIRONMENT 2.2 ELECTRICAL ABSOLUTE RATINGS 2.2.1 TFT LCD MODULE 2.2.2 BACKLIGHT UNIT

3. ELECTRICAL CHARACTERISTICS

4. BLOCK DIAGRAM

-------------------------------------------------------

5. INTERFACE PIN CONNECTION

-------------------------------------------------------

6. INTERFACE TIMING

-------------------------------------------------------

7. OPTICAL CHARACTERISTICS

-------------------------------------------------------

8. DEFINITION OF LABELS

-------------------------------------------------------

9. PACKAGING

-------------------------------------------------------

10. PRECAUTIONS

-------------------------------------------------------

11. MECHANICAL CHARACTERISTICS

-------------------------------------------------------

4.1 TFT LCD MODULE

5.1 TFT LCD MODULE 5.2 BACKLIGHT UNIT 5.3 INVERTER UNIT 5.4 BLOCK DIAGRAM OF INTERFACE 5.5 LVDS INTERFACE 5.6 COLOR DATA INPUT ASSIGNMENT 6.1 INPUT SIGNAL TIMING SPECIFICATIONS 6.2 POWER ON/OFF SEQUENCE 7.1 TEST CONDITIONS 7.2 OPTICAL SPECIFICATIONS

8.1 CMO MODULE LABEL

9.1 PACKING SPECIFICATIONS 9.2 PACKING METHOD 10.1 ASSEMBLY AND HANDLING PRECAUTIONS 10.2 SAFETY PRECAUTIONS

REVISION HISTORY Version

Date

Ver 1.0

Jun. 15,â&#x20AC;&#x2122;05

Page (New) All

Section All

Description Preliminary Specification was first issued.

1. GENERAL DESCRIPTION 1.1 OVERVIEW V270B1- L01 is a TFT Liquid Crystal Display module with 14-CCFL Backlight unit and 1ch-LVDS interface. The display diagonal is 27”. This module supports 1366 x 768 WXGA format and can display true 16.7M colors(8-bits colors). The inverter module for backlight is built-in.

1.2 FEATURES - Excellent brightness (550 nits) - Ultra high contrast ratio (1000:1) - Fast response time (8ms) - High color saturation NTSC 75% - WXGA (1366 x 768 pixels) resolution - DE (Data Enable) only mode - LVDS (Low Voltage Differential Signaling) interface - Optimized response time for both 50/60 Hz frame rate - Ultra wide viewing angle: 176(H)/176(V) (CR>20) Super MVA technology - 180 degree rotation display option - Low color shift function option - Color reproduction (Nature color)

1.3 APPLICATION - TFT LCD TVs -

High brightness, multi-media displays

1.4 GENERAL SPECIFICATI0NS Item Active Area Bezel Opening Area Driver Element Pixel Number Pixel Pitch (Sub Pixel) Pixel Arrangement Display Colors Display Operation Mode Surface Treatment

Specification 596.259 (H) x 335.232 (V) (27” diagonal) 603.22 (H) x 341.98 (V) a-si TFT active matrix 1366 x R.G.B. x 768 0.1460 (H) x 0.4365 (V) RGB vertical stripe 16.7M Transmissive mode / Normally black Hardness : 3H, Haze : 40% Anti-reflective coating < 2% reflection

Unit mm mm pixel mm color -

Note (1)

1.5 MECHANICAL SPECIFICATIONS Item Horizontal(H) Vertical(V) Module Size Depth(D) Depth(D) Weight

Min. 636.85 379.1 33.9 39.2 3700

Typ. 637.55 379.8 35.4 40.7 4000

Max. 638.25 380.5 36.9 42.2 4300

Unit mm mm mm mm g

Note To PCB cover To inverter cover

Note (1) Please refer to the attached drawings for more information of front and back outline dimensions. 4

2. ABSOLUTE MAXIMUM RATINGS 2.1 ABSOLUTE RATINGS OF ENVIRONMENT Item

Symbol

Storage Temperature Operating Ambient Temperature Shock (Non-Operating) Vibration (Non-Operating)

Min. -20 0 -

TST TOP SNOP VNOP

Value

Max. +60 +50 50 1.0

Unit

Note

ºC ºC G G

(1) (1), (2) (3), (5) (4), (5)

Note (1) Temperature and relative humidity range is shown in the figure below. (a) 90 %RH Max. (Ta ≦ 40 ºC). (b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC). (c) No condensation. Note (2) The maximum operating temperature is based on the test condition that the surface temperature of display area is less than or equal to 60 ºC with LCD module alone in a temperature controlled chamber. Thermal management should be considered in final product design to prevent the surface temperature of display area from being over 60 ºC. The range of operating temperature may degrade in case of improper thermal management in final product design. Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z. Note (4) 10 ~ 500 Hz, 10 min, 1 time each X, Y, Z. Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that the module would not be twisted or bent by the fixture.

Relative Humidity (%RH) 100 90 80

Operating Range 40

Storage Range

10 -40

-20

Temperature (ºC)

2.2 ELECTRICAL ABSOLUTE RATINGS 2.2.1 TFT LCD MODULE Item Power Supply Voltage Input Signal Voltage

Symbol Vcc VIN

Min. -0.3 -0.3

Value

Max. 6.0 3.6

Unit

Note

V V

(1)

2.2.2 BACKLIGHT UNIT Item

Symbol

Lamp Voltage Power Supply Voltage Control Signal Level

VW VBL －

Test Min. Condition Ta = 25 ℃ －－ 0 － -0.3

Type

Max.

Unit

Note

－－－

3000 30 7

VRMS V V

(1) (1), (3)

Note (1) Permanent damage to the device may occur if maximum values are exceeded. Functional operation should be restricted to the conditions described under normal operating conditions. Note (2) No moisture condensation or freezing. Note (3) The control signals includes Backlight On/Off Control, Internal PWM Control, External PWM Control and Internal/External PWM Selection.

3. ELECTRICAL CHARACTERISTICS Ta = 25 ± 2 ºC

3.1 TFT LCD MODULE Parameter

Min. 4.5 -

Value Typ. 5.0 1.8 1.2 1.65

Max. 5.5 150 3.0 -

VLVTH

+100

VLVTL

-100

VLVC RT VIH VIL

1.125

1.25 100 -

1.375

V ohm V V

Symbol

Power Supply Voltage Power Supply Ripple Voltage Rush Current White Power Supply Current Black Vertical Stripe Differential Input High Threshold Voltage LVDS Differential Input Low Interface Threshold Voltage Common Input Voltage Terminating Resistor CMOS Input High Threshold Voltage interface Input Low Threshold Voltage

VCC VRP IRUSH ICC

2.7 0

3.3 0.7

Unit

Note

V mV A A A A

(1)

Note (1) The module should be always operated within above ranges. Note (2) Measurement Conditions: +5.0V Q1

2SK1475 Vcc FUSE

1uF

R1 47K

(High to Low) (Control Signal)

2SK1470

SW 1K +12V

VR1

47K

0.01uF

1uF

Vcc rising time is 470us +5V 0.9Vcc 0.1Vcc

GND

470us

(LCD Module Input)

(2) (3)

Note (3) The specified power supply current is under the conditions at Vcc = 5 V, Ta = 25 ± 2 ºC, fv = 60 Hz, whereas a power dissipation check pattern below is displayed. b. Black Pattern

a. White Pattern

Active Area

c. Vertical Stripe Pattern

R G B R G B B R G B R G B R B R G B R G B R R G B R G B Active Area

3.2 BACKLIGHT INVERTER UNIT 3.2.1 CCFL (Cold Cathode Fluorescent Lamp) CHARACTERISTICS (Ta = 25 ± 2 ºC) Min.

Value Typ.

Max.

1120

Lamp Current

4.2

Lamp Starting Voltage

Operating Frequency

Lamp Life Time

LBL

Parameter

Symbol

Lamp Voltage

Unit

Note

VRMS

IL = 4.7mA

4.7

5.2

mARMS

(1)

1650

VRMS

(2), Ta = 0 ºC

1500

VRMS

(2), Ta = 25 ºC

50 50,000

60,000

KHz

(3)

Hrs

(4)

3.2.2 INVERTER CHARACTERISTICS (Ta = 25 ± 2 ºC)

VBL

Min. 22.8

Value Typ. 92 24

Max. 25.2

Power Supply Current

IBL

3.8

Non Dimming

Input Ripple Noise

500

mVP-P

VBL =22.8V

1790

VRMS

Ta = 0 ºC

1200

VRMS

Ta = 25 ºC

Parameter

Symbol

Power Consumption

PBL

Power Supply Voltage

Backlight Turn on Voltage

VBS

Unit

Note

(5), IL = 4.7mA

VDC

Oscillating Frequency

kHz

Dimming Frequency

150

160

170

Minimum Duty Ratio

DMIN

Note (1) Lamp current is measured by utilizing high frequency current meters as shown below:

A A A A A A A A A A A A A A

LCD Module

HV (Pink) HV (White)

1 2

HV (Pink) HV (White)

1 2

HV (Pink) HV (White)

1 2

HV (Pink) HV (White)

1 2

HV (Pink) HV (White)

1 2

HV (Pink) HV (White)

1 2

HV (Pink) HV (White)

1 2

Inverter

LV (Gray)

Note (2) The lamp starting voltage VS should be applied to the lamp for more than 1 second under starting up duration. Otherwise the lamp could not be lighted on completed. Note (3) The lamp frequency may produce interference with horizontal synchronous frequency from the display, and this may cause line flow on the display. In order to avoid interference, the lamp frequency should be detached from the horizontal synchronous frequency and its harmonics as far as possible. 9

Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value and the effective discharge length is longer than 80% of its original length (Effective discharge length is defined as an area that has equal to or more than 70% brightness compared to the brightness at the center point.) as the time in which it continues to operate under the condition Ta = 25 ±2℃ and IL = 4.2 ~ 5.2 mARMS. Note (5) The power supply capacity should be higher than the total inverter power consumption PBL. Since the pulse width modulation (PWM) mode was applied for backlight dimming, the driving current changed as PWM duty on and off. The transient response of power supply should be considered for the changing loading when inverter dimming.

3.2.3 INVERTER INTERTFACE CHARACTERISTICS Item

Symbol ON

On/Off Control Voltage

OFF HI

Internal/External PWM Select Voltage

Internal PWM Control Voltage

MAX

External PWM Control Voltage

VBLON VSEL

Test

Min.

Typ.

Max.

Unit

－

2.0

－

5.0

－

0.8

－

2.0

－

5.0

－

0.8

－

3.0

minimum duty ratio

－

maximum duty ratio

2.0

－

5.0

duty on

－

0.8

duty off

Condition

VIPWM

VSEL = L

VEPWM

VSEL = H

Control Signal Rising Time

－

100

Control Signal Falling Time

－

100

PWM Signal Rising Time

TPWMR

－

PWM Signal Falling Time

TPWMF

－

Input impedance

RIN

－

MΩ

BLON Delay Time

Ton

－

BLON Off Time

Toff

－

MIN LO

Note

Note (1) The SEL signal should be valid before backlight turns on by BLON signal. It is inhibited to change the internal/external PWM selection (SEL) during backlight turn on period.

Note (2) The power sequence and control signal timing are shown as the following figure.

VBL

VBLON 0

2.0V 0.8V Tr

VSEL 0

VEPWM 0

Toff

Ton

2.0V 0.8V

Backlight on duration

Tf Int. Dimming Function

Ext. Dimming Function TPWMR

TPWMF

3.0V VIPWM 0

VW External PWM Period

External PWM Duty Minimun Duty

100%

4. BLOCK DIAGRAM 4.1 TFT LCD MODULE

RX3(+/-) RXCLK(+/-)

Vcc GND

INPUT CONNECTOR

RX2(+/-)

(JAE,FI-X30SSL-HF)

RX1(+/-)

TIMING CONTROLLER

SCAN DRIVER IC

FRAME BUFFER

RX0(+/-)

TFT LCD PANEL (1366x3x768)

DATA DRIVER IC DC/DC CONVERTER & REFERENCE VOLTAGE

CN1 VBL GND CN2 VBL GND SEL E_PWM I_PWM BLON

CN3-CN9:SM02 (8.0)B-BHS-1-TB(LF)(JST)

BACKLIGHT UNIT

INVERTER CONNECTOR CN1:S10B-PH-SM3-TB(D)(LF)(JST) CN2: S12B-PH-SM3-TB(D)(LF)(JST)

CN10: S2B-ZR-SM3A-TF (D)(LF)(JST)

5. INTERFACE PIN CONNECTION 5.1 TFT LCD MODULE CNF1 Connector Pin Assignment Pin No. Symbol Description 1 GND Ground 2 RPF Display Rotation 3 SELLVDS Select LVDS data format 4 NC No Connection 5 NC No Connection 6 ODSEL Overdrive Lookup Table Selection 7 EN LCS Low Color Shift 8 GND Ground 9 RX0Negative transmission data of pixel 0 10 RX0+ Positive transmission data of pixel 0 11 RX1Negative transmission data of pixel 1 12 RX1+ Positive transmission data of pixel 1 13 RX2Negative transmission data of pixel 2 14 RX2+ Positive transmission data of pixel 2 15 RXCLKNegative of clock 16 RXCLK+ Positive of clock 17 RX3Negative transmission data of pixel 3 18 RX3+ Positive transmission data of pixel 3 19 GND Ground 20 GND Ground 21 GND Ground 22 GND Ground 23 GND Ground 24 GND Ground 25 GND Ground 26 VCC Power supply: +5V 27 VCC Power supply: +5V 28 VCC Power supply: +5V 29 VCC Power supply: +5V 30 VCC Power supply: +5V Note (1) Connector Part No.: FI-X30SSL-HF(JAE) or compatible

Note (3) (5) (2) (4) (6)

Note (2) Reserved for internal use. Left it open. Note (3) Low : normal display (default), High : display with 180 degree rotation Note (4) Overdrive lookup table selection. The Overdrive lookup table should be selected in accordance to the frame rate to optimize image quality. ODSEL Note L Lookup table was optimized for 60 Hz frame rate. H Lookup table was optimized for 50 Hz frame rate. Note (5) Please refer to 5.5 LVDS INTERFACE (Page 17) Note (6) Enable Low color shift function. EN LCS L H

Note

Low color shift off Low color shift on

5.2 BACKLIGHT UNIT The pin configuration for the housing and leader wire is shown in the table below. CN3-CN9 (Housing): BHR-03VS-1 (JST)

Pin No. 1 2

Symbol

Description

HV HV

High Voltage High Voltage

Wire Color Pink White

Note (1) The backlight interface housing for high voltage side is a model BHR-03VS-1, manufactured by JST. The mating header on inverter part number is SM02(8.0)B-BHS-1-TB(LF) or equivalent.

Pin No. 1 2

CN10 (Housing): ZHR-2 (JST) or equivalent Symbol Description LV NC

Low Voltage (+) No Connection

Wire Color Gray -

Note (2) The backlight interface housing and return cable for low voltage side is a model ZHR-2 , manufactured by JST or equivalent. The mating header on inverter part number is S2B-ZR-SM3A-TF(D)(LF) or equivalent.

5.3 INVERTER UNIT CN1(Header):S10B-PH-SM3-TB(D)(LF)(JST) or equivalent. Pin Name Description 1 2 VBL +24V Power input 3 4 5 6 7 GND Ground 8 9 10 CN2(Header): S12B-PH-SM3-TB(D)(LF)(JST) or equivalent. Pin 1 2 3 4 5 6 7 8

Name

Description

VBL

+24V Power input

GND

Ground

SEL

Internal/external PWM selection High : external dimming Low : internal dimming

E_PWM

I_PWM

BLON

External PWM control signal E_PWM should be connected to low when internal PWM was selected (SEL = low). Internal PWM control signal I_PWM should be connected to ground when external PWM was selected (SEL = high). Backlight on/off control

CN3-CN9(Header): SM02(8.0)B-BHS-1-TB(LF)(JST) or equivalent Pin

Name

Description

CCFL HOT CCFL high voltage

CN10(Header): S2B-ZR-SM3A-TF(D)(LF)(JST) or equivalent Pin 1 2

Name

Description

CCFL COLD CCFL low voltage NC

Note (1) Floating of any control signal is not allowed. 15

5.4 BLOCK DIAGRAM OF INTERFACE CNF1

Rx0+ R0-R7

51Ω 51Ω

Rx1+

G0-G7

100pF

Rx2+

Rx2Rx3+

Graphics

PLL

Controller

51Ω

B0-B7

51Ω 100pF

51Ω 51Ω

Rx3Host

R0-R7 G0-G7

51Ω

Rx1-

B0-B7

RxOUT

100pF

Rx0-

TxIN

100pF

51Ω

CLK+

51Ω 100pF

CLK-

51Ω

PLL

LVDS Transmitter

LVDS Receiver

THC63LVDM83A

THC63LVDF84A

DCLK Timing Controller

(LVDF83A) R0~R7

: Pixel R Data ,

G0~G7

: Pixel G Data ,

B0~B7

: Pixel B Data

: Data enable signal

Note (1) The system must have the transmitter to drive the module. Note (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is used differentially.

5.5 LVDS INTERFACE

SIGNAL

TRANSMITTER

INTERFACE

RECEIVER

TFT CONTROL

THC63LVDM83A

CONNECTOR

THC63LVDF84A

INPUT

SELLVDS SELLVDS

INPUT

Host

TFT-LCD

OUTPUT

TxIN0

TxIN1

TxIN2

SELLVDS SELLVDS =L

Rx OUT0

Rx OUT1

Rx OUT2

TxIN3

Rx OUT3

TxIN4

Rx OUT4

TxIN6

Rx OUT6

TxIN7

Rx OUT7

TxIN8

Rx OUT8

TxIN9

Rx OUT9

TxIN12

Rx OUT12

TxIN13

Rx OUT13

TxIN14

Rx OUT14

TxIN15

Rx OUT15

TxIN18

Rx OUT18

TxIN19

Rx OUT19

bit

TxIN20

Rx OUT20

TxIN21

Rx OUT21

TxIN22

Rx OUT22

TxIN26

Rx OUT26

TxIN27

Rx OUT27

TxIN5

Rx OUT5

TxIN10

Rx OUT10

TxIN11

Rx OUT11

TxIN16

Rx OUT16

TxIN17

Rx OUT17

RSVD 1

TxIN23

Rx OUT23

RSVD 2

TxIN24

Rx OUT24

RSVD 3

TxIN25

Rx OUT25

DCLK

RxCLK OUT

TA OUT0+

TA OUT0-

TA OUT1+

TA OUT1-

TA OUT2+

TA OUT2-

TA OUT3+

TA OUT3-

Rx 0+

Rx 0-

Rx 1+

Rx 1-

Rx 2+

Rx 2-

Rx 3+

Rx 3-

TxCLK IN TxCLK OUT+ RxCLK IN+ TxCLK OUT- RxCLK IN-

R0~R7: Pixel R Data (7; MSB, 0; LSB) G0~G7: Pixel G Data (7; MSB, 0; LSB) B0~B7: Pixel B Data (7; MSB, 0; LSB) DE: Data enable signal Notes(1) RSVD(reserved)pins on the transmitter shall be “H” or “L”. 17

DCLK

5.6 COLOR DATA INPUT ASSIGNMENT The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the color. The higher the binary input, the brighter the color. The table below provides the assignment of color versus data input. Data Signal Color

Red

Green

Blue

R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0

Black

0 0 0 0 0

0 0

0 0 0

Red

1 0 0 0 0

0 0

0 0 0

Green

0 1 1 1 1

0 0

0 0 0

Basic Blue

0 0 0 0 0

1 1

1 1 1

Colors Cyan

0 1 1 1 1

1 1

1 1 1

Magenta

1 0 0 0 0

1 1

1 1 1

Yellow

1 1 1 1 1

0 0

0 0 0

White

1 1 1 1 1

1 1

1 1 1

Red(0) / Dark

0 0 0 0 0

0 0

0 0 0

Red(1)

1 0 0 0 0

0 0

0 0 0

Red(2)

0 0 0 0 0

0 0

0 0 0

Red(253)

1 0 0 0 0

0 0

0 0 0

Red(254)

0 0 0 0 0

0 0

0 0 0

Red(255)

1 0 0 0 0

0 0

0 0 0

Green(0) / Dark 0

0 0 0 0 0

0 0

0 0 0

Green(1)

0 0 0 0 0

0 0

0 0 0

Green(2)

0 0 0 0 0

0 0

0 0 0

Green(253)

0 1 1 1 1

0 0

0 0 0

Green(254)

0 1 1 1 1

0 0

0 0 0

Green(255)

0 1 1 1 1

0 0

0 0 0

Blue(0) / Dark

0 0 0 0 0

0 0

0 0 0

Blue(1)

0 0 0 0 0

0 0

0 0 1

Blue(2)

0 0 0 0 0

0 0

0 1 0

Blue(253)

0 0 0 0 0

1 1

1 0 1

Blue(254)

0 0 0 0 0

1 1

1 1 0

Blue(255)

0 0 0 0 0

1 1

1 1 1

Gray Scale Of Red

Gray Scale Of Green

Gray Scale Of Blue

Note (1) 0: Low Level Voltage, 1: High Level Voltage

6. INTERFACE TIMING 6.1 INPUT SIGNAL TIMING SPECIFICATIONS The input signal timing specifications are shown as the following table and timing diagram. Signal

Item Frequency Input cycle to

LVDS Receiver Clock

Symbol 1/Tc

Min. 60

Typ. 86

Max. 88

Unit MHZ

Trcl

200

cycle jitter Setup Time Hold Time

Note

Tlvsu 600 ps Tlvhd 600 ps Fr5 47 50 53 Hz (2) Frame Rate 57 60 63 Hz Fr6 Vertical Active Display Term Total Tv 770 795 888 Th Tv=Tvd+Tvb Display Tvd 768 768 768 Th Blank Tvb 2 27 120 Th Total Th 1436 1798 1936 Tc Th=Thd+Thb Horizontal Active Display Term Display Thd 1366 1366 1366 Tc Blank Thb 70 432 570 Tc Note (1) Since this module is operated in DE only mode, Hsync and Vsync input signals should be set to LVDS Receiver Data

low logic level. Otherwise, this module would operate abnormally. (2) Please refer to 5.1 for detail information.

INPUT SIGNAL TIMING DIAGRAM

Tv Tvd

Tvb

DE Th

DCLK Tc DE

Thd

Thb

DATA

Valid display data (1366 clocks)

LVDS RECEIVER INTERFACE TIMING DIAGRAM Tc

RXCLK+/RXn+/Tlvsu Tlvhd

1T 14

3T 14

5T 14

7T 14

9T 14

11T 14

13T 14

6.2 POWER ON/OFF SEQUENCE To prevent a latch-up or DC operation of LCD module, the power on/off sequence should be as the diagram below.

0.9 VCC

Power Supply VCC 0V

0.9 VCC 0.1Vcc

0.1VCC

0≦T1≦10ms

0≦T2≦50ms 0≦T3≦50ms 500ms ≦T4

VALID

Signals 0V

Power Off

Power On

50%

Backlight (Recommended) 500ms≦T5 100ms≦T6

50%

Power ON/OFF Sequence

Note (1) The supply voltage of the external system for the module input should follow the definition of Vcc. Note (2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD operation or the LCD turns off before the backlight turns off, the display may momentarily become abnormal screen. Note (3) In case of Vcc is in off level, please keep the level of input signals on the low or high impedance. Note (4) T4 should be measured after the module has been fully discharged between power off and on period. Note (5) Interface signal shall not be kept at high impedance when the power is on.

7. OPTICAL CHARACTERISTICS 7.1 TEST CONDITIONS Item Ambient Temperature Ambient Humidity Supply Voltage Input Signal Lamp Current Oscillating Frequency (Inverter)

Symbol Value Unit o Ta C 25±2 Ha %RH 50±10 VCC 5.0 V According to typical value in "3. ELECTRICAL CHARACTERISTICS" IL mA 4.7 ± 0.5 FW KHz 56 ± 3

7.2 OPTICAL SPECIFICATIONS The relative measurement methods of optical characteristics are shown in 7.2. The following items should be measured under the test conditions described in 7.1 and stable environment shown in Note (6). Item Contrast Ratio Response Time Center Luminance of White White Variation Cross Talk Red Color Chromaticity

Green Blue White Color Gamut

Viewing Angle

Horizontal Vertical

Symbol CR Gray to gray average LC δW CT Rx Ry Gx Gy Bx By Wx Wy CG θx+ θxθY+ θY-

Condition

Min.

Typ. (1000)

Unit -

Note (2)

(8)

(3)

(550)

cd/m2 % -

(4) (7) (5)

θx=0°, θY =0° Viewing Normal Angle

CR≥20

(0.652) (0.331) (0.275) (0.597) (0.143) (0.063) (0.285) (0.293) (75) (88) (88) (88) (88)

Max.

(1.3) (4)

(6)

Target

NTSC

Deg.

(1)

Note (1) Definition of Viewing Angle (θx, θy): Viewing angles are measured by EZ-Contrast 160R (Eldim) Normal θx = θy = 0º θyx-

θX- = 90º

θx−

6 o’clock θy- = 90º

θy+ y+ θx+

12 o’clock direction θy+ = 90º

θX+ = 90º

Note (2) Definition of Contrast Ratio (CR): The contrast ratio can be calculated by the following expression. Contrast Ratio (CR) = L255 / L0 L255: Luminance of gray level 255 L 0: Luminance of gray level 0 CR = CR (5) CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note (7). Note (3) Definition of Gray to Gray Switching Time :

100% 90%

Optical Response 10% 0%

Gray to gray switching time

Time

The driving signal means the signal of gray level 0, 63, 127, 191, 255. Gray to gray average time means the average switching time of gray level 0 ,63,127,191,255 to each other . 23

Note (4) Definition of Luminance of White (LC, LAVE): Measure the luminance of gray level 255 at center point and 5 points LC = L (5) LAVE = [L (1)+ L (2)+ L (3)+ L (4)+ L (5)] / 5 L (x) is corresponding to the luminance of the point X at the figure in Note (7). Note (5) Definition of Cross Talk (CT): CT = | YB â&#x20AC;&#x201C; YA | / YA Ă&#x2014; 100 (%) Where: YA = Luminance of measured location without gray level 0 pattern (cd/m2) YB = Luminance of measured location with gray level 0 pattern (cd/m2) (0, 0)

Active Area

(0, 0)

YA, U (D/2,W/8)

Active Area YB, U (D/2,W/8)

(D/4,W/4) YA, L (D/8,W/2)

Gray 128

YA, R (7D/8,W/2)

YB, L (D/8,W/2)

Gray Gray0 0

YB, R (7D/8,W/2) (3D/4,3W/4)

YA, D (D/2,7W/8)

YB, D (D/2,7W/8)

Gray 128

(D,W)

Note (6) Measurement Setup: The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature change during measuring. In order to stabilize the luminance, the measurement should be executed after lighting Backlight for 1 hour in a windless room.

LCD Module LCD Panel Center of the Screen

Display Color Analyzer (Minolta CA210)

Light Shield Room (Ambient Luminance < 2 lux)

Note (7) Definition of White Variation (Î´W): Measure the luminance of gray level 255 at 5 points Î´W = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]

Horizontal Line D

Vertical Line

D/4

W/4

D/2

3D/4

W/2

: Test Point X=1 to 5

3W/4

Active Area

8. DEFINITION OF LABELS 8.1 CMO MODULE LABEL The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.

CHI

MEI

OPTOELECTRONICS

V270B1

-L01 Rev. XX

E207943 MADE IN TAIWAN

XXXXXXXYMDLNNNN

(a) Model Name: V270B1-L01 (b) Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc. (c) Serial ID: X X X X X X X Y M D L N N N N Serial No. Product Line Year, Month, Date CMO Internal Use CMO Internal Use Revision CMO Internal Use Serial ID includes the information as below: (a) Manufactured Date: Year: 1~9, for 2001~2009 Month: 1~9, A~C, for Jan. ~ Dec. Day: 1~9, A~Y, for 1st to 31st, exclude I ,O, and U. (b) Revision Code: Cover all the change (c) Serial No.: Manufacturing sequence of product (d) Product Line: 1 -> Line1, 2 -> Line 2, …etc.

9. PACKAGING 9.1 PACKING SPECIFICATIONS (1) 4 LCD TV modules / 1 Box (2) Box dimensions : 742(L) X 327 (W) X 510 (H) (3) Weight : approximately 19Kg ( 4 modules per box)

9.2 PACKING METHOD Figures 9-1 and 9-2 are the packing method

LCD TV Module

Carton dimensions: 742(L)x327(W)x510(H)mm Weight : Approx 19Kg(4modules per carton)

Anti-Static Bag

PE Foam(Bottom)

Drier

Carton Label

Carton

Figure.9-1 packing method

Corner Protector:L1020*50mm*50mm Pallet:L1100*W1100*H135mm Corrugated Fiberboard:L1100*W1100mm Pallet Stack:L1100*W1100*H1160mm Gross:168kg PE Sheet Carton Label Film

PP Belt

Figure. 9-2 packing method

10. PRECAUTIONS 10.1 ASSEMBLY AND HANDLING PRECAUTIONS (1) Do not apply rough force such as bending or twisting to the module during assembly. (2) It is recommended to assemble or to install a module into the user’s system in clean working areas. The dust and oil may cause electrical short or worsen the polarizer. (3) Do not apply pressure or impulse to the module to prevent the damage of LCD panel and backlight. (4) Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the damage and latch-up of the CMOS LSI chips. (5) Do not plug in or pull out the I/F connector while the module is in operation. (6) Do not disassemble the module. (7) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and easily scratched. (8) Moisture can easily penetrate into LCD module and may cause the damage during operation. (9) High temperature or humidity may deteriorate the performance of LCD module. Please store LCD modules in the specified storage conditions. (10) When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the response time will become slow, and the starting voltage of CCFL will be higher than that of room temperature.

10.2 SAFETY PRECAUTIONS (1) The startup voltage of a backlight is over 1000 Volts. It may cause an electrical shock while assembling with the inverter. Do not disassemble the module or insert anything into the backlight unit. (2) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case of contact with hands, skin or clothes, it has to be washed away thoroughly with soap. (3) After the module’s end of life, it is not harmful in case of normal operation and storage.

CHI MEI

奇美電子股份有限公司

11. MECHANICAL CHARACTERISTICS

31 CHI MEI

奇美電子股份有限公司

SPARE PART LIST LC27HAB CUSXM1-A01 Item Component 一, ELECT PART 1 E1301-041090 2 E1501-001001 3 E1501-001004 4 E2509-094001 5 E2701-023002 6 E3101-171001 7 E3204-023001 8 E3403-001001 9 E3403-004001 10 E3403-005001 11 E3421-229007 12 E3421-925029 13 E3421-925030 14 E3421-925031 15 E3421-925032 16 E3421-925033 17 E3421-925034 18 E3421-925035 19 E3421-925036 20 E3421-925037 21 E3421-925038 22 E3421-925039 23 E3421-925040 24 E3421-941001 25 E3451-000406 26 E3451-000407 27 E3731-052020 28 E4101-027001 29 E4102-044001 30 E4801-123001 31 E6203-024001 32 E7802-004001 33 E7802-004002 34 E7802-004003 二, MECH PART 1 200-26LA21-04AV 2 202-26LA11-01AV 3 206-26LA01-01PV 4 230-26LA11-02RV 5 269-290803-01S 6 269-290804-01L 7 277-26LA01-01S 8 361-101261-01

AKAI

MICO

USA

LCT2715(FULL PIP)

Description/Country Origin

Unit

Quantity

CAPACITOR EC V A SAII 100M 16DC T05 RESISTOR CBF H 1/6W 100J T52 RESISTOR CBF H 1/6W 103J T52 DIODE LED A D3.0 GR/RD (LT036 DETECTOR IR AT138A PLUG V HX2007(PH)-12A P2.0 12P WHT SOCKET AC HF-301 FOR 26LA TUBE SHRINKABLE D30.0 BLK 600V TUBE SUMITUBE D5.0 BLK 600V TUBE SHRINKABLE D20.0 BLK WIRE ASSY 1H3.96-2KN3 0N2 L400 CJ WIRE ASSY PH2.0-12Y/12Y L=550MM KEY WIRE ASSY PH2.0-8Y/8Y 5V/12V L=220 WIRE ASSY PH2.0-5Y/5Y L=250MM 5VSB WIRE ASSY PH2.0-4Y/4Y L=450MM AMP2 WIRE ASSY PH2.0-12Y/12Y L=250MM IN WIRE ASSY PH2.0-10Y/10Y L=250MM INV WIRE ASSY PH2.0-4Y/4Y L=100MM AUDI WIRE ASSY PH2.0-12Y/12Y L=280MM TU WIRE ASSY TTJC3-2Y L=450MM SPK-R WIRE ASSY TJC3-2Y L=850MM SPK-L WIRE ASSY LVDS L=300MM 30P/30P WIRE ASSY TJC3-6Y/6Y L=350MM POWER WIRE ASSY 1KN5-2TKN0 45 L110 BJ WIRE WD 1672#20 RED L=250MM WIRE WD 1672#20 BLACK L=250MM PCB KEY V0 124.5X20.5MM W 1.6MM 2 LA SWITCH POW MR-22-N2BB-F2 ROCKET SWITCH TACT H 6*6*5W SPEAKER 8 OHM 10W D2.5X4" YDT711 (SG DISPLAY LCD 27" V270W1-L03 PCB ASSY MAIN BOARD FOR 27" LCD MICO PCB ASSY POWER200 BOARD FOR 27" LCD PCB ASSY TUNER AMP BOARD FOR 27" LCD

PCS PCS PCS PCS PCS PCS PCS M M M PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS SET SET SET

1 1 7 1 1 1 1 0.04 0.105 0.03 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7 2 1 1 1 1

CABINET FRONT AKAI BLK LCT2715 (MICO BACK CABINET 26LA A (470+70%) THE BACK COVER SPEAKER 26LA P (470 STAND COVER 26LA BLK LCT2715 R POWER LENS (D) 2908 SENSOR LENS (D) 2908 FUNCTION KNOB 26LA CABLE TIE

PCS PCS PCS PCS PCS PCS PCS PCS

1 1 2 1 1 1 1 5

9 370-42D101-01 10 379-972501-01Y 11 379-972502-01Y 12 388-L27AB01-01H 13 389-26LA01-07H 14 389-26LA02-01H 15 389-27LA01-01H 16 423-27LA07-01 17 423-27LA08-01 18 423-27LA09-01 19 426-27LA11-01 20 428-27LA11-01 21 436-27LA01-01 22 449-27LA01-01 23 481-27LA01-01 24 481-27LA02-01 25 486-M32111-01 26 521-100105-01 27 521-150105-01 28 563-11929 579-LC2701-03 30 579-LC2702-03 31 580-L26ABHM-TU01 32 590-LC2701-03 33 590-LC2701-04 34 601-305008-00 35 601-305010-00 36 602-305004-10 37 602-305008-10 38 604-305022-00 39 604-508022-00 1 610-300210-10 2 614-300108-10 3 614-400412-10 4 614-400420-10 5 615-400414-10 6 802-005005-20 三, PACKING 1 300-27AB01-02C 2 300-27AB02-02C 3 310-111404-07V 4 310-453510-07V 5 510-27LA02-03K 7 E3404-157001 8 E7301-010002 9 E7501-051004

RUBBER FOOT 20X20X7.0MM 42D1 SPECIAL RUBBER PARTS SPK 9725 SPECIAL RUBBER PARTS 9725 POWER PLATE AKAI LC26HAB H PVC PLATE AKAI FOR TERMINAL SHEET LC OTHER PVC PLATE 26LA PVC SHEET FOR BACK CABINET GATE STAND SUPPORT PLATE SPCC 27LA METAL PLATE FOR STAND SUPPORT PLATE METAL PLATE FOR WALL BRACKET 27LA SUPPORT BRACKET FOR POWER JACK 27LA MAIN METAL PLATE FOR PANEL 27LA BACK TERMINAL SHEET 27LA METAL PLATE FOR STAND BASE SHIELD COVER FOR MAIN PCB 27LA TINPL SHIELD COVER FOR POWER PCB 27LA TINP NAME PLATE M AKAI FELT PAPER 100X10X0.5 FELT PAPER 150X10X0.5 SERIAL NO. LABEL UPC LABEL (50X23)MM OF UNIT LCT2715( UPC LABEL OF G/B LCT2715 MICO) L IB E FOR AKAI LC26HAB CMO MICO USA INSERTION CARD AKAI LC26HAB WARRANTY CARD AKAI LCT2715 216X279MM MACH.SCREW CTS 3X8 BZN + MACH.SCREW CTS 3X10 BZN + MACH. SCREW PAN-WASHER M3X4 NIP +H MACH.SCREW WHR 3X8 NIP + MACH. SCREW BINDING M3X22MM B ZNP +H MACH. SCREW BINDING M5X22MM B ZNP +H TS RBD3X10 A NIP +H S-TAP SCREW BID 3.0X8 S-TAP.SCREW BID 4X12 D NIP + S-TAP.SCREW BID 4X20 T NIP + S-TAP.SCREW BWH 4X14 T NIP + TAPE 2S T4000 5X50M

PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS PCS RLS

4 8 8 1 1 2 1 1 1 2 1 1 1 1 1 1 1 10 25 1 1 2 1 1 1 3 5 30 12 2 8 11 4 40 8 8 0.0198

POLYFOAM TOP 27AB POLYFOAM BOTTOM 27AB POLYBAG 11"X14"X0.04 BAG LAMIFILM GIFT BOX AKAI LCT2715 (MICO) K AC CORD UL 1.88M MET-4D7+SJT 16AWG/ BATTERY AAA R03P1.5V <2> REMOTE CRTL FOR 27" USA LCT2716

PCS PCS PCS PCS PCS PCS PCS SET

1 1 1 1 1 1 2 1

If you forget your V-Chip Password - Omnipotence V-Chip Password: 8205. - Press MENU button. - Press LEFT RIGHT buttons to highlight "MISC" Menu. - Press Up, Down buttons to highlight "Parentald". - Press ENTER button to pop up "Input your Password Please". - Use the Number buttons (0~9) to enter an omnipotence Password. - Press ENTER button to confirm and your can select "CHANGE PASSWORD". - Suggest: Change to your familiar Password again.

Software upgrade - Connect the RS-232C input jack to an external control device (such as a computer) and software upgrade.

Type of connector; D-Sub 9-pin male No. 1 2 3 4 5 6 7 8 9

Pin name No connection RXD (Receive data) TXD (Transmit data) DTR (DTE side ready) GND DSR (DCE side ready) RTS (Ready to send) CTS (Clear to send) No Connection

9 6

RS-232C configurations 3-wire configuration (Not standard)

7-wire configuration (Standard RS-232C cable)

RXD TXD GND DTR DSR RTS CTS

PDP

2 3 5 4 6 7 8

2 3 5 6 4 8 7

D-Sub 9

TXD RXD GND DSR DTR CTS RTS

RXD TXD GND DTR DSR RTS CTS

PDP

2 3 5 4 6 7 8

D-Sub 9

TXD RXD GND DTR DSR RTS CTS

Software upgrade Process - Power Switch OFF. - Connect the serial port of the control device to the RS-232 jack on the LCD-TV back panel. RS-232C connection cables are not supplied with the LCD-TV. - Power Switch ON. The power indicator on the front of the panel should now display red, means that the LCD-TV is in standby mode. - Copy the software (MTKTOOL) to the computer. - Open the software (MTKTOOL.EXE) - Select MTK 8205 and Point "browse" on the interface of the MTKTOOL.exe. - Select the file which will be update. - Point "update" on the interface of the MTKTOOL.exe. - Waiting for the upgrader programing, when it is finished, the bar will display 100%. - After the upgrader is finished, shut down the power switch, take out the RS-232C connection after the power indicator is extinguished.

Note: After upgrading, the first time of power on will be some long.