Lab 6: Introduction to LogicSimulation and Verilog
Objectives:
The purpose of this lab is to learn the basic functionality of circuit building and simulation using verilog code. We learned the basics of coding in verilog using the same concepts learned in lab 5.
Design:
1. Include the source code with comments for all modules you simulated. You do not have to include test bench code.
Results:
2. Include screenshots of all waveforms captured during simulation in addition to the test bench console output for each test bench simulation.
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https://www.solvedcollegepapers.com/product/ecen-248-sequential-logic
