Technical Insight
Towards a Domain-Centralized Automotive E/E Architecture JYOTSANA SINGH & SREEJA KS
Tata Elxsi
T
he automotive industry is gradually moving away from a traditional E/E architecture consisting of several ECUs over a multi-bus gateway to a centralized high-performance computer with a zone-based architecture to accomplish a software-defined vehicle concept. Heterogeneous technologies running on hardware with high-end computing power, software features partitioned across different execution environments, overthe-air update, communication to backendsystems, service-oriented architecture, high-speed Ethernet interfaces with AVB/ TSN support, etc. are key technologies for transitioning to the future. This necessitates the development of sophisticated, flexible, and scalable platform solutions for ECUs in vehicles. A domain controller platform can be designed considering requirements for moving towards a cross-domain controller platform, thus fulfilling the ECU consolidation concept.
Challenges that lie ahead & Current Trends Legacy E/E architectures are getting more and more complex when it comes to bringing in new vehicle functions. ECUs will reach their tipping point in due course for resources, and it calls for hardware and software level changes to meet the performance KPIs and future application needs. Numerous hardware-level changes necessitate platform migration, including increased performance of the uC/SoC and other components in terms of memory, power consumption, the number of parallel processing cores available, compliance with functional safety standards, the availability of hardware accelerators such as powerful GPUs, and high-speed communication interfaces such as CAN FD, Ethernet or
14 | Telematics Wire | February 2022
PCIe. hardware architecture, longer the system’s In addition, the semiconductor vendor processing time and thus the more latency has no explicit roadmap agreement, the system exhibits. This interferes with the resulting in hardware dependencies. real-time requirements. ECU consolidation Compliance with cybersecurity standards, eliminates, to some extent, timing such as availability of HSM peripheral and performance issues. interfaces such as I2C, SPI, and UART, must The unrestricted access of network also be considered when migrating to a new interfaces to the outside world exposes them platform. At the very least, some of these to various security threats. On one hand, factors must be considered when selecting Ethernet as a backbone increases speed hardware for the new E/E architecture. and introduces quality of service (QoS), To address scalability with newer determinism, time-sensitive networking functions, more H/W resources such as (TSN), and fault-tolerant communication, additional CPU cores, powerful processing thereby mitigating safety and security engines, hardware accelerators, etc., are vulnerabilities. On the other hand, software required. This adds to the overall H/W development cost increases in the functioncomplexity since additional controllers' based ECU approach, and S/W redundancy external ASICs need to be interfaced. cannot be eliminated when functions Such complexities can be resolved by are distributed. Therefore, adopting a moving towards a single multi/many-core structured S/W architecture approach in a SoC-based architecture from multi-chip Centralized system also reduces software solutions. development costs. There are challenges when introducing Possible Future new features and their deployment in the vehicle throughout the vehicle lifecycle Traditionally, in-vehicle architectures when it comes to function-based ECU consist of a single ECU, performing architecture. This has led to a transition a single function. Unfortunately, this towards Service Oriented Architecture. has resulted in current architectures Services can exist in multiple ECUs, other vehicles, and external infrastructure devices. The migration strategy needs to be defined when moving away from functionbased ECUs, such as identifying services and defining service catalog. The more complex the overall Figure 1: Multi-chip to Single-chip Solution
