Testing LVDS devices at the margins with an AWG

Advanced arbitrary waveform generators have simplified the testing associated with communications over low-voltage differential signaling lines.

Chris Loberg | Tektronix

First introduced in 1994, low-voltage differential signaling (LVDS) has gone on to become widely used in products such as LCD panels, automotive infotainment systems, industrial cameras and machine vision, notebook and tablet computers, communications systems, and more. Unlike other 90s-era standards that have come and gone, LVDS continues to thrive in its traditional applications as well as in newer applications that require high-data-rate transmissions including automotive radar and lidar, industrial, Internet of Things (IoT), and high-energy physics applications.

The need for robust signal margin performance rises as a generalpurpose interface like LVDS is applied in these more demanding settings. This testing requires robust signal generation to test and stress LVDS receivers from R&D through to production. In the past, these signals were generated in number of ways, ranging from use of a data-pattern generator to development of custom FPGAs.

Those methods have become outdated with the introduction of arbitrary waveform generators (AWG) which have the channel counts and data rates needed to thoroughly test LVDS protocol and receiver margins. LVDS applications often require a large number of outputs, with over five differential pairs being the norm.

To meet these requirements, the latest AWGs feature highresolution DACs and up to eight analog channels and 32 digital channels in the same box. Multiple units can be synchronized for even higher channel counts. Given the growth in application areas for LVDS, the data signals involved are progressively becoming more complex, just as the use-cases become more varied. The availability of pattern generation software for AWGs simplifies signal creation for a large number of channels. Using this software, or by importing CSV or text files generated from an external tool, designers can quickly and flexibly create the signals they need to determine how well a device is working.

LVDS basics

LVDS is a differential signaling system defined under ANSI/TIA/ EIA-644 that transmits information as the difference between the voltages on a twisted pair of wires. The two wire voltages are compared at the receiver. In a typical implementation, the transmitter injects a constant current of 3.5 mA into the wires, with the direction of current determining the digital logic level.

As long as there is tight electric- and magnetic-field coupling between the two wires, LVDS reduces EMI output and susceptibility, making it suitable for challenging automotive and industrial applications. This noise reduction arises because of the current flow in the two wires creating equal and opposite electromagnetic fields that tend to cancel each other. The tightly coupled transmission wires also reduce susceptibility to electromagnetic noise interference because the noise is common mode. An LVDS receiver is unaffected by commonmode noise because it senses the differential voltage – changes in common mode voltage doesn’t affect reception. LVDS transmitters also consume a constant current, placing less demand on supply decoupling and reducing or eliminating phenomena such as ground bounce.

The low common-mode voltage of about 1.2 V permits the use of LVDS in a wide range of integrated circuits with power supply voltages down to 2.5 V or lower. The low differential voltage, about 350 mV, enables LVDS to consume little power compared to other signaling technologies. At a 2.5 V supply voltage, the power to drive 3.5 mA becomes 8.75 mW, compared to the 90 mW dissipated by the load resistor for an RS-422 signal.

For a thorough evaluation of an LVDS receiver, there are a number of jobs that must take place before a design can move into production. Here is a rundown on what typically takes place testing an LVDS receiver, such as a flatpanel display system:

Protocol-level testing:

Validate functionality with a known-good signal. Test how protocol defects affect the receiver performance.

Digital receiver margin testing:

Inter-channel skew margin performance. Jitter and SSC margin performance. Data-rate margin performance. Amplitude margin performance. Offset margin performance. Duty cycle margin performance. Analog receiver margin testing. Characterize receiver performance across a wide range of analog pulses.

In addition, an AWG-based test set up is useful for performing environmental margin testing on an ASIC or other device that incorporates LVDS. In this case, the AWG generates a known-clean signal that is sent to the device under test (DUT) sitting in a temperature chamber. The impact of temperature variations is then evaluated using an oscilloscope.

For testing applications that involve large numbers of channels, pattern generation software makes it possible to use both analog and digital outputs for as many as 40 channels on a single AWG. This is accomplished by assigning bit sequences to both analog and digital outputs.

For complex test requirements, pattern generation tools make it possible to create digital pattern waveforms with a variety of custom-defined impairments and distortions.

In the case of imported text files with predefined bit patterns, these patterns can be edited and modified within the tool after importing. Periodic and sinusoidal jitter with different amplitudes, frequencies and phases can be added to a base pattern, and skew can be applied between both analog and digital channels. And for LVDS applications, both inter-channel and intra-channel skew can be applied, and LVDS pairs can be created from a single bit pattern by copying and inverting bits.

After importing a data sequence, the pattern generation tool allows for receiver margin testing. Before compiling the waveform, users first select the desired data-rates for margin testing. By selecting a low and high data rate, and by specifying the step increment, the software creates a sequence of waveforms that run the digital pattern through a stepped range of data rates.

Alternatively, margin testing with skew, jitter, amplitude, and offset adjustments can be realized with individual signal parameter selections. It’s also possible to adjust the amplitude, as well as add skew and periodic jitter. Offset can be adjusted in the AWG after signals are assigned to a given output.

Push the limits

Despite the emergence of wireless and fiber optic transmissions, plenty of data transmissions still go through good old-fashioned copper using LVDS signaling. With its combination of high performance, low power consumption and immunity to EMI, LVDS continues to serve in wide range of high-performance applications.

True margin and stress testing of LVDS devices involves the use of complex waveforms such as bio signals for medical applications, automotive test bus signal simulations and telecommunications network testing as well as the need to add a range of impairments. The recent availability of high-channel count AWGs coupled with pattern generation software significantly simplifies the task of thoroughly testing LVDS devices.

Tektronix AWG5200 | https://www.tek.com/arbitrary-waveform-generator/awg5200

Both analog and digital channels are being used to stimulate an LVDS video display device.