YILDIRIM BEYAZIT UNIVERSITY EE 205 – DIGITAL DESIGN LABORATORY MANUAL – 6 – FLIP-FLOP & COUNTER & CLOCK DIVIDER Laboratory Exercise: 1. Design and implement an 8-bit counter. To describe the circuit structurally in Verilog, you can use the adder and flip-flop modules you implemented previously. Actually, it is a lot easier to code it behaviorally. To describe any sequential circuit, we can use the similar always block as the one we used to describe a D flipflop. To implement the counter behaviorally, there are three statements we need to make:
When will the always block be triggered? The output of the counter will be updated at the rising edge of the clock (functionality of FF) or the rising edge of the reset signal (asynchronous reset). How does output react when reset is asserted? The output of the counter will be reset to '0' when reset is asserted. How does output react when the rising edge of clock arrives? The output is updated to the output of the adder, which is the output of the counter before the rising edge arrives, plus 1.
After you finish your modules, test them on a board. 2. Open your clock divider module that you have formed in the prelab work. Now write a UCF file that maps clk to the global clock on board, rst to a push button, and led to an on-board LED. Check if your module works correctly. For example, if your board has a 100 MHz clock, you should see that the LED blinks once every 1.45 seconds. 3. Design and implement a clock divider with a counter and a comparator. You should use this clock divider to implement a signal of exactly 1 Hz frequency. First, you will need to calculate the constant. As an example, if the input clock frequency of your board is 100 MHz and you want your clk_div to be 1 Hz, it should take 100000000 clock cycles before clk_div goes to '1' and returns to '0'. In another words, it takes 50000000 clock cycles for clk_div to flip its value. So the constant you need to choose here is 50000000. To implement your circuit these are the steps you need to follow: Create a Verilog module for clock divider. Define the constant as a local parameter. Describe the counter in an always block. Describe the flip-flop together with the comparator. 4. Now that you have a counter that increases by 1 when the clock rising edge arrives and a clock divider that can provide a clock signal that is exactly 1 Hz, write a wrapper module. In the 1
YILDIRIM BEYAZIT UNIVERSITY wrapper, you should use the output of this clock divider to provide the clock signal for the 8-bit counter you designed in Question 1. Thus, you will get a counter that increases every second. After you finish your modules, test them on a board. Tie the outputs of the counter to the LEDs.
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