YILDIRIM BEYAZIT UNIVERSITY EE 205 – DIGITAL DESIGN PRELIMINARY WORK – 2 – Modular Implementation of Complex Logic Circuits Background Knowledge: This week you will learn how to construct a complex logic diagram with interconnected modules, each representing specific gates. In order to do so you will first break down the diagram into simple single gates and write Verilog modules for them. Then you will call and connect these in a main module. For this week you are responsible for preliminary work. You are supposed to answer Question #) marked sections and prepare them in a report format. You will upload your reports into moodle. These should be individual reports(i.e. everyone in the groups should prepare and submit them). Question 1) is on page2 and Question 2) is on page3.
Modular Design Tutorial: There is an example of modular implementation of logic circuits is given below. Follow the steps and construct your own modular system sketched in Figure1. Find the truth table of the block diagram shown in Figure 1.
Figure 1
First of all, you should write codes that represent gates for each one of them. For AND gate an example is given below.
b Figure 2 1/7
YILDIRIM BEYAZIT UNIVERSITY The code shown in Figure2 is written as behavioral model. Outputs for this model are defined as reg types since they are used inside always blocks. Part of the always block after @ symbol, in parenthesis, is called sensitivity list. The statements inside an always block will be executed by the simulator only when one or more of the signals in the sensitivity list, (a,b) in our case, changes value. When you assign a value to a register, you should use “<=” item instead of “=”.
Question 1) Write behavioral codes for the other gates; OR and NOT inside the same project Add behavioral codes to your report. Write also testbench codes and simulate them for every possible case in their respective truth tables. Add timing diagrams, i.e. simulation results, and testbench codes to your reports.
Open a new module on the Hierarchy panel and name it topmodule. This module will be the main module to call and connect other gate modules; AND, NOT and OR. o To set this new module as the top-module right click on it in Hierarchy panel and click on Set as Top Module.
Figure 3 Verilog code of the topmodule for the block diagram in Figure 1 is given below.
Figure 4a 2/7
YILDIRIM BEYAZIT UNIVERSITY In the red box, two variables e and g are defined to connect the gates to each other. For example, e is not only the output of AND gate but also input for OR gate. Both of the variables should be set as wire type.
Figure 4b In the green box, and gate module is called in topmodule. To do this; o o o
First, write the name of module that is invoked, like “andgate”. Second, give a name to this module as you desire, like “AND” At the end of the line write inputs and outputs in parenthesis for the invoked module, like “(a,b,e)” in the order they are written in the called module.
Question 2) Write a testbench for the code shown in Figure 4a. Run the simulation for the given input values a, b, c on Table1 and check if the output waveform is correct. Add timing diagram and testbench code to your report. a
B
c
1 0 0 1 1
0 1 0 0 1
0 0 0 1 1
Time(n s) #50 #20 #30 #50 #100
Table1
To be able to send verilog codes to Basys2 FPGA board, you should download Digilent Adept program to your computer. This program is an interface to provide connection between the computer and FPGA board. Follow the instructions in the pdf file “Setup of Digilent” that is given in moodle.
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YILDIRIM BEYAZIT UNIVERSITY Generating Implementation Constraints Files To send the code to Basys2 board, you should create an “.ucf” file that indicates where the inputs and outputs of our design are going to be on the board. To do this;
Right click on Hierarchy panel and select New Source.
Figure5
On the new source wizard window (Figure5) select Implementation Constraints File and give it any name then click Next. After that ***.ucf file should be generated on the Hierarchy panel as seen in Figure6.
Figure6
Write the codes in Figure7 to your ***.ucf files.
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Figure7 -
Statement in the Red box means that input “a” is connected to the switch located on “N3” pin on the board. “b” and “c” are also design inputs of the topmodule that are connected to other switches. “fout” is design output connecting to an LED on the board. Do not forget to save the file.
Selecting topmodule from Hierarchy panel, double click on Synthesize-XST, Implement Design and Generate Programming File, respectively. (Wait until each operation done. When it is completed, you will see a green tick icon on the left of them.)
Figure8 After all these steps the ***.bit file should be generated inside the project file.
Programming the BASYS2 board 5/7
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Open the Digilent Adept by double-clicking onto the icon (shown in Figure9) that is created on desktop after you installed the program.
Figure 9
Window shown below should be opened.
Figure10
Plug the USB cable both your computer BASYS2 Board. After plugging, be sure that power switch is ON in board. When you do this, Red LED should be ON state. Then click the pop-up menu on Figure10 and change “no devices connected” part to Basys2. The new window in Figure11 is opened. Click the Browse… button to select ***.bit file that is generated in previous section. 6/7
YILDIRIM BEYAZIT UNIVERSITY
Figure11
Your ***.bit file is ready to install in FPGA chip on BASYS2 board. Finally, click on program button and see results on the program. YOU SHOULD INSTALL DIGILENT ADEPT TO YOUR COMPUTERS BEFORE COMING TO LAB SESSION THIS WEEK!!!!!!! FAILURE TO DO SO WILL RESULT IN DEDUCTION OF YOUR LAB GRADE
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