ECE 205 Digital Design Fall 2015
Due on Monday 30/11/2014 at 5:00 pm. Please submit it to course assistant Alp GĂźrkaynak. Collaboration / Academic Integrity It is acceptable to discuss with others possible general approaches to problems. It is not acceptable to work together on a detailed solution, to copy a solution, or to give away a solution.
Homework III 1. Construct a logic circuit that combines two 16-to-1 MUXs to form a 32-to-1 MUX. (Hint:
Use an inverter to select the appropriate MUX.) 2. Use an 8-to-1 MUX to implement each of the following functions, assuming that all inputs
and outputs are active high.
3. Repeat Problem 2 but instead use a 4-to-1 MUX to implement each function. To do this use
minimum external logic and the two most significant inputs as the data select variables. 4. a) Configure a 6-to-64 decoder by using only 3-to-8 decoders.
b) Configure a 6-to-64 decoder by using only 4-to-16 and 2-to-4 decoders. 5. Write a Verilog model for 1-to-4 demultiplexer. 6. Write a Verilog model for 3-to-8 decoder. Do the following questions from Digital Design with an Introduction to Verilog By Morris Mano 5th Edition. (page 185 ) 7. Problem 4.21 8. Problem 4.22 9. Problem 4.23 10. Problem 4.24 11. Problem 4.25 12. Problem 4.26 13. Problem 4.28b 14. Problem 4.32 15. Problem 4.33 16. Problem 4.35b 17. Problem 4.38 18. Problem 4.43 19. Problem 4.47 20. Problem 4.56