EE 205 Digital Design Fall 2015
Due on Friday 11/12/2014 at 5:00 pm. Please submit it to course assistant Alp Gurkaynak. Verilog Questions can be submitted from the Moodle until Sunday (13/12/2014) 23:59 pm. Collaboration / Academic Integrity It is acceptable to discuss with others possible general approaches to problems. It is not acceptable to work together on a detailed solution, to copy a solution, or to give away a solution.
Homework IV Note: Active low D-latch: enabled when enable signal low. Disabled when enable signal high. Active high D-latch: enabled when enable signal high. Disabled when enable signal low. 1. Design a positive edge triggered D Flip-Flop using active low D-latches. 2. Design a negative edge triggered D Flip-Flop using active low D-latches. 3. Design a positive edge triggered D Flip-Flop using one active low D-latch and one active high Dlatch. (1st latch is active low; 2nd latch is active high) 4. Design a positive edge triggered D Flip-Flop using one active high D-latch and one active low Dlatch. (1st latch is active high; 2nd latch is active low) 5. Design a negative edge triggered D Flip-Flop using one active low D-latch and one active high Dlatch. (1st latch is active low; 2nd latch is active high) 6. Design a negative edge triggered D Flip-Flop using one active high D-latch and one active low Dlatch. (1st latch is active high; 2nd latch is active low) 7. Design an active high D latch with enable input C using only NOR gates and inverters. 8. Design an active low D latch with enable input C using only NOR gates and inverters. 9. Design an active low D latch with enable input C using only NAND gates and inverters. 10. Given the following S-R latch and S, R timing waveforms, Sketch the outputs Q and QN. Assume that the delay through the NOR gate is 10ns, and that each time division below is 10 ns.
11. Given the following Clock and Data signals. Sketch the corresponding output Q signal a) For positive edge D FF. b) For negative edge D FF.
EE 205 Digital Design Fall 2015
12. Write a Verilog model for a 4 bit positive edge triggered D flip flop (inputs: CLK, D; output: Q). 13. Write a Verilog model for a 4 bit negative edge triggered D flip flop (inputs: CLK, D; output: Q). 14. Write a Verilog model for a 4 bit positive edge triggered D flip flop with an active high reset (inputs: CLK, D, RST; output: Q). 15. Write a Verilog model for a 4 bit negative edge triggered D flip flop with an active low reset (inputs: CLK, D, RST_N; output: Q). 16. Draw the waveform generated by the following verilog statements:
17. Draw the logic diagram for the sequential circuit described in the following.
18. Using an initial statement with begin ‌. end block, write a verilog description of the following waveform.