ECE 205 Digital Design Fall 2015
Due on Thursday 30/12/2015 at 5:00 pm. Please submit it to course assistant Alp Gurkaynak. Collaboration / Academic Integrity: It is acceptable to discuss with others possible general approaches to problems. It is not acceptable to work together on a detailed solution, to copy a solution, or to give away a solution.
Homework V 1.
Write a Verilog model for the following state machine, which uses positive edge triggered D FFs.
2. A sequential circuit with two D FFs A and B, two inputs x and y, and one output z is specified by the following next-state and output equations.
a) Draw the logic diagram of the circuit. b) List the state table for the sequential circuit. c) Draw the corresponding state diagram. 3. In this problem you are supposed to develop a state diagram for a “101” sequence detector. This sequence detector will examine a string of 0’s and 1’s applied to the input x and generate an output z=1 only when the input sequence ends in 101. The input x can change only between positive clock active edges. The detector can be designed as either a Mealy FSM or a Moore FSM. If the sequence detector is designed as a Mealy FSM, the output z=1 coincides with the last 1 in “101”. If it is designed as a Moore FSM, the output z=1 coincides with the clock edge during the last 1 in “101”, typically behind the Mealy output. A typical input sequence and the corresponding output sequence are x=011101001010100 Mealy z = 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 Moore z = 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 a) Design a Mealy finite state machine that will detect “101” b) Design a Moore finite state machine that will detect “101” 4. Write separate Verilog models for Mealy and Moore FSMs in Problem 20. Verify the functionality by applying the typical input sequence. 5. Write a Verilog model for the Mealy Sequence detector (3 consecutive 1’s). Verify functionality by applying a typical input sequence you choose and observe the output waveform in simulation.