ECE 4200
Department of Electrical and Computer Engineering
Advanced Digital Design Lab
University of Colorado at Colorado Springs "Illuminate, Investigate, Innovate"
Spring Semester Dr. Greg Tumbush, greg@tumbush.com
Lab #9: Design Example: Keypad Scanner and Encoder - Part 4 (200 pts) Objective The objective of lab assignments 5 through 9 are to systematically design and implement an FPGA-based keypad scanner. The keypad scanner will utilize a FIFO for data storage and retrieval, a display mux, and the seven-segment displays, slide switches, and LEDs of the Digilent Spartan3 prototyping board. The top level block diagram of the system is shown in Figure 1 and the I/O in Table 1. When a button of the hex keypad is pressed the system must decode the button and store the data in an internal FIFO. The read button will be used to read data from the FIFO and display the data on the seven-segment displays. The mode_toggle input will be used to toggle between display states so that more than eight signals can be presented for view on the LED’s. The LEDs will display the status of the FIFO and other information. The hardware prototype will be verified to operate with the Grayhill 072 hex Keypad. A system partition is shown in Figure 2. As input mode_toggle is depressed output DGrp will toggle between DGrp1, DGrp2, and DGrp3 as denoted in Table 3.
Figure 1: Keypad scanner top level Name clk
Direction input
Width Purpose 50MHz clock
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Lab 9 Version 1.4
ECE 4200
Department of Electrical and Computer Engineering
Advanced Digital Design Lab
University of Colorado at Colorado Springs "Illuminate, Investigate, Innovate"
Spring Semester
reset
input
read mode_toggle Row Col seven_seg seven_seg_0_en seven_seg_1_en seven_seg_2_en seven_seg_3_en DGrp
Asynchronous active high reset input Read from the fifo. input Toggle between LED display states input [3:0] Keypad row output [3:0] Keypad column output [6:0] 7-segment – active low output 7-segment character 0 enable – active low output 7-segment character 1 enable – active low output 7-segment character 2 enable – active low output 7-segment character 3 enable – active low output [7:0] 8 LED’s Table 1: Keypad scanner I/O
Figure 2: Partition of keypad scanner The objectives of this lab assignment are to 1. Synthesize the integrated system developed in Lab 8 2. Implement the synthesized system on the Digilent board Page 2 of 4
Lab 9 Version 1.4
ECE 4200
Department of Electrical and Computer Engineering
Advanced Digital Design Lab
University of Colorado at Colorado Springs "Illuminate, Investigate, Innovate"
Spring Semester
3. Conduct a hardware verification of the working system.
Signal FPGA Pin clk T9 reset L14 read L13 mode_toggle M14 Row[3] D8 on A2 Expansion Connector Row[2] D10 on A2 Expansion Connector Row[1] B4 on A2 Expansion Connector Row[0] B5 on A2 Expansion Connector Col[3] D5 on A2 Expansion Connector Col[2] D6 on A2 Expansion Connector Col[1] E7 on A2 Expansion Connector Col[0] D7 on A2 Expansion Connector seven_seg_0[6] E14 seven_seg_0[5] G13 seven_seg_0[4] N15 seven_seg_0[3] P15 seven_seg_0[2] R16 seven_seg_0[1] F13 seven_seg_0[0] N16 seven_seg_0_en D14 seven_seg_1_en G14 seven_seg_2_en F14 seven_seg_3_en E13 DGrp[7] P11 DGrp[6] P12 DGrp[5] N12 DGrp[4] P13 DGrp[3] N14 DGrp[2] L12 DGrp[1] P14 DGrp[0] K12 Table 2: Mapping of signals to FPGA pins Be sure to assign pull-downs to 4-bit input Row when creating the pin assignments.
Data Group DGrp1 DGrp2
System Debug Info {1â&#x20AC;&#x2122;b0, read_ptr[2:0], 1â&#x20AC;&#x2122;b0, write_ptr[2:0] {<your choice>, empty, full} Page 3 of 4
Lab 9 Version 1.4
ECE 4200
Department of Electrical and Computer Engineering
Advanced Digital Design Lab
University of Colorado at Colorado Springs "Illuminate, Investigate, Innovate"
Spring Semester
DGrp3 {Row, Col} Table 3: LED System Debug info
Deliverables 1. Explanation of any warnings not fixed. 2. How many total registers are in the FPGA? How many did your design use? Is the number of registers utilized appropriate 3. How many total LUTs are in the FPGA? How many did your design use? Is the number of LUTs utilized appropriate? 4. What is the maximum clock frequency that you could run the clock in this design and still meet timing? What logic path in your design limits the maximum clock frequency? (hint, see Synthesis report). 5. What is the maximum combinatorial path delay in your design? What logic path in your design has set this delay? Do you expect this path to have the longest delay? Why? (hint, see Synthesis report) 6. Test plan Grading 1. Demonstration of proper operation of prototype â&#x20AC;&#x201C; 125 pts 2. Lab report â&#x20AC;&#x201C; 75pts
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Lab 9 Version 1.4