א א١٦٧
א
א١٦٧
א
א
W،،אא،א
א א א אא א א א א
אאא،אאאאאא אאאאא
אWאאאאאא K אא
אאאאאאא
א ،א אא
א א א א א א א ،
א،אאאא
אאאאאאא אאאאא אאא،א
Kאא،א
???א?אא
אאאאאאא
Kאאאאאאאא
،א،אאאא Kאאאאא
W א א א א
Kא
אאאא
א١٦٧
א
א
،KKKאאאאא
א،אאאאאא Kאאא
אאאאאאא
א،אא،אאא אאאאאאאא
،אאא אאאאאKאא
،אאאאאא
א،אאא
א אאאאא
אאאאאאאKאאאא
Kאאאאאא
،אאאאאא،אאא Kאא،א
،אאאא،
אא،אאאא Kא
KKKKKK،א
אאא
אא
אא
١
אא
א١٦٧
א
אא
א
אאא
Wאאא Kאאא •
Kאא •
Kאאאאאא• א Kאאאא• א
Kאאאאא •
-١-
אא
א١٦٧
א
אא
א
Introduction١ J١
K א א
א (Binary Number System)אאאאא K(Digital Electronic Circuits) אאאאאא Decimal )אא،אאאא
אאאאKא(Number System Octal )אאאאא
K(Hexadecimal Numbering System) אאא(Number System אאאאא אאאאא
אאאאאKאאאא
אKאאאאא Wאאאא
KאK١
KאאאK٢
KאאאאאאK٣ KאאאאK٤
KאאאאאK٥
א(Digit)אאאא
אאאאא(Symbol)،(Number)
אא א א(0,1,2,3,4, ... , 8,9)،א
אאאאאאאא،אא ،א(123)אאא(14)אאא،א
אאאא(4و1)(14)אאאא
אא(6)(3و2و1)(123) Kא
-٢-
אא
א١٦٧
א
אא
א
Decimal Numbering Systemאאא٢ J١ אאא אאאאאא (10)אאאאK אאא
(10)(10)א K9 8 7 6 5 4 3 2 1 0
א(128)אא(Positional Weight)אא
،א EאFאא(8)א א(2)אא،(8 × 1 = 8) 1אאא
אאאE אאFא E אFאאE1Fאא،(2 × 10 = 20)10
אK(1 × 100 = 100) 100אאא W،אאאאא
(1 × 100) + (2 × 10) + (8 × 1) = 100 + 20 + 8 = 128
אאאE10Fאאא
W100 = 110 אאא
........ 105 104 103
102 101
100
W128א 1
(128)10
2
8
אאאא 102 1 × 102 = 100
101 100 + 2 × 101 + 8 × 100 + 20 + 8
אא10אא(128)אא
Kאאאא(Subscript) -٣-
אא
א١٦٧
א
אא
א
אאאאאאא
W10-1
102
101 100 • 10-1 10-2
10-3 ........
אא (Decimal Point)
Binary Numbering Systemאאא٣ J١ אאאאא (2)(2) (2)אאאאאאא .(0 و1)א ..... 2
4
..... 16
2 8
3
2 4
2
2 2
1
W
0
2 1
Wאאאא
W(11001)אא 24 23 22 21 20 1 1 0 0 1 4 3 = (1 × 2 ) + (1 × 2 ) + (0 × 22) + (0 × 21) + (1 × 20) = 16 + 8 + 0 + 0 + 1 = (25)10
אא،אאאאא
אא(2)אאאאאא K(11001)2אא
Wאאאאא
אא (Binary Digit)א(Bit)א אW(Bit)אא■
אE אFאאאK אאא
א(4-bits)(1001)2א،אא
Kא(7-bits)(1101101)2
-٤-
אא
א١٦٧
א
אא
א
אא W(Number of Binary Combinations)אא■ K(bits)אאאא N = 2n
Wאאא
אאא= NW (bits)א= n
Wאא(2)אא
N = 22 = 4 N = 23 = 8 4
N = 2 = 16
Wאא(3)אא Wאא(4)אא
Kאאאאא
אאאW(Bit)אא■ א(1)(1)20אאאא
22א(2)21אאא
אאאאאאאKא(4) אאא،אאא،אא
אאא(LSB)אא(Least Significant Bit) K(MSB)אא (Most Significant Bit) אאאא
אאא(Bit)אאWEByte) א ■ (0)אאאאא،אאאא
אאאEFאא(1)אא אאאKאאא א K
-٥-
אא
א١٦٧
א
אא
א
(Byte)א
K אאאא
Wאאא
1 byte = 8 bits
Decimal-to-Binary Conversion אאאאא٤ J١ אאאא،אאא
(2)אאאא(Sum of Weights Method) אאא(Repeated Division–by–2 Method) Kאאא
אאאאאא١ J٤ J١
א،214א،א(14)10אא
.(0)א2א אאאK אאאא אא
אא،(MSB)אאאא(LSB)
W
א
14 ÷ 2 = 7 7 ÷2=3 3 ÷2=1 1 ÷2=0
0 1 1 1
1 1 1 0 (MSB)
(LSB)
W
(14)10 = (1110)2
Kא(25)10אאWE١ J١F
Wא
-٦-
אא
א١٦٧
א
אא
א
א 25 ÷ 2 = 12 12 ÷ 2 = 6 6 ÷2=3 3 ÷2=1 1 ÷2=0
1 0 0 1 1
(LSB)
(MSB)
Wא
(25)10 = (11001)2
Kא(87)10אאWE٢ J١F
Wא
א 87 ÷ 2 = 43 43 ÷ 2 = 21 21 ÷ 2 = 10 10 ÷ 2 = 5 5 ÷2=2 2 ÷2=1 1 ÷2=0
1 1 1 0 1 0 1
(LSB)
(MSB)
Wא
(87)10 = (1010111)2
אאאאא٢ J٤ J١
אאאאאאא
אא (Decimal Fractions)אאאK(2)א
K(2)אא
،(2)(0.3125)אאאא(0.3125)אא
א אאא(2)אאא
א(Carried Digits)אאKאאאא(0) אKאאאאאאאא WאK(LSB)אאא(MSB)אא
-٧-
אא
א١٦٧
א
אא
א
א
0.3125 × 2 = 0.625
0
0.625 × 2 = 1.25
1
0.25 × 2 = 0.5
0
0.5
× 2 = 1.00
1 (LSB) 1 0 1 0 (MSB)
א
אאא
אאא
KEא F
Kא(39.25)10אאWE٣ J١F
W(2)אאאאאWא
א 39 ÷ 2 = 19 19 ÷ 2 = 9 9 ÷2=4 4 ÷2=2 2 ÷2=1 1 ÷2=0
1 1 1 0 0 1
(LSB)
(MSB)
Wא
W(2)אאאא
(39)10 = (100111)
0.25 × 2 = 0.5 0.5 × 2 = 1.00
א 0
1
W
(0.25)10 = (0.01)2
Wאאא -٨-
אא
א١٦٧
א
אא
א
(39.25)10 = (100111.01)2
Binary-to-Decimal Conversion אאאאא٥ J١ (2)אאאאאאא
אאאKא 1 و2 و4 و8و16אאאא (1)אא(Bit)אא
Kאאאאאא Wאאא
Kא1101001אאWE٤ J١F
אאאא(1)Wא 26
25
24
23 22
21 20 : א
1
1
0
1
0
0
W
1 : אא
= 1 × 26 + 1 × 2 5 + 0 × 2 4 + 1 × 2 3 + 0 × 2 2 + 0 × 2 1 + 1 × 2 0 = 64 + 32 + 8 + 1 = (105)10
(Bits ) ﺧﺎﻧ ﺎتאאאאאא
אאאאא (Binary Point)אא
אאאאאא(Decimal Point)אא ……24
23
22
21
20 • 2-1
2-2
2-3
2-4…….
W
אא
Kא(0.1011)2אאאWE٥ J١F • 2-1 0• 1
2-2 0
2-3 1
Wא
2-4 1
∴(0.1011)2 = 1 × 2-1 + 1 × 2-3 + 1 × 2-4 = 0.5 + 0.125 + 0.0625 = (0.6875)10
-٩-
אא
א١٦٧
א
אא
א
Binary Arithmetic אאאא٦ J١ אאאאאא KאאאאאKאא
Binary Addition אא١ J٦ J١
אאא،אאאא 0 0 1 1
+ + + +
0 1 0 1
= = = =
0 1 1 0 carry EאF 1 ⇒ = 10
W(Binary Digits)
1 + 1 = אאא،אאאאא
אאאאא(1)אא،(2)10 WאאאאKאאא K011, 110אאאWE٦ J١F
WאאאאWא 1 6 +3 EF 9
4 +3 EF 7
+ 1
1 1 0 0
1 1 0
0 1 1
K011, 100אאאWE٧ J١F 1 0 1
0 1 1
0 1 1
Wא
Binary Subtraction אא٢ J٦ J١ Wאא
Kאאא J١
Kאא J٢
-١٠-
אא
א١٦٧
א
אא
א
אK אא،אא
אאאאאאE אFאא 0–0=0 1–0=1 1–1=0 0–1=1
Wאאאאאא
(1) א (1)א
Wאאא
Kאא •
Wאאאאאאאא• א K(0)א(1)(1)(0)(0)
K(1)א(1)(0)
אFאא(0)(1)א(0)(1) K(0)(1)(1)E
Kאאאאא
K(011)אא(101)אאאWE٨ J١F
(0)א (1)א אא(1)א (1)(10)א
0 1 –0
0
(1)א
1 0
1 א
Wא
0
1 1
1
א
אאאאא٧ J١ One's and Two's Complements of Binary Numbers אKאאאאאאא
K אאאאאאאא
א(1)(0)(0)(1)אא
Wא
-١١-
אא
א١٦٧
א
אא
א
1 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0
אא
אא
Wאאאא
א (1)אK אאWאא Wאאאא 1 +אאZאא
K10110011אאאא Kאא(1)אאא 1 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 + 1 0 1 0 0 1 1 0 1
אא
אא
אא
(1)
אא(LSB)אאאאWאא
אא(0) אאאאאאאאאא
אאאאאא Fא
،E אאאאאא Wאא(10101101)2אא
אא
1 0 1 0 1 1 0 1 0 1 0 1 0 0 1 1
אא
אא
Representation of Signed Numbersאאאא٨ J١ אאאאאאאא
אאאאאא אאא
(1)،א(0)א،אאא
אאאא אאאKא -١٢-
אא
א١٦٧
א
אא
א
אא (Sign Bit)אאאא .(Magnitude) אאW אאאאאא .(2's Complement)אא (1's Complement) אא(Sign-Magnitude) (Sign-Magnitude System) אא١ J٨ J١
אאא(Bit)אא،אאאא
אK אאאאאא
אאאאאא
(+23)אאKאאאאא Wאאא
0 0 0 1 0 1 1 1
א (Sign Bit)
אא
(Magnitude Bits)
W –( ﻓﺈﻧﻨﺎ23)אא 1 0 0 1 0 0 1 1 1 Kא(–23) , (+23)אאא (1's Complement System) אא٢ J٨ J١
אאאאאאאאאא
K אא אאאאאK אא
Wאאא(–23) אא 00010111
1 1 1 0 1 0 0 0
(+23)א
(–23)א
אאאאאאאא
Kא
-١٣-
אא
א١٦٧
א
אא
א
(2's Complement)אא٣ J٨ J١
אאאאא אאא
K אאאאאאKאא
W(+23)אאא(–23)אא 00010111
1 1 1 0 1 0 0 1
(+23)א
(–23)א
Kאאאאאאא Arithmetic Operations with Signed אאאאאא٩ J١ Numbers ، אאאא
אאאאאאאא
אאKE٦ J١Fאא، אאאאאאאא אאאאאאאKאאא
Wא
Kאאאא11111010אא00001110אאאWE٩ J١F
WאWא
14 – (– 6) = 14 + 6 = 20
Wא 00001110 + 00000110 00010100
א(+14)
אא(+6) א(+20)
Wאאאאא אWE١٠ J١F
(00001000)2 – (00000100)2
WאWא
8 – 4 = 8 + (– 4) = 4
W
-١٤-
אא
א١٦٧
א
אא
א
00001000 +11111100 100000100 א
א(+8)
אא(– 4) א(+4)
(Discard carry)
Kאאאאא אWE١١ J١F
(11100111)2 – (00001001)2
WאWא
– 25 – (+9) = – 25 – 9 = – 34 11100111 +11110111 111011110 א
W
א(– 25)
אא(– 9)
–( א34)
(Discard carry)
The Octal Numbering Systemאאא١٠ J١ (8)(8)אאאא אאאאאאE7و6و5و4و3و2و1و0F
אאאאאא،אאא
Kאאאאאאאא
Octal-to-Decimal Conversion אאאא١ J١٠ J١
(8)אאאאאאא
אאאא ،א(……83
82
81
80)
אאאאאK،א(…... 512 64 8 1)
אא(2275)8אאאKאאא W
אא: 83 82 81 80
א א: 2
2
7 5
∴ (2275)8 = (2 × 83) + (2 × 82) + (7 × 81) + (5 × 80) -١٥-
אא
א١٦٧
א
אא
א
= (2 × 512) + (2 × 64) + (7 × 8) + (5 × 1) = 1024 + 128 + 56 + 5 = (1213)10 Decimal–to–Octal Conversion אאאא٢ J١٠ J١
אאאאאא
אאאאאאא،(8)א
K(2)(8)
אאאאאא١ J٢ J١٠ J١
(8)150אאא(150)10אא
.(0)א א(8)אא
K אאאא אא
אאא אאאא {Most Significant Digit} אאאא{Least Significant Digit} (LSD) Wאא(MSD)
א 150 ÷ 8 = 18 18 ÷ 8 = 2 2 ÷8=0
6 2 2
(LSD) (MSD)
Wא
(150)10 = (226)8
Kאא(624)10אאWE١٢ J١F
א 624 ÷ 8 = 78 78 ÷ 8 = 9 9 ÷8=1 1 ÷8=0
0 6 1 1
Wא
(LSD) (MSD)
Wא
(624)10 = (1160)8
אאאאא٢ J٢ J١٠ J١
אאאאאאאא
אא(0.265)אאK(8)אא -١٦-
אא
א١٦٧
א
אא
א
אאא ،(8)0.265אא
אאא(0)אאאא(8)
K אאאא( אCarried Digits)אאKא א(MSD) אא(LSD)אאא
W
اﻟﺤﺎﻣﻞ 0.265 × 8 = 2.12 0.12 × 8 = 0.96 0.96 × 8 = 7.68 0.68 × 8 = 5.44 0.44 × 8 = 3.52 0.52 × 8 = 4.16
2 (MSD) 0 7 5 3 4 (LSD) Wאא(6)אאאאא (0.625)10 = (0.207534)8
Kאא(44.5625)10אאWE١٣ J١F
K(8)אאאאאWא א
44 ÷ 8 = 5 5 ÷8=0
4 5
(LSD) (MSD)
Wא
(44)10 = (54)8
W(8)אאאא
اﻟﺤﺎﻣﻞ 0.5625 × 8 = 4.5 0.5 × 8 = 4.00
4 4
W
(0.5625)10 = (0.44)8
Wאאא
(44.5625)10 = (54.44)8 -١٧-
אא
א١٦٧
א
אא
א
Octal-to-Decimal Conversion
אאאאא٣ J١٠ J١
(8)אאאאאאא
אא אKא 1 و8 و64 و512و4096אא (Digit)אאאא
K אאאאא
Kאא
Kאא(324)8אאWE١٤ J١F
Wא
אא: 82 81 80
אא: 3 2 4
∴ (324)8 = (3 × 82) + (2 × 81) + (4 × 80) = (3 × 64) + (2 × 8) + (4 × 1) = 192 + 16 + 4 = (212)10
אאאאאאאאא
אא (Octal Point) אאא ……84
83
82
81
Wאאאא
80 • 8-1
8-2
8-3
8-4…….
אא
Kאא(567.14)8אאWE١٥ J١F אא: 82 81 80 • 8-1 8-2
אא: 5 6 7 • 1 4
∴ (567.14)8 = (5 × 82) + (6 × 81) + (7 × 80) + (1 × 8-1) + (4 × 8-2) = (5 × 64) + (6 × 8) + (7 × 1) + (1 × 0.125) + (4 × 0.015625) = 320 + 48 + 7 + 0.125 + 0.0625 = (375.1875)10
-١٨-
Wא
אא
א١٦٧
א
אא
א
Octal-to-Binary Conversion אאאאא٤ J١٠ J١
אא (Digit)
אאKאאאאא،(3-bits) KE١ J١F
אא
0
1
2
3
4
5
6
7
אא
000
001
010
011
100
101
110
111
KאאאE١ J١F א
אאא
Kא
Kאא(357)8אאWE١٦ J١F (357)8 =
3 011
5
Wא
7
101 111
= (011101111)2
Kא(1276.543)8אאWE١٧ J١F (1276.543)8 =
1 001
2
7
6 • 5
Wא
4
3
010 111 110 • 101 100 011
= (1010111110.101100011)2
Kאאא
Binary-to-Octal Conversion אאאאא٥ J١٠ J١
אאאאאאאא
J –אאKא
אאאא
אא אאאאאא -١٩-
אא
א١٦٧
א
אא
א
אא
Kאאאא
Kאא(1011001011100.00101)2אאWE١٨ J١F 001 1
011 3
001 1
011 3
100 4
• 001 010 •
Wא
1
2
אאאאא
W
(1011001011100.00101)2 = (13134.12)8 Arithmetic Operations in Octal System אאאא٦ J١٠ J١
Kאאאא
Octal Addition אא١ J٦ J١٠ J١
א(9و0)א–אאאאא
א(10)א(9)אאא،(9)
א אאK אאאאא
אא(10)אא(1و0)אאאא
אKאאאא אאאאאאאאאאא
א(7)אאא–אאא(7) و16 و15 و14 و13 و12و11)אאאאאא،א(10)
( 37 و..... و31و30)אאא( 27 و...... و22و21و20) אאא(17
אאאאאE٢ J١F אKא אאאאאאא
אK אא אאאא
Wאא
-٢٠-
אא
א١٦٧
א
אא
א
אאאאאאא • K(7)
(2)אא(7)אאא •
א(7)א(8)אא(7)אא،א אא(2)א(10)אא אאאאFאאא KEאאא
7 7 10 11 12 13 14 15 16
6 6 7 10 11 12 13 14 15
5 5 6 7 10 11 12 13 14
4 4 5 6 7 10 11 12 13
3 3 4 5 6 7 10 11 12
2 2 3 4 5 6 7 10 11
1 1 2 3 4 5 6 7 10
0 0 1 2 3 4 5 6 7
+ 0 1 2 3 4 5 6 7
KאאאE٢ J١F א
K(42)8، (34)8אאאWE١٩ J١F 34 + 42 76
WאאWא
∴(34)8 + (42)8 = (76)8
(7)E4و3)E2و4Fאא
Kא
-٢١-
אא
א١٦٧
א
אא
א
K(63)8(56)8אאאWE٢٠ J١F
Wא
5 6 + 6 3 1 4 1 א(2)(7)אאא
Kאא(Carry)א
Subtraction in Octal Systemאאא٢ J٦ J١٠ J١
Wאאא
K אאאאא •
אאא–אא(1)אאא •
אאאאאאא(8)
Kאא
(657)8 – (346)8 6 5 7 – 3 4 6 3 1 1
א
Wאא אWE٢١ J١F
WאWא
א
∴(657)8 – (346)8 = (311)8
אאא
K אא
(732)8 – (634)8Wאא אWE٢٢ J١F
Wא
6 2 1 7 3 2 – 6 3 4 0 7 6
א א
∴(732)8 – (634)8 = (76)8 -٢٢-
אא
א١٦٧
א
אא
א
אא(2)(4)אא
א،אאאאאא(1)א Kאא(2)(3)אאא
Hexadecimal Numbering Systemאאאא١١ J١ (16)אאאאא (FوEوDوCوBوAو9و8و7و6و5و4و3و2و1و0) א(16)
KאE 15 و14 و13 و12 و11و10Fאא(FوEوDوCوBوA)א
Hexadecimal–to–Decimal Conversionאאאא١ J١١ J١
16אאאאאאאא
(... 4096 256 16 1 )אאאא(……163 162 161 160) W(522.39)16אאא
אא: 162 161 160 • 16-1 16-2
אא: 5
2
2
• 3
9
∴ (522.39)16 = (5 × 162) + (2 × 161) + (2 × 160) + (3 × 16-1) + (9 × 16-2) = (5 × 256) + (2 × 16) + (2 × 1) + (3 × 0.0625) + (9 × 0.0039062) = 1280 + 32 + 2 + 0.1875 + 0.0351558 = (1314.222655)10
אKא אאאאא
K אא(16)אאא
Decimal-to-Hexadecimal Conversion אאאא٢ J١١ J١
(16)אאאאאאאא
אאאאאאאאאא
.(2)(8)(16)אא
אאאאאאא١ J٢ J١١ J١
(16)97אאא(97)10אא
א א(16)אא
אאאאאK(0) -٢٣-
אא
א١٦٧
א
אא
א
אאא،אאאKאא
Wאא(MSD)אא(LSD)
א 97 ÷ 16 = 6 6 ÷ 16 = 0
1 6
(LSD) (MSD)
Wא
(97)10 = (61)16
Kאאא(314)10אאWE٢٣ J١F
Wא
א
314 ÷ 16 = 19 19 ÷ 16 = 1 1 ÷ 16 = 0
A 3 1
(LSD) (MSD)
Wא
(314)10 = (13A)16
אאאאאא٢ J٢ J١١ J١
אאאאאאא
(0.78125)10אאK(16)אאא
אא(16)אאאאא
(0)אאאאא(16)א אאאאאאKאאאא
(MSD)אאא(LSD)אאאKאא اﻟﺤﺎﻣﻞ 0.78125 × 16 = 12.5 0.5 × 16 = 8.00
Wא
C 8
W
∴(0.78125)10 = (0.C8)16
-٢٤-
אא
א١٦٧
א
אא
א
Kאא(329.52)10אאWE٢٤ J١F
W16אאאאאWא א
329 ÷ 16 = 20 20 ÷ 16 = 1 1 ÷ 16 = 0
9 4 1
(LSD) (MSD)
Wא
∴(329)10 = (149)16
Wאא(16)אא
א 0.52 × 16 = 8.32 0.32 × 16 = 5.12 0.12 × 16 = 1.92 0.92 × 16 = 14.72 0.72 × 16 = 11.52 0.52 × 16 = 8.32
8 (MSD) 5 1 E B 8 (LSD)
Wא(6)אאאאא (0.52)10 = (0.851EB8)16
Wאאא
(329.52)10 = (149.851EB8)16 Hexadecimal-to-Decimal Conversion
אאאא٣ J١١ J١
אאאאאאא
אאאאאK(16)א
WאאKאא Kאא(F9B)16אאאWE٢٥ J١F
Wא
אא: 162 161 160
א: F
9
B -٢٥-
אא
א١٦٧
א
אא
א
∴ (F9B)16 = (F × 162) + (9 × 161) + (B × 160) = (15 × 256) + (9 × 16) + (11 × 1) = 3840 + 144 + 11 = (3995)10
אאאאאאאאאאא
Wאאאאא
……163
162
161
160 • 16-1
16-2
16-3 …….
אא
Kא(A15.C3)16אאאWE٢٦ J١F אא: 162 161 160 • 16-1 16-2
אא: A
1
5 • C
Wא
3
∴ (A15.C3)16 = (A × 162) + (1 × 161) + (5 × 160) + (C × 16-1) + (3 × 16-2) = (10 × 256) + (1 × 16) + (5 × 1) + (12 × 0.0625) + (3 × 0.0039062) = 2560 + 16 + 5 + 0.75 + 0.0117186 = (2581.7617)10
Hexadecimal-to-Binary
אאאאא٤ J١١ J١
Conversion
EFوEوDوCوBوAو9و……و2و1و0Fאאאא
אאאאEFوEوDوCوBوAFאאא
אאאאאKE15و14و13و12و11و10F (4-bits)אאא،אא WE٣ J١Fאא
Kא(3A5)16אWE٢٧ J١F
(3A5)16
=
3 0011
A
5
1010 0101
= (001110100101)2 -٢٦-
Wא
אא
א١٦٧
א
אא
א
אאא
אא
0 1 2 3 4 5 6 7 8 9 A B C D E F
אא
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
KאאאE٣ J١F א
Kאא(B35.D1)16אWE٢٨ J١F (B35.D1)16 =
B
3
5
•
Wא
D
1
1011 0011 0101 • 1101 0001 = (101100110101.11010001)2 Binary-to-Hexadecimal Conversionאאאא א٥ J١١ J١
אאאאאא
אאאאאאא
אאאא
אאאאאאK
אאאא
Kאאאא -٢٧-
אא
א١٦٧
א
אא
א
Kאא(110111101.101001)2אאWE٢٩ J١F
Wא
0001 1011 1101 • 1010 0100 1
B
•
D
A
4
Kאאא
∴(110111101.101001)2 = (1BD.A4)16 Kאאא(11010010011.011001)2אאWE٣٠ J١F
Wא
0001 1010 1011 • 0110 1000 1
A
•
B
6
8
∴(11010010011.011001)2 = (1AB.68)16
Hexadecimal-to-Octal Conversionאאאאא٦ J١١ J١
אאאאאאאאא
אאאאאאא Wאאא
Kאא(AB3E.87D)16אWE٣١ J١F
WאאאאWא
(AB3E.87D)16 = (1010101100111110.100001111101)2
אאאאא
W
001 010 101 001 111 110 • 100 001 111 101 1
2
5
4
7
6
•
4
1
7
5
Kאא -٢٨-
אא
א١٦٧
א
אא
א
∴(AB3E.87D)16 = (125476.4175)8 Octal-to-Hexadecimal Conversionאאאא א٧ J١١ J١
אאאא
א،
،אאאא
Wאאאא
Kאאא(25.342)8אאWE٣٢ J١F ∴(25.342)8 = (010101.011100010)2
WאאWא
Wאאאאא
0001 0101 • 0111 0001 1
2
•
7
1
Kאאאאאא ∴(25.342)8 = (12.71)16
אאאאא٨ J١١ J١
Arithmetic Operations in Hexadecimal System
Kאאאא
Hexadecimal Additionאאאא١ J٨ J١١ J١
(F)אאאאEfو0Fאאאא
אאאאאאא(10)אא،(10) א K אאא אאאא
אאאאאאא
(B)16(9)16אא(A)16א(9)16אא
K(F)16א
-٢٩-
אא
א١٦٧
א
אא
א
אא(10)16א(F)16אא
אאא(11)16א(F)16אאאאא
Kאאאאא
،אאאאE٤ J١Fא
אאאאאאאאאא Kאאאאא
F F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E
E D C B E D C B F E D C 10 F E D 11 10 F E 12 11 10 F 13 12 11 10 14 13 12 11 15 14 13 12 16 15 14 13 17 16 15 14 18 17 16 15 19 18 17 16 1A 19 18 17 1B 1A 19 18 1C 1B 1A 19 1D 1C 1B 1A
A A B C D E F 10 11 12 13 14 15 16 17 18 19
9 9 A B C D E F 10 11 12 13 14 15 16 17 18
8 8 9 A B C D E F 10 11 12 13 14 15 16 17
7 7 8 9 A B C D E F 10 11 12 13 14 15 16
6 6 7 8 9 A B C D E F 10 11 12 13 14 15
5 5 6 7 8 9 A B C D E F 10 11 12 13 14
4 4 5 6 7 8 9 A B C D E F 10 11 12 13
3 3 4 5 6 7 8 9 A B C D E F 10 11 12
2 2 3 4 5 6 7 8 9 A B C D E F 10 11
1 1 2 3 4 5 6 7 8 9 A B C D E F 10
0 0 1 2 3 4 5 6 7 8 9 A B C D E F
+ 0 1 2 3 4 5 6 7 8 9 A B C D E F
KאאאאE٤ J١Fא
WאאWE٣٣ J١F
(35AB2)16 + (1A675)16
Kאאאאא אWא 1 3 + 1 5
1 5 A 0
1 A 6 1
B 7 2
∴(35AB2)16 + (1A675)16 = (50127)16 -٣٠-
2 5 7
אא
א١٦٧
א
אא
א
Hexadecimal Subtractionאאאא٢ J٨ J١١ J١
Wאאאאא
אאאאאאא • Kאאאאא
אאאאא(1)אאא •
אאאאאאאא
Wאא
Wאא אWE٣٤ J١F
(F2ABD)16 – (EF4CE)16
Wא E F – E
1
2 F 3
9 A 4 5
1A B C E
1
D E D
Kאאא
-٣١-
אא
א١٦٧
א
אא
א
a) 64 e) 77.0625
a) 11011 e) 10101.1101
b) 112 f) 47.875
Wאאאאא E١ c) 257 g) 33.125
Wאאאאא E٢
b) 1110101 f) 1100001.11011
d) 1110.11
b) 1110.11 + 11.10 d) 1001.101 + 1101.11
Wאאאאא E٤
a) 1101 – 0100 c) 11010 – 10111
a) 11110110
c) 111111
WאאאאE٣
a) 100 + 111 c) 1111 + 1101
a) 00110101
d) 27.26
b) 1001 – 0111 d) 1100 – 1001
b) 11100100
b) 01011101
WאאאאאאE٥ c) 00010101
Wאאאאאא E٦
c) 00110011
אאאאאאאאאאE٧ a) +28
b) – 83
W(8-bits) אא
c) +99
d) – 120
אאאאאאאאאאE٨ a) +14
b) – 63
W(8-bits) אא
c) +107
d) – 122
-٣٢-
אא
א١٦٧
א
אא
א
KאאאאE٨FאאE٩
WאאאאאאאאאאאE١٠
a) 10111000
b) 01100100
c) 10110011
WאאאאאאאאאאאE١١
a) 10011101
b) 01100110
c) 10101101
WאאאאאאאאאאאE١٢
a) 10101011
b) 000111101
c) 10111011
Wאאאאא אE١٤
a) 00010110 – 00110011 c) 10001100 – 00111001
a) 50 e) 120.515625
a) 42 e) 96.11
a) 72 e) 122.775
Wאאאאאא E١٥
b) 100 f) 144.5625
b) 254 f) 115.3
c) 6391 g) 915.141
d) 77.375
WאאאאאאE١٦
b) 113 f) 417.632
a) 110101.1101 d) 10001001011.1001
a) (15)8 + (17)8 c) (123)8 + (321)8
b) 01110000 – 10101111 d) 11011001 – 11100111
c) 1057 g) 14367.12
d) 37.5
WאאאאאאE١٧ c) 16.3 g) 276.621
d) 37.6
WאאאאאאE١٨
b) 11110100.110101 e) 1010111.11101
c) 110110111.10101
WאאאאE١٩
b) (44)8 + (66)8 d) (272)8 + (456)8 -٣٣-
אא
א١٦٧
א
אא
א
WאאאאE٢٠
a) (32)8 – (25)8 c) (315)8 – (222)8
b) (147)8 – (74)8 d) (437)8 – (340)8
WאאאאאאאE٢١
a) 14 e) 62500
b) 80 f) 204.125
b) D52 f) B3.E
a) 37 e) 1600.524
c) 67F g) 1111.1
d) ABCD h) 888.8
WאאאאאאאאE٢٣
b) 1C
a) 1001.1111 d) 10100111.111011
a) 13A e) 78.D3
d) 3000 h) 631.25
WאאאאאאE٢٢
a) 9F e) F.4
a) 8
c) 560 g) 255.875
c) A64
d) 1F.C
e) 239.4
WאאאאאאאE٢٤ b) 10000.1 e) 1000000.000111
b) 25E6 f) 2659.F41
b) 725 f) 3000.6125
a) (41)16 + (36)16 c) (9B)16 + (65)16 f) (77CB5)16 + (A5F72)16
c) 110101.11001 f) 1111100.1000011
WאאאאאE٢٥
c) 3016
d) B4.C
WאאאאאE٢٦
c) 2476.2
d) 1117.16
WאאאאE٢٧ b) (C8)16 + (3A)16 d) (11D)16 + (2E1)16 g) (13EFD)16 + (21BB3)16
-٣٤-
אאא
אאאא
אאאא
٢
אא
א١٦٧
א
אאאא
א
אאא
Wאאא
Kאאאאא •
Kאאאאא •
Kאאאאאא •
Kאאאאא •
Kאאאא •
Kאאא• א
- ٣٥ -
אא
א١٦٧
א
אאאא
א
Introduction١ J٢ אאאאא אאאאא،אא Jא אאאא،אאאא
Kאאאאאאא،אא ،אאאאא
אאאאאא?אא? Kאא
אאאאאאאא
אK(INVERTER)אNOTאORאANDאא
،אאאאאאאאא
Kאאאאאאא
AND Gate ANDא٢ J٢ אאאאאאאאANDאא אא،א ANDאאK(Logic Functions) אאאא،(Logical Multiplication)א אA, Bא،E١ J٢F אאאא
א(0)(Two Binary Variables)אאא
K(Closed) אא(1)(Open) א
(A) (B)
Voltage Source
(L)
KאאANDאאE١ J٢Fא - ٣٦ -
אא
א١٦٧
א
אאאא
א
(1)אאא"L"א
אאK(OFF)א(0)(ON)א
אאE١ J٢F، א،
(L)אאK א(L)א
K(Truth Table)אאאא، א A
B
L
KE١ J٢F אאE١ J٢F א
א،ANDא(Standard)אאאE٢ J٢Fא
אאE٢ J٢FאK ANDאא،Yא BA KAND
א
A 0 0 1 1
B 0 1 0 1
א Y 0 0 0 1
A B
Y
ANDאאE٢ J٢FאKANDאאE٢ J٢F א
K
א(1)א،(bits)א
،אאANDא ،א(1) BAא K(1)א(1)א
WאאאEאFאא N = 2n
- ٣٧ -
אא
א١٦٧
א
אאאא
א
KאאN W Kאאn
W
N = 2 2 = 4 אאא N = 2 3 = 8 אא
N = 2 4 = 16 אא
WE١ J٢F
KANDאא• א ؟ANDאא •
E٣ J٢F،אאאANDאWא Kאאא
א
א
A B C Y 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 KANDאאE٣ J٢Fא
Wאאא•
N = 2 n = 2 5 = 32
אאאא(Boolean Algebra)אא
אא(Boolean Expression)אא،א
WאANDאאאK
Y = A•B - ٣٨ -
אא
א١٦٧
א
אאאא
א
א،EAND • FA AND BYאWא
Wאא
Y = AB
KA AND BYא
אאא
אK(LOW)א(HIGH)אא(Pulses)
אא،אאANDא Kא
א(1) BAאE٣ J٢F،
Aא،t2אא،(1)א Yאאt1א
אאא،(0)YאBא(0)
אאאאאאK אא
K(Timing Diagram)
A B
t1
Y
t2 t3
t4
t5
t6 t7
A B
Y
KANDאאאE٣ J٢F א OR Gate ORא ٣ J٢ אאK אאאאאאאאORאא
אאא،אOR אאאאאאא ،(Logical Addition) BAאANDאאKE٤ J٢F א(1)(Open) א(0)
K(Closed)
- ٣٩ -
אא
א١٦٧
א
אאאא
א
(A)
(B)
Voltage Source
KאאORאאE٤ J٢Fא
אא،אאאE٤ J٢F
K א(L)אא
A
B
L
KE٤ J٢FאאE٤ J٢Fא
אA, Bא،ORאאאאE٥ J٢Fא
KORאאE٥ J٢FאKY
א
א
A B Y 0 0 0 0 1 1 A Y 1 0 1 B 1 1 1 ORאאE٥ J٢FאKORאאE٥ J٢Fא
K
א (1)אE٥ J٢Fא
א(0)א،(1)א
WאORאאאKא(0) - ٤٠ -
אא
א١٦٧
א
אאאא
א
Y=A+B
K(OR+)A OR BYאWא
،אאORאא
אאאANDא Kא
אt1אא(1) BAא E٦ J٢F
Aא،t2א א،(1)א Yא
אאאא،(1)YאBא(0)
Kא
A
B t1
t2
t3
t4
t5
t6
A B
Y
t7
Y
KORאאאE٦ J٢Fא NOT Gate (INVERTER) EאF NOT א٤ J٢ א(Inversion)אNOTאא
(1)א،אאא K(Complementation) K(1)(0)א،(0)א
אאE٧ J٢FK אא אאNOTאא
KאאאE٦ J٢Fא،אאא
א
A 0 1
א
Y 1 0
A
Y
KאNOTאאE٦ J٢FאKNOTאאE٧ J٢Fא
- ٤١ -
אא
א١٦٧
א
אאאא
א
אא،אאא
Wא
Y= A א barAאnot AYאWאא
KE A FA barYא،א
NAND Gate NAND א٥ J٢ אא،AND(NOT AND)א(NAND) ،E٨ J٢FANDאאאאא
אאANDאאאאאא
KNANDאאE٧ J٢FKאאא
א
א
A B Y 0 0 1 0 1 1 A 1 0 1 Y 1 1 0 B KNANDאאE٧ J٢FאKNANDאאE٨ J٢Fא
אאא(0)אא
(0)אאא (1) א،א(1)
אאאאאאNANDאאKANDאאא،א אאא،א
NANDאא،אא، AND ORNOTא
Wא
Y = AB
،אאNANDאא
K(1)א(0) NANDאא
- ٤٢ -
אא
א١٦٧
א
אאאא
א
אt1אא(1) BAא E٩ J٢F
Aא،t2אא،(0)א Yא
אאא،(1)Yא(1)Bא(0) Kאא
A
A
B
Y
B t1
t2
t3
t4
t5
t6
t7
Y
KNANDאאאE٩ J٢Fא
NOR Gate NOR א٦ J٢ אא،OR(NOT OR)א(NOR) ORאא(NOT gate)אאא
NORאאKNORאאאא،E١٠ J٢F KE٨ J٢F
א
א
A B Y 0 0 1 0 1 0 A 1 0 0 Y B 1 1 0 KNORאאE٨ J٢FאKNORאאE١٠ J٢Fא
אא(0)(Y)אא
אא(1) א،א (1)א
Kא(0)
- ٤٣ -
אא
א١٦٧
א
אאאא
א
אאאאאאNANDאאאNORאא
אK، AND ORNOTא،א
WNORאא
Y= A+B
،אא BAאNORאE١١ J٢F
Kא(Y)אאNORאא
A
A
B
Y
B
t1
t2
t3
t4
t5
Y
KNORאאאE١١ J٢Fא
Exclusive-OR Gate EאF אOR א٧ J٢ ،XOR-gate??אאORאא
KאאאE١٢ J٢F
א
A 0 0 1 1
B 0 1 0 1
א
Y 0 1 1 0
A B
Y
KXORאאE٩ J٢FאKXORאאE١٢ J٢Fא
(Y)אא،(9-2)XORאא ،א(0)א(1)، BAאא(1) Kא(0) - ٤٤ -
אא
א١٦٧
א
אאאא
א
אאאORאאXORאא (1)XORאא ،A = B = 1 ، א אא(1) (1)א Kאאאאאא Wאאאאאא Y = AB + AB
Wאאאא
Y=A⊕B XORאאאאKBA⊕א
אאE١٣ J٢Fאא، NOT ORANDאאאא
KאXORאאא
A B
Y
K NOT ORANDאXORאאE١٣ J٢Fא
אXORאאE١٤ J٢F
אאא،א
Kא
A
A B
B t1
Y
t2
t3
t4
t5
t6 t7
Y
t8
KXORאאאE١٤ J٢Fא
Exclusive-NOR Gate EאF אNOR א٨ J٢ - ٤٥ -
אא
א١٦٧
א
אאאא
א
KאאאE١٥ J٢F،XNOR-gateאNORאא (Y)אא،E١٠ J٢F XNORאא
(0) A = B = 1A = B = 0 BAאא(1)
،א(0)א(1)א
אא، א אא(1) Kאאאא
א
א
A B Y 0 0 1 0 1 0 A 1 0 0 Y B 1 1 1 KXNORאאE١٠ J٢FאKXNORאאE١٥ J٢Fא
Y = AB + A B
Wאאאאאא Wאאאא
Y=A~B XNORאאאאK א~א
אאE١٦ J٢Fא א، NOT ORANDאאאא
KאXNORאאא
A B
Y
KAND, OR, NOTאXNORאאE١٦ J٢Fא
،א BAאXNORאE١٧ J٢F
K(Y)אאXNORאא
- ٤٦ -
A
A B
אא
א١٦٧
א
אאאא
א
Y
KXNORאאאE١٧ J٢Fא
The Boolean Expression for a Logic Circuitאאאא٩ J٢ אא، אאא אאא،Kאאאאא WאאאאאKE١٨ J٢Fא
K AB A, B אאANDאאאK١
K AC A ,C אאANDאאאK٢
K AB + AC AB, AC אאORאאאK٣ Wאאא
Y = AB + AC A B
B A
AB
C
Y
AC
KאאאאE١٨ J٢Fא
KE١٩ J٢FאאאאאאWE٢ J٢F
Wא
A B
A+B B
- ٤٧ -
D( A + B ) Y
אא
א١٦٧
א
אאאא
א
KאאאE٢ J٢FאאאE١٩ J٢Fא Y = D( A + B ) + ( B + C)
Wאאאאא
אאאאאא١٠ J٢ Implementation of a Logic Circuit Using a Boolean Expression אאאא WאאאאKאא
Y = AB(CD + EF)
(CD + EF) BAאאאאא
FE،ANDא C , D (CD + EF) א،ANDא
KORאANDאא ،ANDא Wאא
- ٤٨ -
אא
א١٦٧
א
אאאא
א
AND
NOT OR
Y = A B (CD + EF)
AND
( ؛CD + EF) אא אאא אא ؛CD, EF אאאאא
K אאא، D
W AB(CD + EF) אאאאאא K D אNOTאK١
K CD, EF אANDאK٢
K (CD + EF) אאORאK٣
KYאאANDאK٤
KE٢٠ J٢F אאאאאאא
A B
Y
C D
E F
K AB(CD + EF) אאאאE٢٠ J٢Fא
אאאא١١ J٢ Implementation of a Logic Circuit via a Truth Table אאאאא אאאאא،אא - ٤٩ -
אא
א١٦٧
א
אאאא
א
אאאאא،אאE١٢ J٢FKא WאאאאKאא
אא،Y = 1אאאא K١
،A = 0, B = 1, C = 0אY = 1אא
،(1)אא ABC אא
אאאא(1)א،(0)א K ABC אא
א
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
א C 0 1 0 1 0 1 0 1
Y 0 0 1 0 0 0 1 0
KאאאE١٢ J٢Fא
WORאY = 1אאאאא K٢ Y = AB C + ABC
אאא ABC אאאאא
ABC א אאא،ANDא A, B, C
ORאאאא،ANDא A, B, C אאא KYאאא
אאאאאאא NOTאW
ORא، ABC ، ABC אאANDא ؛A, C א
אאאאאאא، ABC + ABC אאא
KE٢١ J٢F
- ٥٠ -
אא
א١٦٧
א
אאאא
א
A B C
Y
K AB C + AB C אאאאE٢١ J٢Fא
KE١٣ J٢F אאאאאאאWE٣ J٢F
א
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
א C 0 1 0 1 0 1 0 1
Y 0 1 0 1 0 1 0 0
KאאאאאE١٣ J٢Fא
אאאאאאאWא WORאEאאFY = 1
Y = ABC + ABC + ABC KE٢٢ J٢F אאא
A
B C
Y
K A B C + ABC + AB C אאאאE٢٢ J٢Fא - ٥١ -
אא
א١٦٧
א
אאאא
א
אאא١٢ J٢ Converting a Boolean Expression to a Truth Table אאאאאא
،(22 = 4)،אאK(1or 0) Kא،(23 = 8)،אא
אאאא،אא
،אא(Y)א(1)אא
Kאא،אא(0)
WאאאWE٤ J٢F
Y = AB C + ABC + ABC + ABC
א،אאא (C BAF אWא
KE١٤ J٢F אאאאא Wאאאאאא
A B C = 000, AB C = 010, AB C = 110, ABC = 111
،(Y)א(1)אא
K(Y)א(0)אאא
א A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
א C 0 1 0 1 0 1 0 1
Y 1 0 1 0 0 0 1 1
K Y = AB C + AB C + AB C + ABC אאE١٤ J٢Fא - ٥٢ -
אא
א١٦٧
א
אאאא
א
א،BAאאANDאXאאאE١ A
B
K١ J אא
X
١ Jא
א،BAאאORאXאאאE٢ K١ J אא
א،A,BאאNANDאXאאא E٣ K٢ J אא
A
B
X
٢ Jא - ٥٣ -
אא
א١٦٧
א
אאאא
א
אא،A,BאאNORאXאאא E٤ K٣ J אא
A
B
X
٣ Jא
א،BAאאXORאXאאא E٥ K٣ J אא
א،A,BאאXNORאXאאא E٦ K٣ J אא
K٤ JאאאאאE٧ A B C
٤ Jא
- ٥٤ -
Y
אא
א١٦٧
א
אאאא
א
WאאאאאאאאE٨
a) AB + AB c) AB(C + D)
b) AB + AB + ABC d) A + B[C + D(B + C )]
KאאאאאאאE٩
א A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
א C 0 1 0 1 0 1 0 1
Y 0 1 0 1 0 1 0 1
a) (A + B)C c) A(AC + AB)
WאאאאאE١٠
b) (A + B)( B + C) d) A(A + AB)
- ٥٥ -
אאא
אאאאא
אאאאא
٣
אא
א١٦٧
א
אאאאא
א
אאא
Wאאא Kאאאא •
K •
Kאאאאאאא •
K(POS)(SOP)אאא •
Kא(POS)(SOP)אאא •
Kא(POS)(SOP)אא •
Kא(POS)(SOP)אא• א K NOR NANDאאאא •
Kאאאא •
אא
א١٦٧
א
אאאאא
א
Introduction١ J٣ א،אאאאאא
א אKאאאאאאא אKאא،אאא
Kאאא
EאאאFאאאאא
אאא Kאאאא
K(K–map)K –אא (Karnaugh-Map)א Rules of Boolean Algebra אאא٢ J٣ אאאאאאאE١ J٣F Kא
1. 3. 5. 7. 9.
A A A A A
+ 0 =A • 0 =0 + A=A • A=A =A
2. A + 1 = 1 4. A • 1 = A 6. A + A = 1 8. A • A = 0 10. A + AB = A
KאאאאE١ J٣Fא
אאאאאאא
Kא
אאאA + 0 = A :(1)א
אK(0)(1)אא،A،אא(0) אORא
(0)אA=0אKAא(1)אA=1
Kאאא(0)ORאKA
א(1)אORאאאאA + 1 = 1:(2)א
אORאא(1)K(0)א(1)אא،A،א
K אאאאא(1) .(1) אא(1)ORא
אא
א١٦٧
א
אאאאא
א
(0)אANDאאאאA • 0 = 0:(3)א
K אאאאא(0)אא،A،אא
.(0)אא(0)ANDא
(1)אANDאאאאA • 1 = A:(4)א
ANDאאA=0אא،(A)אא،A،אא
אא(1)ANDאאA=1אא،(0)
Kאאא(1)ANDאK(1) ORאאאאA + A = A:(5)א
א،0 + 0 = 0A = 0אאK אאא،Aא K1 + 1 = 1אA = 1א
אAאW א A + A = 1 W(6)א
A=0אK(1)אא אאאא A אOR K1 + 1 = 1 + 0 = 1A = 1אK 0 + 0 = 0 + 1 = 1
אאANDאאAאאA • A = A:(7)א
،1 • 1 = 1אA = 1אא،0 • 0 = 0A = 0אאKא KAאANDאאא
אא A אANDאAא A • A = 0 :(8)א A Aאאא،(0) אאאא
K (0)אאANDא(0)، א(0)
אאK אאאא A = A :(9)א (0)(1)א،(1)A = 0 Kאא
W(4)א(2)אאא:(10)א A + AB = A (1 + B) = A (1) =A
אא
א١٦٧
א
אאאאא
א
Demorgan's Theorems٣ J٣ אאא،אא א אאKORאANDא
Wאא،אאא(bars)
A+B=A•B
A • B = A + B
Wא
Wא
ANDאORאא
ANDאאאאNORאאE١ J٣F Kאאאאאאאא
KE٢ J٣Fאאא
K(negative AND)אANDאאאאאאא
A
A+B
B
AB
A B
KANDORאE١ J٣Fא א
א
A
B
+ B A
• B A
0 0 1 1
0 1 0 1
1 0 0 0
1 0 0 0
KאאE٢ J٣Fא ORאANDאא
אORאאאאNANDאאE٢ J٣F א،EאאאאאאFא
אא
א١٦٧
א
אאאאא
א
ORאאאאאאKE٣ J٣Fאאא
K(negative OR)א
A
AB
B
≡
A
A+B
B
KORANDאE٢ J٣Fא א
א
A
B
• B A
+ B A
0 0 1 1
0 1 0 1
1 1 1 0
1 1 1 0
KאE٣ J٣Fא K אאאא
Kאאאא
WאאאWE١ J٣F
Y = (A + B + C) • (A + B + C )
Wא Y = (A + B + C) • ( A + B + C) = (A + B + C ) + (A + B + C ) = A BC + A BC= AB C+ A BC
Wאא א WE٢ J٣F Y = (A + B) + CD
Wא
אא
א١٦٧
א
אאאאא
א
Y = (A + B) + CD = (A + B).CD = (A.B)(C + D) = A B(C + D)
Wאא א WE٣ J٣F
Y = ( A + BC) + B(A + C )
Wא
Y = ( A + BC) + B(A + C )
) = A(BC) • (B + (A + C ) ) (
= (A + BC) • B(A + C ) = A(B + C )(B + A + C )
אאאאאאא٤ J٣ Simplification of Boolean Expressions Using Boolean algebra Rules E אאאFאאאאאאא
،א،אאא
א،א ، אאא Kאאא
WאאאאאאאאWE٤ J٣F
Y = AB + A(A + C) + B(A + C)
WאאאאאאאWא Y = AB + AA + AC + AB + BC
WאאEאאא7אאFAAAא Y = AB + A + AC + AB + BC
אא
א١٦٧
א
אאאאא
א
Wאא،AB + AB = AB،A + A = A5א Y = AB + A + AC + BC
Wאאאא Aא
Y = A(B + 1 + C) + BC Y = A (1) + BC Y = A + BC
W،A + 1 = 12א W،A(1) = A4אא
Kאאא
אאאאאאאא
אאאאאאאא،א
Kאא
אאאאE٣ J٣F
אאאא،EEFאFאא A B
C
KEEFאFאא
E F
Y
A
Y
B C
EF
KE٤ J٣FאאאE٣ J٣Fא
א، אאאא
Kאאא، C BA
אאאאאאאWE٥ J٣F Y = AB C + ABC + ABC + ABC
Kא
אא
א١٦٧
א
אאאאא
א
W،אאאא،אאאWא
Y = ( AB C + ABC) + ( ABC + ABC)
= AB( C + C) + BC( A + A)
W6א Y = AB • 1 + BC • 1
Wאאא4א
Y = A B + B C
Kאאאא E٤ J٣F
A
B C
E F
A Y
B Y C
EF
KE٥ J٣FאאאE٤ J٣Fא Standard Forms of Boolean Expressions אאאא٥ J٣ ،،א ،אאא ،(SOP)אא(sum-of-products) אאאא
אK(POS)אא(product-of-sums)אאאא
Kאאאאאא
אא
א١٦٧
א
אאאאא
א
The Sum-of-Products (SOP) form (SOP)א١ J٥ J٣
אא אאK(product term)אא
KאK ABCD , AB AB,אאא
אא אא W(Sum-of-Products)
A BC+ABC+ABC
אאאאאאא
אאא،אאאא
א،ANDאאאKאאא
KEANDאאאF(0)(1)
The Product-of-Sums (POS) form (POS)א٢ J٥ J٣
K(sum term)אא،אאאא
KאK A + B + C , A + B אאאא
אא אא ( A + B + C )(A + B + C )(A + B + C)
W(Product-of-Sums)
א אאאאאא
אא،אא אא
،ORאאאKאאאא KEORאאאF(1)(0)א
(POS) אא(SOP)אאא٦ J٣
Converting Standard (SOP) to Standard (POS) א (binary values)אא
אאא،K(POS)אאא(SOP)
، K(POS)אאא(SOP)אא Wאאא،(POS)אא(SOP)אא
אא
א١٦٧
א
אאאאא
א
אאאא،(SOP)אאWאא Kאא
KאאאאאאWאא
אאאא אאWאא K(POS)א
אאא،אאאאא
K(SOP)אא(POS)
Kא(POS)אאא(SOP)אWE٦ J٣F Y = A BC+ A BC+ A BC + A BC
אאאאאאWא
W،(0)אאא،(1)א
Y = 001 + 011 + 100 + 110 +111
K(23)אא ،אאא
א،א(SOP)א
א،000, 010, 101אאא(POS) W
Y = (A + B + C)(A + B + C)(A + B + C )
אאא ،(0)אאא
K(1)
Kא(POS)אאא(SOP)אWE٧ J٣F
Y=A BC+A BC+ABC+ABC Y = 000 + 001 + 101 + 110
010, 011, 100, 111
WאאאWא Wאאא Wאא(POS)אא
Y = (A + B + C)(A + B + C )(A + B + C)(A + B + C )
אא
א١٦٧
א
אאאאא
א
(SOP) אא(POS)אאא٧ J٣
Converting Standard (POS) to Standard (SOP) ،אאאאא،אא
אאאK(SOP)אא(POS)אאא
Kא
Kא(SOP)אאא(POS)אWE٨ J٣F
Y = (A + B + C)(A + B + C )(A + B + C )(A + B + C )(A + B + C)
אאאאאאWא
W،(1)אאא،(0)א
Y = (000)(001)(011)(101)(110) (SOP)א،א (POS)א
Wא،010, 100, 111אאא
Y = ABC + AB C + ABC Kא(SOP)אאא(POS)אWE٩ J٣F Y = (A + B + C)(A + B + C )(A + B + C )(A + B + C )
WאאאWא
Y = (010)(011)(101)(111) Y = 000 001 100 110
Wאאא Wאא(SOP)אא
Y=A BC+A BC+ABC+ABC
אא(SOP)אא٨ J٣
Converting Standard (SOP) Expressions to Truth Table Format א،א(SOP)א
،K אאאא אא
א،(23 = 8)אא
(1)אK(24 = 16)אא
אא(0)،אאאא(Y)א KאאKא
אא
א١٦٧
א
אאאאא
א
Wא(SOP)אאאWE١٠ J٣F
Y = ABC + AB C + ABC
،א אאWא אאאKE٤ J٣Fאאאא ABC ⇒ 001
AB C ⇒ 100
ABC ⇒ 111
Wאא
،א(Y)א(1)،אא
Kא(0)אאא
א A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
א C 0 1 0 1 0 1 0 1
Y 0 1 0 0 1 0 0 1
KE١٠ J٣FאE٤ J٣Fא Wא(SOP)אאאWE١١ J٣F Y = ABC + ABC + ABC + ABC WאאאאאWא
ABC ⇒ 010
ABC ⇒ 011
ABC ⇒ 101
ABC ⇒ 110
(Y)א(1)،אא
Kא(0)אאא،E٥ J٣Fא
אא
א١٦٧
א
אאאאא
א
א A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
א C 0 1 0 1 0 1 0 1
Y 0 0 1 1 0 1 1 0
KE١١ J٣FאE٥ J٣Fא אא(POS)אא٩ J٣
Converting Standard (POS) Expressions to Truth Table Format אא،אא،
אא אאא،א(POS) Kאא
Wא(POS)אאאWE١٢ J٣F
Y = (A + B + C)(A + B + C)(A + B + C)
،אאאאWא
אאאKE٦ J٣Fאאאא
Wא(POS)א
A + B + C ⇒ 000
A + B + C ⇒ 010
A + B + C ⇒ 100
،א(Y)א(0)،אא
Kא(1)אאא
אא
א١٦٧
א
אאאאא
א
א A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
א C 0 1 0 1 0 1 0 1
Y 0 1 0 1 0 1 1 1
KE١٢ J٣FאE٥ J٣Fא Wא(POS)אאאWE١٣ J٣F
Y = (A + B + C )(A + B + C )(A + B + C)(A + B + C )
WאאאאאאWא
A + B + C ⇒ 001 , A + B + C ⇒ 011 , A + B + C ⇒ 110 , A + B + C ⇒ 111
(Y)א(0)،אא
Kא(1)אאא،E٦ J٣Fא
א A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
א C 0 1 0 1 0 1 0 1
Y 0 1 1 0 1 1 0 0
KE١٣ J٣FאE٦ J٣Fא
אא
א١٦٧
א
אאאאא
א
אאאאא١٠ J٣
Determining Standard Expressions from a Truth Table אא،אא(SOP)אא
א(1)א،אאאK(1)
0101אא،Kאא(0)، W
0101 ⇒ ABC D
אא،אא(POS)אא
א(0)א،אאאK(0)
1010אא،K אא(1)، W
1010 ⇒ A + B + C + D
W(POS)،(SOP)אאא،E٧ J٣FאWE١٤ J٣F
א A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
א C 0 1 0 1 0 1 0 1
Y 0 0 0 1 1 0 1 1
KE١٤ J٣FאE٧ J٣Fא K011, 100, 110, and 111W אאאא1'sW א 011⇒ ABC
Wאא
100 ⇒ AB C
110 ⇒ ABC
111⇒ ABC
אא
א١٦٧
א
אאאאא
א
W(Y)(SOP)אא
Y = ABC + AB C + ABC + ABC
אK and 101 010 001000אא(0)א،(POS)
Wא
000 ⇒ A + B + C 001 ⇒ A + B + C 010 ⇒ A + B + C 101 ⇒ A + B + C
W(Y)(POS)אא
Y = (A + B + C)(A + B + C )(A + B + C)(A + B + C )
NOR وNANDאאאא١١ J٣
The Universal Property of NAND and NOR Gates א،ANDאאאאאאאא
אNORאNANDאאאKאא،OR
אאאK (Universal Gates)
KNOR،ANDאאאNANDא، NORאאאNORא
KNANDORANDאאא
NANDאא١ J١١ J٣ NAND gate as a Universal Logic Element ،AND،אאאאNANDאא
NANDאאאKNOR،OR
K אNANDאEEF٥ J٣F אאא
KEEF٥ J٣F NANDאאAND
אא
א١٦٧
א
אאאאא
א
NOR אאאKEEF٥ J٣FNANDא אORאא KEEF٥ J٣F
A
A
≡
A
A
E F
A
AB
B
AB = AB
≡
A
AB
B
EF
A
A
A .B = A + B
B
B
≡
A
A+B
B
E F A B
A B
A .B = A + B
A+B
≡
A B
A+B
EF
KNANDאאאE٥ J٣Fא NOR Gate as a Universal Logic Element NORאא٢ J١١ J٣
،ORAND، אאאNOR אא،NAND א
NOTאNORאאE٦ J٣FKNANDא
KNANDאORא
אא
א١٦٧
א
אאאאא
א
A
A
≡
A
A
E F
A+B A
A+B = A+B
B
≡
A
A+B
B
EF
A
A
A + B = A.B
B B
≡
A
AB
B
EF A
A
A + B = A.B
B B
AB
≡
A B
AB
EF
KNORאאאE٦ J٣Fא NOR , NANDאאאאאאא١٢ J٣ Design of Combinational Logic Circuits using NAND and NOR Gates
אא
א١٦٧
א
אאאאא
א
אאNORא،NANDאאא
،(Negative - OR)אORאאNANDאאאאא
אK(Negative - AND)אANDאאNORאא
Kא (Logic diagram) אאאאAND،ORא NAND LogicNANDאאא١ J١٢ J٣
א،אOR אNAND אNANDא،
Wא
A • B = A + B Negative-OR
NAND
KE٧ J٣Fאאאאא
A
AB
B
Y = AB + CD
C D
CD
KNANDאאאאאE٧ J٣Fא
Wאאאאאא(Y)אא Y = (AB)(CD)
Wא Y = AB + CD
W(bars)אאא Y = AB + CD
ANDא ،AB+CD ،(Y)אא
אNANDאא(Y)אאא.ORא
KORאאNANDאANDאE٧ J٣F
אא
א١٦٧
א
אאאאא
א
NANDאאאאEEF٨ J٣Fא(Y)אא
אאK אOR אא
אאE٧ J٣Fאא،EEF٨ J٣Fא
Wא،EEF٨ J٣F
(NAND-NAND-NAND)(AND-AND-OR) A B
≡
Y = AB + CD
C D
A
AB
E F
CD
B
Y = AB + CD
C
EF
D
.(٧-٣) ﺗﻜﺎﻓﺊ اﻟﺪاﺋﺮة ﻓﻲ ﺷﻜﻞAND-AND-OR ( إﺛﺒﺎت أن٨-٣) اﻟﺸﻜﻞ אאאNANDאאאאE٩ J٣F Kא JORאאא
A
AB
B C
ABC
D
Y
DE
E
F
DE F
Kא JORאאאאא אE٩ J٣Fא
WE٩ J٣Fא(Y)א
Y = [(AB)C] • [(DE)F] = [(A + B)C] • [( D + E )F] = ( A + B )C + ( D + E ) F ∴ Y = ( A + B )C + ( D + E ) F
א אא NANDא א א JOR א א
Kאאא(Y)א،E١٠ J٣F
אא
א١٦٧
א
אאאאא
א
A
A+B
B
( A + B )C
C
Y = ( A + B )C + ( D + E )F
D
D+E
E ( D + E )F
F
Kא JORאאE٩ J٣F אא אE١٠ J٣Fא
WNANDא אאאWE١٥ J٣F
(a ) Y = ABC + DE
(b) Y = ABC + D + E
KE١١ J٣FאאWא
B
ABC
C D E
A
A
DE
B Y = ABC + DE
C
E F
D E
ABC
Y = ABC + D + E
EF
KE١٥ J٣Fאאא אE١١ J٣F א
NOR Logic NORאאא٢ J١٢ J٣
א JANDאNORאNORאא
Wא
A + B = A • B NOR
Negative-AND
KE١٢ J٣Fאאאא
אא
א١٦٧
א
אאאאא
א
A
A+B
B
(A + B) (C + D)
C D
C+D
NORאאאאאE١٢ J٣Fא
Wאאאאא Y = (A + B) + (C + D)
Wא
Y = (A + B) • (C + D)
Wאאא
Y = (A + B) • (C + D)
א،ANDאORא(A + B)(C + D)א
ANDאאאאORאאאא
אאאEEF١٣ J٣F אאאKEEF١٣ J٣F
Kא JAND
A
A
A+B
B
(A + B) (C + D)
C D
C+D
E F
≡
B C
A+B
(A + B) (C + D)
D
EF
Kא JANDאאE١٢ J٣FאאאE١٣ J٣Fא
אאא،NORאאא אE١٤ J٣F
Wא(Y)א Kא JANDאא
אא
א١٦٧
א
אאאאא
א
Y = [(A + B) + C] + [(D + E) + F]
= [ AB + C] + [ D E + F] = ( AB + C)( D E + F) A+B
A B
( A + B) + C
C
Y
D+E
D
E ( D + E) + F
F
KNORאאאאE١٤ J٣Fא
KE١٥ J٣FאאNORאאא JANDאא
A
AB
B
E F
A B + C
C D
DE
Y = ( A B + C) (D E + F)
DE + F
KE١٤ J٣FאאאאE١٥ J٣Fא
אא
א١٦٧
א
אאאאא
א
WNORאאאאאWE١٦ J٣F Y = A B C + (D + E)
A B C D E
KE١٦ J٣FאאWא
A+B+C=A BC
Y = A B C + (D + E)
KNORאאאאאE١٦ J٣Fא Karnaugh Map١٣ J٣ אא،אאאK- אKאא
אאאאאאא
אא א،אאא KKאאא
אאא
،אKא
אא ،(cells)א (array)
אאאאKא Kא
،אאאא
K אא،א
אאאא אאא
אאאאא
אאאאא (Quine - McClusky) אאאKא
אא
א١٦٧
א
אאאאא
א
אאK אא،
K 2 4 = 16 אא 2 3 = 8 א١ J١٣ J٣
Karnaugh Map for Two, Three, and Four Variables
KEאFאאא
( A, B )א(A وB)א،E١٧ J٣F KE11100100FEאF
A
B
Y
0
0
AB
0
1
AB
1
0
1
1
AB AB
B
B
A
AB
AB
A
AB
AB
KאE١٧ J٣Fא K אאא אאא
E١٨ J٣Fא(Input Labels)א
אאא،Kאא ،אא A
אא B אאKאאAא אאאא،KאאאBא،א
K AB א
B
B
A
A
KE22 = 4FE١٨ J٣Fא
אא
א١٦٧
א
אאאאא
א
،E FאEEF١٩ J٣F،EEF١٩ J٣F
KEFא
CD
CD
CD
AB BC
BC
BC
B C
CD
AB
A
AB
A
E F
AB
EF
KאE١٩ J٣Fא Karnaugh Map (SOP) Minimization
(SOP)אא٢ J١٣ J٣
،א
א،K(SOP)אאא KEEF٢٠ J٣Fאא
،אאאאאא
(SOP)אאאא(1)אא
KEEF٢٠ J٣F
אאKEEF٢٠ J٣F אאא אאאא
KEEF٢٠ J٣Fאאא
אא
א(1)אK אאאא
(0)א(0)א،אא(1)
K אא אא(1)
אא
א١٦٧
א
אאאאא
א
אאKEABFאאא،E A B Fא
Kאא(0)،א(0)( AB, A B )
A A B B
א
א Y
A
B
Y
0
0
0
0
1
0
1
0
1
AB
1
1
1
AB
Y=AB+AB
EF
EF
E F B
B
A
0
0
A
A
1
1
A
B
B
0
0
1
1
A A B B Y=A
A
EFEFEF KאאאאE٢٠ J٣Fא אאאא
אאאK A + A = 1 א،EComplements)
Kאאאאא،EEF٢٠ J٣F אאEEF٢٠ J٣F א
א אKא(adjacent cells)
אאאK א،א
אאאEEF٢٠ J٣Fא(1)
אא
א١٦٧
א
אאאאא
א
B B AB, A B אאאKאאא WA،א،א
EאאאF Y = A B + AB Y = A(B + B) = A •1 = A
EEF٢٠ J٣Fאאאאאאא
אאאK(A)א(Y)אא
KEEF٢٠ J٣F
EEF٢١ J٣FאאאWE١٧ J٣F Kא
،אאא،אWא KEEF٢١ J٣F
EEF٢١ J٣F א(1)אאאא
אאא אא،אאא(0)KEEF٢١ J٣F
אאאאאא،EEF٢١ J٣F
אEאאF A , A אאאK K A B א C , C אאא، BC א
אאאאאאאאא
אאאאKEF٢١ J٣،א אORאאANDא
אאא،١٦אאאא
אאא،ORאANDא
KEEF٢١ J٣Fא٦אא
אא
א١٦٧
א
אאאאא
א
א A 0 0 0 0 1 1 1 1
B C 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 E F
א Y 0 0 1 0 1 1 1 0
BC
A A B B C C
BC
A
Y
BC
BC 1
A 1 1 1
Y = AB + B C A B BC EF EF
KאאאאE٢١ J٣Fא
EאFא(1's)א
،אE٢٢ J٣FK2 אא،، אאKאאאא
אאאאאE1'sFאא
אאאא Kא
אאFאא،א א،אא، KEאאא
אא
א١٦٧
א
אאאאא
א
AB
C D CD
CD
CD
AC
CD
CD
AB
1
1
1
1
AB
1
0
AB
1
0
0
1
AB
1
0
AD
AB
1
1
1
0
AB
1
AB C
AB
0
1
1
0
AB
1
AD Y = A B C D + A B C D + A B CD + A B C D + AB C D + ABC D + AB C D + AB C D + ABCD + A B C D + A B CD Y = AB C + AD + AB D + A B
E F
AB
1
AB
1
1
1
1
CD
AB
1
0
AB
1
1
1
1
Y = AC + B C + D
EאF
EF
0
1
1
1
EאF
EאF
B
C D CD
CD
CD
AB
0
1
0
0
AB
1
1
0
1
AB
1
1
0
1
1
1
1
1
AB
BD
EאF
CD
AB
Y = A B C D + ABC D + ABC D + ABCD
+ AB C D + ABCD + A B CD + ABCD Y = B+D
1
EF
Y = A B C D + A B C D + A B CD + A B C D + A B C D + A B C D + AB C D + A B C D
1
+ A B C D + A B CD + A B C D
D 1
0
1
+ ABCD + ABC D + AB C D + ABC D
1
0
1
Y = A B C D + A B CD + A B C D + AB C D
EאF EאF
C D C D CD
CD
BC
D
CD
+ ABC D + ABC D + ABCD + AB C D + AB C D + ABCD + ABCD EאF Y = C D + AB + B D
EאF
EF
KאאE٢٢ J٣Fא
אא
א١٦٧
א
אאאאא
א
אאא(SOP)אאאאאW١٨ J٣
Kא،E٨ J٣F
א A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
א D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Y 0 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1
KE١٨ J٣FאאאאE٨ J٣Fא אאאאWא (Y)אאא Wאאאא،(1)אא
Y = A BCD + A BCD + ABCD + ABCD + A BCD + ABCD
،E٢٣ J٣Fאאא
Kאאא(Y)אאא
אא
א١٦٧
א
אאאאא
א
AD
CD
CD
CD
CD
AB
0
1
1
0
AB
0
1
1
0
AB
0
0
1
0
AB
0
0
1
0
CD
KE١٨ J٣FאE٢٣ J٣Fא
אE٢٣ J٣F
אאאא K(1's)א
K AD א C א C א B א B א אאא
WאאאK CD א A A B B אא
Y = AD + CD Karnaugh Map (POS) Minimization
(POS)אא٣ J١٣ J٣
א،(SOP)אאא א
K(POS)אאא
אאא(POS)אאאאאW١٩ J٣
Kא،E٩ J٣F
אאאאWא אא،(POS)
(POS)א،(0)אא(Y)אא
Wאא
אא
א١٦٧
א
אאאאא
א
Y = (A + B + C + D)(A + B + C + D )(A + B + C + D)(A + B + C + D ) (A + B + C + D )(A + B + C + D)(A + B + C + D)
א A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
א D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Y 0 1 0 1 0 0 1 0 0 1 1 1 0 1 1 1
KE١٩ J٣FאאאאE٩ J٣Fא
،E٢٤ J٣F אאא
Kאאא(Y)אאא א E٢٤ J٣F
K א א ،(0's) א ، B א B א א א א א א אKA+C א D א D א
KC+Dא A A B B אא א ، A + B + D א، C אCאא
W(POS)אאא
Y = (C + D)(A + C)(A + B + D )
אא
א١٦٧
א
אאאאא
א
A + C AB
CD
CD
CD
CD
0
0
1
1
AB
0
0
0
1
AB
0
1
1
1
AB
0
1
C+D
1
A+B+D
1
KE١٩ J٣FאE٢٤ J٣Fא
אא
א١٦٧
א
אאאאא
א
WאאאE١ b) AB(CD + EF)
a) AB(C + D ) c) (A + B + C + D ) + ABCD
d) (A + B + C + D) (AB C D)
Wאאאאאאאא E٢
a) F = AB + A(B + C) + B(B + C) b) F = [AB(C + BD) + AB]CD
c) F = A B C + A B C + A B C + A B C d) F = A B + A C + A B C :( اﻟﻘﻴﺎﺳﻴﺔPOS) ( اﻵﺗﻴﺔ إﻟﻰ اﻟﺘﻌﺒﻴﺮاتSOP) ﺣﻮل اﻟﺘﻌﺒﻴﺮات اﻟﻘﻴﺎﺳﻴﺔE٣ a) F = A B C + A B C + A B C + A B C b) F = A B C + A B C + A B C + A B C c) F = A B C + A B C + A B C + A B C + A B C
Wא(SOP)אאא(POS)אאאE٤ a) F = (A + B + C)(A + B + C )( A + B + C )( A + B + C) b) F = (A + B + C)(A + B + C)(A + B + C )(A + B + C) c) F = (A + B + C )(A + B + C)( A + B + C )( A + B + C)( A + B + C )
Wא(SOP)אאאאE٥ a) F = A B C + A B C + A B C + A B C + A B C b) F = A B C + A B C + A B C + A B C c) F = A B C + A B C + A B C + A B C + A B C
אא
א١٦٧
א
אאאאא
א
Wא(POS)אאאאE٦ a) F = (A + B + C)(A + B + C)(A + B + C )(A + B + C) b) F = (A + B + C )(A + B + C)(A + B + C )(A + B + C) c) F = (A + B + C)(A + B + C)(A + B + C )(A + B + C)(A + B + C )
Wאא (POS),(SOP) אאאאE٧
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
F 1 1 0 0 1 0 1 0
WNANDא אאאא E٨ a) ABCD + DE b) ABC + AB + D c) AB C + D + E d) ABC + ABC + ABC + ABC WNORא אאאאE٩ a) (A + B + C) (A + B) b) ABC + (D + E ) c) (AB + C) (DE + F)
d) (A + B) + ( C + D)
،(SOP)א אE١٠ Wאא
אא
א١٦٧
א
אאאאא
א
א
א
A
B
C
Y
0
0
0
1
0
0
1
1
0
1
0
0
0
1
1
0
1
0
0
1
1
0
1
0
1
1
0
1
1
1
1
1
W(SOP), (POS)אאאא אE١١ a) F1 = AB C D + ABCD + ABCD + ABC D + ABC D + ABCD b) F2 = ABCD + ABC D + AB C D + ABC D + ABCD + ABCD + ABCD c) F3 = ABC D + ABC D + ABC D + ABC D + AB C D
d) F4 = AB C D + + AB C D + ABC D + ABC D + ABCD + ABCD + AB C D + ABCD
אאא
אאאאא
אאאאא
٤
אאא אאאאא
א١٦٧
א
א
אאא
Wאאא
Kאאאאאאא •
Kאא(Decoder)אא •
Kאא(Encoder)אאא •
Kאא(Multiplexer)אאא •
Kאא(Demultiplexer)אא • Kאא(Comparator)אא •
אאא אאאאא
א١٦٧
א
א
Introduction ١ J٤ א،אאאאאא אאאKאאאאאאא
،אאאא א
،אאאאאK אאאאא، Kאאא(10)א
אאאאאאא
،א אא אא،אאאא
אאאאKאא،אאא
Kא
אאא אאאאא
א١٦٧
א
א
Binary Adders and Subtractors אאאא٢ J٤ אאאאאאאאא
Kאאאאאאא،א
אאאאאאאאא Kאאאאאאאאא
The Half-Adder Circuit אאא١ J٢ J٤
אאאE١ J٤Fא،אאאא
.[Carry (C)]אאא[Sum(S)]אא A , B א
א
א
A 0
B 0
S 0
C 0
0 + 0 = 0
0
1
1
0
0 + 1 = 1
1
0
1
0
1 + 0 = 1
1
1
0
1
1 + 1 = 102 or 210 1 0 א
KאאאאE١ J٤Fא
אאK(XOR)אאא(S )אא
EEF١ J٤FKANDאא(C)א
Kאאא C, S אא A, B אאא
Kאאאא A
A B
S(sum) א
≡
B
HA
C(carry) א
S C EF EF
KאאאאE١ J٤Fא
אאא אאאאא
א١٦٧
א
א
אEEF١ J٤Fאאאאא
CSאאאאK אא(Half Adder) HA
Wא،אא
S = AB + A B
C = AB
The Full-Adder Circuit אאא٢ J٢ J٤
אאאא (2-bits)
،אאא(carry)אאאא
אאא (3-bits)
א،א אאאא
Kאאאאא،א
(3-bits)אאאאא
אאאBAאא،،א
אאאא אEInput carryFCinאא
אאא.(Sum ٍ )א ، (Carry)אKא
KE٢ J٤Fאא
א
א
A 0
B 0
Cin 0
S 0
C 0
0+0+0=0
0
0
1
1
0
0+0+1=1
0
1
0
1
0
0+1+0=1
0
1
1
0
1
1
0
0
1
0
0 + 1 + 1 = 102 or 210 1 0א
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
1+0+0=1
1 + 0 + 1 = 102 or 210 1 0 א 1 + 1 + 0 = 102 or 210 1 0 א 1 + 1 + 1 = 112 or 310 1 1 א
KאאאאE٢ J٤Fא
אאא אאאאא
א١٦٧
א
א
א A, B, C אאאאאא
א C, S אאKאE 2 3 = 8 Fא
Kאאאאא Wא S , C אאאא
S = A BC in + ABC in + A BC in + ABC in C = ABC in + A BC in + ABC in + ABC in
אא،אאאאאא
WSאאאא
S = A BC in + ABC in + A BC in + ABC in = (AB + A B)C in + (A B + AB)C in
XNOR
A B + AB אא،XOR AB + A B אא
Wאאאא
S = (A ⊕ B)C in + (A ⊕ B)C in
Cin א (A ⊕ B) XORא
WSאא
S = (A ⊕ B) ⊕ C in = A ⊕ B ⊕ C in
א A, B א، XOR אא S
K Cin א
Wאא C א
אאא אאאאא
א١٦٧
א
א
C = ABC in + A BC in + ABC in + ABC in = (AB + A B)C in + AB(C in + C in ) = (A ⊕ B)C in + AB ⇐ ( Cin + C in = 1)
אאאKEEF٢ J٤FאCS
אFAאEEF٢ J٤Fאא
Kאא (Full Adder)
A B
A
B Cin
S(sum)
≡
FA
Cin
C(carry)
E F
S
C
EF
KאאאאE٢ J٤Fא
אאאEEF٢ J٤Fאא
ORא2אא אאORאא KE٣ J٤Fא
A
Cin S
A
HA B
C
B
S
S
HA C
KאאאE٣ J٤Fא
C
אאא אאאאא
א١٦٧
א
א
Half Subtractor Circuit אאא٣ J٢ J٤
אאא
K אאא אאK K א،אאאאאא
אאאא(bit)،א
،אאאK(difference)אא(bit)
K אא(Borrowed)(1)א K،
א(2-bits)אאאא
A K אא(1)
KBא
، A ≥ B KB, A א(A – B)
א א.(Difference bit) אא0 – 0 = 0, 1 – 0 = 1, 1 – 1 = 0W
אאאK אא(1)אאא،0 – 1A < B (10)א،אא،א2 K2 – 1 = 1א،(2)א،א
אא (D)א،אא
K(B0)אא
אא אאאא
אא( B 0 )א،(D)אאKE٣ J٤F Wא
D = AB + A B B 0 = AB
אא(S)א(D)א
A א א א (C) א ( B 0 ) א ، XOR א K B A א AND א( B 0 )א
אאא אאאאא
א١٦٧
א
א
א A 0 0 1 1
א
B 0 1 0 1
D 0 1 1 0
B0 0 1 0 0
KאאאאE٣ J٤Fא אEEF٤ J٤Fא،אאEEF٤ J٤Fא K(Half Subtractor)א HS א،א A A B
D(difference) א
≡
B
E F
HS
B0(borrow) א
Kאאא אE٤ J٤F א
EF D
B0
The Full-Subtractor Circuit אאא٤ J٢ J٤
א (2-bits)אאאאא
אK אאK אא(1)א
K א( B i n ) אא(B)א(A)א A, B, B in א
KE٤ J٤FאאאאKאאא D, B 0 א א 0's,1's אאאאא
K A − B − B in אאא 0's,1's Kאא
Kאאאא B in = 0 אא
(2) B 0 = 1אאא(1) A = 0, B = 0, B in = 1 K D = 1 ،2 – 0 – 1 = 1،A
אאא אאאאא
א١٦٧
א
א
א
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
א
Bin 0 1 0 1 0 1 0 1
D 0 1 1 0 1 0 0 1
B0 0 1 1 1 0 0 0 1
KאאאאE٤ J٤Fא אאא(1) A = 0, B = 1, B in = 1
K D = 0 ،2 – 1 – 1 = 0،A = 2 B 0 = 1
K D = 0 ، B 0 = 0 אA – B – Bin = 0، A = 1, B = 0, B in = 1
אאא(1) A = 1, B = 1, B in = 1 א K D = 1 ،3 – 1 – 1 = 1،A=3، B 0 = 1
Wאאאאא D = ABB in + ABBin + AB Bin + ABBin
אא،אא(S) D = (A ⊕ B) ⊕ Bin = A ⊕ B ⊕ Bin
Wא
Wאא،(B0)א B 0 = ABB in + ABBin + ABB in + ABBin = B in ( AB + AB) + AB( Bin + B in ) B 0 = B in (A ⊕ B) + AB ⇐ ( Bin + B in = 1)
אאא אאאאא
א١٦٧
א
א
אאאא،EEF٥ J٤F (B0), (D)א
(Full Subtractor)אFSא،EEF٥ J٤Fא
Kאא
אאאEEF٥ J٤F אאא
א2אאאא،ORאא
KE٦ J٤FאOR
A
A B
B
≡
FS
B0
D
KאאאאE٥ J٤Fא
D
A D
HS B
B0
B0
D
B0
B
HS A
EF
E F
Bin
D
Bin
Bin
B0
Kאאא E٦ J٤Fא
אאא אאאאא
א١٦٧
א
א
Decoderא٣ J٤ (bits)אאאאא Kאאא،א
،(n)אא
א،אאא
K(2n)א،(n)
،ANDאאאK(1001)אא
،(1)אא(1) ANDאא
א،(1001)א(1)ANDאאא KE٧ J٤F (0's)אא
1 0
1
0 1
1
1
E F
A0 A1
(LSB)
A 1
A2 A3
A
Y=A A A A 3 2 1 0
EF
2
(MSB)
K(1001)ANDאאE٧ J٤Fא
EEF٧ J٤Fאאאא
א א(0)ANDאאKEEF٧ J٤F KA0 = 1, A1 = 0, A2 = 0, and A3 = 1Wא
KאאE٨ J٤F A0 A1
2-to-4 line decoder
D0 D1 D2 D3
Kא אE٨ J٤Fא
אאא אאאאא
א١٦٧
א
א
א،(2-bits)אא
E אFE אF אאK(22 = 4)AND KאאאאE٥ J٤FK(2-to-4 line decoder)
א A1 0 0 1 1
א
A0 0 1 0 1
D0 D1 D2 D3 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1
KאE٥ J٤Fא
ANDאאאאא D 0 = A1 A 0
D1 = A 1 A 0
W
D 3 = A1 A 0
D 2 = A1A 0
א אאאE٩ J٤F
KE٥ J٤Fא
A1
A0
D0 D1 D2 D3
KאאאE٩ J٤Fא
אאאא
אאא،א
Kאאא،א
אאא אאאאא
א١٦٧
א
א
Encoderא٤ J٤ K אאאאא ،(digit)אא
K אאאאאK אא
Kאאאאאאאא
אאאאאE١٠ J٤F
KאאאאKא
D0
D1 Octal input digits
D2 D3
A0
8-to-3
line encoder
D4 D5 D6 D7
A1
Binary outputs
A2
אאא E١٠ J٤Fא
אא،E١٠ J٤FאאאE٦ J٤F
Kאאאאאא
א
א
اﻷرﻗﺎم اﻟﺜﻤﺎﻧﻴﺔ
A2
A1
A0
D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
KאאאאE٦ J٤Fא
אאא אאאאא
א١٦٧
א
א
(1)A2(MSB)אאאא
אA2אORאKD7D4אא
Wא
A2 = D4 + D5 + D6 + D7
WA1, A0אORא
A1 = D2 + D3 + D6 + D7 A0 = D1 + D3 + D5 + D7
א אאאאא
אא ORאאאאאKא KE١١ J٤FאאאאאאK
D1 D2 D3 D4 D5 D6
A0 (LSB)
A1 A2 (MSB)
D7
KאאאE١١ J٤Fא (1)W E١١ J٤Fאאא
D6אא،K אא،אא
א(1)אאE(0)אאF(1)
אא(110)אאא،A0א(0)A2,A3 K(6)
Multiplexer (MUX)א٥ J٤ אאאאאאא Kאאא
אKאאא
Kאאאאאא
אאא אאאאא
א١٦٧
א
א
KE١٢ J٤Fאאאאאא
Kאאאאא
D0
א
D1
4-to-1 MUX
D2
Y אא
D3
אא
S1
S0
Kאאא אE١٢ J٤F א
(S0, S1)אאאא،E١٢ J٤F
(S0, S1)אאאKאאא
אK אD0אאא،S1 = 0, S0 = 0 D1אאא،S1 = 0, S0 = 1(S0, S1)אא
(S0, S1)אאאK א
אאאK אD2אאא،S1 = 1, S0 = 0 D3אאא، S0 = 1 S1 = 1(S0, S1)אא KE٧ J٤FאאאKא
א
S1 0 0 1 1
S0 0 1 0 1
א
Y D0 D1 D2 D3
KאאאאאE٧ J٤Fא
אאKאאאאאאא
אא Kאאאאא
אאא אאאאא
א١٦٧
א
א
(Y)אאK אאא
WS1 = 0, S0 = 0א(D0)אא
∴ Y = D 0 S1 S0
WS1 = 0, S0 = 1א(D1)אא(Y)אא ∴ Y = D1 S1 S0
WS1 = 1, S0 = 0א(D2)אא(Y)אא ∴ Y = D 2S1 S0
WS1 = 1, S0 = 1א(D3)אא(Y)אא ∴ Y = D 3S1 S0
Wאאא،ORאאא
Y = D 0 S1 S0 + D1 S1S0 + D 2S1 S0 + D 3S1S0
،א(AND)אאאא
(NOT)א،א(OR)א
KE١٣ J٤F(S0, S1)
S1
S0
D0
D1 Y D2
D3
KאאאאE١٣ J٤Fא
אאא אאאאא
א١٦٧
א
א
Demultiplexer (DMUX)א٦ J٤ אאאא Kאאא،א
א،אאאאE١٤ J٤F
אאאאאא،א Kאא
D0
I
א
1-to-4 DMUX
D1
א
D2
D3
א
S1
S0
Kאאא אE١٤ J٤F א (S0, S1)אאאא،E١٤ J٤F
(S0, S1)אאאKא(I)א
אKD0א(I)אאא،S1 = 0, S0 = 0
אא،S1 = 0, S0 = 1(S0, S1)אא
(S0, S1)אאאKD1א(I)א
אאאKD2 א(I) אאא،S1 = 1, S0 = 0
אא،S1 = 1, S0 = 1(S0, S1)אא
KE٨ J٤FאאאKD3א(I)א
א
S1 0 0 1 1
S0 0 1 0 1
א D0 D1 D2 D3 I 0 0 0 0 I 0 0 0 0 I 0 0 0 0 I
KאאאאE٨ J٤Fא
אאא אאאאא
א١٦٧
א
א
אאKאאאאאאא
אאK אאאאא
(D0)אאKאאא
W S0 = 0 S1 = 0א(I)אא
∴ D 0 = I S1 S0
WS0 = 1S1 = 0,א(I)אא(D1)אא ∴ D1 = I S1 S0
W S0 = 0S1 = 1א(I)אא(D2)אא ∴ D 2 = IS1 S0
W S0 = 1S1 = 1א(I)אא(D3)אא ∴ D 3 = IS1 S0
אאאאE١٥ J٤F
KE٨ J٤Fאא
א
S1
S 0
I
D0
א
D1 D2
א
D3
KאאאאE١٥ J٤Fא Comparatorsא٧ J٤ K אאאאאאא
Kא אאא،אאא
אא(1)אא(XOR)אא،אא
אאא אאאאא
א١٦٧
א
א
אאאאE١٦ J٤FKאא(0)، K(XOR)
0 0
0 א
0 1
1 א
1 0
1 א
1 1
0 א
Kא אE١٦ J٤F א אאאאאא
א ،EBAF
KאאאאE١٧ J٤FKE A > B A < BA = BFא
B
X(A=B)
א Comparator
A
Y(A<B)
Z(A>B)
Kאא אE١٧ J٤F א KE١٧ J٤FאאאE٩ J٤F
א
א
A
B
0 0 1 1
0 1 0 1
X A=B 1 0 0 1
Y A<B 0 1 0 0
Z A>B 0 0 1 0
KE١٧ J٤FאאאE٩ J٤Fא
אאא אאאאא
א١٦٧
א
א
Wאא
X = A B + AB ⇒ (A = B) Y = A B ⇒ (A < B) Z = A B ⇒ (A > B)
(Y)א ،(XNOR)א(X)אאא
KאאאאאE١٨ J٤FK(AND)א،(Z)א
A
B
X (A=B)
Z (A>B)
Y (A<B)
KאאאE١٨ J٤Fא
אאא אאאאא
א١٦٧
א
א
(1 or 0)אא،E٢ J٤F אאאא E١ Wאא
a) A = 1, B = 1, Cin = 1 c) A = 0, B = 1, Cin = 0
b) A = 0, B = 1, Cin = 1 d) A = 1, B = 1, Cin = 0
WאאאאאאאאאאE٢ a) S = 0, Cout = 0 c) S = 1, Cout = 1
b) S = 1, Cout = 0 d) S = 0, Cout = 1
(1 or 0)אא،E٥ J٤F אאאא E٣ Wאא
a) A = 1, B = 1, Bin = 1 c) A = 1, B = 1, Bin = 0
b) A = 1, B = 0, Bin = 1 d) A = 0, B = 1, Bin = 1
אאא،א(AND)א(1)אE٤ ؟אא
A0 A1
A0 A1
A2
A2
A3
A3
E F
EF
Wאאאאאא،(NOT)א(AND)אE٥ a) 1101 e) 101010
b) 1000 f) 111110
c) 11011 g) 000101
d) 11100 h) 1110110
אE אאF א،E١١ J٤FאאE٦ ؟D5 = 1א
Wאאא،E١٣ J٤FאאE٧
D0 = 0, D1 = 1, D2 = 1, D3 = 0, S0 = 1, S1 = 0
אאא
אאא
אאא
٥
٣٥
אא אאא
א١٦٧
א
א
אאא
Wאאא
Kאאאאא •
KאאS-Rאאא •
KאאDאאא •
KאאTאאא •
KאאJ-Kאאא •
אאא J אאאאאא • Kא
- ١١٤ -
אא אאא
א١٦٧
א
א
Introduction١ J٥ אאאאאא،אאא
אאאא(Combinational Logic Circuits) אא،אא אאאאאא،א
אאאאא (Sequential Logic Circuits) אאא
Kאאאאאאא(Memory)
אא،אאאאאאאאאא
אא ،(Flip-Flop Circuit)אאאאא (1)א(0)אאא
،(1)א(1)אאאאK
אאאאK(0)א(0)אאא
אאא
אאאאא
אא.(Bistable Multivibrator)אאאאאא
K(Digital Integrated Circuits)אאNORאNAND
אא،(Counters)אאא אאא
Kאאאאא(Shift Registers)
Latchesא٢ J٥ אאאאאא אאאאא אKאא
אאאאאאא
אאאאאאKאא
Kאא
K(Bistable Multivibrator)אאאאא(Latch)א
S-RאאאאאE١ J٥F (Set Input)"1" אאא(S)
- ١١٥ -
אא אאא
א١٦٧
א
א
(Reset Input)"0"אאא(R)
Kא Q אQ
SET INPUT
S
Q
Q output
RESET INPUT
R
Q
Q output
KS-RאאאאאE١ J٥Fא
Q =1, Q =0(Set Condition)אא
א .Q =0, Q = 1(Reset Condition)
אא(1)אSאא
אאא،אQאEאאFQ = 1
אF Q = 0אא(1)אRאאK Q = 0
אRSא، Q = 1אאEא
،(unpredictable)אא(1)א Kאאא
אאאאNORאS-Rאא
KE٢ J٥Fאאאאא
S
Q
Q
R
KאאאאS-RאאE٢ J٥Fא
אאF(1)NORאאאאא
אאאאאאא،E א - ١١٦ -
אא אאא
א١٦٧
א
א
אאאאאאאאא،E١ J٥F
K(Active High Inputs)
א S R
א Q
0
0
Q0
0
1
0
1
0
1
1
1
?
א (Mode of Operation) EאFא No Change אא Latch RESETS אא Latch SETS אאא Invalid condition
KאאאS-RאאאE١ J٥Fא
Wאאא
אאRSא(0)אא -١ אאאEאאאF(Q)א Kא
Qאא(1)(0)Rאאא -٢
אא،אא אE אאFQ = 0 (0) KQ = 0
אאא(1)(0)S אאא -٣
א،אאאEאאFQ = 1(1)(0)Q KQ = 1א
אאאRSא(1)אא -٤ א אאא،NORאא
Kא
אאאאא -٥
،אאאאא،אא
Kא
- ١١٧ -
אא אאא
א١٦٧
א
א
אאאE٣ J٥FNANDאאא
E٢ J٥Fאאאאא(0)NANDא
K(Active Low Inputs)אאאאאאאאא
S
Q
Q
R
KאאאאS-RאאE٣ J٥Fא
א
S
R
א Q
0
0
?
0
1
1
1
0
0
1
1
Q0
א (Mode of Operation) אאא Invalid condition אא Latch SETS אא Latch RESETS EאFא No Change
KאאאS-RאאאE٢ J٥Fא Wאאא
Qאאאאא (1)אא -١ KEאאF
אא R = 1א، S = 0אאא -٢ Q = 1אא،אא א(1) K
אא R = 0א، S = 1 אאא -٣
Q = 0אא،אא אא،(0) K
- ١١٨ -
אא אאא
א١٦٧
א
א
אאאאאא(0)א -٤ KאNAND
אאאאא(Logic Symbol)אאE٤ J٥Fא
Kאאאאאאא
S
R
Q
Q
Q
Q
S
S
Q
Q
R
R
Q
Q
EFEF אאאא Kאאאאא E٤ J٥Fא
אאאא אאאא
، S = 0, R = 0 K(Q)א S, R
Kאא
אKE٥ J٥F S, R אאW١ J٥
KQ = 0אQאאא(Q)א Wא
S R
Q
KאאאאE٥ J٥Fא - ١١٩ -
אא אאא
א١٦٧
א
א
Clocked S-R Flip–Flop אאS-Rא٣ J٥ אאאאאא S − R S-Rא אא אא(Q)אא
Kאאאאאאאא،אאאאא EאFאאאאא
אא אאאא
K אאאS-Rאא،אא
אאא
،(CK)אא(Clock Pulses)אאא Kאאאאא
אאS-RאאE٦ J٥F
K(CK)אאא
Q
S
CK R
Q
S CK
Q
R
Q
EFEF
KאאS-RאאE٦ J٥Fא
אאאEEF٦ J٥Fא
(Positive Edge Trigger) אאאS-Rא
אאאEEF٦ J٥Fא،(1)(0)אא
אאאאאא
K(0)(1)אא (Negative Edge Trigger)
א،NANDאאאאS-RאאE٧ J٥F
אאK אאאאNAND אאאא(Q)אR Sא Kאאא
- ١٢٠ -
אא אאא
א١٦٧
א
א
S
Q
CK
Q
R
KאאS-RאאE٧ J٥Fא
WאאאאS-RאE٣ J٥Fא
(0)אאRSאא،אCKאא J١ Kאאאאא
(0)אא(S = 0,R = 1)אRאא J٢ .(Reset)אאא(0) א(1)
(0)אא(R = 0 وS = 1)אאSאא J٣ .(Set)אאאQ = 1א(1)
אא R = 1S = 1אא
K
א S R CK
א (Mode of Operation) א Q0 X X No Change EאFא Q0 0 0 X No Change אא 0 1 0 Latch RESETS אא 1 0 1 Latch SETS אאא 1 1 ? Invalid condition ↑Z(1)א(0)א
XZ
א Q
Q0Zאאא
KאאS-RאאאE٣ J٥Fא - ١٢١ -
אא אאא
א١٦٧
א
א
(1)א]אאאS-Rאא
אאאאאא[(0) K(0)(1)אא
א،E٦ J٥FאS-Rאא (Q)אאW٢ J٥
אאאKE٧ J٥FCKRSא
KאאQ = 0
CK
1
2
3
4
5
6
S
R
Q
KאאS-RאאאאE٧ J٥Fא Wא
KQ = 0(Q)א، R = 0S = 0אאא -١
K(Reset) Q = 0א، R = 1S = 0אאא -٢
K(Set) Q = 1(1)Q א، R = 0S = 1אאא -٣ .(Reset) Q = 0א، R = 1S = 0אאאא -٤
K(Set)Q =1א، R = 0S = 1אאא -٥
KQ = 1 (1)א، R = 0 S = 1אאא -٦
- ١٢٢ -
אא אאא
א١٦٧
א
א
D-Type Flip-FlopD אאא٤ J٥ (Single Bit)אאאDאאאא
אאאאאS-RאאאK(10)א KE٨ J٥FDאא S
D
Q
CK R
Q
KDאאאE٨ J٥Fא
אאDאאDאאא
א،CKאאא(1)אאDאKCK
R = 0א،S = 1אא،[Set](1)אאא אKQ = 1אE٣ J٥FאאS-Rאאא
אא،CKא אא(0)אאD
R = 1 א،S = 0אא،[Reset](0)אא
א(1)(Set)אאKQ = 0אE٣ J٥F Kאא(0)(0)אא،א
אאאאDאאאאא
KE٤ J٥Fא(Positive Edge Trigger) אא
א D CK
א Q
X
Q0
0
0
א (Mode of Operation) EאFא No Change אא(RESET)
1
1
אא(SET)
↑Z(1)א(0)א
KאאD אאאE٤ J٥Fא - ١٢٣ -
אא אאא
א١٦٧
א
א
אK אא(D)א(Q)אא
(D)אאאDאאE٩ J٥F
E١٠ J٥FאK אאא(CK) אא
D D
CK
S
Q
KNANDאDאא
Q CK
Q
R
Q
KDאאE٩ J٥FאKNANDאDאאE١٠ J٥Fא
אE٩ J٥FאDאאאEQFאאW٣ J٥
אאאKE١١ J٥FEDFא
KאQ = 0 Wא
CK
D Q
KDאאאאאE١١ J٥Fא א(1)(0)אאאא(D)א(Q)א
Kא
- ١٢٤ -
אא אאא
א١٦٧
א
א
J-K Flip FlopאאJ-Kא٥ J٥ אאKJא אKאאאאJ-Kאא אS-Rאאא،א
אאאS-RאJ-KאKא J-Kאא.(Reset)אא(Set)אאאא KS-Rאא
K אאאאJ-KאאE١٢ J٥Fא
אאאS-Rאאא Kאא(1)אאKJאאא
J CK
K
Q
Q
J CK
Q
K
Q
KאאאאJ-KאאE١٢ J٥Fא אS-RאאאאאE١٢ J٥F
Kא Q ،Q
אאאJ-KאE٥ J٥Fא
אאאא،(0)KJא
א،אא K = 1J = 0אא(0)א(Reset)א
K = 0 J = 1אאJ-K(Set)אאאא
אKא א אJ-Kאאאא
Qא(1)אאKJא ،(Toggle) KCKאאאאא - ١٢٥ -
אא אאא
א١٦٧
א
א
א J K CK
א Q
א (Mode of Operation) א Q0 X X No Change EאFא Q0 0 0 No Change אא 0 1 0 (RESET) אא 1 0 1 (SET) א Q0 1 1 Toggle ↓Z(0)א(1)א
Q0Zאאא
KאאJ-KאE٥ J٥Fא
אE١٢ J٥FאJ-Kאא(Q)אאW٤ J٥ אKE١٣ J٥FCKJ-Kא
KאQ = 0 א
Wא
CK
1
2
3
4
5
J K
Q
KאאJ-KאאאאE١٣ J٥Fא Q אאא(1)KJ،אאא -١ K(1)א
KJ = K = 0אאאאאאא -٢
KQ = 0(Reset) K = 1J = 0،אא -٣ - ١٢٦ -
אא אאא
א١٦٧
א
א
KQ = 1(Set) K = 0J = 1،אאא -٤
QאKJאאא(Set) א-٥ K(1)א
T-Type Flip-Flop T אאא٦ J٥ אאJ-KאאTאאא אא،E١٤ J٥FאKJא
(Toggle)אTאKאאTאאT Kאא
אא،אאCKא(1)א(T)א
אאאאאCKאאא KE١٤ J٥FCKאאאאאא
T
J
Q
CK
K
Q
KTאאאאאE١٤ J٥Fא
KE٦ J٥FTאאאא
اﻟﻤﺪﺧﻼت T CK
وﺿﻊ اﻟﺘﺸﻐﻴﻞ (Mode of Operation) ﻋﺪم اﻟﺘﻐﻴﺮ Q0 X No Change (وﺿﻊ اﻹﻣﺴﺎك )ﻋﺪم اﻟﺘﻐﻴﺮ Q0 0 No Change وﺿﻊ اﻟﺘﺒﺪﻳﻞ Q0 1 Toggle ↓Z(0)א(1)א
اﻟﺨﺮج Q
Q0Zאאא
KTאאE٦ J٥Fא
- ١٢٧ -
אא אאא
א١٦٧
א
א
E١٤ J٥Fא(T)אאאQאאW٥ J٥
אאE١٥ J٥FCKאTאא
KאQ = 0 Wא
CK T Q
KTאאאאאE١٥ J٤Fא
،אאאT = 1אQאא
T = 1אא،Q = 0QT = 0אאא
Kא(1)(0)Qא
Master-Slave Flip-Flopא–א٧ J٥ אאאאאא K(Edge Triggered)אאאאא
אאאאא
אא ،(Master-Slave)א–אא(Pulse Triggered)
א(Complete Clock Pulse)אאא
Kאא
א،א JאאJ-KאEEF١٦ J٥F
(Master)אא،(Slave)א(Master)אאאJ-K
(Slave)אא،(CK)אאאא
K( CK )אא
- ١٢٨ -
אא אאא
Master J
CK
K
א١٦٧
א
א
Slave Y
Q
CK
Y
Q
Kא JאJ-KאאEEF١٦ J٥Fא
،EEF١٦ J٥FCK CK אא
، אא(CK)אאאא(Master)אא
אאאאא(Slave)אא
K( CK )אאאאא
WKJאQ Q
(Master)אא(CK)(High)אאWאא
KKJאא(Enabled)א
(slave) אא(CK)(Low)אאWאא
KYאאאאQא(Enabled)א
J-KאאאEEF١٦ J٥Fאא
K אאJ-KאאאאKא Jא
אאא אא(CK)א
Kאא(Low)א(High)
אא،א JאJ-KאאאEEF١٦ J٥F KKJאאאt5t0א(CK)
- ١٢٩ -
אא אאא
א١٦٧
א
א
א(Enabled)א (Master)אא،t0א •
אא K = 0 J = 1 א(CK)אא(High)א K( Y = 0 )Y = 1א،אא(Set)
(Low)אא(Disabled)אא،t1א • אא(Enabled)א(Slave)אא،CK
אQא،אאא Y, Y K CK (High)
אאאאKQ = 1(Set )א Fאאא
KE CK = 1אא Q = 1, Q = 0 א Y = 1, Y = 0
Kאאאאאאא
א J K CK 0 0 0 1
א Q Q0
א (Mode of Operation) EאFא
0
א( אRESET)
1
0
1
א(אSET)
1
1
Q0
א
Kא JאJ-KאאאEEF١٦ J٥Fא - ١٣٠ -
אא אאא
t0
א
א
Master Enable
Master Enable
CK
א١٦٧
t1
t2 t3
J
K
Y
Y
Master Enable
Master Enable
t4
t5
ﻜﺎل أﺷ ﻧﺒﻀﺎت اﻟﺘﺎﺑﻊ (Master)
CK
Slave Enable
Slave
Enable
Slave Enable
Y
Y Q
أﺷﻜﺎت ﻧﺒﻀﺎت اﻟﻤﺘﺒﻮع (Slave)
KאאJ-KאאאאEEF١٦ J٥Fא CK(High)אא،אאא،t2א •
אא Y = 0, Y = 1 א K = 1J = 0א .(Reset) א،CK (Low)אאאא،t3א • (Reset)אאאאK אא
KQ = 0א
،Yא(Low)אKJא،t4א •
Jא،t4אאK(Y = 0)אאא
KY = 1אא(High)א
- ١٣١ -
אא אאא
א١٦٧
א
א
א ،אאאאא،t5א • KQ = 1QאY = 1
אאאא
א (PRE) (PRESET)אאאKאא
אאE١٧ J٥Fא (CLR ) (CLEAR)אא
א אK CLR ، PRE S-R א ،Q = 1(SET)אאא،אאא
א،Q = 0 (RESET)אא
(RESET)אאאKאQא
(PRE ) אK אאא א(CLEAR)א ، PRE = 0 (1)אQא،א
(0)אQא (CLR ) א S-Rאאא אE٧ J٥FK CLR = 0
QאE F PRE = 0 א CLR = 1א
PRE = 1 אאאKCK, S, Rאא،(1)
א(0)QאאEF CLR = 0
KCK, S, Rא
PRE
S
CK R
Q
Q
CLR
K CLR ، PRE S-RאאאאE١٧ J٥Fא - ١٣٢ -
אא אאא א PRE CLR CK S 0 1 X X 1 0 X X
0
0
X
X
א١٦٧
א
א
R X
א Q 1
א (Mode of Operation) אא(SET)
X
0
א( אRESET)
X
?
א
KS-Rאא CLR PRE אE٧ J٥Fא
- ١٣٣ -
אא אאא
א١٦٧
א
א
אאאאS-Rאא(Q)אא E١
אא(negative edge trigger)אא
KאאQ=0 אאאK CK
S
R
א אאאDאאא(Q)אאE٢
Kאא(positive edge trigger)אא KאאQ=0 אאא
CK
D
אאאאJKאא(Q)אאE٣ אKאא(negative edge trigger)אא KאאQ=0 אא - ١٣٤ -
אא אאא
א١٦٧
א
א
CK
J
K
אאאאTאאא(Q)אאE٤ אא(negative edge trigger)אא
KאאQ=0 אאאK
CK
T
- ١٣٥ -
אאא
אאאא
אאאא
٦
אא אאאא
א١٦٧
א
א
אאא
Wאאא Kאאאאאא •
Kאאאאאאאאאא •
Kאאאאאאאאאא • Kאאאאאאאא •
- ١٣٦ -
אא אאאא
א١٦٧
א
א
Introduction١ J٦ ،אאאאאא
אאאKאאא אאאאאאKאא
אאאאאאKאא אאאאאא
Registersא٢ J٦ ،אא،אאאאאא
אא(bit)אאאא א،אאא،
אאא
Shift )א (Shift Left)אאא(Buffer Register)אא
א(Parallel Data)א(Serial Data)אאא(Right K(Shift Registers)אא
Buffer Registersא١ J٢ J٦
(Digital word)א
אEEF١ J٦FK(bits)אא
אאאאאD אאאא(4-stages) K(Positive edge-triggered)
- ١٣٧ -
אא אאאא
א١٦٧
א
א
(4-bit word to be stored)אאאא D1
D2 Q
D
CLR
Q
D
Q
D4
D3
CLR
Q
D
Q
CLR
Q
D
Q
CLR
Q
CK CLR
Q1
Q2
Q3
Q4
(parallel data outputs)אאא
E F
KDאאאאאEEF١ J٦Fhg
Clock
א Input data
1
D1
0
D2
1
D3
0
D4
Q1
א Output data
Q2
Q3 Q4
E F
KEEF١ J٦FאאאEEF١ J٦Fא
- ١٣٨ -
אא אאאא
א١٦٧
א
א
אא(4-bits)אאא
אQ1,Q2, Q3,Q4אD1,D2,D3,D4 K(CK)אא
אאאאEEF١ J٦Fאאא
אאQ1,Q2, Q3,Q4א
KאאKאאא
א،אאא
אא Jאאא،אא
אאא(Clear-input)אK(Parallel-in, Parallel-out Registers) KEאFאא(active-low)
Shift Registersאא٢ J٢ J٦
א(Shift)א(move)אאאא
WKE٢ J٦FאאאאאאK
(Serial-in, Serial-out Shift Registers)אא–אאא -١
K(SISO)אא
(Serial-in, Parallel-out Shift Registers)אא–אאא -٢ .(SIPO)אא
(Parallel-in, Serial-out Shift Registers) אא–אאא J٣ K(PISO)אא
- ١٣٩ -
אא אאאא
א١٦٧
א
א
Serial-in, serial-out (SISO) Shift Registers
Shift Right Serial-In
Serial-Out
Shift Left Serial-In
Rotate Right
Rotate Left
E F
Serial-in, parallel-out (SIPO) Shift Registers
Serial-In
Parallel-in, Serial-out Shift (PISO) Registers Parallel Data In
Serial-Out
EF
Parallel Data Out
KאאE٢ J٦Fא א אא
Wא
אאא–אאאאא١ J٢ J٢ J٦
Serial-in, Serial-out (SISO) Shift registers
אאK אאא،E١ J٦F
1001אאאאEאאF0110אא
Kאאא
- ١٤٠ -
אא אאאא
א١٦٧
א
א
אא אאא
א Q0
Q1
Q2
Q3
—
0
1
1
0
1st
1
1
0
1
1
2nd
0
0
1
0
1
3rd
0
0
0
1
0
4th
1
1
0
0
1
Clock
Input
—
KאאE١ J٦Fא
אא( א1st Clock pulse)אאא
אאאאאא אאאא
،(2nd Clock pulse)אאאK אאאאא
אאא (0110)אא
K אאא،אאאK(1001)אאא א(0110)אאא،אאאא
אאאא(1001)אאא،א
K
אא،אאאאא
Kאאאאא
אא(4-bits)אאEEF٣ J٦F
א،(FF0)אאאDאאאאKDאא
(Q1)אאא،(FF1)אאאDא(Q0)אא
אא(Q2)אאא،(FF2)אאאא
אאאאאאאאאאא،(FF3)אאא
Kא
- ١٤١ -
אא אאאא
א١٦٧
א
א
Serial Data Input
FF1
FF0 D
Q
0
CK
Q 1
D CK
FF2
D
Q
2
Serial Data Out
D CK
CK
FF3
Clock Input
SISO Shift Right
Serial Data Out
Q CK
Clock Input
E F
FF3
3
Q
D CK
FF2
2
D
Q 1 CK
FF1
D
Q
Serial Data Input
0
CK
FF0
SISO Shift Left
E F
SISO Rotate Right
SISO Rotate Left
EF
KאאאאאE٣ J٦Fא ،אא(Clock input)אא
،אא(1-bit)אאא (Positive edge) אאא אא–אאאא
אאאא،אא
Kא
- ١٤٢ -
אא אאאא
א١٦٧
א
א
EEF٣ J٦Fאאא،
אאא–אאאאאאDאא
EEF٣ J٦Fאאא .(SISO Shift-Right Shift Register) א–אאDאאאא
K(SISO Shift- Left Shift Register)א
EEF٣ J٦F،EEF٣ J٦Fאאא،א
אא،אא א
אאא–אאא
(SISO Rotate-Left) אאא–אא(SISO Rotate-Right) KEEF٣ J٦F
אא–אאא٢ J٢ J٢ J٦
Serial-in, parallel out (SIPO) Shift registers
אאאאאאאאE٤ J٦Fא
Kאא–א
(4-bits)אאאא،אאא
אFאאאאא(Serial data input)אאא
KEאאא
Serial Data Input
FF1
FF0 D
Q
D
0
CK
CK
FF2
Q 1
D
FF3 Q
D
2
CK
Q
3
CK
Clock Input
Q
0
Q 1
Q
2
Parallel data outputs
Kאא JאאאE٤ J٦Fא - ١٤٣ -
Q
3
אא אאאא
א١٦٧
א
א
אאאאא(4-bits)
אאאאאאאKא
Kאא(4-bits)(Q3,Q2,Q1,Q0)
אא–אאא٣ J٢ J٢ J٦
Parallel-in, Serial-out (PISO) Shift registers
אאאאE٥ J٦F
אאאKDאאאאאא –
،(Low)א SHIFT / LOAD אK SHIFT / LOAD א
א(Enabled)אאAND אא
אאאאK אInverterא
אאKאאאא(D3,D2,D1,D0)א
.(Q3,Q2,Q1,Q0)אאאא ،(Clock pulse)
(SHIFT / LOAD) control
Parallel data inputs
(1 for shift , 0 for load )
D
D 1
0
D
FF1
FF0 D CK
Q
0
D
D
2
3
FF2 Q 1
D
FF3 Q
2
CK
CK
Clock Input
Kאא JאאאE٥ J٦Fא - ١٤٤ -
D
Q
CK
Serial Out 3
אא אאאא
א١٦٧
א
א
ANDאא،(High)א SHIFT / LOAD א
Q0אאאאK(Enabled)אא
،(FF2)אאאאQ1א،(FF1)אאאDא
אא،אאK(FF3)אאאאQ2א
(1-bit)אאאאאאא .(clock inputFאאאא
Shift Register Sequencer (Ring Counter)EאFאאא٤ J٢ J٢ J٦
אאאEEF٦ J٦F
KED0Q3אFFF0אאא(FF3)אאא
אאאאאאאאאא
אQ0אLowא SRART אK
E CLR = 0 FLowא Q1,Q2,Q3א،( PRE = 0 )High KEEF٦ J٦Fא
Q
D
PRE
0
Q
0
CK
0
D 1
PRE
Q 1
FF0
Q
D
CK
CLR
Clock
Q 1 PRE
2
Q
2
CK
CLR
2
D
PRE
3
3
CLR
FF2
START
E F
KאאאEEF٦ J٦Fא
- ١٤٥ -
Q
CK
CLR
FF1
FF3
Q
3
אא אאאא
0
1
א١٦٧
א
א
3
2
1
0
2
3
0
1
2
Clock START
Q
1
Q 1 Q
Q
0
0
0
0 0
1
0
0
0
0
1
0
0
0
0
2 1
3
E F
KאאאEEF٦ J٦Fא Clock Pulses 0 1 2 3
אא Q0 1 0 0 0
Q1 0 1 0 0
Q2
Q3
0 0 1 0
0 0 0 1
Four flip-flops will have Four output states.
Repeat Sequence
KאאאE٢ J٦Fא ،אאא(1000)אאא
אאאאאאא(1)א KE٢ J٦Fא
Johnson Counterא٥ J٢ J٢ J٦ - ١٤٦ -
אא אאאא
א١٦٧
א
א
א،אאאEEF٧ J٦F
אאאאאאא
K(D0)אאאאE Q 3 F
אאאאא،אאא
Q3،1000،E٣ J٦FאאEEF٧ J٦Fא
אא(High)א Q 3 ،אא(Low)א א (High inputs)אאאא،D0א Q3K(High)אאאאאא
،(Low)א Q 3 ،EאאאF(High)א
Low )אאאאאאK(Low)D0
Q3K(Low)אאאא(inputs
(High)א Q 3 ،EאאאF(Low)א
Kאאאא(High)D0
Clock Pulses
אא Q0
Q1
Q2
Q3
Q3
0
1
0
0
0
1
1
1
1
0
0
1
2
1
1
1
0
1
3
1
1
1
1
0
Four flip-flops will have
4
0
1
1
1
0
eight output states.
5
0
0
1
1
0
6
0
0
0
1
0
7
0
0
0
0
1
Repeat Sequence
KאאE٣ J٦Fא
- ١٤٧ -
אא אאאא
א١٦٧
א
א
Q
D
PRE
0
Q
Q 1
0
D 1
0
CK
Q 1
D
PRE
2
CLR
FF0
Q
2
D
2
CK
CK
CLR
Clock
PRE
Q
3
CLR
1
2
3
4
5
Q 3
6
Clock
Q 3
FF3
FF2
E F 0
3
CK
CLR
FF1
PRE
Q
7
0
1
2
3
START
Q
0
Q 1 Q
Q
2
3
Q
3
E F
KאאאאאE٧ J٦Fא ،אאאאאאאאא
Fאאאאא
אאאאאאKEE٢ J٦F - ١٤٨ -
אא אאאא
א١٦٧
א
א
EEF٧ J٦Fאאא،א
KE٣ J٦F(2 × 4 flip-flops = 8)
- ١٤٩ -
אא אאאא
א١٦٧
א
א
Countersאאא٣ J٦ אאאאאאאאאא ،(binary bits)אאאKא אאאאאאאא
אאאאאאאK(clock input)אא
אאאאאאאא
Kאא
אאאאאאאא
K(Synchronous Counters ) אאאאאא(Asynchronous Counters) אאאאאאאאאאאא
אאאאאאאאKאא
K(Master Clock)אאאאאאא،א
،אאאאאאאאאא
Kאאאאאאא
Asynchronous Binary-Up Counters אאאאאאא١ J٣ J٦
K אאאEEF٨ J٦F
אאאא אאK אאJ-K
K אאאאא
אא ،(High)אKJא K אא(Negative edge)(Toggle)
א(Q)אאאאאאא
א(4-bit word)אאQ3,Q2,Q1,Q0אKEEF٨ J٦F
אאא0000אא
FF0אאKE٤ J٦Fאאאא K(MSB)א(Q3)FF3אא(LSB)(Q0)
- ١٥٠ -
אא אאאא
FF0 J Clock Input
א١٦٧
א
א
Q
Q 1
J
0
J
Q
CK
CK
CK
K
K
K
Q
FF3
FF2
FF1
Q 1
0
J
2
Q
3
CK K
Q
2
Q
3
E F 1
Q0
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17
0
Q1
0
Q2
0
Q3
0
E F
KאאאאE٨ J٦Fא ،(Clock input)אאא(FF0)אא
،אאא (Toggle)Q0א
אאאאאאKEEF٨ J٦FQ0א
אKא"0""1"אאא"1""0"Q0
Q0،FF1אאאQ0א
אQ1K(Toggle)Q1א
KQ3אQ2،Q2
- ١٥١ -
אא אאאא
א١٦٧
א
א
אא Q3
Q2
Q1
Q0
א
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Cycle Repeats
Binary Count
KאאאאאE٤ J٦Fא The Maximum Count (N) of a Counter א• אאא،E٤ J٦Fאאא אאאא،[אא(1)א]0001אאא
0011אאאאא،[ אא(2)]א0010א
אאאKא،[אא(3)] Wאאא،אאאא
N = 2 n − 1
W
(N = maximum count before cycle repeats) אאא = N
(n = number of flip-flops in the counter circuit)אאאאא = n WאEF٣٢ J٤אאאא - ١٥٢ -
אא אאאא
א١٦٧
א
א
N = 2n − 1 = 24 − 1 = 16 − 1 = 1510 (11112 ) The Modulus (MOD) of a counterאאא•
א(MOD)(Modulus of a counter)אאא
K אאא MODEEF٨ J٦Fאאא
א11110000 (16)אא(16) WאאאMODKE٤ J٦F
MOD = 2n MOD = modulus of the counter n = number of flip-flops in the counter circuit
WאאאאאEEF٨ J٦Fאאאא
MOD = 2 n = 24 = 16 The Frequency Division of a counter אא•
EEF٨ J٦Fאאאאא
א(frequency divider)אא אא،2אאאאאא
، א2אK2אא
،א2א2א
4אאאאאא
אאאאEEF٨ J٦F ،2אאאאא، KQ1 א - ١٥٣ -
אא אאאא
א١٦٧
א
א
א،8א،4אאאא WאאאאאאKא16
Division Factor = 2n EאF
n = number of flip-flops in the counter circuit
The Propagation Delay Time (tp) of a counterאא• אא،(Ripple counter)אאאאאא Kאאאאא،א
אא، אאאאאא Kאאאא
E אאאFאאא،
אאK10000111אאאא
0111אא (4 Flip-Flops × 10ns) 40ns 10ns (tp)א
אא(counting speed)אK1000
אאKאאאאאאא Wאאא
1 × 10 9 f= n× tp
f = upper clock pulse frequency limit n = number of flip-flops in the counter circuit tp= propagation delay time of each flip-flop in nanoseconds
W
Asynchronous Binary Down Countersאאאאאאא٢ J٣ J٦
אאאאאאאאא
אאאאאאאאאK"1"
אEEF٩ J٦FאK א"1"א
- ١٥٤ -
אא אאאא
א١٦٧
א
א
Q אKJ-Kאאאא KאאאQאא
אKEEF٩ J٦FאאאQאאא
Q3,Q2,Q1,Q0 (RESET)אאאא Q אLowQאאאאK0000
FF1FF2FF3אאאאאאK1111
אHighאאאKJאאKHigh
Kאאא(Toggle) Q Q Q Q 0 1 2 3
HIGH FF1
FF0 Q
J Clock Input
CK K
Q 1
J
0
FF2
CK Q
2
CK Q 1
K
0
Q
J
K
FF3 Q
J
3
CK Q
2
K
Q
3
E F 1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17
Clock Input 0
Q1
0
Q2
0
Q3
0
Q0
E F
KאאאאE٩ J٦Fא "0"Q0א،FF0אאאאאא
אא"0""1" Q 0 אא،"1" - ١٥٥ -
אא אאאא
א١٦٧
א
א
Q1 א"0""1"Q1א،FF1אא
،FF2א"0""1" Q1 אאK"0""1"
Kא
א
אא Q3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Q2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
Q1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
Q0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Binary Count
Cycle Repeats
KאאאאאE٥ J٦Fא (15)10 = 1111Q3,Q2,Q1,Q0אאאאאא
אאאאKE٥ J٦Fאאא אKאאאאא
FF0אא،EEF٩ J٦Fא
،אא א،אQ0א
KאאאאאאQ3,Q2,Q1
- ١٥٦ -
אא אאאא
א١٦٧
א
א
אאאLאאאאא٣ J٣ J٦
Asynchronous Binary Up/Down Counters
אאאא،אאאאאאא
Qאאאאאאאאא
K Q אאאאאאאאא
LאE١٠ J٦F
K UP / DOWN אאAND-OR
Q
HIGH FF0 Q
J Clock Input
0
CK K
UP/DOWN control
Q 1
0
FF1 Q 1 J
0
K
FF2 Q
J
2
Q 1
K
Q
2
Q
2
3
FF3 Q
J
3
CK
CK
CK Q
Q
K
Q
3
KאאאאE١٠ J٦Fא אANDאא،Highא UP / DOWN אא
אאאאQ،(Enabled)א אא،אאא،א
אאאאא،Lowא UP / DOWN
(Enabled)אאאאאא(Disabled)א אא، אאאאא Q
Kא
- ١٥٧ -
אא אאאא
א١٦٧
א
א
Asynchronous Decade (MOD-10) Counters אאאאאא٤ J٣ J٦
אאאאאאאEEF١١ J٦F
K(MOD-10)אא
HIGH FF1
FF0 J Clock Input
Q
Q 1
J
0
CK K
FF2 J
CLR
Q
J
2
CK
CK K
FF3
K
CLR
Q
3
CK K
CLR
CLR
Q
Q 1
0
Q
2
Q
3
E F 1
2
3
4
5
6
7
8
9 10
Clock Input 0
Q1
0
Q2
0
Q3
0
Q0
CLR
E F
KאאאאE١١ J٦Fא
אE9F1001E0F0000אאאא
אEEF١١ J٦Fאא KE٦ J٦Fא
- ١٥٨ -
אא אאאא
א١٦٧
א
א
א1510F1111 1010אאאא א
אאE CLR FאאאאNAND אEא
אאKQ3אאQ1אאאKא
،HighאQ1Q3Eאא10F1010א
אKא (CLEAR)Low NANDא
א(inactive) CLR אEEF١١ J٦Fא
אKHighאQ1Q3אאאאK10010000
אאא(CLEAR)،Q3 وQ1א E٦ J٦FאאאאאK CLR אאא
Kא9א0אא،אא א
אא Q3 0 0 0 0 0 0 0 0 1 1
Q2 0 0 0 0 1 1 1 1 0 0
Q1 0 0 1 1 0 0 1 1 0 0
Q0 0 1 0 1 0 1 0 1 0 1
0 1 2 3 4 5 6 7 8 9
Cycle Repeats
Binary Count
KאאאאאE٦ J٦Fא אא(MOD-10)90אאאא (
1 )Q3א،א 10 .(Clock input)אאא
- ١٥٩ -
אא אאאא
א١٦٧
א
א
אאאאאא
אא(Digital Voltmeter)אא ،(Digital clocks)אאא
K(Frequency Counter)א
Synchronous Binary Counters אאאאאאא٥ J٣ J٦
ANDאJ-KאאE١٢ J٦F
אא(MOD-16) (4-bit)אאאא
אאאאאאאEFאא
אאאאK אאא(Triggered)
Kאאאא، אאא
Q
Q 1
0
HIGH
J
Clock Input
A
FF1
FF0 Q
0
Q 1
J
Q
B
FF2 J
Q
CK
CK
CK
K
K
K
Q
2
FF3 J
2
3
Q
3
CK K
KאאאE١٢ J٦Fא
FF0אאKJאאאאא
א(Toggle)א،Highא
Lowא،אאאאאאאא KאLowHigh High
א2אאאFF1אאKJא
אאQ1א،LowאQ0אאKFF0א
Q1א،HighאQ0א(No change)FF1 K(Toggle)
- ١٦٠ -
אא אאאא
א١٦٧
א
א
AND(A)אאFF2אאKJא
،High AND(A)אQ0 = Q1 = HighאKQ1Q0 KאאFF2אא(Enable)אא
אAND(B)אאFF3אאKJא
AND(B)אHighאQ2,Q1,Q0אKQ0Q1Q2 KאFF3אאאאHigh
Synchronous Counters Advantages אאאאאא ٦ J٣ J٦
(Ripple counters)אאאאאאאאא
אאאאאאא،אא
KEEF٩ J٦FאאאאאאEEF٨ J٦F
אאאאאאאא
אאא،אאאKא
אאK אאא
אאאא (Propagation-delay time) Kאאאאאא
אאאא
EאאFאאא،אאא
אאאאא אאאאאK
אאאאא،א
אאא،א
Kאאאאא،א
אאאאאא
אאאאאKאאאא
Wאאאאאא
tp = Single (flip-flop) tp + Single (AND-gate) tp
- ١٦١ -
אא אאאא
א١٦٧
א
א
אא،אאאE١ J٦F E١
K א1101א אאא،EאאF1010א Kאאא
א، אEאאאFאאאE٢ Kא
א אאאאאאE٣ Kאאא،א
؟אאאא؟אאאאאE٤ (16)אאא(f) אאאE٥ K10ns(tp)אאא،א
א،אאאאאאE٦ K5nsANDאא،10ns(tp)אא
- ١٦٢ -
א
א١٦٧
א
א
א א אאWאא ١ ............................................................................................................................................... אאא ٢ .................................................................................................................................... Introduction١ J١ ٣ ...................................................................................... Decimal Numbering Systemאאא٢ J١ ٤ .......................................................................................... Binary Numbering Systemאאא٣ J١ ٦ ......................................................... Decimal-to-Binary Conversionאאאאא٤ J١ ٩ ........................................................ Binary-to-Decimal Conversionאאאאא٥ J١ ١٠ ...................................................................................... Binary Arithmeticאאאא٦ J١ ١١ ..................................................................................................................אאאאא٧ J١ ١٢ ........................................................................ Representation of Signed Numbersאאאא٨ J١ ١٤ ..................................... Arithmetic Operations with Signed Numbersאאאאאא٩ J١ ١٥ ................................................................................. The Octal Numbering Systemאאא١٠ J١ ٢٣ ................................................................... Hexadecimal Numbering Systemאאאא١١ J١ ٣٢ ......................................................................................................................................................... אאאאWאא ٣٥ ............................................................................................................................................. אאא ٣٦ ................................................................................................................................ Introduction١ J٢ ٣٦ ........................................................................................................................ AND Gate ANDא٢ J٢ ٣٩ ............................................................................................................................... OR Gate ORא ٣ J٢ ٤١ ...................................................................................... NOT Gate (INVERTER) EאF NOT א٤ J٢ ٤٢ ..................................................................................................................... NAND Gate NAND א٥ J٢ ٤٣ ......................................................................................................................... NOR Gate NOR א٦ J٢ ٤٤ ......................................................................................... Exclusive-OR GateEאF אOR א٧ J٢ ٤٥ ................................................................................... Exclusive-NOR GateEאF אNOR א٨ J٢ ٤٧ .................................................The Boolean Expression for a Logic Circuitאאאאא٩ J٢ ٤٨ ...................................................................................................... אאאאאא١٠ J٢ ٤٩ .......................................................................................................... אאאא١١ J٢ ٥٢ .............................................................................................................. אאא١٢ J٢ ٥٣ .........................................................................................................................................................
א
א١٦٧
א
א
אאאאאWאא J٥٦ J .................................................................................................................................... אאא J٥٧ J ....................................................................................................................... Introduction١ J٣ J٥٧ J ................................................................................. Rules of Boolean Algebraאאא٢ J٣ J٥٩ J ...........................................................................................Demorgan's Theorems٣ J٣ J٦١ J .................................................................................. אאאאאאא٤ J٣ J٦٣ J.......................................... Standard Forms of Boolean Expressionsאאאא٥ J٣ J٦٤ J ............................................................................ (POS)אא(SOP)אאא٦ J٣ J٦٦ J ........................................................................... (SOP)אא(POS)אאא٧ J٣ J٦٦ J .......................................................................................אא(SOP)אא٨ J٣ J٦٨ J ....................................................................................... אא(POS)אא٩ J٣ J٧٠ J ................................................................................................ אאאאא١٠ J٣ J٧١ J ................................................................................................... NAND, NORאאאא١١ J٣ J٧٣ J .................................................................. NOR,NANDאאאאאאא١٢ J٣ J٧٩ J ......................................................................................................... Karnaugh Map١٢ J٣ J٩٠ J ................................................................................................................................................ אאאאאWאאא J٩٣ J .................................................................................................................................... אאא J٩٤ J .......................................................................................................................... Introduction١ J٤ J٩٥ J ....................................................................Binary Adders and Subtractorsאאאא٢ J٤ ١٠٣ ................................................................................................................................. Decoderא٣ J٤ ١٠٥ ......................................................................................................................................... Encoderא٤ J٤ ١٠٦........................................................................................................................ Multiplexerא٥ J٤ ١٠٩ ...................................................................................................................... Demultiplexerא٦ J٤ ١١٠ .............................................................................................................................. Comparatorsא٧ J٤ ١١٣ ........................................................................................................................................................ אאאWאא J١١٤ J ................................................................................................................................... אאא J١١٥ J ........................................................................................................................Introduction١ J٥ J١١٥ J ........................................................................................................................... Latchesא٢ J٥ J١٢٠ J .....................................................................................Clocked S-R Flip–FlopאאS-Rא٣ J٥ J١٢٣ J ......................................................................................... D-Type Flip-FlopD אאא٤ J٥ J١٢٥ J .................................................................................................... J-K Flip FlopאאJ-Kא٥ J٥ J١٢٧ J..........................................................................................T-Type Flip-FlopT אאא٦ J٥
א
א١٦٧
א
א
J١٢٨ J................................................................................... Master-Slave Flip-Flopא–א٧ J٥ ١٣٦ ....................................................................................................................................................... אאאאWאא ١٣٩............................................................................................................................................ אאא ١٤٠ K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K Introduction١ J٦ ١٤٠ ................................................................................................................................. Registersא٢ J٦ ١٥٢ .................................................................................................................................. Countersאאא٣ J٦ J١٦٢ J ..............................................................................................................................................