International Conference on Intelligent Computing and Systems
33
International Conference on Intelligent Computing and Systems 2017 [ICICS 2017]
ISBN Website Received Article ID
978-81-933235-5-7 icics.asia 10 – January – 2017 ICICS065
VOL eMail Accepted eAID
01 icics@asdf.res.in 28 - January – 2017 ICICS.2017.065
Role of Reconfigurable Techniques in Wireless Sensor Network Applications by using FPGA with Microcontroller 1
B Kirubakaran1, P Gomathi2 Assistant Professor, Department of ECE, Professor, Department of EEE, NSN College of Engineering and Technology, India 2
Abstract: Reconfigurable techniques are done a major role in recent embedded and developed applications for the competent message transmissions through the wireless sensor networks(WSNs).Recent days, the industrial based inventions are try to avoid complicated things like size, cost and power. In this type of problems the VLSI oriented concepts play a major role at the same time read the analogue values from the environmental condition is difficult one for the VLSI boards for this difficulties the microcontrollers play a major role for avoiding the complicates. For the period of runtime the superfluous dangle and setback are avoided by this reconfigurable technique. In modern world Field Programmable Gate Array (FPGA) based VLSI kits are extensively used for software and hardware applications. In this paper, major part of the work deals with whatever changes may done by the user during the runtime it ought to not influence the present consecutively process. Here the analogue sensors and digital sensors are read by the microcontroller through that the FPGA and monitor the interior industrial application problems and help the user during the complicated situations.
ISBN Website Received Article ID
978-81-933235-5-7 icics.asia 10 – January – 2017 ICICS066
VOL eMail Accepted eAID
01 icics@asdf.res.in 28 - January – 2017 ICICS.2017.066
Reduction of Delay and Area in Binary Comparator Using Tree-Based Techniques 1
Poomaran A1, P Gomathi2 Assistant Professor, Professor, Department of ECE, NSN College of Engineering and Technology, India 2
Abstract: The concept of majority gates is used in this system to design cascade-based and Tree-based structures of a 32-bit comparator in Xilinx. Comparators normally perform a comparison function of a<b, b<a, a=b. This function is being checked by Model simulator for both the Cascade and Tree based structures. This system deals with the majority gates reduction thereby it results in the reduction of power and delay indirectly. The majority gate reduction analysis is obtained in this paper resulting in reduction of majority gates lesser than 85 Gates in the Tree based structure. Since the QCA is a design layout nanotechnology tool. The changes of results in whole structural change and association function formed due to crossing of wires are eliminated by implementing in Xilinx. This paper is prepared exclusively for International Conference on Intelligent Computing and Systems 2017 [ICICS 2017] which is published by ASDF International, Registered in London, United Kingdom under the directions of the Editor-in-Chief Dr M Sivaraja and Editors Dr. Daniel James, Dr. Kokula Krishna Hari Kunasekaran and Dr. Saikishore Elangovan. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage, and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honoured. For all other uses, contact the owner/author(s). Copyright Holder can be reached at copy@asdf.international for distribution.
2017 © Reserved by Association of Scientists, Developers and Faculties [www.ASDF.international]