D10 PCB: 820-00188-08
S UAT1_RF
L 80
TP8000_RF
C 80 00 08 8_ _R RF F
P P8000_RF n o_refdes+9
C6716_RF L 6707_RF
F
C 80
F _R 07 80
F _R 30 77
C6721_RF
C
U2402
C PP2404
RF 4_
0 67
PP2401
_R F
C
05
R6706_RF C6714_RF
USPDT2_RF
L 8007_RF
R T_
C6700_RF
D SP
L8
U
S UAT2_RF
C6720_RF
09_R F
PP2402 XW3333 S GND_RF
C2904
C2902
C2901
C2911
C2914
C2910
C2933
C2926
C4707
C4804
C2921
C2908
C2905
C2906
DZ2906
C2008
R2002
R4813
R4812
C2528
C2522
FL4403
C2513
C4403
C4418
C4405
R4406
C4404 C4401
C4731
C4406
DZ4401
C4408
DZ4402
R4405
C2418
J4504
C0410 FL4406 C0408
DZ4404
DZ2905
FL2910 R2915
C2932
R4708
C2935
C2530
FL2902
5_RF
C4420
C0413 TP 750
C0411 C0409 C4417 C4421
J4501
DZ4403
C2529
FL2909
FL2903 C2927 FL2901 FD0407
P P7604_RF P P7608_RF
P P7603_RF
TP7500_RF
R4810
R4811
C2903
C2915
C4813
C4812
C4803
FL2911
FL2501
n o_refdes+10
C2909 FL2505
R4815
C2510
FL4815
FL4405 XW4501
TP0413
XW3203
J4503
PP2403 C4419
FL2908
FL2907
FL2913
C2931
R2903
C2934
FL2906
C2924
TP0423
R2904
C2503
R4706
C2508
C2506
C4708
R4705
FL2904
C2521
C2520
FL2914
R2905
R4707
M2600
TP0414
C6705_RF
FL6703_RF
C2917
BS0402
C2514
R4401
FL4404
C4411
C4412
C4422
C4407
C4414
C4416
BS0403
DZ2907
C6702_RF n o_refdes+8
FL4732
FL4731 C4415
C4732
C4410
C4413
C4402
C4409
C0405 C0403
C2524
C0401
C2523
C0404
C2526
ZT0401
C2525
C0406
R2001 C2007
FL2504
FL4402
PP5302
C0402
C2512
R4402
FL4401
FL4407
FD0402
FL6702_RF
TUNFX_RF
FL6701_RF
FD0409
C6703_RF
C2401
FL6700_RF
C6701_RF
n o_refdes+6
C7510_RF
C3327
C3313
C3328
R3301
R4603
R4604
R7512_RF
C1811
R3332
C3331
R3333
C3312
C3311
C7731_RF
XW1801
XW1402
C2408
JUAT2_RF 77 C
XW1807 XW2001
FL2506
C2519
C7706_RF
MCEW_RF
XW1403
XW1803
R6703_RF
L 6200_RF
R7711_RF
F _R 10
L 6700_RF
R6711_RF MHBL N_RF
C6629_RF
C1512
C1615 C6713_RF R6705_RF R6710_RF
C6726_RF R6708_RF L BLN_RF
C6602_RF R6601_RF C0412
C0407
C2609
C2610
XW1802
L1806
C6614_RF
C2614
L1808
U0700 L1807
C2613
R7702_RF
C7709_RF
C0420
PP0902 PP1410 C1873 C1872 PP1411 L1809
C6627_RF
FL6603_RF
C0418
XW1401
U2403
C0419
L1813
R6709_RF C6727_RF
C2413
C2421
C0417
L1812
L 6710_RF
R2422 C2423
C0422
C2422 R2403 C2414
C0421
C3315 C3316
L1811
C6728_RF
NFCS W_RF
S WPMX_RF
C2511
C3501
C2502
C3319
C2518
L3302
C4817
C3318
L 7702_RF
L1801
C3324
C3325
C4816
C1804
C2515
C1806
C3308 C3306
P P7614_RF
C7512_RF C7514_RF
L1810
C2916
C1808
C2420
L1803
P P7615_RF
C1810
70 9_ RF
P P7612_RF
R7508_RF
C7516_RF C7518_RF
R7509_RF
L7
C2405
W5BP F_RF C7711_RF C7729_RF
R7703_RF
C7705_RF
WLAN_RF
P P7613_RF
C7515_RF
C7507_RF C7508_RF
C1869
R0901
R1305
L1804
B ALUN_RF
L 7500_RF
C3326
L 7501_RF
R7520_RF
U3301
C7509_RF
R4809
R4808
C3332
C3329
C6735_RF
C6732_RF
C6733_RF C6730_RF
C6731_RF
C6734_RF
C6711_RF
C6201_RF
C6619_RF
C6617_RF
C6620_RF
C6625_RF
C6601_RF
G LNA_RF
MLBL N_RF
FL6602_RF
FD0405
C6611_RF
FD0404
C6613_RF R6606_RF
C2505
C2612
C2509
UPPDI_RF
C2501 FL2500
C2611
L 7703_RF
C7702_RF
W25DI_RF
C2504
R4816
W2BP F_RF
C2531 C2507
L 7700_RF
C7701_RF
R7700_RF
FD0406
L 7701_RF
C7700_RF
P P7616_RF
U2501
FL2502
C0415
C2527 R4817 FL2503
C0414
C0416
P P7605_RF
C6610_RF
P P7606_RF
JUAT1_RF
P PLXR_RF C6622_RF
R6605_RF
P P7607_RF
P P7501_RF
C6729_RF
R6715_RF
C3333
C1923
C1930
R2008 C7525_RF PP5301
C3323
SH0401
XW1901 XW1902 C7703_RF C1405
C3208
C3209
C1602
C5736_RF
R4109
FL4101
C3705
C2114
C2104 G PIO_RF
R2103
R2104
C5906_RF
C5907_RF
C2706
U4806
L3703
C3724 L3704
FL3911
C3702 C3718
C4701
FL3913 FL3917
C3901
C3917 C3904 FL3903
FL3901
C3939
C3933
C3920
C3714
FL3902
C3712
C3725
C3713
R6401_RF
C6415_RF C6406_RF C6408_RF C6417_RF
4
C5620_RF
C5634_RF
L 5602_RF
L 5605_RF
C5624_RF
C5632_RF
C5616_RF L ATDI_RF C4741 FL4741
C3807
C3902
C3804 C3806 C3803
FL3904
C3814 C3826 C3802
FL3910
C3927 C4507
R7130_RF
C7201_RF C6503_RF C6514_RF C6505_RF C6502_RF
C6515_RF
C6512_RF R6503_RF
R6006_RF
L 6111_RF C6118_RF S WLATCP_RF
C6407_RF FL6402_RF
C7012_RF
C6349_RF C6348_RF C6204_RF
C6001_RF
R7109_RF L ATCP_RF
C6504_RF
L 7122_RF
C6014_RF
C6317_RF
L 6104_RF C6104_RF
FL3918
C3921
C4702 FL3920
C6302_RF
L 6305_RF C6315_RF
R7101_RF
C3709 C3708 UATCP_RF
C3918
C2109 C3938
C3704
U3702
C3716
C7111_RF
U4802
C3719
C2113
C6314_RF L 6304_RF
C3721
U3701
L 6308_RF
R6001_RF
S E2_RF
C6508_RF
L 6309_RF
C3706
C1753 R1703
R6003_RF
L 6306_RF C6316_RF C6342_RF 16 _R F
U2710
U2101
L 6307_RF
C
R3701
R4805
R7107_RF
C6007_RF
C6310_RF
61
C2112 C2103
C2703
G SMRX_RF
C6308_RF
C3525 C3929
C2617
C3407
C2700
C2102
C4807
U4805
R4804 Q2102 C3727 C3726
C3538
C6404_RF
C2110 R2102
C5908_RF C5909_RF R4803 R2706
R2105
C7101_RF
C2448
C3425
C7531_RF
C4004 R4001
FL4114
C6006_RF
L 6103_RF C6009_RF
C3524
C3405
FL4103
S E2LDO_RF
20 0
1 XW 22 0
C3937
L 6313_RF
FL4730
C6352_RF
C3539
FL4729
C1723
C7530_RF
C6341_RF C7017_RF
C3916
C3535
C3430
C6333_RF
C6103_RF
C3429
FL4604
C3404
C6329_RF
FL4107
FL3807
C3912
C6332_RF
C3432
C3823
C3911
C3403
TP0409
C3914
C3710
FL4121
C6328_RF
C3428
L 6312_RF
C4003
C7122_RF
JLAT3_RF
C3909
R7511_RF R7114_RF
C7112_RF
C6010_RF
R2441
C6015_RF C6003_RF
C2449
C6018_RF
FL3919
C1746
L 6325_RF
XW
XW3202
C4107 C4104
C1741 DZ690 0_RF
C1718 C1750
C7016_RF
C7127_RF
C1728
C7126_RF
C1712
C6410_RF C6402_RF
FL3916
C1742 C1714 R3808
C3822
C1708
U1701
R1304 C1726
C1905
C1703
C1744 R6501_RF C6510_RF
U5801_RF
C0905
C0904
C0909 R1306
C1855 C1919 C5752_RF R3202
R3201
C1704
FL4116
C1731 C1705
C4729
R1701
C1719
FL4105
C1717
C7524_RF
X W5616_RF
C1435
C1438 R1114
R2005
C2303
C1809 C5708_RF
C3212
R1901
C0701
C5710_RF
C5719_RF
C5743_RF
C7500_RF
C0900
C1461
C1417 C1433 C1431
C1430 C1422
C1404
R0700
XW1804 C5727_RF
C5707_RF C5705_RF C5716_RF
C5723_RF
C5715_RF
R5803_RF
C5735_RF
C5732_RF
C5740_RF
R4713
R4714
C1935
C0810
C0809
C0808
C0807
L2301
C1519
C1415 Y2001
C2003 R2012
U1801 R3602
R0803
C1725
C1707
C0908
R7704_RF C1421 C1416
C1613 C1609
R7600_RF
R0900 C1005
C1006
R1601
C1933
C1918
C1514
C1825 C1803 C1864
C1460
C7521_RF
C1459 C1432
C1010
R0906
R0907
C1457
C1454 C1439
C1452 C1870
C1420
C1518 C1610
C1444
C1612 R2010
C1842
C1004
C1011
C7604_RF
R0413 C7601_RF
C7600_RF
C1508
C1527
C1506
C0813
C0814
C1833 C1828
C0812
C0811
C2618
C1827 C1865
C1820
C1844
R3605 C5635_RF C1706
C4710
U3801
R1702
R0802
R3807
C3931
C1735
C4709
C3811
C3935
R4701
R1704
TP0408
C3818
R0805
TP0412
C3825
R4702
C3824
TP0410
C3816
C3107
C5625_RF
C5630_RF C6013_RF
C3817
C3936
C5905_RF C5636_RF
C5738_RF C5607_RF
X CVR0_RF
C3819
C5615_RF
C6019_RF
C3801
RFBUF_RF
C7523_RF
C2445
C3932 C3910
C1845
C1510 C1859
C3211
R6904_RF
C2705 U2404
C3913
R5906_RF
R5601_RF C5703_RF
C7009_RF C7008_RF
R4806
C3607
C7014_RF
C4809
C5623_RF
L 7123_RF
C4810
C5745_RF
C1830
C3605
C6409_RF
R4807
R3607
C5734_RF
C1802 C6350_RF
FL3801
C5728_RF
C0804
C6414_RF
PP3801
C3821
C5753_RF C5704_RF C5744_RF C5731_RF
C5725_RF C5706_RF
C5742_RF
C5733_RF
R0800
C3606
C2203
FL3922 C3922
Y0700
C2013
C6506_RF
C3815
C0704
C5741_RF
R5802_RF C5714_RF
C5749_RF
FL0700
U3602
C1868
C1854
C0703
C5608_RF
C1912
C4143
C1836
C1504
C5609_RF
C1921
C1807
C2307
C0800
C1466
R2006
C2204
C3934 C3813
R0807 R5907_RF
C2117
R2404
QPOET_RF
C1857 C1851
C5613_RF
C0700
C5720_RF C5739_RF C5726_RF
J2201
MBHBPA_RF
R1504
C6501_RF
C2201
C1927
R1506
C1720
R4104
C1862
C1727
FL4112
C1904
C1801
C1410
C7603_RF
C1838
R7599_RF C7503_RF C7506_RF
C1831
C1448
C1002
C7132_RF
M2800
C1607
C7607_RF C1909
C1101
U2301
XW3801
C6021_RF
R4710
R4110 08 04
J3801
L3901
R3805
C3828
FD
C3930
TP0419
FL3924
FL3802 FL3804
C3919
TP0424
C3925
FL3803
R3802
C3928
TP0401
C3923 R3908
C3926
TP0400
C3915
L3903
C3905
TP0411
R4501
FL3806
PP4501
FD0403
FL4742 C4711
L3902
C3903
C4712
R3923
C3717
C6418_RF
TP0420
C3722 C3715
U3703
FL3912
C3940
FL3811
R3811
JLAT1_RF
n o_refdes+4
C4742
J4502
C3530
C3707
R3809
R3801
R6405_RF
C3812
R3901 R4711 FL3915
C3805
C2115
C4601
C3711
C7004_RF FL7001_RF
C7005_RF
R3915 FL3909
R4712
n o_refdes+7
C2105
D3701
L 6101_RF
C6101_RF
C7001_RF
G SMPA_RF
C7011_RF C7007_RF C7006_RF
C6416_RF FL3908
XW2404
C3924
C3534
FL3906 C3424
C3703
UATDI_RF BS0405
C2442
C2443
C3426
R2101
D3702
C6403_RF
R2703
TP0422
TP0415
C2118
C2202
C4006
C3536
R2704
C3720
C6411_RF
PP4001
LBPA_RF
C1437
C7606_RF C5904_RF
R4801 XW2700
C0806
C1511
R5505_RF
C7527_RF
C1401
R4802 C4103
CL0401
R6404_RF
FD0410
PP1701
C4135
R2201
C1710
R6900_RF
R0505
C0906
C5602_RF
C3532
C4136
C4005
C4001
C2106
U2701 R2702
C2009
FL6401_RF C6400_RF
PP1702
C7520_RF
Y 5501_RF
C3531 P P7601_RF
P P7622_RF
C0901
R7506_RF
C1914
P P7600_RF
C1875
R1503
C1901 n o_refdes+3
C3542
C4134 C4126
C4008 C2707
R7108_RF
C1907
C7502_RF
C4102
C3529
TDDPA_RF
R4102 C4101
PP2440
Q2701
Q2700
L4022
L4021
C4007
R2701
C7120_RF
C7010_RF
C2101
Q2101
C2108
C6115_RF L 6102_RF
C6401_RF
C2702
R2003
C7118_RF
R6402_RF
C3528
C6307_RF
C6306_RF
R6400_RF C6113_RF C6405_RF
L 6109_RF
C6107_RF
C2111
C2701
C6305_RF
C6106_RF
D2700
MLBPA_RF
C4116
C4002
R2705
C6301_RF
X W5615_RF
C1911 C4130
C3422
R2711
C6309_RF
X W5614_RF
BB_RF C4129
C4608 U3402
C3537
L2700
C6343_RF
R7110_RF
C5614_RF C4119
FL4118
C3527
U2700
C7119_RF
R7105_RF
C6323_RF
R7104_RF C7125_RF SH0402
L 6110_RF
R3508
C7123_RF
R7106_RF
C2620
J4101
C4120
FL4117
C4730
C1748
C2708
TP0407
C4122
C3434
C1716
U4001
FL4106
C2619
TP0406
R4709
C4111
C4121
FL4108
C1740
C1749
C1747
FL4115
C4110
C4128
C1739
C4106
FL4119
FL4120
MCNS _RF
R3101 C1737
TP0405
C4131
C4117
DZ690 2_RF
TP0402
TP0404 C4118
C4133
DZ690 5_RF
TP0403
FL4102
C4132
DZ690 3_RF
U3502
C6012_RF C6114_RF C6020_RF C6011_RF C6002_RF C6804_RF R6005_RF C7106_RF R7103_RF C7124_RF
C7013_RF FD0400
C6108_RF
C6004_RF
C7108_RF C6024_RF
C6803_RF
C6105_RF
C6805_RF
C6117_RF
C6319_RF L 6311_RF C6320_RF L 6310_RF
R6008_RF
C6806_RF C6802_RF
L 6322_RF L 6201_RF
R6007_RF
C6203_RF
C6022_RF
C6801_RF C6807_RF
C6344_RF
G FIL T_RF
C7110_RF
C6420_RF
C6334_RF
C1745
C3431
C6351_RF
L1817
C1910 ZT0404
C4127
C1732
SH0403
C4109
XW2707
C3221
C3526
C6511_RF R6301_RF R6502_RF C6318_RF C6311_RF L 6301_RFL 6320_RF
L 6321_RF
C6346_RF
C6513_RF
R7132_RF
Q4001
C6324_RF
L 6328_RF
L 6323_RF
R4002
C6008_RF
C6325_RF
C6509_RF
C6345_RF C6205_RF R6201_RF
L 6319_RF
C7131_RF
C6016_RF
C6335_RF
RXFIL_RF
C3427
L 6318_RF C6340_RF
X CVR1_RF
L 6324_RF C6338_RF
C7117_RF
C6507_RF
L BDS M_RF
C7113_RF
R7113_RF
R7002_RF C7114_RF R7131_RF
MHB DS M_RF
S WDS M_RF
1_RF
C6102_RF
C6005_RF
C712
C6023_RF C6017_RF
P P6944_RF
TP0416
C4105
TP0421
C4108
C2710
C7015_RF
C7529_RF
C5903_RF
C5751_RF C5747_RF
C3205
R1103
C3213
C1711
R2710
C1738
R6004_RF
C6112_RF C6110_RF
C6336_RF C6337_RF
P P6938_RF
P P6940_RF
C3215
C1729
R7102_RF
C7128_RF R6002_RF R7111_RF C7129_RF C6111_RF R7112_RF C6109_RF
C7105_RF
C7501_RF
C1860
C0815 C0817
C3217 C5748_RF
U3101 C3214 C3220
C3106
C1752
C7130_RF
C6419_RF
C0818 C0816 P P6936_RF
C1733
C7528_RF
C0805
P P6952_RF
P P6943_RF
C1722
C7133_RF
C1861
P P7000_RF P P6935_RF P P6939_RF
P P6913_RF
C2704 C5746_RF
C1730
C7104_RF
C5618_RF
C1856 C2301
C2309
P P6974_RF
C1702
C7103_RF
P P6980_RF
n o_refdes+2
P P6905_RF P P6977_RF
P P6972_RF
C1701 C6901_RF
P P6978_RF
P P6914_RF
C4704 P P6979_RF P P6953_RF
DZ690 4_RF
C1715
L 5604_RF
C4703
P P6969_RF PP2003
P P6973_RF
C1915
C1721
C1743
C5633_RF
P P6942_RF
R2301
C1713
C1751
P P6929_RF
R4704
R2015
R4703
R4716
R4715
U1101
C1754
C1736
C5617_RF
J_SIM_RF
C1513
P P6918_RF P P6917_RF P P6919_RF
R1113
C2306
C2304
C5755_RF
R3103
R3104
C3112
C3113
C1709
P P6906_RF
C1522
C1853
C2001
C3202 C3222
C3223
C1756
L1816
P P6941_RF
PP5304 DZ690 1_RF
R5911_RF
P P6920_RF
R1116
C3225
R1101
P P6933_RF
R1501
C1528
C1458
C2302
C1403
C1805
C5627_RF
C3224
C1724
C5622_RF C3603
C5626_RF
C5804_RF
C5611_RF
R1707
C5629_RF
C5610_RF
C5612_RF
R1118
R5502_RF
C1734
R5801_RF
C5628_RF
C5601_RF C6900_RF
C5901_RF
R5504_RF
R5908_RF
E PRO M_RF
P P6912_RF
L 5603_RF
R0501
C1407
C1442
R1303
C2308
C5603_RF
XW
R2020
C1608
C1412
C1523
C5724_RF
C3203
U3601
P P6921_RF
R1505
C1529
C3204
P P6909_RF
P P6925_RF
C1926
C5701_RF
C5711_RF
C3201
C5718_RF
C1916
R3611
P P6911_RF C5709_RF
P P6924_RF
C5502_RF
R5503_RF
B BPMU_RF
C5750_RF R5806_RF C5712_RF C5717_RF
C5722_RF
C5604_RF
L1805
C5721_RF
C5621_RF C5902_RF
C5631_RF
R0702 C0702
C1850
C5605_RF C5737_RF
R3603 R5912_RF
R2009
P P7502_RF
n o_refdes+5
R1210
PP2001
L 5601_RF
PP3602 PP3601
R0503
C1925
P P6926_RF
C5754_RF C5729_RF C5713_RF
R3604 R5206
P P6904_RF C1816 R5909_RF C5801_RF
C1846
R5807_RF
C1603
C3604
R6921_RF R6922_RF
C5702_RF
C1858
R0701
C0910
C1902
C1932
R2011
C1876
C0802
R2000
C2006
C1507
C1835
C1841
R0804
C2002
C1822
C1847
C1436
C1829
C1601
C3602
C1503
C2010
C0705
L1818
P P6945_RF
C1614
C1411
C2004
R2004 R2007
C1908
L1815
R0508
PP1408
FL1501
C0801
P P6970_RF
PP0801 P P6915_RF C5730_RF P P6916_RF PP0802
R0504
C1406
C1424
C1606
C1840
C1848 R1502 C1849 R2700
C1501
C1852 C1877
C3601
PP1403
P P6971_RF
P P6931_RF
C1418
C1427
C1419
C1408 R1602
PP0701
R3601
C1449
C1423
C1428
C1502
C1465 C1434
C1913
P P6908_RF
R5511_RF
R5501_RF C5501_RF
5
C1515
C1413
PP1401 PP1402
XW2003
0 20
P P7503_RF P P7504_RF
C7526_RF
L1814
XW
C7504_RF
C1863
L1802
P P6930_RF
U3603
C1509
C1456
C1402
C1429
C1819
C1818
C1837
C1823
C7505_RF R7502_RF
P P7509_RF
C1426
VIETMOBILE.VN
R7510_RF
NFC_RF
R0509
18 05
NFBS T_RF
C1871
P P6923_RF
P P6981_RF
P P7506_RF P P7617_RF P P7507_RF P P7508_RF P P7500_RF P P7505_RF C0903 C0902
R3304
C7517_RF
C7511_RF
C1409
C0803
C1843
C1832
C1826
C1874
R5910_RF
C1611
C1604
C2011 R0806
PP2002
P P6900_RF P P6903_RF PP5303
L 7502_RF
C1821
C1834
C1839
R0801
XW1806
C1440
P P7610_RF P P7624_RF
C7522_RF
C1922
C1425
C1013
C1414
PP1409
P P6907_RF
C1001
R1001
C1605
C0907
C1813
C1814
C1866
C7602_RF
L 7600_RF
P P7623_RF
P P7621_RF
SH0400
C7704_RF
P P7611_RF
P P7619_RF
C7707_RF
P P7620_RF
P P7609_RF P P7618_RF
C1867
XW2002
R7701_RF
C7708_RF
BS0406 n o_refdes+1
8
7
6
5
4
3
2
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
REV
1 ECN
APPD
DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
8
0006400877
ENGINEERING RELEASED
2016-06-14
D10 MLB - DVT D
D LAST_MODIFICATION=Tue Jun 14 15:20:28 2016 PAGE
C
B
<CSA>
CONTENTS
SYNC
DATE
PAGE
<CSA>
SYNC
CONTENTS
DATE
1
<CSA_PAGE1>
TABLE OF CONTENTS
<SYNC_MASTER1>
<SYNC_DATE1>
46
<CSA_PAGE46>
SMALL FORM FACTOR SPECIFIC
<SYNC_MASTER46>
<SYNC_DATE46>
2
<CSA_PAGE2>
SYSTEM:BOM TABLES
<SYNC_MASTER2>
<SYNC_DATE2>
47
<CSA_PAGE47>
I2C MAP: AP, TOUCH, HOMER, I2C5
<SYNC_MASTER47>
<SYNC_DATE47>
3
<CSA_PAGE3>
MLB SPECIFIC: BOM TABLE
<SYNC_MASTER3>
<SYNC_DATE3>
48
<CSA_PAGE48>
I2C MAP AOP
<SYNC_MASTER48>
<SYNC_DATE48>
4
<CSA_PAGE4>
<SYNC_MASTER4>
<SYNC_DATE4>
49
<CSA_PAGE49>
I2C TABLE
<SYNC_MASTER49>
<SYNC_DATE49>
5
<CSA_PAGE5>
SYSTEM:MECHANICAL, TESTPOINTS SYSTEM:BOARDID
<SYNC_MASTER5>
<SYNC_DATE5>
50
<CSA_PAGE50>
spare
<SYNC_MASTER50>
<SYNC_DATE50>
6
<CSA_PAGE6>
spare
<SYNC_MASTER6>
<SYNC_DATE6>
51
<CSA_PAGE51>
spare
<SYNC_MASTER51>
<SYNC_DATE51>
7
<CSA_PAGE7>
SOC:JTAG,USB,XTAL
<SYNC_MASTER7>
<SYNC_DATE7>
52
<CSA_PAGE52>
MLB UNIQUE
<SYNC_MASTER52>
<SYNC_DATE52>
8
<CSA_PAGE8>
SOC:PCIE
<SYNC_MASTER8>
<SYNC_DATE8>
53
<CSA_PAGE53>
CELL,WIFI,NFC
<SYNC_MASTER53>
<SYNC_DATE53>
9
<CSA_PAGE9>
SOC:MIPI AND ISP
<SYNC_MASTER9>
<SYNC_DATE9>
54
<CSA_PAGE54>
WIFI_MLB SCHEMATIC
<SYNC_MASTER54>
<SYNC_DATE54>
10
<CSA_PAGE10>
SOC:LPDP
<SYNC_MASTER10>
<SYNC_DATE10>
55
<CSA_PAGE55>
PERENNIAL
<SYNC_MASTER55>
<SYNC_DATE55>
11
<CSA_PAGE11>
SOC:SERIAL
<SYNC_MASTER11>
<SYNC_DATE11>
56
<CSA_PAGE56>
WIFI FRONT-END [77]
<SYNC_MASTER56>
<SYNC_DATE56>
12
<CSA_PAGE12>
SOC:GPIO & UART
<SYNC_MASTER12>
<SYNC_DATE12>
57
<CSA_PAGE57>
page1
<SYNC_MASTER57>
<SYNC_DATE57>
13
<CSA_PAGE13>
SOC:AOP
<SYNC_MASTER13>
<SYNC_DATE13>
58
<CSA_PAGE58>
NFC
<SYNC_MASTER58>
<SYNC_DATE58>
14
<CSA_PAGE14>
SOC:POWER (1/3)
<SYNC_MASTER14>
<SYNC_DATE14>
59
<CSA_PAGE59>
page1 [1]
<SYNC_MASTER59>
<SYNC_DATE59>
15
<CSA_PAGE15>
SOC:POWER (2/3)
<SYNC_MASTER15>
<SYNC_DATE15>
60
<CSA_PAGE60>
UAT MATCH AND TUNER CONNECTOR [2]
<SYNC_MASTER60>
<SYNC_DATE60>
16
<CSA_PAGE16>
SOC:POWER (3/3)
<SYNC_MASTER16>
<SYNC_DATE16>
61
<CSA_PAGE61>
BOM LIST
<SYNC_MASTER61>
<SYNC_DATE61>
17
<CSA_PAGE17>
NAND
<SYNC_MASTER17>
<SYNC_DATE17>
62
<CSA_PAGE62>
page1
<SYNC_MASTER62>
<SYNC_DATE62>
18
<CSA_PAGE18>
SYSTEM POWER:PMU (1/3)
<SYNC_MASTER18>
<SYNC_DATE18>
63
<CSA_PAGE63>
BOM_OMIT_TABLE
<SYNC_MASTER63>
<SYNC_DATE63>
19
<CSA_PAGE19>
SYSTEM POWER:PMU (2/3)
<SYNC_MASTER19>
<SYNC_DATE19>
64
<CSA_PAGE64>
PMU: CONTROL AND CLOCKS
<SYNC_MASTER64>
<SYNC_DATE64>
20
<CSA_PAGE20>
SYSTEM POWER:PMU (3/3)
<SYNC_MASTER20>
<SYNC_DATE20>
65
<CSA_PAGE65>
PMU: SWITCHERS AND LDOS
<SYNC_MASTER65>
<SYNC_DATE65>
21
<CSA_PAGE21>
SYSTEM POWER:CHARGER
<SYNC_MASTER21>
<SYNC_DATE21>
66
<CSA_PAGE66>
BASEBAND: POWER2
<SYNC_MASTER66>
<SYNC_DATE66>
22
<CSA_PAGE22>
SYSTEM POWER:BATTERY CONN
<SYNC_MASTER22>
<SYNC_DATE22>
67
<CSA_PAGE67>
BASEBAND: CONTROL
<SYNC_MASTER67>
<SYNC_DATE67>
23
<CSA_PAGE23>
SYSTEM POWER:BOOST
<SYNC_MASTER23>
<SYNC_DATE23>
68
<CSA_PAGE68>
BASEBAND GPIOS
<SYNC_MASTER68>
<SYNC_DATE68>
24
<CSA_PAGE24>
SENSORS
<SYNC_MASTER24>
<SYNC_DATE24>
69
<CSA_PAGE69>
TRANSCEIVER0/1: POWER
<SYNC_MASTER69>
<SYNC_DATE69>
25
<CSA_PAGE25>
B2B FILTERS: UTAH
<SYNC_MASTER25>
<SYNC_DATE25>
70
<CSA_PAGE70>
TRANSCEIVER0/1: TX PORTS
<SYNC_MASTER70>
<SYNC_DATE70>
26
<CSA_PAGE26>
CAMERA:STROBE DRIVER
<SYNC_MASTER26>
<SYNC_DATE26>
71
<CSA_PAGE71>
TRANSCEIVER0/1: PRX PORTS
<SYNC_MASTER71>
<SYNC_DATE71>
27
<CSA_PAGE27>
Accessory: Buck Circuit
<SYNC_MASTER27>
<SYNC_DATE27>
72
<CSA_PAGE72>
RECEIVE MATCHING
<SYNC_MASTER72>
<SYNC_DATE72>
28
<CSA_PAGE28>
TRINITY: FF SPECIFIC
<SYNC_MASTER28>
<SYNC_DATE28>
73
<CSA_PAGE73>
LOWER ANTENNA & COUPLERS
<SYNC_MASTER73>
<SYNC_DATE73>
29
<CSA_PAGE29>
B2B:FOREHEAD
<SYNC_MASTER29>
<SYNC_DATE29>
74
<CSA_PAGE74>
DIVERSITY RECEIVE ASM'S
<SYNC_MASTER74>
<SYNC_DATE74>
30
<CSA_PAGE30>
spare
<SYNC_MASTER30>
<SYNC_DATE30>
75
<CSA_PAGE75>
DIVERSITY RECEIVE LNA'S
<SYNC_MASTER75>
<SYNC_DATE75>
31
<CSA_PAGE31>
AUDIO:CALTRA CODEC (1/2)
<SYNC_MASTER31>
<SYNC_DATE31>
76
<CSA_PAGE76>
UPPER ANTENNA FEEDS
<SYNC_MASTER76>
<SYNC_DATE76>
32
<CSA_PAGE32>
AUDIO:CALTRA CODEC (2/2)
<SYNC_MASTER32>
<SYNC_DATE32>
77
<CSA_PAGE77>
PMU: ET MODULATOR
<SYNC_MASTER77>
<SYNC_DATE77>
33
<CSA_PAGE33>
<SYNC_MASTER33>
<SYNC_DATE33>
78
<CSA_PAGE78>
TEST POINTS & BOOT CONFIG
<SYNC_MASTER78>
<SYNC_DATE78>
79
<CSA_PAGE79>
TDD TRANSMIT
<SYNC_MASTER79>
<SYNC_DATE79>
AUDIO:SPEAKER AMP 2
34
<CSA_PAGE34>
AUDIO:SPEAKER AMP 1
<SYNC_MASTER34>
<SYNC_DATE34>
35
<CSA_PAGE35>
ARC:DRIVER
<SYNC_MASTER35>
<SYNC_DATE35>
80
<CSA_PAGE80>
FDD TRANSMIT
<SYNC_MASTER80>
<SYNC_DATE80>
36
<CSA_PAGE36>
ARC:MAGGIE
<SYNC_MASTER36>
<SYNC_DATE36>
81
<CSA_PAGE81>
ICEFALL, SIM, DEBUG_CONN
<SYNC_MASTER81>
<SYNC_DATE81>
37
<CSA_PAGE37>
DISPLAY & MESA:POWER
<SYNC_MASTER37>
<SYNC_DATE37>
<CSA_PAGE82>
<SYNC_MASTER82>
<SYNC_DATE82>
38
<CSA_PAGE38>
B2B:ORB & MESA
<SYNC_MASTER38>
<SYNC_DATE38>
<CSA_PAGE83>
<SYNC_MASTER83>
<SYNC_DATE83>
39
<CSA_PAGE39>
B2B FILTERS: DISPLAY & TOUCH
<SYNC_MASTER39>
<SYNC_DATE39>
<CSA_PAGE84>
<SYNC_MASTER84>
<SYNC_DATE84>
40
<CSA_PAGE40>
TRISTAR 2
<SYNC_MASTER40>
<SYNC_DATE40>
<CSA_PAGE85>
<SYNC_MASTER85>
<SYNC_DATE85>
41
<CSA_PAGE41>
B2B:DOCK FLEX
<SYNC_MASTER41>
<SYNC_DATE41>
<CSA_PAGE86>
<SYNC_MASTER86>
<SYNC_DATE86>
42
<CSA_PAGE42>
spare
<SYNC_MASTER42>
<SYNC_DATE42>
<CSA_PAGE87>
<SYNC_MASTER87>
<SYNC_DATE87>
43
<CSA_PAGE43>
spare
<SYNC_MASTER43>
<SYNC_DATE43>
<CSA_PAGE88>
<SYNC_MASTER88>
<SYNC_DATE88>
44
<CSA_PAGE44>
B2B FILTERS: RIGHT BUTTON FLEX
<SYNC_MASTER44>
<SYNC_DATE44>
<CSA_PAGE89>
<SYNC_MASTER89>
<SYNC_DATE89>
45
<CSA_PAGE45>
B2B: SMALL FF SPECIFIC
<SYNC_MASTER45>
<SYNC_DATE45>
<CSA_PAGE90>
<SYNC_MASTER90>
<SYNC_DATE90>
C
B
TABLE OF CONTENTS
A
Schematic & PCB Callouts
SCH 051-00419 BRD 820-00188 MCO 056-01342
System Block Diagram: TABLE_5_HEAD
PART#
QTY
DESCRIPTION
051-00419
1
SCH,MLB,D10
820-00188
1
PCBF,MLB,D10
REFERENCE DESIGNATOR(S)
<rdar://problem/16684269>
TABLE OF CONTENTS SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
CRITICAL
BOM OPTION
SCH
CRITICAL
?
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
PCB
CRITICAL
?
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
TABLE_5_ITEM
R
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
NAND BOM Options
5
4
Active Diode Alternate TABLE_5_HEAD
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
CRITICAL
NAND_32G
ALTERNATE FOR PART NUMBER
BOM OPTION
REF DES
COMMENTS:
376S00106
376S00047
ALTERNATE
Q2101
DIODES INC. ACT DIODE
2
ACC BUCK CIRCUIT Alternates
TABLE_ALT_HEAD
PART NUMBER
3
1
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR PART NUMBER
BOM OPTION
REF DES
COMMENTS:
371S00087
371S00064
ALTERNATE
D2700
DIODE,SHOTTKY,30V,200MA,0201
152S00558
152S00557
ALTERNATE
L2700
IND,MLD,0.47UH,2.5A,80Mohm,1608
376S00166
376S00164
ALTERNATE
Q2700,Q2701
PFET,12V,CSP4
353S01007
353S01039
ALTERNATE
U2710
IC,LOAD SWITCH,WLCSP4
TABLE_5_ITEM
335S00169
1
U1701
NAND,H,32GB,16nm,MLC
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_5_ITEM
335S00182
1
U1701
NAND,H,128GB,16nm,TLC
CRITICAL
NAND_128G
TABLE_ALT_ITEM
TABLE_5_ITEM
335S00156
1
U1701
NAND,H,256GB,3Dv3,TLC
CRITICAL
DDR PLL Alternate
NAND_256G TABLE_5_ITEM
138S0867
5
CAP,X5R,10UF,20%,6.3V,0.65MM,HRZTL,0402
C1748,C1713,C1716,C1721,C1733
CRITICAL
NAND_32G
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR PART NUMBER
BOM OPTION
REF DES
COMMENTS:
155S00095
155S00068
ALTERNATE
FL1501
FERR BD,100OHM,25%,100MA,2OHM,01005
TABLE_5_ITEM
D
138S00003
5
CAP,X5R,15UF,20%,,6.3V,0.65MM,HRZTL,0402
C1748,C1713,C1716,C1721,C1733
CRITICAL
NAND_128G
5
CAP,X5R,15UF,20%,,6.3V,0.65MM,HRZTL,0402
C1748,C1713,C1716,C1721,C1733
CRITICAL
NAND_256G
ALTERNATE FOR PART NUMBER
BOM OPTION
REF DES
COMMENTS:
335S00201
335S00169
ALTERNATE
U1701
T,15nm,MLC,32GB
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR PART NUMBER
BOM OPTION
REF DES
COMMENTS:
152S00118
152S00075
ALTERNATE
ALL
IND,PWR,SHLD,1.2 UH,3.0A,0.080 OHM,2016
152S00077
152S00397
ALTERNATE
ALL
IND,PWR,SHLD,1.0 UH,2.25A,0.150 OHM,2016
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
335S00209
335S00169
ALTERNATE
U1701
S,16nm,MLC,32GB
TABLE_ALT_ITEM
TABLE_ALT_ITEM
335S00195
335S00182
ALTERNATE
U1701
SS,1Ynm,TLC,128GB
335S00182
ALTERNATE
U1701
T,15nm,TLC,128GB
335S00182
ALTERNATE
U1701
SD,15nm,TLC,128GB
335S00183
ALTERNATE
U1701
SD,3Dv2,TLC,256GB
335S00190
335S00183
ALTERNATE
U1701
SS,3Dv3,TLC,256GB
152S00081
ALTERNATE
ALL
IND,PWR,SHLD,0.47 UH,3.8A,0.048 OHM,2012
152S00123
152S1936
ALTERNATE
ALL
IND,PWR,SHLD,15 UH,0.72A,0.900 OHM,3225
152S00402
152S00366
ALTERNATE
ALL
IND,MULT,1UH,1.2A,0.320 OHM,0603
TABLE_ALT_ITEM
TABLE_ALT_ITEM
335S00148
152S00121
TABLE_ALT_ITEM
TABLE_ALT_ITEM
335S00179
updated 11/12 TABLE_ALT_ITEM
TABLE_ALT_ITEM
335S00180
D
Power Inductor Alternates
TABLE_ALT_HEAD
PART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_5_ITEM
138S00003
TABLE_ALT_ITEM
updated 11/12 TABLE_ALT_ITEM
152S00297
152S1843
ALTERNATE
ALL
reverted 11/13
CYNTEC 2012 1UH
TABLE_ALT_ITEM
TABLE_ALT_ITEM
152S00365
152S00297
ALTERNATE
ALL
CYNTEC 2012 1UH
152S00398
152S00204
ALTERNATE
ALL
IND,PWR,0.22UH,20%,6.7a,23MOHM,2012
152S00120
152S00077
ALTERNATE
ALL
For Chestnut inductor only
152S00117
152S00074
ALTERNATE
L1806,L1810,L1814,L1816,L1817
IND,PWR,SHLD,1.0 UH,3.0A,0.060 OHM,2016
#22686038:See Radar
TABLE_ALT_ITEM
For Chestnut inductor; so it doesn't interfere with PMU inducotr Buck 7 alts Except BUCK5 LX (BUCK5 LX is Taiyo only) TABLE_ALT_ITEM
Global R/C Alternates
C
C
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR PART NUMBER
BOM OPTION
REF DES
COMMENTS:
118S0764
118S0717
ALTERNATE
ALL
RES, 3.92K, 0.1%, 0201
138S0702
138S0657
ALTERNATE
ALL
CAP, X5R, 4.3UF, 4V, 0610
138S00006
138S0835
ALTERNATE
ALL
CAP, 3-TERM, 4.3UF, 4V, 0402
138S00005
138S00003
ALTERNATE
ALL
CAP,X5R,15UF,6.3V,0.65MM,0402,TAIYO
138S00048
138S00003
ALTERNATE
ALL
CAP,X5R,15UF,6.3V,0.65MM,0402,KYOCERA
138S0648
138S0652
ALTERNATE
ALL
CAP,X5R,4.7UF,6.3V,0.65MM,0402,TAIYO
132S0400
132S0436
ALTERNATE
ALL
CAP,X5R,0.22UF,6.3V,01005,TDK
138S00024
138S0986
ALTERNATE
ALL
CAP,CER,3-TERM,7.5UF,20%,4V,0402,TAIYO/TDK
138S0706
138S0739
ALTERNATE
ALL
CAP,CER,1UF,20%,10V,X5R,0201,MURATA
138S0945
138S0739
ALTERNATE
ALL
CAP,CER,1UF,20%,10V,X5R,0201,KYOCERA
132S0436
132S0400
ALTERNATE
ALL
CAP,CER,X5R,0.22UF,20%,6.3V,20%
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
Magnesium Alternates
TABLE_ALT_ITEM
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR PART NUMBER
BOM OPTION
REF DES
TABLE_ALT_ITEM
COMMENTS:
TABLE_ALT_ITEM
TABLE_ALT_ITEM
338S00173
338S00203
ALTERNATE
U2402
Larger Wafer (-29 flow) Magnesium TABLE_ALT_ITEM
Carbon Alternates TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR PART NUMBER
BOM OPTION
REF DES
COMMENTS:
338S00087
338S00226
ALTERNATE
U2401,U2404
Updated version of Carbon
TABLE_ALT_ITEM
Global Ferrite Alternates
B
B
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR PART NUMBER
BOM OPTION
REF DES
COMMENTS:
155S00067
155S0581
ALTERNATE
ALL
FERR, 240OHM, 0.38OHM DCR, 0201
155S0581
155S00067
ALTERNATE
ALL
FERR, 240OHM, 0.38OHM DCR, 0201
155S00012
155S00168
ALTERNATE
ALL
FLTR, 65 OHMS, 0605
155S00194
155S0610
ALTERNATE
ALL
FERR BD, 150OHM, TDK
155S00200
155S0610
ALTERNATE
ALL
FERR BD, 150OHM, TY
152S00489
152S00456
ALTERNATE
ALL
FERR BD, 0.47UH, TY
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
UT LDO Alternates
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR PART NUMBER
BOM OPTION
REF DES
COMMENTS:
353S00889
353S00015
ALTERNATE
U2501
ST, LDO REG, 2.925V, CSP 0.65x0.65
TABLE_ALT_ITEM
Mamba LDO Alternates
Global Varistor Alternates
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR PART NUMBER
BOM OPTION
353S00576
ALTERNATE
REF DES
COMMENTS: TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR PART NUMBER
BOM OPTION
REF DES
COMMENTS:
377S0168
377S0140
ALTERNATE
ALL
VARISTOR, 6.8V, 100PF, 01005
TABLE_ALT_ITEM
353S00932
U3801
ST, LDO REG, 2.75V TABLE_ALT_ITEM
A
I2C5 Alternate TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR PART NUMBER
BOM OPTION
REF DES
COMMENTS: SYNC_MASTER=Sync
335S00234
335S00233
ALTERNATE
U1101
SYNC_DATE=05/17/2016
PAGE TITLE
TABLE_ALT_ITEM
spare
I2C5 ALTERNATE
DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
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THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
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7
6
5
4
3
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7
6
5
4
3
2
1
D10 EEEE CALLOUTS TABLE_5_HEAD
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION TABLE_5_ITEM
825-6838
1
EEEE CODE FOR 639-01754
EEEE_GXD5
CRITICAL
EEEE_BEST
825-6838
1
EEEE CODE FOR 639-01755
EEEE_GXD6
CRITICAL
EEEE_SUPREME
825-6838
1
EEEE CODE FOR 639-01756
EEEE_GXD7
CRITICAL
EEEE_EXTREME
825-6838
1
EEEE CODE FOR 639-02372
EEEE_H6TF
CRITICAL
EEEE_BEST_ROW
825-6838
1
EEEE CODE FOR 639-02373
EEEE_H6TG
CRITICAL
EEEE_SUPREME_ROW
825-6838
1
EEEE CODE FOR 639-02374
EEEE_H6TH
CRITICAL
EEEE_EXTREME_ROW
TABLE_5_ITEM
TABLE_5_ITEM
D
D
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CAYMAN DDR Alternates TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR PART NUMBER
BOM OPTION
REF DES
COMMENTS:
339S00254
339S00253
ALTERNATE
ALL
DDR-H, 2G, B1
339S00255
339S00253
ALTERNATE
ALL
DDR-S, 2G, B1
TABLE_ALT_ITEM
TABLE_ALT_ITEM
Cap 2.2UF Alternates TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR PART NUMBER
BOM OPTION
REF DES
COMMENTS:
138S00049
138S00032
ALTERNATE
(C2507,C2531)
CAP,CER,X5R,2,2UF,20%6.3V,20%, KYOCERA
TABLE_ALT_ITEM
#25634778: Exclude Kyocera as 2.2UF alt at only C2507/C2531 REFDES (other refdes no impact) TABLE_ALT_ITEM
138S0831
C
138S00032
ALTERNATE
ALL
CAP,CER,X5R,2,2UF,20%,6.3V,20%,MURATA
D10x Specific BOM Callouts
C
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
CRITICAL
B5LX_TAIYO
TABLE_5_ITEM
152S00117
1
L1803
TAIYO,IND,PWR,SHLD,1UH,3.6A,0.060OHM,2016
#24681501 TABLE_5_ITEM
117S0156
2
R4808,R4809
RES,MF,1K OHM, 5%, 1/32W, 01005
CRITICAL
#24629229
UTAH_C
B
B
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
Current as of D10 MCO 056-01342-78 D
C0413
1
16V NP0-C0G 01005
25V 2 NP0-C0G-CERM 01005
100PF 5%
Contained in radio_mlb pages
O
POWER 1
2
C0414 56PF 5%
1
C0415 18PF
2% 16V 2 CERM 01005
1
CHASSIS_GND_BS401
4PF
41 40 21
5% 10V 2 C0G-CERM 01005
0P5SM1P0SQ-NSP 1
ROOM=ASSEMBLY
TP0421 1
PP5V0_USB
TP-P55
FD0409
VBUS
A
FID
1
44
CHASSIS_GND_BS402
1
4
CHASSIS_GND_BS403
1
C0402 220PF
5% 10V 2 C0G-CERM 01005
1
C0403 100PF
5% 16V 2 NP0-C0G 01005
1
C0404
1
56PF
5% 25V 2 NP0-C0G-CERM 01005
C0405 18PF
2% 16V 2 CERM 01005
1
ROOM=ASSEMBLY
TP0415 1 VBATT A
PP_BATT_VCC
FD0405 FID
TP-P55
4
TP0422 1
0P5SM1P0SQ-NSP 1
TP-P55
FD0406
ROOM=ASSEMBLY
A
ROOM=TEST
FID
0P5SQ-SMP3SQ-NSP 1
TP0408 1
PP_VDD_MAIN
TP-P55
C0406
ROOM=ASSEMBLY
A
VDD_MAIN
FD0404
Note: Fiducial used as test point
FID
ROOM=TEST
FD0408
4PF
0P5SQ-SMP3SQ-NSP 1
FID
+/-0.1PF 16V 2 NP0-C0G 01005
ROOM=ASSEMBLY
0P5SM1P0SQ-NSP 1
FD0403 FID
0P5SQ-SMP3SQ-NSP 1
ROOM=TEST 4
CHASSIS_GND_BS402 1
C0407
1
220PF
5% 10V 2 C0G-CERM 01005
4
220PF 5%
10V 2 C0G-CERM 01005
1
C0409 100PF 5%
16V 2 NP0-C0G 01005
1
C0410
1
56PF
5% 25V 2 NP0-C0G-CERM 01005
C0411 18PF
2% 16V 2 CERM 01005
1
C0412 4PF
+/-0.1PF 16V 2 NP0-C0G 01005
C0417 220PF
5% 2 10V C0G-CERM 01005
1
220PF
5% 2 10V C0G-CERM 01005
1
C0419 100PF
5% 2 16V NP0-C0G 01005
1
C0420 56PF
1
5% 2 25V NP0-C0G-CERM 01005
C0421 18PF
1
TP-P55
TP-P55
PMU_TO_AP_FORCE_DFU
A
C0422
E75
4PF
41 40
90_TRISTAR_DP1_CONN_P
FD0400
ROOM=ASSEMBLY
FID
0P5SQ-SMP3SQ-NSP 1
A
ROOM=TEST
FD0402 FID
GND TP
0P5SQ-SMP3SQ-NSP 1
ROOM=TEST
ROOM=ASSEMBLY
TP0414 1 TP-P55
+/-0.1PF 2 16V NP0-C0G 01005
2% 2 16V CERM 01005
TP0424 1
DFU 20 12
C0418
TP0419 1 ROOM=TEST
CHASSIS_GND_BS403 1
C
C0408
A
FORCE DFU
ROOM=TEST
C
TP0402 1 TP-P55
A
FD0407
ROOM=TEST
Front Shields
Back Shields 1
1
SH0400 SM
SH0401
41 40
90_TRISTAR_DP1_CONN_N
SHLD-EMI-UPPER-FRT-D10
FID
0P5SM1P0SQ-NSP 1
TP0403 1 TP-P55
A
ROOM=TEST
ROOM=TEST
41 40
90_TRISTAR_DP2_CONN_P
TP0404 1 TP-P55
A
ROOM=TEST
SM
SHLD-EMI-UPPER-BK-D10
D
0P5SM1P0SQ-NSP 1
ROOM=TEST
53 28 27 26 25 23 21 19 18 10 9 52 46 41 40 39 37 35 34 33 31
220PF
FID
ROOM=TEST
BS0403 STDOFF-2.56OD1.4ID.99H-SM
BS0402 STDOFF-2.56OD1.4ID-1.10H-SM
2.70R1.80-NSP
C0401
FD0410
POWER GROUND
A
ROOM=TEST
ZT0401
1
TP0420 1
C0416
+/-0.1PF 16V 2 NP0-C0G 01005
FIDUCIALS TP-P55
22 21
1
1
TESTPOINTS
NORTH_SCREW_EXPOSED
O O
2
41 40
90_TRISTAR_DP2_CONN_N
TP0405 1 TP-P55
A
ROOM=TEST
41 40
PP_TRISTAR_ACC1
TP0406 1 TP-P55
A
ACCESSORY ID AND POWER
ROOM=TEST
1
1
SH0402 SM
SH0403
41 40
PP_TRISTAR_ACC2
TP0407 1
SM
TP-P55
A
ROOM=TEST
SHLD-EMI-LOWER-BK-D10
TP0416 1
SHLD-EMI-LOWER-FRT-D10
TP-P55
A
ROOM=TEST
ZT0404
B
2.70R1.80-NSP 1
41 40
TRISTAR_CON_DETECT_L
TP0412 1 TP-P55
A
TP IS TO HELP WITH USB SI IN THE FACTORY FIXTURE.
B
FOR DIAGS
ROOM=TEST
AMUX 20
TP0413 1
PMU_AMUX_AY
TP-P55
A
ANALOG MUX A OUTPUT
ROOM=TEST
1
R0413 200K
20
PMU_AMUX_BY
1% 1/32W MF 2 01005 ROOM=PMU
TP0423 1 TP-P55
A
#25244799 100k to 200k
ANALOG MUX B OUTPUT
ROOM=TEST
MOJAVE
BS0405
38 37
STDOFF-2.56OD1.4ID.99H-SM
MESA_TO_BOOST_EN
TP0400 1 TP-P55
A
ROOM=TEST
1
BS0406
38 37
STDOFF-2.9OD1.9ID-0.85H-SM
PP16V0_MESA
TP0401 1 TP-P55
A
ROOM=TEST
1
LCM
A CLIP-MLB-COAX-RETENTION-D10
CL0401 SM-SP
45 39
PP_LCM_BL_CAT1_CONN
SYNC_MASTER=Sync
TP0409 1 LCM BACKLIGHT SINK1 A
1
spare DRAWING NUMBER
ROOM=TEST
PP_LCM_BL_CAT2_CONN
TP0410 1 TP-P55
A
Apple Inc. LCM BACKLIGHT SINK2
ROOM=TEST
TOP SIDE 7
PAGE TITLE
TP-P55
45 39
8
SYNC_DATE=05/17/2016
6
45 39
PP_LCM_BL_ANODE_CONN
TP0411 1 LCM BACKLIGHT SOURCE A TP-P55
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
ROOM=TEST
051-00419
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
D
D
BOOTSTRAPPING:BOARD REV BOARD ID BOOT CONFIG 12
12
12
12
BOARD_REV3 BOARD_REV2 BOARD_REV1 BOARD_REV0
NOSTUFFROOM=SOC
R0509 1 01005
MF
5%
NOSTUFFROOM=SOC
R0505 1 01005
MF
5%
R0508 1ROOM=SOC 01005
MF
5%
NOSTUFFROOM=SOC
R0504 01005
1 MF
5%
2 1.00K 1/32W 2
PP1V8
1.00K
1/32W 2
BOARD_REV[3:0] FLOAT=LOW, PULLUP=HIGH
1.00K
1/32W 2 1.00K 1/32W
C SELECTED -->
BOARD_ID4=No connect 11
11
PP1V8 BOARD_ID2 0=EUREKA, 1=KAROO
11
BOARD_ID1
MAKE_BASE=TRUE
NOSTUFFROOM=SOC
R0503 01005
1 MF
5%
NOSTUFF ROOM=SOC
R0501
1 01005 MF 0=FORM FACTOR A, 1=FORM FACTOR B
5%
Pre-Proto w/D520 (non enclosure) PROTO1 PROTO2 PROTO2v5 EVT1 EVT2 SPARE CARRIER SPARE DVT SPARE PVT
C
FLOAT=LOW, PULLUP=HIGH SELECTED -->
1.00K
2 1/32W
PP1V8
1111 1110 1101 1100 1011 1010 xxxx 1000 xxxx 0010 xxxx 0000
BOARD_ID[4:0]
2 1.00K 1/32W
BOARD_ID0=No connect
12
7 8 9 11 12 13 16 17 18 25 29 39 46 47 48 52
01000 01001 01010 01011 01100 01101 01110 01111
D10 MLB D10 DEV D11 MLB D11 DEV D101 MLB D101 DEV D111 MLB D111 DEV 0=MLB, 1=DEV 0=FORM FACTOR A, 1=FORM FACTOR B 0=EUREKA, 1=KAROO
MAKE_BASE=TRUE
BOOT_CONFIG1=No connect
BOOT_CONFIG0=No connect
B
B
BOOT_CONFIG[2:0]
SELECTED -->
FLOAT=LOW, PULLUP=HIGH 000 SPI0 001 SPI0 TEST MODE 010 NVME0_X2 011 NVME0 X2 TEST 100 NVME0 X1 101 NVME0 X1 TEST 110 SLOW SPI0 TEST 111 FAST SPI0 TEST
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
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A
8
7
6
5
4
3
2
1
D
D
C
C
B
B
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
SOC - USB, JTAG, XTAL
2
1
VDD18_USB: 1.71-1.89V @20mA MAX
PP1V8 1
5 7 8 9 11 12 13 16 17 18 25 29 39 46 47 48 52
C0700 0.1UF
20% 2 6.3V X5R-CERM 01005
ROOM=SOC
D
D VDD11_XTAL:1.06-1.17V @TBD mA
FL0700
MAX
240-OHM-25%-0.20A-0.9DCR PP1V1_XTAL
1 1
PP1V1
2
C0704
01005
1
ROOM=SOC
0.1UF 20%
2.2UF
ROOM=SOC
ROOM=SOC
MAX
PP3V3_USB 25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39 29
C0705
20% 2 6.3V X5R-CERM 0201-1
2 6.3V X5R-CERM 01005
VDD18_AMUX: 1.62-1.98V @1mA
15 18
PP1V8
1
C0701
19
3.14-3.46V @20mA MAX
0.1UF
20% 6.3V 2 X5R-CERM 01005
ROOM=SOC
CKPLUS_WAIVE=PWRTERM2GND
VDD33_USB CG26
8 9 10 15 18
tbd - tbd V @5mA MAX
VDD_FIXED_USB CC25
U0700
VDD11_XTAL CG50
VDD18_USB CE25
C
VDD18_AMUX AJ60
VDD12_UH1_HSIC0 CL20
PP0V9_SOC_FIXED
C
CAYMAN-2GB-20NM-DDR-M CSP
SYM 1 OF 16
CM22 UH1_HSIC0_DATA NC CM20 UH1_HSIC0_STB NC
ANALOGMUX_OUT N64
Dev ONLY
USB_DP CM26 USB_DM CL26
CL31 JTAG_SEL
40 40
20 13 40 37 20 13
PP0701 P2MM-NSM
B
SM
PP
20
1 17
CL29 NC CG37 NC CJ35 NC CK33 CH37
SWD_DOCK_BI_AP_SWDIO SWD_DOCK_TO_AP_SWCLK PMU_TO_SYSTEM_COLD_RESET_L
JTAG_TRST* JTAG_TDO JTAG_TDI JTAG_TMS JTAG_TCK
USB_VBUS CH26
BJ3 CFSB
AP_TO_PMU_TEST_CLKOUT
BJ2 TST_CLKOUT
90_USB_AP_DATA_P 90_USB_AP_DATA_N
USB_VBUS_DETECT
20
40 40
21
USB_ID CJ26NC
CM14 COLD_RESET*
PMU_TO_AOP_TRISTAR_ACTIVE_READY
AP_TO_PMU_AMUX_OUT
USB_REXT CK26
AP_USB_REXT 1
B
200
1% 1/32W MF 2 01005
BL65 S3E_RESET*
AP_TO_NAND_RESET_L
R0700 ROOM=SOC
WDOG CK35
BJ4 HOLD_RESET
AP_TO_PMU_WDOG_RESET
20
XTAL_AP_24M_IN XTAL_AP_24M_OUT
1
BL3 TESTMODE XI0 CM42 XO0 CL42
R0701
CRITICAL ROOM=SOC
511K
1% 1/32W MF 2 01005
ROOM=SOC
Y0700
R0702 1
0.00 0% 1/32W MF 01005
ROOM=SOC
1.60X1.20MM-SM
24.000MHZ-30PPM-9.5PF-60OHM
2 1
SOC_24M_O
1
C0702 12PF
2
5% 16V 2 CERM 01005
ROOM=SOC
3 4
1
C0703
2
5% 16V CERM 01005
12PF
ROOM=SOC
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
SOC - PCIE INTERFACES R0804 1
0.00
2
0% 1/32W MF 01005
ROOM=SOC
VDD12_PCIE_REFBUF:1.08-1.26V @40mA
MAX
PP1V2_SOC_PCIE_REFBUF 1
C0802 0.1UF
20% 2 6.3V X5R-CERM 01005
VDD_FIXED_PCIE_xxx:0.855-0.990V @225mA MAX
ROOM=SOC
PP0V9_SOC_FIXED 7
D
R0803
R0805
5 7 9 11 12 13 16 17 18 25 29 39 46 47 48 52
17 17
BW55 CC47 VDD_FIXED_PCIE_REFBUF
CC53 CC62 CE55 CE60
20% 2 6.3V X5R-CERM 01005
0% 1/32W MF 01005
0.1UF
2
0.1UF
2
20% 6.3V X5R-CERM 01005
ROOM=SOC
C0800
1
D
C0806 2.2UF
1.0UF
20% 2 6.3V X5R 0201-1
2
ROOM=SOC
20% 6.3V X5R-CERM 0201-1 ROOM=SOC
ROOM=SOC
ROOM=SOC
CAYMAN-2GB-20NM-DDR-M CSP
ROOM=SOC
PCIE_NAND_BI_AP_CLKREQ_L
C0804
0.00
1
U0700
100K
5% 1/32W MF 2 01005 17
1
1
C0803
90_PCIE_AP_TO_NAND_REFCLK_P 90_PCIE_AP_TO_NAND_REFCLK_N
BC64
PCIE_CLKREQ0*
CJ48 CK48
PCIE_REF_CLK0_P PCIE_REF_CLK0_N
SYM 2 OF 16
PCIE_CLKREQ3* BE66 PCIE_REF_CLK3_P CL64 PCIE_REF_CLK3_N CM64
PCIE_WLAN_BI_AP_CLKREQ_L
52
90_PCIE_AP_TO_WLAN_REFCLK_P 90_PCIE_AP_TO_WLAN_REFCLK_N
52 52
PCIE LINK 3
1
ROOM=SOC
VDD_FIXED_PCIE_ANA
ROOM=SOC
PP1V8
C0801 0.1UF
20% 6.3V 2 X5R-CERM 01005
CA55 CA60
C0805 2.2UF
20% 6.3V X5R-CERM 0201-1
VDD_FIXED_PCIE_CLK
2
1
VDD12_PCIE_REFBUF
1
CC49 CE49
VDD12_PCIE: 1.14-1.26V @10mA MAX
PP1V2_SOC
VDD12_PCIE CE58
19 16 10
PP0V9_SOC_FIXED_PCIE_REFBUF
1
9 10 15 18
#24557655:replace with 20% caps. SI no negative impact
C
C0807 20%1
PCIE LINK 0
17
90_PCIE_NAND_TO_AP_RXD_P 90_PCIE_NAND_TO_AP_RXD_N
ROOM=SOC
X5R 1 20% ROOM=SOC X5R D10 NAND is now Gen3 (was Gen2). Caps 1 20% ROOM=SOC X5R 1 ROOM=SOC 20% X5R
C0808 C0809
17
90_PCIE_AP_TO_NAND_TXD_P 90_PCIE_AP_TO_NAND_TXD_N
17
PCIE_AP_TO_NAND_RESET_L
17
1
C0810
CM46 CL46
PCIE_RX0_P PCIE_RX0_N
PCIE_RX3_P CM61 PCIE_RX3_N CL61
90_AP_PCIE3_RXD_C_P 90_AP_PCIE3_RXD_C_N
CK44 CJ44
PCIE_TX0_P PCIE_TX0_N
PCIE_TX3_P CK63 PCIE_TX3_N CJ63
90_AP_PCIE3_TXD_C_P 90_AP_PCIE3_TXD_C_N
BJ65
PCIE_PERST0*
52 52
52 52
PCIE_PERST3* BJ66
PCIE_AP_TO_WLAN_RESET_L 52 1
R0802
LINK0
100K
5% 1/32W MF 2 01005
ROOM=SOC
BG66 NC CL54 NC CM54 NC
PCIE_CLKREQ2* BE65 PCIE_REF_CLK2_P CK59 PCIE_REF_CLK2_N CJ59
PCIE_REF_CLK1_P PCIE_REF_CLK1_N
R0806 100K
LINK3
PCIE_CLKREQ1*
5% 1/32W MF 2 01005 ROOM=SOC
PCIE_BB_BI_AP_CLKREQ_L
52
90_PCIE_AP_TO_BB_REFCLK_P 90_PCIE_AP_TO_BB_REFCLK_N
52 52
PCIE LINK 1
WLAN RX PP's are now managed on Page 52
B
CK52 NC CJ52 NC
PCIE_RX1_P PCIE_RX1_N
PCIE_RX2_P CK56 PCIE_RX2_N CJ56
90_AP_PCIE2_RXD_C_P 90_AP_PCIE2_RXD_C_N
CM50 NC CL50 NC BG64 NC
PCIE_TX1_P PCIE_TX1_N
PCIE_TX2_P CM57 PCIE_TX2_N CL57
90_AP_PCIE2_TXD_C_P 90_AP_PCIE2_TXD_C_N
52 52
LINK 1 USED ON AP_DEV ONLY
LINK1
CH57 CG57
52
PCIE_AP_TO_BB_RESET_L52
LINK2
1
PCIE_EXT_REF_CLK_P PCIE_EXT_REF_CLK_N
2
PCIE_REXT CG63
R0801 100K
5% 1/32W MF 01005
ROOM=SOC
AP_PCIE_RCAL 1
2
R0800 3.01K
1% 1/32W MF 01005
ROOM=SOC
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
B
52
PCIE_PERST2* BE64
PCIE_PERST1*
C
PCIE LINK 2
17
2 GND_VOID=TRUE 0.22UF 6.3V 01005 90_PCIE_NAND_TO_AP_RXD_C_P 2 GND_VOID=TRUE 0.22UF 90_PCIE_NAND_TO_AP_RXD_C_N 6.3V 01005 intentionally 0.22uF 2 GND_VOID=TRUE 0.22UF 6.3V 01005 90_PCIE_AP_TO_NAND_TXD_C_P 2 GND_VOID=TRUE 0.22UF 90_PCIE_AP_TO_NAND_TXD_C_N 6.3V 01005
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
SOC - MIPI & ISP INTERFACES D
1.62-1.98V @7mA MAX
0.825-0.94V @25mA MAX
PP0V9_SOC_FIXED
6.3V 2 X5R-CERM 01005 ROOM=SOC
C0900
1
2.2UF 20%
C0901
1
20% 6.3V X5R-CERM 0201-1
2
2.2UF
6.3V 2 X5R-CERM 0201-1 ROOM=SOC
2
PP1V8
5 7 8 11 12 13 16 17 18 25 29 39 46 47 48 52
C0903 0.1UF 20%
ROOM=SOC
VDD18_MIPI
0.1UF 20%
1
G10 G15 G19 G21
C0902
VDD_FIXED_MIPI
1
G13 G17 G6
18 15 10 8 7
D
6.3V X5R-CERM 01005 ROOM=SOC
U0700 CAYMAN-2GB-20NM-DDR-M CSP
45 45
45 45
45
I2C_ISP_UT_SCL I2C_ISP_UT_SDA
MIPI0C_DPDATA1 MIPI0C_DNDATA1
ISP_I2C1_SCL U64 ISP_I2C1_SDA R65
I2C_ISP_NV_SCL I2C_ISP_NV_SDA
C24 NC B24 NC
MIPI0C_DPDATA2 MIPI0C_DNDATA2
ISP_I2C2_SCL U65 ISP_I2C2_SDA U66
I2C_ISP_NH_SCL I2C_ISP_NH_SDA
A26 NC B26 NC
MIPI0C_DPDATA3 MIPI0C_DNDATA3
ISP_I2C3_SCL W64 NC ISP_I2C3_SDA W66 NC
A18 B18
MIPI0C_DPDATA0 MIPI0C_DNDATA0
90_MIPI_NH_TO_AP_DATA1_P 90_MIPI_NH_TO_AP_DATA1_N
B20 C20
C 45
ISP_I2C0_SCL N65 ISP_I2C0_SDA N66
90_MIPI_NH_TO_AP_DATA0_P 90_MIPI_NH_TO_AP_DATA0_N
B22 A22
90_MIPI_NH_TO_AP_CLK_P 90_MIPI_NH_TO_AP_CLK_N
E24
MIPI0C_REXT
SYM 3 OF 16
48 48
46 46
48 48
1
MIPI0C_DPCLK MIPI0C_DNCLK
33.2
2
1% 1/32W MF 01005
SENSOR_INT AA64NC
MIPI0C_REXT
C
R0906
Dev ONLY
1
C0906
2
5% 35V NP0-C0G 01005
R0900 1 4.02K
1% 1/32W MF 01005 2 ROOM=SOC
39 39
39 39
B4 A4
90_MIPI_AP_TO_LCM_DATA0_P 90_MIPI_AP_TO_LCM_DATA0_N
B5 C5
90_MIPI_AP_TO_LCM_DATA1_P 90_MIPI_AP_TO_LCM_DATA1_N
C9 B9
NC_MIPI_AP_TO_LCM_DATA2_P NC_MIPI_AP_TO_LCM_DATA2_N D11/111 ONLY
A11 B11
NC_MIPI_AP_TO_LCM_DATA3_P NC_MIPI_AP_TO_LCM_DATA3_N
39 39
B
26 36
B7 A7
90_MIPI_AP_TO_LCM_CLK_P 90_MIPI_AP_TO_LCM_CLK_N AP_TO_STROBE_DRIVER_HWEN SPI_AP_TO_MAGGIE_CS_L NC
MIPID_REXT
SENSOR0_CLK B50 SENSOR1_CLK A48 SENSOR2_CLK C48
MIPID_DPDATA0 MIPID_DNDATA0
AP_TO_UT_CLK_R NC_AP_TO_NV_CLK_R AP_TO_NH_CLK_R
1
33.2 1% 1/32W MF 01005
SENSOR0_RST SENSOR1_RST SENSOR2_RST SENSOR3_RST SENSOR4_RST
MIPID_DPDATA3 MIPID_DNDATA3
A50 E50 AA65 AE64 AC65 NC
SENSOR0_ISTRB E52 SENSOR1_ISTRB D50 NC
MIPID_DPCLK MIPID_DNCLK
BN4 BR2
DISP_TOUCH_BSYNC0 DISP_TOUCH_BSYNC1
BR4
DISP_TOUCH_EB
E11
MIPID_REXT
SENSOR0_XSHUTDOWN C50 NC SENSOR1_XSHUTDOWN B48
ROOM=SOC
AP_TO_UT_SHUTDOWN_L NC_AP_TO_NV_SHUTDOWN_L AP_TO_NH_SHUTDOWN_L TP_SENSOR3_RST
25
AP_TO_NH_CLK
29
R0907
D11/111 ONLY
MIPID_DPDATA1 MIPID_DNDATA1 MIPID_DPDATA2 MIPID_DNDATA2
AP_TO_UT_CLK
100PF
ROOM=SOC
Spare
NOSTUFF
25
2
NOSTUFF 1
C0907
2
5% 35V NP0-C0G 01005
100PF
D11/111 ONLY 29
1
PP
SM
PP0902 P2MM-NSM <---
ROOM=SOC
Radar 20511449 Needed for Cayman debug; this pin cannot be input
NC_SENSOR0_ISTRB
AP_TO_MUON_BL_STROBE_EN
B
37
MIPI1C_REXT E16 MIPI1C_DPDATA0 B12 MIPI1C_DNDATA0 C12
R0901 1 4.02K
MIPI1C_DPDATA1 B16 MIPI1C_DNDATA1 C16
1% 1/32W MF 01005 2 ROOM=SOC
Dev only
MIPI1C_DPCLK B14 MIPI1C_DNCLK A14
Per Radar 21221938
A
53 28 27 26 25 23 21 19 18 10 4 52 46 41 40 39 37 35 34 33 31
PP_VDD_MAIN
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
1
C0904
1
220PF
C0905 220PF
5% 2 10V C0G-CERM 01005
5% 2 10V C0G-CERM 01005 ROOM=SOC
ROOM=SOC
1
C0908
1
220PF
5% 10V 2 C0G-CERM 01005
C0909
1
5% 10V C0G-CERM 01005
2
220PF
2
ROOM=SOC
ROOM=SOC
spare
C0910 220PF
DRAWING NUMBER
5% 10V C0G-CERM 01005
Apple Inc.
ROOM=SOC
051-00419
REVISION
R
AC return path for LCM MIPI which is referenced to GND and VDD_MAIN Radar 21203307
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
D
D VDD12_PLL_LPDP:1.14-1.26V @3mA MAX VDD12_LPDP:1.14-1.26V @60mA MAX
C1013 2.2UF
20% 6.3V 2 X5R-CERM 0201-1
1
C1001 2.2UF
20% 6.3V 2 X5R-CERM 0201-1 ROOM=SOC
C1004
1
0.1UF
C1005
1
0.01UF
20% 6.3V 2 X5R-CERM 01005
CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND
15PF
10% 6.3V 2 X5R 01005
ROOM=SOC
C1002
5% 16V 2 NP0-C0G-CERM 01005
ROOM=SOC
ROOM=SOC Desense for Wifi frequencies
VDD12_LPDP_RX
VDD12_LPDP_TX
ROOM=SOC
1
VDD12_PLL_LPDP G23
1
G25 G28 G30 G55 G58 G60 G62
PP1V2_SOC
U0700 CAYMAN-2GB-20NM-DDR-M 25 25
25 25
C
CSP
LPDP_TX0P B27 NC LPDP_TX0N C27 NC
90_LPDP_UT_TO_AP_D0_P 90_LPDP_UT_TO_AP_D0_N
A54 LPDPRX_RX_D0_P B54 LPDPRX_RX_D0_N
90_LPDP_UT_TO_AP_D1_P 90_LPDP_UT_TO_AP_D1_N
B56 LPDPRX_RX_D1_P C56 LPDPRX_RX_D1_N
LPDP_TX1P A29 NC LPDP_TX1N B29 NC
NC_90_LPDP_NV_TO_AP_D2_P NC_90_LPDP_NV_TO_AP_D2_N
A61 LPDPRX_RX_D2_P B61 LPDPRX_RX_D2_N
LPDP_TX2P B31 NC LPDP_TX2N C31 NC
NC_90_LPDP_NV_TO_AP_D3_P NC_90_LPDP_NV_TO_AP_D3_N
B63 LPDPRX_RX_D3_P C63 LPDPRX_RX_D3_N
LPDP_TX3P A33 NC LPDP_TX3N B33
SYM 4 OF 16
Dev ONLY
C
LPDP Lanes swapped between D10 and D11 46 46
D11/111 ONLY 46 46
A64 LPDPRX_RX_D4_P B64 LPDPRX_RX_D4_N
GND ON MLB; other on Dev
D11/111 ONLY
25
LPDP_UT_BI_AP_AUX
46
NC_AP_LPDP_AUX2
D54 E56 NC D61 E63 NC D64 NC
18 15 9 8 7
LPDP_CAL_DRV_OUT E35 NC LPDP_CAL_VSS_EXT E31 NC EDP_HPD BN3 NC DP_WAKEUP AP2 NC
B59 LPDPRX_BYP_CLK_P C59 LPDPRX_BYP_CLK_N
GND ON MLB; other on Dev
B
LPDP_AUX_P D33 NC LPDP_AUX_N E33 NC
LPDPRX_AUX_D0_P LPDPRX_AUX_D1_P LPDPRX_AUX_D2_P LPDPRX_AUX_D3_P LPDPRX_AUX_D4_P
PP0V9_SOC_FIXED
A57 LPDPRX_RCAL_P
AP_LPDPRX_RCAL_NEG
B57 LPDPRX_RCAL_N
Reserved for PanelID[1:0] on ap_dev board Reserved for PanelID[1:0] on ap_dev board
B
R1001 1 300
1% 1/32W MF 01005-1 2 ROOM=SOC
C1006
1
100PF
NC
5% 16V NP0-C0G 2 01005 ROOM=SOC
A
D57 LPDPRX_EXT_C
#24401637:Unconnect LPDPRX_EXT_C
53 28 27 26 25 23 21 19 18 9 4 52 46 41 40 39 37 35 34 33 31
PP_VDD_MAIN SYNC_MASTER=Sync
1
C1010
1
33PF
5% 2 16V NP0-C0G-CERM 01005
SYNC_DATE=05/17/2016
PAGE TITLE
C1011
spare
33PF
2
5% 16V NP0-C0G-CERM 01005
ROOM=SOC
DRAWING NUMBER
Apple Inc.
ROOM=SOC
051-00419
REVISION
R
AC return path for LCM LPDP which is referenced to GND and VDD_MAIN
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
SOC - SERIAL INTERFACES D
D R1103 32
I2S_AP_TO_CODEC_MCLK
1
33.2
2
1% 1/32W MF 01005
32 32
ROOM=SOC
32 32
BV65 BY66 BU64 BR64 BU65
I2S_AP_TO_CODEC_MCLK_R I2S_AP_TO_CODEC_MSP_BCLK I2S_AP_TO_CODEC_MSP_LRCLK I2S_CODEC_TO_AP_MSP_DIN I2S_AP_TO_CODEC_MSP_DOUT I2S1/2/3 MCLK NC #24559456
53 53 53 53
36 35 34 33 32 36 35 34 33 32 36 36
C
53 53 53 53
5 5
I2S_AP_TO_BT_BCLK I2S_AP_TO_BT_LRCLK I2S_BT_TO_AP_DIN I2S_AP_TO_BT_DOUT
I2S_MAGGIE_TO_AP_L26_CODEC_BCLK I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK I2S_MAGGIE_TO_AP_DIN I2S_AP_TO_MAGGIE_DOUT
I2S_BB_TO_AP_BCLK I2S_BB_TO_AP_LRCLK I2S_BB_TO_AP_DIN I2S_AP_TO_BB_DOUT
BOARD_ID2 BOARD_ID1 BOARD_ID0
5
R1116 36 32
SPI_AP_TO_CODEC_MAGGIE_SCLK
1
Route as daisy-chain. No T's allowed.
0.00
36 32 36 32
2
0% 1/32W MF 01005
32
PP1V8
R1101 39
SPI_AP_TO_TOUCH_SCLK
1
0.00 0% 1/32W MF 01005
39 39
2 39
SPI_TOUCH_TO_AP_MISO SPI_AP_TO_TOUCH_MOSI SPI_AP_TO_TOUCH_SCLK_R SPI_AP_TO_TOUCH_CS_L
ROOM=SOC 38
B
38 38 38
D48 NC E48 A46 C46 E46
I2S1_MCK I2S1_BCLK I2S1_LRCK I2S1_DIN I2S1_DOUT
BU66 BR66 BN64 BN65 BJ64
I2S2_MCK I2S2_BCLK I2S2_LRCK I2S2_DIN I2S2_DOUT
CH11 NC CM7 CK9 CG18 CJ9
I2S3_MCK I2S3_BCLK I2S3_LRCK I2S3_DIN I2S3_DOUT
NC
CB2 BY4 BY3 NC CB4
N2 N3 N4 R3
SPI_CODEC_MAGGIE_TO_AP_MISO SPI_AP_TO_CODEC_MAGGIE_MOSI SPI_AP_TO_CODEC_MAGGIE_SCLK_R SPI_AP_TO_CODEC_CS_L
ROOM=SOC
SPI_MESA_TO_AP_MISO SPI_AP_TO_MESA_MOSI SPI_AP_TO_MESA_SCLK MESA_TO_AP_INT
I2S0_MCK I2S0_BCLK I2S0_LRCK I2S0_DIN I2S0_DOUT
C44 B44 A44 D44
B42 A42 E44 C42
U0700 CAYMAN-2GB-20NM-DDR-M CSP SYM 6 OF 16
I2C0_SCL CK7 I2C0_SDA CG12
I2C0_AP_SCL I2C0_AP_SDA
I2C1_SCL AG64 I2C1_SDA AG66
I2C1_AP_SCL I2C1_AP_SDA
I2C2_SCL U3 I2C2_SDA U4
I2C2_AP_SCL I2C2_AP_SDA
I2C3_SCL AE66 I2C3_SDA AE65
I2C3_AP_SCL I2C3_AP_SDA
47 47
47 47
47 47
47 47
SPI4_SCLK CJ12NC SPI4_MISO CG22NC SPI4_MOSI CM9NC I2C5_SCL CH16 I2C5_SDA CJ14
C I2C5_SCL I2C5_SDA
11 47 11 47
GPIO_42 CH20NC GPIO_43 CH22NC
SPI0_MISO SPI0_MOSI SPI0_SCLK SPI0_SSIN
PP1V8 1
R1113 10K
5% 1/32W MF 01005
2 ROOM=SOC
SPI1_MISO SPI1_MOSI SPI1_SCLK SPI1_SSIN
PMU_SCLK AH65 PMU_MISO AH66 PMU_MOSI AK64 DWI_CLK AK65 DWI_DO AM64
SPI2_MISO SPI2_MOSI SPI2_SCLK SPI2_SSIN
SPI_PMGR_TO_PMU_SCLK SPI_PMU_TO_PMGR_MISO SPI_PMGR_TO_PMU_MOSI
1
R1114 10K 5% 1/32W MF 01005
2 ROOM=SOC
20 20 20
DWI_PMGR_TO_BACKLIGHT_CLK DWI_PMGR_TO_BACKLIGHT_DATA
37 37
DROOP AE3 GPU_TRIGGER BY2
PMU_TO_AP_PRE_UVLO_L PMU_TO_AP_THROTTLE_GPU_L
SOCHOT AG4 SPI3_MISO SPI3_MOSI SPI3_SCLK SPI3_SSIN
5 7 8 9 11 12 13 16 17 18 25 29 39 46 47 48 52
20 20
AP_TO_PMU_SOCHOT_L
CLK32K_OUT AM66
AP_TO_CUMULUS_CLK32K
NAND_SYS_CLK BN66
AP_TO_NAND_SYS_CLK_R
20
B
39
R1118
1
0.00
2
AP_TO_NAND_SYS_CLK 17
0% 1/32W MF 01005
ROOM=SOC
I2C5
See Radar#25316444 for Details PP1V8 1
C1101 1.0UF
A1
25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39 29
VCC
20% 6.3V 2 X5R 0201-1
I2S_AP_TO_CODEC_MCLK
U1101
ROOM=SOC
B1
A
SCL
WLCSP
SDA
A2
I2C5_SDA I2C5_SCL
B2
VSS ROOM=SOC CRITICAL
I2S_AP_TO_CODEC_MCLK_R I2S_AP_TO_CODEC_MSP_BCLK I2S_AP_TO_CODEC_MSP_LRCLK I2S_CODEC_TO_AP_MSP_DIN I2S_AP_TO_CODEC_MSP_DOUT
I2C0_AP_SCL I2C0_AP_SDA
11 47 I2S_AP_TO_BT_LRCLK I2S_BT_TO_AP_DIN I2S_AP_TO_BT_LRCLK 11 47 I2S_AP_TO_BT_LRCLK I2S_BT_TO_AP_DIN I2S_AP_TO_BT_DOUT I2S_MAGGIE_TO_AP_L26_CODEC_BCLK I2S_MAGGIE_TO_AP_L26_CODEC_BCLK I2S_MAGGIE_TO_AP_DIN I2S_MAGGIE_TO_AP_L26_CODEC_BCLK I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK I2S_AP_TO_MAGGIE_DOUT I2S_MAGGIE_TO_AP_DIN I2S_AP_TO_MAGGIE_DOUT I2S_BB_TO_AP_BCLK I2S_BB_TO_AP_BCLK I2S_BB_TO_AP_BCLK I2S_BB_TO_AP_BCLK I2S_BB_TO_AP_LRCLK I2S_BB_TO_AP_DIN I2S_AP_TO_BB_DOUT
I2C2_AP_SCL I2C2_AP_SDA
I2C1_AP_SCL I2C1_AP_SDA
To Cayman
SYNC_MASTER=Sync
I2C3_AP_SCL I2C3_AP_SDA
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
I2C5_SCL I2C5_SCL I2C5_SDA I2C5_SDA I2C5_SCL I2C5_SCL I2C5_SDA I2C5_SDA
BOARD_ID2 BOARD_ID2 BOARD_ID2 BOARD_ID2
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
D
D
SOC - GPIO INTERFACES
27 36
#24557547:Delete R1204
44 20
AP_TO_ACC_BUCK_VSEL
AP_TO_MAGGIE_CRESETB_L BUTTON_VOL_UP_L DEV ONLY
53
AP_TO_BB_RESET_L
MAGGIE_TO_AP_CDONE
36
RESERVERD FOR SSHB ID ON DEV BOARD D101/D111 ONLY D101/D111 ONLY
C
53
D101/D111 ONLY
NC_AP_TO_BB_IPC_GPIO2 NC_AP_TO_GNSS_WAKE AP_TO_BB_TIME_MARK NC_AP_TO_GNSS_TIME_MARK
BB_TO_AP_RESET_DETECT_L 33 AP_TO_SPKAMP2_RESET_L 29 ALS_TO_AP_INT_L
53 29 25 18 17 16 13 11 9 8 7 5 52 48 47 46 39
PP1V8
NOSTUFF 1 Nostuff per #24511702
R1210 10K
53
5% 1/32W MF 01005
17 39
2 ROOM=SOC 20
AP_TO_NFC_FW_DWLD_REQ
AP_TO_NAND_FW_STRAP TOUCH_TO_AP_INT_L BOOT_CONFIG0
PMU_TO_AP_THROTTLE_CPU_L #24608280 53
D10/D11 ONLY
53 39 36
AP_TO_BBPMU_RADIO_ON_L AP_TO_ICEFALL_FW_DWLD_REQ AP_TO_LCM_RESET_L AP_BI_HOMER_BOOTLOADER_ALIVE BOOT_CONFIG1
20 4
Dev only 5
PMU_TO_AP_FORCE_DFU NC_DFU_STATUS PP1V8 BOARD_ID4
53
53 53
AP_TO_BB_IPC_GPIO1
53 53 5
B
AP_TO_NFC_DEV_WAKE
PMU_TO_AP_BUF_RINGER_A AP_TO_BT_WAKE AP_TO_WLAN_DEVICE_WAKE BOARD_REV3 BOARD_REV2 BOARD_REV1 BOARD_REV0 AP_TO_TOUCH_MAMBA_RESET_L AP_TO_BB_MESA_ON AP_TO_BB_COREDUMP
20
5 5 5 39 53
20 20
BB64 NC BC65 BB66 AY65 AY66 NC AV65 AV67 AT67 AT66 AT64 AP66 AP65 AH64 AE4 AC3 AE2 BB2 BB4 BC3 NC BC4 BE2 NC BE4 BE3 BG2 CJ11 CL9 NC CH14 CK11 CG20 AA2 NC AA3 D42 E42 A41 C41 E41 A39 AT4 AT2 AV3 AY2 AY3 BU2 BU3
PMU_TO_AP_BUF_POWER_KEY_L PMU_TO_AP_BUF_VOL_DOWN_L
GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GPIO_16 GPIO_17 GPIO_18 GPIO_19 GPIO_20 GPIO_21 GPIO_22 GPIO_23 GPIO_24 GPIO_25 GPIO_26 GPIO_27 GPIO_28 GPIO_29 GPIO_30 GPIO_31 GPIO_32 GPIO_33 GPIO_34 GPIO_35 GPIO_36 GPIO_37 GPIO_38 GPIO_39 GPIO_40 GPIO_41
U0700 CAYMAN-2GB-20NM-DDR-M CSP SYM 5 OF 16
TMR32_PWM0 AG2 NC TMR32_PWM1 AH4 PROX_BI_AP_AOP_INT_PWM_L AH3 TMR32_PWM2 NC_BB_TO_AP_RESET_ACT_L UART0_RXD CL5 UART0_TXD CJ7
UART_AP_DEBUG_RXD UART_AP_DEBUG_TXD
UART1_CTS* UART1_RTS* UART1_RXD UART1_TXD
E39 D39 C39 B39
UART_BT_TO_AP_CTS_L UART_AP_TO_BT_RTS_L UART_BT_TO_AP_RXD UART_AP_TO_BT_TXD
UART2_CTS* UART2_RTS* UART2_RXD UART2_TXD
AM4 AK3 AK4 AH2
NC_AP_UART2_CTS_L NC_AP_UART2_RTS_L NC_AP_UART2_RXD NC_AP_UART2_TXD
UART3_CTS* UART3_RTS* UART3_RXD UART3_TXD
AA4 W2 W4 U2
UART_NFC_TO_AP_CTS_L UART_AP_TO_NFC_RTS_L UART_NFC_TO_AP_RXD UART_AP_TO_NFC_TXD
UART4_CTS* UART4_RTS* UART4_RXD UART4_TXD
D37 C37 B37 A37
UART_WLAN_TO_AP_CTS_L UART_AP_TO_WLAN_RTS_L UART_WLAN_TO_AP_RXD UART_AP_TO_WLAN_TXD
UART5_RTXD BG4
SWI_AP_BI_TIGRIS
13 29
D101/D111 ONLY
C
40 40
53 53 53 53
D101/D111 ONLY; for GNSS
53 UART_AP_TO_BT_RTS_L 53 53 53 NC_AP_UART2_RXD NC_AP_UART2_RXD 53 53 53 53
21
B
UART6_RXD CG16 UART6_TXD CG14
UART_ACCESSORY_TO_AP_RXD UART_AP_TO_ACCESSORY_TXD
UART7_RXD AP3 UART7_TXD AM2
UART_HOMER_TO_AP_RXD UART_AP_TO_HOMER_TXD
40 40
36 36
REQUEST_DFU1 REQUEST_DFU2
#25120460:REQUEST_DFU Assignment
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
SOC - AOP D
D
PP1V8 1
U0700 CAYMAN-2GB-20NM-DDR-M
2
CSP
CM16 CM29
AOP_DDR_REQ AOP_DDR_RESET*
SPI_AOP_TO_COMPASS_CS_L COMPASS_TO_AOP_INT PROX_BI_AP_AOP_INT_PWM_L ACCEL_GYRO_TO_AOP_DATARDY SPI_AOP_TO_ACCEL_GYRO_CS_L ACCEL_GYRO_TO_AOP_INT SPI_AOP_TO_PHOSPHORUS_CS_L LCM_TO_MANY_BSYNC TRISTAR_TO_AOP_INT AOP_TO_MAGGIE_EN
AUDIO_TO_AOP_INT_L AOP_TO_MESA_I2C_ISO_EN PMU_TO_AOP_IRQ_L
CK12 CK16 CK18 CJ29 CG31 CH31 CK20 CJ31 CK27 CK24 CK29 CK22 CM12 CK31 CG33 CJ33
AOP_FUNC_0 AOP_FUNC_1 AOP_FUNC_2 AOP_FUNC_3 AOP_FUNC_4 AOP_FUNC_5 AOP_FUNC_6 AOP_FUNC_7 AOP_FUNC_8 AOP_FUNC_9 AOP_FUNC_10 AOP_FUNC_11 AOP_FUNC_12 AOP_FUNC_13 AOP_FUNC_14 AOP_FUNC_15
I2C_AOP_SCL I2C_AOP_SDA
CM11 CJ24
AOP_I2C0_SCL AOP_I2C0_SDA
CJ18 CJ27 CJ16
AOP_SPI_MISO AOP_SPI_MOSI AOP_SPI_SCLK
UART_BB_TO_AOP_RXD UART_AOP_TO_BB_TXD
CK14 CJ20
AOP_UART0_RXD AOP_UART0_TXD
MAGGIE_TO_AOP_INT UART_AOP_TO_MAGGIE_TXD
CJ22 CL11
AOP_UART1_RXD AOP_UART1_TXD
UART_TOUCH_TO_AOP_RXD UART_AOP_TO_TOUCH_TXD
CG29 CH29
AOP_UART2_RXD AOP_UART2_TXD
32
I2S_CODEC_XSP_TO_AOP_BCLK I2S_CODEC_XSP_TO_AOP_DIN I2S_AOP_TO_MAGGIE_L26_MCLK_R I2S_CODEC_XSP_TO_AOP_LRCLK
CL35 CJ39 CM35 CK37
AOP_I2S_BCLK AOP_I2S_DIN AOP_I2S_MCK AOP_I2S_LRCK
DOCK_ATTENTION CG41
32
I2S_AOP_TO_CODEC_XSP_DOUT
CG39
AOP_I2S_DOUT
DOCK_CONNECT CL37
20 15
#24512059: Remove R1300 PU
24 24
Use internal pullup in SOC (AOP side).
29 12 24 24 24
C
24 53 39 23 20 40 36 24 24 24 35 34 33 32 48
Internal pullup in AOP.
Radar 21210869
20
48 48
#25756894:North Carbon R1 (+Mg,P)
24
SPI_AOP_TO_IMU_SCLK_R1
24
49.9 2
1
1% 1/32W MF 01005
#25756894:South Carbon R2
24
SPI_AOP_TO_IMU_SCLK_R2
53
ROOM=SOC
53
R1306
36
49.9 2
1
PHOSPHORUS_TO_AOP_INT_L SPI_AOP_TO_BOT_ACCEL_GYRO_CS_L BOT_ACCEL_GYRO_TO_AOP_DATARDY
SPI_IMU_TO_AOP_MISO SPI_AOP_TO_IMU_MOSI 24 SPI_AOP_TO_IMU_SCLK
R1305
36
1% 1/32W MF 01005
39 39
ROOM=SOC
B
R1303 36 35 34 33
I2S_AOP_TO_MAGGIE_L26_MCLK
1
33.2 1% 1/32W MF 01005
ROOM=SOC
SYM 7 OF 16
AOP_TO_PMU_SLEEP1_REQUEST PMU_TO_AOP_SLEEP1_READY
20
32 32
2
CFSB_AOP CH35 AWAKE_REQ CM31 AWAKE_RESET* CJ37 AOP_PDM_CLK0 CM37 AOP_PDM_DATA0 CH41 AOP_PDM_DATA1 CK39 RT_CLK32768 CM33 AOP_SWD_TCK_OUT CL14 AOP_SWD_TMS0 AOP_SWD_TMS1 SWD_TMS2 SWD_TMS3
CL16 CG35 BU4 BV3
5 7 8 9 11 12 16 17 18 25 29 39 46 47 48 52
NOSTUFF
R1304 1.00K
5% 1/32W MF 01005
ROOM=SOC
PMU_TO_SYSTEM_COLD_RESET_L
7 20
AOP_TO_PMU_ACTIVE_REQUEST PMU_TO_AOP_TRISTAR_ACTIVE_READY
20 7 20 37 40
AOP_TO_MESA_BLANKING_EN AOP_TO_WLAN_CONTEXT_B AOP_TO_WLAN_CONTEXT_A
53
PMU_TO_AOP_CLK32K
20
SWD_AP_TO_MANY_SWCLK
17 36 53
38
53
HOMER_TO_AOP_WAKE_INT SWD_AOP_BI_BB_SWDIO SWD_AP_BI_NAND_SWDIO SWD_AP_BI_HOMER_SWDIO
C
36 53
BB_SWDIO has pullup in Radio_MLB pages
17 36
B 34 AOP_TO_SPKAMP1_ARC_RESET_L MESA_TO_AOP_FDINT 38
35
DOCK_CONNECT can be GPIO, but input only. Radar 21680759
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
SOC - CPU, GPU & SOC RAILS PP1401
PP_CPU_VAR
P2MM-NSM
14 18
SM
PP_GPU_VAR
1
PP
14 18
PP_SOC_VAR
ROOM=SOC
1.06V @17.4A MAX 0.9V @tbd A MAX 0.625V @tbd A MAX
PP1402
SM
1
PP
P2MM-NSM
PP_CPU_VAR
1
14 18
1
D
C1401
1
15UF
C1408 15UF
20% 6.3V 2 X5R 0402-1
C1434
1
15UF
20% 6.3V 2 X5R 0402-1
20% 6.3V 2 X5R 0402-1
2
C1449 2.2UF
2
ROOM=SOC
C1404
C1411
7.5UF 1
20% 4V CERM 0402
C1417
7.5UF
3
1
20% 4V CERM 0402
2 4
3
1
20% 4V CERM 0402
3
1
20% 4V CERM 0402
4.3UF 3
ROOM=SOC
ROOM=SOC
C1418
C1423
4.3UF
4.3UF
1UF
1UF 20%
1
3
1
2 4
3
1
2 4
20% 4V CERM 0402
1
3
2 4
3
3
C1428 1
2 4
20% 4V CERM 0402
3
2 4
ROOM=SOC
20% 4V CERM 0402
C1430 1
1UF
4V CERM 0402 1
ROOM=SOC
4.3UF
2 4
C1412 20% 4V CERM 0402
20% 4V CERM 0402
2 4
C1405 20% 4V CERM 0402
C1427
4.3UF
2 4
ROOM=SOC
ROOM=SOC
C1422
7.5UF
2 4
ROOM=SOC
ROOM=SOC
ROOM=SOC
C1431 1UF
20% 4V CERM 0402 1
3
2 4
3
2 4
C ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
C1406
C1413
C1419
C1424
C1460
0.47UF
0.47UF
0.47UF
0.47UF
7.5UF
1
20% 6.3V CERM 0402
3
1
20% 6.3V CERM 0402
2 4
3
1
2 4
20% 6.3V CERM 0402
3
1
2 4
20% 6.3V CERM 0402
3
1
20% 4V CERM 0402
2 4
2 4
ROOM=SOC
C1461 7.5UF
3
20% 4V CERM 0402 1
3
2 4
AD10 AD15 AD19 AD23 AF13 AF17 AJ23 AL21 AL8 AN10 AN19 AN23 AR13 AR17 AR21 AU10 AU15 AW13 AW17 AW21 BA10 BA23 BD21 BD8 BF10 BF23 BH13 BH17 BH21 BK10 BK15 AJ10
U0700 CAYMAN-2GB-20NM-DDR-M CSP SYM 8 OF 16
VDD_CPU
VDD_GPU
OMIT
XW1402
BUCK0_PP_CPU_FB
18
1.06V @1.0A MAX 0.80V @TBDA MAX
ROOM=SOC
ROOM=SOC
ROOM=SOC
4
3 2
1
3
ROOM=SOC
4
PP_GPU_SRAM_VAR ROOM=SOC
ROOM=SOC
C1439
C1437 7.5UF
7.5UF 20% 4V CER 0402
1
3 2 4
1
20% 4V CERM 0402
3
1
C1459
10UF
20% 2 6.3V CERM-X5R 0402-9 ROOM=SOC
ROOM=SOC
XW1403
SHORT-20L-0.05MM-SM 1 2
ROOM=SOC
BUCK2_PP_SOC_FB
D
18
ROOM=SOC
C1414
1
20% 6.3V X5R 0402-1
2
15UF
2
ROOM=SOC
ROOM=SOC
C1402 4.3UF 1
20% 4V CERM 0402
3
C1466 2.2UF
1
20% 6.3V X5R-CERM 0201-1
ROOM=SOC
C1409
2 4
AF43 AF47 AF51 P17 P21 P25 P30 P34 P38 P43 P47 P51 Y15 Y19 Y23 Y40 Y45 Y49 Y53
ROOM=SOC
ROOM=SOC
ROOM=SOC
ROOM=SOC
C1454
C1416
C1421
C1426
4.3UF
4.3UF
7.5UF
7.5UF
7.5UF
1
2 4
20% 4V CERM 0402
3
1
20% 4V CERM 0402
2 4
ROOM=SOC
ROOM=SOC
1
1UF
3
1
20% 4V CERM 0402
2 4
2 4
1
20% 4V CERM 0402
3
1
2 4
C1415
1UF
20% 4V CERM 0402
3
2 4
C1410
3
20% 4V CERM 0402
3
1
2 4
20% 4V CERM 0402
3
1
2 4
20% 4V CERM 0402
3
2 4
C1425
ROOM=SOC
C1429
C1456
ROOM=SOC
C1457
1UF
0.47UF
0.47UF
0.47UF
0.47UF
20% 4V CERM 0402 1
3
2 4
1
20% 6.3V CERM 0402
ROOM=SOC
3
1
2 4
20% 6.3V CERM 0402
2 4
3
1
20% 6.3V CERM 0402
2 4
3
ROOM=SOC
1
20% 6.3V CERM 0402
3
2 4
AP_VDD_CPU_SENSE 20 1
PP
SM
VDD_GPU_SRAM
VSS_SENSE AJ47
PP1403 P2MM-NSM
1
SM PP
PP1408 P2MM-NSM ROOM=SOC
ROOM=SOC
VDD_GPU_SENSE AJ45 VDD_SOC_SENSE AL47
AP_VDD_GPU_SENSE 20 1
TP_VDD_SOC_SENSE
PP SM
PP1410 P2MM-NSM ROOM=SOC
1
TP_VSS_SENSE
C1442
7.5UF
0.47UF
20% 4V CERM 0402
3
1
20% 4V CERM 0402
3
1
2 4
20% 4V CERM 0402
2 4
3
1
20% 6.3V CERM 0402
3
2 4
C1432 7.5UF
ROOM=SOC
C1420
VDD_CPU_SENSE BK23
TP_AP_VSS_CPU_SENSE
C1440
1UF
ROOM=SOC
VDD_CPU_SRAM
VSS_CPU_SENSE BK21
C1438
2 4
C1452
4.3UF 3
ROOM=SOC
ROOM=SOC
ROOM=SOC
1
ROOM=SOC
4.3UF 1
20% 6.3V X5R-CERM 0201-1
2
ROOM=SOC
20% 4V CERM 0402
C1448 2.2UF
ROOM=SOC
C1465 14 18
2 4
1.03V @1.44A MAX 0.92V @1.50A MAX 0.80V @TBD A MAX 18
1
PP_GPU_VAR
AD28 AD32 AF60 AJ28 AJ32 AJ36 AL6 AN28 AN32 AN36 AN40 AN45 AN49 AN53 AN58 AR25 AR30 AR34 AR38 AR43 AR47 AR51 AR55 AW30 AW34 AW38 AW43 AW47 AW51 AW55 AW60 BD25 BD30 BD34 BD38 BD43 BD47 BD51 BD55 BD6 BD60 BF28 BF32 BF36 BF45 BF49 BF53 BF58 BK28 BK32 BK36 BK40
=
1
10UF
20% 2 6.3V CERM-X5R 0402-9
20% 6.3V CERM-X5R 0402-9
OMIT
10UF
20% 6.3V 2 CERM-X5R 0402-9
ROOM=SOC
||=
2
3
20% 4V CERM 0402
2
C1403
MAX MAX MAX MAX
-|
7.5UF
20% 4V CER 0402
NO_XNET_CONNECTION
@12.9A @10.7A @TBD A @TBD A
|-
7.5UF
ROOM=SOC
1.03V 0.92V 0.80V 0.67V
18
|||
7.5UF
C1458
1
OMIT
BUCK1_PP_GPU_FB
2
|||
C1433
1
--
AF8 AN15 AR8 AU19 AW8 BA15 BA19 BH8
AB13 AB17 AB21 AB25 AB43 AB47 AB51 AB55 AD40 AD45 AD49 AD53 AF55 AJ40 AJ49 AJ53 J25 J30 J38 J43 J47 J51 L15 L19 L23 L28 L32 L36 L40 L45 L49 L53 P13 T15 T36 T40 T53 V13 V25 V34 V38 V51 V55 Y28
|-
C1435
1
B
ROOM=SOC
C1407 20% 4V CERM 0402
SHORT-20L-0.05MM-SM 2 1 NO_XNET_CONNECTION
PP_CPU_SRAM_VAR
18
10UF
1
XW1401
ROOM=SOC
ROOM=SOC
C1444
0.80V @4.1A MAX 0.67V @TBDA MAX
NO_XNET_CONNECTION
SHORT-20L-0.05MM-SM
ROOM=SOC
20% 6.3V CERM-X5R 0402-9 ROOM=SOC
20% 6.3V X5R-CERM 0201-1
1
10UF
ROOM=SOC
1
C1436
18
PP
SM
1
SM PP
PP1409 P2MM-NSM ROOM=SOC
PP1411
P2MM-NSM ROOM=SOC
U0700 CAYMAN-2GB-20NM-DDR-M CSP
SYM 9 OF 16
VDD_SOC
VDD_SOC
BK45 BK49 BK53 BM55 BP15 BP19 BP23 BP28 BP32 BP36 BP40 BP45 BP49 BP53 BP58 BT13 BT17 BT21 BT25 BT30 BT34 BT38 BT43 BT47 BT51 BT55 BW10 CA13 CA17 CA21 CA25 CA30 CA34 CA38 CA43 CA47 CE13 CE17 CE45 J13 J21 J34 P55 T10 T60 V30 Y10 Y36 Y60 BF40 J60
C
B
AW25
2 4
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
SOC - POWER SUPPLIES DDR IMPEDANCE CONTROL 18 15 7
1.06-1.17V @0.85A MAX 18 15 7
PP1V1
D
1 1
1
C1506 10UF
C1528 10UF
20% 6.3V 2 CERM-X5R 0402-9
20% 6.3V 2 CERM-X5R 0402-9 ROOM=SOC
ROOM=SOC
1
2
C1518 2.2UF
20% 6.3V X5R-CERM 0201-1 ROOM=SOC
TBD-TBDV @1.9A MAX
PP0V9_SOC_FIXED
18 10 9 8 7
ROOM=SOC
C1502
C1527
4.3UF
1UF
1
20% 4V CERM 0402
3
20% 4V CERM 0402 1
ROOM=SOC
C1503 7.5UF 20% 4V CERM 0402 1
3
2 4
C1501 10UF
2
20% 6.3V CERM-X5R 0402-9
ROOM=SOC
C
B
0.797-0.945V @9 mA MAX 0.765-0.840V @60mA MAX 19
PP0V8_AOP 1
C1504 2.2UF
AW23 CC36 CE30 CE40
U0700 CAYMAN-2GB-20NM-DDR-M CSP SYM 10 OF 16
VDD_FIXED
VDD_FIXED
BK6 BM13 BM17 BM21 BM25 BM30 BM34 BM38 BM43 BM47 BM51 BP10 BP60 BW15 BW19 BW23 BW28 BW32 BW36 BW40 BW45 BW49 BW53 BW58 BW8 CC10 CC15 CC19 CC23 CC28 CC32 CC45 G32 G36 J17 J23 J55 J62 L10 L58 L60 T32 T58 T8 Y58 Y8
2
C1519 2.2UF 20% 6.3V X5R-CERM 0201-1
ROOM=SOC
1
C1514 2.2UF
20% 6.3V 2 X5R-CERM 0201-1 ROOM=SOC
1
2
C1522 2.2UF 20% 6.3V X5R-CERM 0201-1
ROOM=SOC
1% 1/32W MF 2 01005
ROOM=SOC
BE1 BJ1 BL1 BM8 BP6 BT8 BW6 CA8 CC6 CD1 CH1
BE67 BH60 BJ67 BK62 BL67 BM60 BP62 BT60 BW62 CD67 CH67
AB8 AC1 AE1 AH1 E1 K1 L6 P8 T6 V8 Y6
AB60 AC67 AD62 AE67 AH67 E67 K67 P60 T62 V60 Y62
VDD_FIXED_CPU
VDD_LOW
R1501
240
U0700 CAYMAN-2GB-20NM-DDR-M CSP VDDIO11_DDR0
SYM 11 OF 16
1
CD3 BY64 K3 K65
DDR0_RREF DDR1_RREF DDR2_RREF DDR3_RREF
DDR0_ZQ DDR3_ZQ
BN2 AA66
DDR0_ZQ DDR3_ZQ
DDR0_RET* DDR1_RET* DDR2_RET* DDR3_RET*
CF3 CB65 K4 K64
PMU_TO_AOP_SLEEP1_READY
VDDIO11_PLL_DDR0 VDDIO11_PLL_DDR1 VDDIO11_PLL_DDR2 VDDIO11_PLL_DDR3
CE8 BW60 J8 P58
R1502 240
1% 1/32W MF 2 01005
DDR0_RREF DDR1_RREF DDR2_RREF DDR3_RREF
1
1
R1503
240
1% 1/32W MF 2 01005
ROOM=SOC
R1504
1
240
ROOM=SOC
R1505
1
240
1% 1/32W MF 2 01005
R1506
D
240
1% 1/32W MF 01005
1% 1/32W MF 01005
2 ROOM=SOC
ROOM=SOC
2 ROOM=SOC
13 20
FL1501 100OHM-25%-0.12A
1.06 - 1.17V @4mA MAX
|- - ||- - ||- | |- | |- || = |- | ||- |- |||= |||| ||||| ||- - - - ||| |||| - - - ||| - - | ||| |-
2 4
3
AB30 AB34 AB38 AD58 AF25 AF30 AF34 AF38 AF62 AJ58 AL25 AL30 AL34 AL38 AL43 AL51 AL55 AL60 AR60 AU28 AU32 AU36 AU40 AU45 AU49 AU53 AU58 AU6 BA28 BA32 BA36 BA40 BA45 BA49 BA53 BA58 BH25 BH30 BH34 BH38 BH43 BH47 BH51 BH55 BK58
1
=|
2 4
1
ROOM=SOC
PP1V1
PP1V1_DDR_PLL 1
C1508
1
0.22UF
2
20% 6.3V X5R 01005-1
1
C1509
1
0.22UF
2
ROOM=SOC
20% 6.3V X5R 01005-1
C1523
1
C1510
0.22UF
2
ROOM=SOC
20% 6.3V X5R 01005-1
PP1V1
2
7 15 18
01005
ROOM=SOC
0.22UF
20% 6.3V X5R 01005-1
2
ROOM=SOC
ROOM=SOC
VDDIO11_DDR1 VDDIO11_RET_DDR0 VDDIO11_RET_DDR1 VDDIO11_RET_DDR2 VDDIO11_RET_DDR3
CG3 CD65 H4 H64
DDR0_SYS_ALIVE DDR1_SYS_ALIVE DDR2_SYS_ALIVE DDR3_SYS_ALIVE
CF4 CB64 H3 H65
VDDIO11_DDR2
VDD2
VDDIO11_DDR3
AM3 AM65 BB3 BB65 BR1 BR67 BV1 BV67 BY1 BY67 C2 C66 CJ2 CJ66 CK2 CK66 D2 D66 N1 N67 R1 R67 W1 W67
C
(CURRENT INCLUDED IN VDD2)
PP1V1_SDRAM
15 18 19
SYSTEM_ALIVE
17 20 21
1.06 - 1.17V @1.74A MAX
PP1V1_SDRAM 1
C1512
2
20% 6.3V CERM-X5R 0402-9
1
10UF
ROOM=SOC
C1513
1
C1507
2
20% 6.3V X5R-CERM 0201-1
10UF
2
20% 6.3V CERM-X5R 0402-9
ROOM=SOC
1
C1529
2
20% 6.3V X5R-CERM 0201-1
2.2UF
ROOM=SOC
2.2UF
ROOM=SOC
1
C1511 2.2UF
20% 2 6.3V X5R-CERM 0201-1 ROOM=SOC
1
B
15 18 19
C1515 2.2UF
20% 2 6.3V X5R-CERM 0201-1 ROOM=SOC
20% 6.3V 2 X5R-CERM 0201-1 ROOM=SOC
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
2
3
1
SOC - POWER SUPPLIES CSP
SYM 13 OF 16
SYM 14 OF 16
SYM 15 OF 16
VSS
VSS
U0700
|- - ||- - ||- | |- | - || ||- |- | |== - - |- || ||| |||| - | ||||| ||||||| - - ||- - ||- | - - | |
VSS
CSP
=|
VSS
CAYMAN-2GB-20NM-DDR-M
D20 D22 D24 D26 D27 D29 D3 D31 D35 D4 D41 D46 D5 D52 D56 D59 D63 D65 D67 D7 D9 E12 E14 E18 E2 E20 E22 E26 E27 E29 E3 E37 E4 E5 E54 E57 E59 E61 E64 E65 E66 E7 E9 F1 F2 F3 F4 F64 F65 F66 F67 G38 G43 G47 G51 G8 H1 H2 H66 H67 J10 J15 J19 J28 J32 J40 J45 J49 J53 J6 K2 K66 L13 L17 L21 L25 L30 L34
CAYMAN-2GB-20NM-DDR-M CSP
SYM 16 OF 16
|- - ||- - ||- | |- | |- || = |- | ||- |- |||= |||| ||||| ||- - - - ||| |||| - - - ||| - - | ||| |-
VSS
|- - ||- - ||- | |- | - || ||- |- | |== - - |- || ||| |||| - | ||||| ||||||| - - ||- - ||- | - - | |
=|
|- - ||- - ||- | |- | - || ||- |- | |== - - |- || ||| |||| - | ||||| ||||||| - - ||- - ||- | - - | |
=|
|- - ||- - ||- | |- | - || ||- |- | |== - - |- || ||| |||| - | ||||| ||||||| - - ||- - ||- | - - | |
=|
VSS
L38 L43 L47 L51 L55 L62 L8 M1 M2 M3 M4 M64 M65 M66 M67 P10 P15 P19 P23 P28 P32 P36 P40 P45 P49 P53 P6 P62 R2 R4 R64 R66 T13 T25 T34 T38 T51 T55 U1 U67 V10 V15 V28 V32 V36 V40 V53 V58 V6 V62 W3 W65 Y13 Y17 Y21 Y25 Y30 Y43 Y47 Y51 Y55 BF38 J58
1.70-1.95V @134mA 47 41 40 37 36 32 21 20 18 16 53 52 48
MAX
PP1V8_SDRAM 1
2
C1615 2.2UF
1
20% 6.3V X5R-CERM 0201-1
2
ROOM=SOC
C1605 2.2UF
20% 6.3V X5R-CERM 0201-1
1
2
ROOM=SOC
C1608 2.2UF
1
20% 6.3V X5R-CERM 0201-1
2
ROOM=SOC
C1612 2.2UF
20% 6.3V X5R-CERM 0201-1
ROOM=SOC
1.62-1.98V @43mA MAX 29 25 18 17 13 12 11 9 8 7 5 52 48 47 46 39
PP1V8 1
C1602 10UF
1
20% 6.3V 2 CERM-X5R 0402-9
2
ROOM=SOC
C1607 2.2UF
20% 6.3V X5R-CERM 0201-1
1
2
ROOM=SOC
C1610 2.2UF
1
20% 6.3V X5R-CERM 0201-1
2
ROOM=SOC
C1614 2.2UF
20% 6.3V X5R-CERM 0201-1
ROOM=SOC
AM1 AM67 BB1 BB67 C3 C65 CK3 CK65
AJ62 AN62 AU62 BA62 BF62 G40 G45 G49 G53 AD6 AJ6 AN6 BA6 BF6 CE19 CE23
47 41 40 37 36 32 21 20 18 16 53 52 48
1.62-1.98V @10mA
PP1V8_SDRAM 1
C1603 2.2UF 20% 6.3V X5R-CERM 0201-1
2
ROOM=SOC
19
1
2
MAX
CE28 CE32 CE34 CE36 CE43 CE38
C1601 0.1UF 20% 6.3V X5R-CERM 01005
ROOM=SOC
PP1V2_REF 1 2
19 10 8
PP1V2_SOC
1
0.00
2
VDD1
CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND
VDD18_EFUSE1 CG7 VDD18_EFUSE2 G34
VDDIO18_GRP1
VDDIO18_GRP2
VDDIO18_GRP3
VDDIO18_GRP4
C VDDIO18_GRP10
VDD18_FMON
1.62-1.98V @1mA MAX
CC40
VDD18_LPOSC
TBD-TBDV @30mA MAX
AU23 T28 Y38
VDD12_CPU_UVD VDD12_GPU_UVD VDD12_SOC_UVD
BA25
VDD12_PLL_CPU
C1611 20% 6.3V X5R-CERM 0201-1
Y32 AD36 AD38 Y34
MAX
D
SYM 12 OF 16
CG9
PP1V2_PLL_CPU 1
CSP
1.62-1.98V @1mA MAX
VDD12_PLL_CPU:1.14-1.26V @13mA
0% 1/32W MF 01005
CAYMAN-2GB-20NM-DDR-M
AR23 BK19 AF21 J36 CE21 BF60
ROOM=SOC
R1602
U0700
1.62-1.98V @2mA MAX
2.2UF
VDD18_TSADC0 VDD18_TSADC1 VDD18_TSADC2 VDD18_TSADC3 VDD18_TSADC4 VDD18_TSADC5
VDD12_PLL_SOC
B
C1606 0.1UF
ROOM=SOC
20% 2 6.3V X5R-CERM 01005 ROOM=SOC
R1601 1
C1604 2.2UF 20% 6.3V X5R-CERM 0201-1
1
0.00
2
VDD12_PLL_SOC:1.14-1.26V @31mA
PP1V2_PLL_SOC
0% 1/32W MF 01005
MAX 1
C1609
0.1UF
ROOM=SOC
20% 2 6.3V X5R-CERM 01005
2
ROOM=SOC
|- - ||- - ||- | |- | - || ||- |- | |== - - |- || ||| |||| - | ||||| ||||||| - - ||- - ||- | - - | |
=|
AW45 AW49 AW53 AW58 AW6 AW62 AY1 AY4 AY64 AY67
CSP
U0700
CH5 CH52 CH54 CH56 CH59 CH61 CH63 CH64 CH65 CH66 CH7 CH9 CJ1 CJ3 CJ4 CJ41 CJ42 CJ46 CJ5 CJ50 CJ54 CJ57 CJ61 CJ64 CJ65 CJ67 CK4 CK41 CK42 CK46 CK5 CK50 CK54 CK57 CK61 CK64 CL1 CL12 CL18 CL24 CL27 CL3 CL33 CL39 CL4 CL41 CL44 CL48 CL52 CL56 CL59 CL63 CL65 CL67 CL7 CM18 CM2 CM24 CM27 CM39 CM4 CM41 CM44 CM48 CM5 CM52 CM56 CM59 CM63 CM66 D1 D11 D12 D14 D16 D18
=|
VSS
CAYMAN-2GB-20NM-DDR-M
CA15 CA19 CA23 CA28 CA32 CA36 CA40 CA45 CA49 CA53 CA58 CA6 CA62 CB1 CB3 CB66 CB67 CC13 CC17 CC21 CC30 CC34 CC38 CC43 CL22 T30 CC8 CD2 CD4 CD64 CD66 CE10 CE15 CE47 CE53 CE6 CE62 CF1 CF2 CF64 CF65 CF66 CF67 CG1 CG11 CG2 CG24 CG27 CG4 CG42 CG44 CG46 CG48 CG5 CG52 CG54 CG56 CG59 CG61 CG64 CG65 CG66 CG67 CH12 CH18 CH2 CH24 CH27 CH3 CH33 CH39 CH4 CH42 CH44 CH46 CH48
|- - ||- - ||- | |- | |- || = |- | ||- |- |||= |||| ||||| ||- - - - ||| |||| - - - ||| - - | ||| |-
VSS
U0700
BL66 BM10 BM15 BM19 BM23 BM28 BM32 BM36 BM40 BM45 BM49 BM53 BM58 BM6 BM62 BN1 BN67 BP13 BP17 BP21 BP25 BP30 BP34 BP38 BP43 BP47 BP51 BP55 BP8 BR3 BR65 BT10 BT15 BT19 BT23 BT28 BT32 BT36 BT40 BT45 BT49 BT53 BT58 BT6 BT62 BU1 BU67 BV2 BV4 BV64 BV66 BW13 BW17 BW21 BW25 BW30 BW34 BW38 BW43 BW47 BW51 CE51 BY65 C11 C14 C18 C22 C26 C29 C33 C35 C4 C52 C54 C57 C61 C64 C7 CA10
=|
B
CAYMAN-2GB-20NM-DDR-M
B1 B3 B35 B41 B46 B52 B65 B67 BA13 BA17 BA21 BA30 BA34 BA38 BA43 BA47 BA51 BA55 BA60 BA8 BC1 BC2 BC66 BC67 BD10 BD23 BD28 BD32 BD36 BD40 BD45 BD49 BD53 BD58 BD62 BF21 BF25 BF30 BF34 BF43 BF47 BF51 BF55 BF8 BG1 BG3 BG65 BG67 BH10 BH15 BH19 BH23 BH28 BH32 BH36 BH40 BH45 BH49 BH53 BH58 BH6 BH62 BK13 BK17 AL49 BK25 BK30 BK34 BK38 BK43 BK47 BK51 BK55 BK60 BK8 BL2 BL4 BL64
|- - ||- - ||- | |- | |- || = |- | ||- |- |||= |||| ||||| ||- - - - ||| |||| - - - ||| - - | ||| |-
C
U0700
AL23 AL28 AL32 AL36 AL40 AL45 AL53 AL58 AL62 AN13 AN17 AN21 AN25 AN30 AN34 AN38 AN43 AN47 AN51 AN55 AN60 AN8 AP1 AP4 AP64 AP67 AR10 AR15 AR19 AR28 AR32 AR36 AR40 AR45 AR49 AR53 AR58 AR6 AR62 AT1 AT3 AT65 AU13 AU17 AU21 AU25 AU30 AU34 AU38 AU43 AU47 AU51 AU55 AU60 AU8 AV1 AV2 AV4 AV64 AV66 AW10 AW15 AW19 CH50 AW28 AW32 AW36 AW40
=|
D
A12 A16 A2 A20 A24 A27 A31 A35 A5 A52 A56 A59 A63 A66 A9 AA1 AA67 AB10 AB15 AB19 AB23 AB28 AB32 AB36 AB40 AB45 AB49 AB53 AB58 AB6 AB62 AC2 AC4 AC64 AC66 AD13 AD17 AD21 AD25 AD30 AD34 AD43 AD47 AD51 AD55 AD60 AD8 AF10 AF15 AF19 AF23 AF28 AF32 AF36 AF40 AF45 AF49 AF53 AF58 AF6 AG1 AG3 AG65 AG67 AJ21 AJ25 AJ30 AJ34 AJ38 AJ43 AL10 AJ51 AJ55 AJ8 AK1 AK2 AK66 AK67
ROOM=SOC
1
C1613 0.1UF
20% 2 6.3V X5R-CERM 01005 ROOM=SOC
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7 315mA 25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39 29
6
MAX
R1703 24.9
PP1V8
1
5
C1726 2.2UF
1
ROOM=NAND
20% 6.3V X5R-CERM 0201-1
2 17
1
2
C1701 15UF
1
20% 6.3V X5R 0402-1
C1741
1
1.0UF
1.0UF
20% 2 6.3V X5R 0201-1
ROOM=NAND
1
ROOM=NAND
C1708
1
220PF
20% 6.3V X5R 0402-1
2
2
20% 6.3V X5R-CERM 01005
2
ROOM=NAND
C1729 15UF 20% 6.3V X5R 0402-1
1
2
ROOM=NAND
C1743
1
1
1.0UF
C1745
ROOM=NAND
1 2
ROOM=NAND
C1711
1
C1717
16V CERM 01005 ROOM=NAND
2 16V NP0-C0G 01005 ROOM=NAND
2
C1705 15UF
1
C1722
2
20% 6.3V X5R 0402-1
1
68PF 5%
C1723
17 8
20% 6.3V X5R 0402-1
17 8
D
90_PCIE_AP_TO_NAND_REFCLK_P 90_PCIE_AP_TO_NAND_REFCLK_N
PP1701 P2MM-NSM
SM
1
PP
ROOM=NAND
PP1702 P2MM-NSM
SM
1
PP
ROOM=NAND
C1747 1.0UF 20% 6.3V X5R 0201-1
ROOM=NAND
1
39PF 5%
16V NP0-C0G 01005 ROOM=NAND
C1730 15UF ROOM=NAND
1.0UF
20% 2 6.3V X5R 0201-1
20% 2 6.3V X5R 0201-1
22PF 5%
5% 2 10V C0G-CERM 01005 ROOM=NAND
19
1
ROOM=NAND
20% 2 6.3V X5R 0201-1
1
PROBE POINTS
C1707 15UF
2
C1739
2
C1710 0.1UF
1
ROOM=NAND
NAND_AGND
ROOM=NAND
1
3
PP1V8_NAND_AVDD
2
1% 1/32W MF 01005
D
4
2
C1712 100PF 5% 16V NP0-C0G 01005
ROOM=NAND
PP0V9_NAND 1007mA
MAX 1
2
C
C1704 15UF
1
20% 6.3V X5R 0402-1
C1702 15UF 20% 6.3V X5R 0402-1
2
ROOM=NAND
1
2
ROOM=NAND
15UF
20% 6.3V X5R 0402-1
ROOM=NAND
ROOM=NAND
1
C1727 15UF
20% 6.3V 2 X5R 0402-1
#24543147:10uF for 32GB #26326159:10uF for C1719
ROOM=NAND
OMIT
1.0UF
20% 2 6.3V X5R 0201-1
5% 16V NP0-C0G 01005
2
ROOM=NAND
ROOM=NAND
C1714
2
5% 10V C0G-CERM 01005
1
220PF
C1720 100PF
2
ROOM=NAND
5% 16V NP0-C0G 01005
20% 6.3V 2 X5R 0402-1
1.0UF
20% 2 6.3V X5R 0201-1
1
1
C1728 68PF
20% 2 6.3V X5R 0201-1
1
C1715 220PF
10% 6.3V X5R 01005
ROOM=NAND
C1725
PCI_AVDD_CLK1 PCI_AVDD_CLK2
1
0.01UF
2
20% 6.3V 2 X5R 0402-1
10% 6.3V X5R 01005
ROOM=NAND
C1750
1
2
1
C1718
2
2
1
1
20% 6.3V X5R 0201-1
20% 2 6.3V X5R 0201-1
C1731
2
ROOM=NAND
C1752
1
2
1
39PF
2
2
ROOM=NAND
C1733 15UF
20% 6.3V X5R 0402-1
ROOM=NAND
C1753
1
20% 6.3V X5R 0201-1
2
C1754 1.0UF 20% 6.3V X5R 0201-1
ROOM=NAND
C1734
1
5% 16V NP0-C0G 01005
5% 10V 2 C0G-CERM 01005
100PF
5% 16V NP0-C0G 01005
ROOM=NAND
20% 6.3V X5R 0402-1
ROOM=NAND
C1732
2
1
1.0UF
ROOM=NAND
1
C1721
ROOM=NAND
1.0UF
68PF
5% 16V NP0-C0G 01005
2
ROOM=NAND
C1751
OMIT
15UF
20% 6.3V CERM-X5R 0402-9
ROOM=NAND
22PF
5% 2 16V CERM 01005
20% 6.3V X5R 0402-1
1
10UF
1.0UF
ROOM=NAND
1
C1719
1
ROOM=NAND
1.0UF
20% 2 6.3V X5R 0201-1
C1716 15UF
ROOM=NAND
ROOM=NAND
NAND_VREF
1
15UF
PP3V0_NAND
OMIT
ROOM=NAND
C1735 220PF
ROOM=NAND
1
C1736 100PF
5% 2 16V NP0-C0G 01005
ROOM=NAND
OA0 OA10 OD0 OD10 OG0 OG10
2
C1724 0.01UF
OMIT
C
MAX (1us peak power)
VCC VCC VCC VCC VCC VCC
1
5% 2 10V C0G-CERM 01005
C1713
1
ROOM=NAND
ROOM=NAND
PP1V8
B
C1749 1.0UF
5% 2 16V NP0-C0G 01005
ROOM=NAND
OMIT
ROOM=NAND
ROOM=NAND
A5 OB0 OB10 OF0 OF10 R5
25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39 29
ROOM=NAND
1
100PF
5% 16V 2 CERM 01005
ROOM=NAND
ROOM=NAND
C1748 15UF
VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO
22PF
C1709
20% 2 6.3V X5R 0201-1
20% 2 6.3V X5R 0201-1
1
C1746
A3 A7 F2 J1 J9 R3 R7
5% 10V 2 C0G-CERM 01005
1
1.0UF
1
VDD VDD VDD VDD VDD VDD VDD
220PF
C1706
1.0UF
C1744
E5
1
1
VREF
C1703
ROOM=NAND
C1742
C3
ROOM=NAND
1
AVDD1
20% 2 6.3V X5R 0201-1
ROOM=NAND
C1740
K4 K6
1.0UF
20% 2 6.3V X5R 0201-1
1
1
PCI_VDD1 PCI_VDD2
1.0UF
C1738
J7
1
PCI_AVDD_H
C1737
M4 J5
1
1230mA
B
U1701
THGBX6T1T82LFXF VLGA
8
1
R1704 3.01K
1% 1/32W MF 01005
8 8
90_PCIE_AP_TO_NAND_REFCLK_P 90_PCIE_AP_TO_NAND_REFCLK_N
H8 H6
PCIE_REFCLK_P PCIE_REFCLK_M
PCIE_NAND_BI_AP_CLKREQ_L
G9
PCIE_CLKREQ*
PCIE_NAND_RESREF
M6
PCI_RESREF
90_PCIE_AP_TO_NAND_TXD_P 90_PCIE_AP_TO_NAND_TXD_N
M8 K8
PCIE_RX0_P PCIE_RX0_M
N5 N3
PCIE_RX1_P PCIE_RX1_M
P8 N7
PCIE_TX0_P PCIE_TX0_M
NC NC
2 ROOM=NAND 8 8
90_PCIE_NAND_TO_AP_RXD_P 90_PCIE_NAND_TO_AP_RXD_N
M2 NC K2 NC
7
AP_TO_NAND_RESET_L
A
NC
BOMOPTION=OMIT_TABLE
CRITICAL
RESET*
D8
TRST* ZQ
R1701 34.8
0.5% 1/32W MF 01005
17
2 ROOM=NAND
EXT_D0 EXT_D1 EXT_D2 EXT_D3 EXT_D4 EXT_D5 EXT_D6 EXT_D7
G3 J3 H2 E3 E7 F6 C7 B8
EXT_NCE
G1
EXT_NRE
F4
SWD_AP_BI_NAND_SWDIO_R
ROOM=NAND
EXT_NWE
C5
SWD_AP_NAND_SWCLK_R
ROOM=NAND
EXT_RNB
G5
EXT_CLE
H4
EXT_ALE
D4
PMU_TO_NAND_LOW_BATT_BOOT_L AP_TO_NAND_FW_STRAP NC NC NC NC NC
20 12
SYSTEM_ALIVE
15 20 21
PCIE_AP_TO_NAND_RESET_L
8
1 1/32W 0%
1/32W
1 0%
0.00 R1702 2 01005 MF 0.00 R1707 2
01005
SWD_AP_BI_NAND_SWDIO 13 SWD_AP_TO_MANY_SWCLK 13
MF
36 53
NC NC
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
B2
1
ROOM=NAND
PCIE_TX1_P PCIE_TX1_M
F8
D6
NAND_ZQ
VER-1
spare
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
17 8
CLK_IN
DRAWING NUMBER
B4 B6 OE10 G7 L3 L5 L7 P2 P4 P6 OC0 OC10 OE0
17 8
AP_TO_NAND_SYS_CLK
VSSA
11
D2
Apple Inc.
051-00419
REVISION
R
NAND_AGND
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4 L1806
10UF
D 1
C1875 2.2UF
20% 6.3V 2 X5R-CERM 0201-1
C1876 2.2UF
20% 2 6.3V X5R-CERM 0201-1 ROOM=PMU
10UF
C1853 10UF
20% 2 6.3V CERM-X5R 0402-9
20% 2 6.3V CERM-X5R 0402-9
ROOM=PMU
ROOM=PMU
ROOM=PMU
1
C1847
1
2.2UF
C1848
1
2.2UF
C1852
1
ROOM=PMU
2
1
2.2UF
C1855
1
2
ROOM=PMU
C1858 20% 6.3V X5R-CERM 0201-1
A17 B17 C17 D17
C1859 2.2UF 20%
A13 B13 C13 D13
6.3V 2 X5R-CERM 0201-1 ROOM=PMU
C1849
1
2.2UF 20%
20% 2 6.3V X5R-CERM 0201-1
A9 B9 C9 D9
ROOM=PMU
ROOM=PMU
C1877
A5 B5 C5 D5
2.2UF
20% 2 6.3V X5R-CERM 0201-1
ROOM=PMU
1
C1854
1
2.2UF
20% 2 6.3V X5R-CERM 0201-1
20% 6.3V CERM-X5R 0402-9 ROOM=PMU
ROOM=PMU
2.2UF
20% 2 6.3V X5R-CERM 0201-1
2
20% 6.3V 2 X5R-CERM 0201-1
ROOM=PMU
C1857
BUCK0_LX1
10UF
2.2UF
20% 6.3V 2 X5R-CERM 0201-1
ROOM=PMU
1
C1851
1
2.2UF
20% 6.3V 2 X5R-CERM 0201-1
1
BAT/USB
1
20% 2 6.3V CERM-X5R 0402-9
ROOM=PMU
1
C1850
H1 H2 H3
C1856 2.2UF 20%
6.3V X5R-CERM 0201-1
2
ROOM=PMU
6.3V X5R-CERM 0201-1
ROOM=PMU
C
D10/D101:#24681501,TY ONLY, D11/D11: Both Vendor
BUCK0_LX2 VDD_BUCK0_23
BUCK0_LX3 VDD_BUCK1_01 BUCK0_FB VDD_BUCK1_23
VDD_BUCK2
VDD_BUCK3
M1 M2 M3
VDD_BUCK4
B1 C1 D1
VDD_BUCK5
K18 K19
VDD_BUCK6
U6 V6
VDD_BUCK7
F18 F19
VDD_BUCK8
BUCK1_LX0
BUCK1_LX1
BUCK5
3.2A MAX
C1867 220PF
5% 2 10V C0G-CERM 01005 ROOM=PMU
1
C1840 15UF
20% 2 6.3V X5R 0402-1 ROOM=PMU
1
C1801 15UF
20% 2 6.3V X5R 0402-1 ROOM=PMU
1
C1803 15UF
20% 2 6.3V X5R 0402-1 ROOM=PMU
1
MEKK2016T-SM
C1807
ROOM=PMU NO_XNET_CONNECTION=1
15UF
20% 2 6.3V X5R 0402-1 ROOM=PMU
OMIT
B2 C2 D2 A2
BUCK1_LX2
ROOM=SOC
BUCK1_LX3
BUCK1_FB
A10 B10 C10 D10
1.5A MAX
C1811
1
220PF
C1804 15UF
5% 2 10V C0G-CERM 01005
20% 2 6.3V X5R 0402-1
ROOM=PMU
1
ROOM=PMU
BUCK2_LX1
F5 BUCK5_FB
BUCK2_FB
1.5A MAX
BUCK7
C1868
1
220PF
C1805 15UF
20% 2 6.3V X5R 0402-1
5% 2 10V C0G-CERM 01005 ROOM=PMU
1
ROOM=PMU
15UF
ROOM=PMU
BUCK3_LX0
BUCK6_LX0
H16 BUCK6_FB VBUCK3_SW
U7 V7
BUCK7_LX0
BUCK4_LX0
XW1803 SHORT-20L-0.05MM-SM 2
ROOM=PMU
1 ROOM=SOC
L1801
CRITICAL
BUCK7_FB NO_XNET_CONNECTION=1
BUCK4_LX1
1
C1869
1
220PF
C1806 15UF
20% 2 6.3V X5R 0402-1
5% 2 10V C0G-CERM 01005 ROOM=PMU
1
C1810
ROOM=PMU
ROOM=PMU
ROOM=SOC
L1802
BUCK9
0.75A MAX
1
BUCK8_FB
C1870
1
220PF
C1862 15UF
20% 2 6.3V X5R 0402-1
5% 2 10V C0G-CERM 01005 ROOM=PMU
ROOM=PMU
1
0603
C1863 15UF
20% 2 6.3V X5R 0402-1
2
20% 6.3V X5R 0402-1
20% 2 6.3V X5R 0402-1
15UF
ROOM=PMU
15UF
ROOM=PMU
C1845
1
15UF
ROOM=PMU
BUCK4_FB
BUCK8_LX0
220PF 5%
2
ROOM=PMU
10V C0G-CERM 01005
ROOM=PMU
L1810
B18 C18 D18 A18
BUCK1_LX0
A16 B16 C16 D16
BUCK1_LX1
1
2 PIQA20161T-SM
NO_XNET_CONNECTION=1
PP_GPU_VAR CRITICAL
ROOM=PMU
L1811
0.22UH-20%-6.7A-0.023OHM 1
A14 B14 C14 D14
ROOM=PMU
L1812
2
BUCK1_LX2
C1813
1
2
20% 6.3V X5R 0402-1
20% 6.3V 2 X5R 0402-1
15UF
1
PINA20121T-SM NO_XNET_CONNECTION=1
CRITICAL
ROOM=PMU
2
1
C1814
1
20% 6.3V X5R 0402-1
20% 2 6.3V X5R 0402-1
ROOM=PMU
C1827 15UF
20% 6.3V 2 X5R 0402-1
ROOM=PMU
15UF
1
C1820 15UF
ROOM=PMU
CRITICAL
PINA20121T-SM
NO_XNET_CONNECTION=1
1
2
1
15UF
1
15UF
C1828 15UF
1
15UF
1
C1834
1
15UF
0.67V - 0.92V 1.03V for overdrive only
15UF
ROOM=PMU
C1866 15UF
1
C1873
C
220PF
5% 2 10V C0G-CERM 01005
20% 2 6.3V X5R 0402-1
ROOM=PMU
C1865
20% 6.3V 2 X5R 0402-1
ROOM=PMU
20% 2 6.3V X5R 0402-1
ROOM=PMU
C1839
20% 6.3V 2 X5R 0402-1
ROOM=PMU
20% 2 6.3V X5R 0402-1
ROOM=PMU
1
20% 6.3V 2 X5R 0402-1
ROOM=PMU
C1821
C1833
14
ROOM=PMU
ROOM=PMU
L1813
A12 B12 C12 D12
1
BUCK1_LX3
2 PINA20121T-SM
NO_XNET_CONNECTION=1
CRITICAL
ROOM=PMU
F12BUCK1_PP_GPU_FB
14
L1814
G1 G2 G3
1
BUCK2_LX0
2 PIQA20161T-SM
PP_SOC_VAR 14 CRITICAL
ROOM=PMU
1
L1815
J1 J2 J3
BUCK2_LX1
J5
BUCK2_PP_SOC_FB
2
2
PIQA20121T-SM
NO_XNET_CONNECTION=1
CRITICAL
ROOM=PMU
14
L1816
C1822
1
C1829
1
2
20% 6.3V X5R 0402-1
20% 2 6.3V X5R 0402-1
15UF
1
R2 R3 R1 R7
1
BUCK3_LX0
20% 6.3V X5R 0402-1
15UF
ROOM=PMU
C1835
1
C1841
2
20% 6.3V X5R 0402-1
15UF
ROOM=PMU
1
15UF
ROOM=PMU
C1864
1
20% 6.3V X5R 0402-1
5% 2 10V C0G-CERM 01005
15UF
2
ROOM=PMU
ROOM=PMU
C1871
0.67V/0.80V
220PF
ROOM=PMU
ROOM=PMU
2 PIQA20161T-SM
NO_XNET_CONNECTION=1
CRITICAL
OMIT
1
XW1804
2
ROOM=SOC
U2 V2
C1816
1
15UF
SHORT-20L-0.05MM-SM 1 2
20% 6.3V X5R 0402-1
C1823
1
20% 6.3V X5R 0402-1
5% 2 10V C0G-CERM 01005
15UF
2
ROOM=PMU
16 PP1V8_SDRAM 47
C1860
20 21 32 36 37 40 41 48 52 53
220PF
ROOM=PMU
ROOM=PMU
N1 N2 N3
1
BUCK4_LX0
2 PIQA20161T-SM
NO_XNET_CONNECTION=1
PP1V1_SDRAM CRITICAL
ROOM=PMU
1
L1 L2 L3 K5
2
2
1 PIQA20121T-SM
NO_XNET_CONNECTION=1
1
15UF
L1818
BUCK4_LX1
C1830
ROOM=PMU OMIT
20% 6.3V X5R 0402-1
ROOM=PMU
C1836
1
20% 6.3V X5R 0402-1
20% 2 6.3V X5R 0402-1
15UF
2
ROOM=PMU
C1802
1
15UF
ROOM=PMU
C1874
1
20% 6.3V X5R 0402-1
2
15UF
2
ROOM=PMU
15 19
C1861 220PF
5% 10V C0G-CERM 01005
ROOM=PMU
CRITICAL
XW1805
SHORT-20L-0.05MM-SM 1 2
BUCK4_FB
ROOM=SOC
M18 M19
BUCK9_LX0
XW1806
SHORT-20L-0.05MM-SM 2 1 ROOM=SOC
U5 V5
BUCK3_SW1
T1 U1
PP1V8
U3 V3
PP1V8_TOUCH PP1V8_MAGGIE_IMU
H15 BUCK8_FB
OMIT
ROOM=PMU
VBUCK4_SW
BUCK9_FB
P16 BUCK9_FB
NO_XNET_CONNECTION=1
5 7 8 9 11 12 13 16 17 25 29 39 46 47 48 52
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
BUCK3_SW2 BUCK3_SW3
PP1V1
U4 V4
Apple Inc.
38 39 46 47 24 36
051-00419
REVISION
R
7 15
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
7
B
L1817
NO_XNET_CONNECTION=1
BUCK4_SW1
8
D
C1872
NO_XNET_CONNECTION=1
1.0UH-20%-1.5A-0.161OHM 1 2 BUCK9_LX0
PP2V8_UT_AF_VAR
G18 G19
XW1801
SHORT-20L-0.05MM-SM 2 1
CRITICAL 25
1
OMIT
20% 2 6.3V X5R 0402-1
A
BUCK8_LX0
PIQA20121T-SM
15UF
ROOM=PMU
1
SWITCH OUTPUTS
0.80V - 0.92V
1.5A MAX
BUCK8
2
PP_GPU_SRAM_VAR
14
0.47UH-20%-3.8A-0.048OHM
R8 BUCK7_FB
1UH-20%-2.1A-0.12OHM 14
ROOM=PMU
C1843
1.0UH-20%-3.6A-0.060OHM
OMIT
20% 2 6.3V X5R 0402-1
2
20% 6.3V X5R 0402-1
15UF 20%
1
CRITICAL
ROOM=PMU
NO_XNET_CONNECTION=1
MCFE2016T-SM
C1809
2 6.3V X5R 0402-1
C1838
BUCK4
1
6.3V X5R 0402-1
1
4.7A MAX
0.80V - 1.06V
PINA20121T-SM
BUCK3_FB
1.0UH-20%-2.25A-0.086OHM 2 1 BUCK7_LX0
PP_CPU_SRAM_VAR
J18 J19
NO_XNET_CONNECTION=1
L1805
2
C1832
2
NO_XNET_CONNECTION=1
BUCK5_LX0
BUCK3_FB
BUCK6_FB
ROOM=SOC
CRITICAL 14
1
1
15UF 20%
ROOM=PMU
0.47UH-20%-3.8A-0.048OHM
XW1807 SHORT-20L-0.05MM-SM 2
15UF
C1826
1.0UH-20%-3.6A-0.060OHM
OMIT
20% 2 6.3V X5R 0402-1
ROOM=PMU
BUCK6_LX0
ROOM=PMU
15UF
ROOM=PMU
1.0UH-20%-3.6A-0.060OHM
PIQA20121T-SM
C1808
ROOM=PMU
BUCK3
1
1
ROOM=PMU
15UF
20% 6.3V 2 X5R 0402-1
1.7A MAX
BUCK6
2
PP1V25_BUCK
ROOM=PMU
15UF
0.625V - 1.06V
(pending vendor qual)
19
1
BUCK0_LX3
F10BUCK0_PP_CPU_FB
1UH-20%-2.1A-0.12OHM
B
20% 6.3V 2 X5R 0402-1
C1844
1
L1809
VDD_BUCK9
NO_XNET_CONNECTION=1
L1804
CRITICAL
BUCK5_FB
2
20% 6.3V X5R 0402-1
15UF
C1842
0.22UH-20%-6.7A-0.023OHM
XW1802
SHORT-20L-0.05MM-SM 2 1
ROOM=PMU
1
20% 2 6.3V X5R 0402-1
CRITICAL
0.22UH-20%-6.7A-0.023OHM
BUCK2_LX0
BUCK5_LX0
1
15UF
ROOM=PMU
C1819
1
1 PINA20121T-SM
NO_XNET_CONNECTION=1
C1837
BUCK2
1
1
2
BUCK0_LX2
20% 2 6.3V X5R 0402-1
1
4.7A MAX
2
PP0V9_SOC_FIXED
ROOM=PMU
L1808
A8 B8 C8 D8
2
C1831
CRITICAL
PINA20121T-SM
NO_XNET_CONNECTION=1
20% 6.3V X5R 0402-1
15UF
ROOM=PMU
2
1
1.0UH-20%-3.6A-0.060OHM
1.0UH-3.6A-0.06OHM
15 10 9 8 7
15UF
C1825
14
0.22UH-20%-6.7A-0.023OHM
L1803
CRITICAL
1
BUCK0_LX1
1
20% 2 6.3V X5R 0402-1
L1807
A6 B6 C6 D6
C1818
1
0.22UH-20%-6.7A-0.023OHM
VDD_BUCK0_01
T2 T3
L18 L19
ROOM=PMU
0.22UH-20%-6.7A-0.023OHM
BUCK INPUT
1
CRITICAL
PIQA20161T-SM
NO_XNET_CONNECTION=1
PP_CPU_VAR
BUCK1
C1846
BUCK0_LX0
B4 C4 D4 A4
2
BUCK0
1
SYM 2 OF 4 ROOM=PMU
Voltages per Cayman Power Spec, Sec. 2.2, rev 0.9.2, #24557869
13.4A MAX
PP_VDD_MAIN
VDD_MAIN_SNS VDD_MAIN VDD_MAIN_E VDD_MAIN_N VDD_MAIN_SW VDD_MAIN_W VDD_MAIN_W
WLCSP
1
13.4A MAX
53 28 27 26 25 23 21 19 10 9 4 52 46 41 40 39 37 35 34 33 31
M8 N7 H6 F11 R13 H14 H13
1
BUCK0_LX0
D2333A1
VDD_MAIN_SNS
2
1.0UH-20%-3.6A-0.060OHM
U1801 19
3
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
4
1
XW1901 SHORT-20L-0.05MM-SM
VDD_MAIN_SNS
2
1
2
1
C1901 15UF
C1910 10UF
20% 6.3V 2 CERM-X5R 0402-9
20% 6.3V X5R 0402-1
ROOM=PMU
ROOM=PMU
1
C1914 10UF
20% 6.3V 2 CERM-X5R 0402-9 ROOM=PMU
1
1
C1911 10UF
20% 6.3V 2 CERM-X5R 0402-9
C1907 10UF
ROOM=PMU
ROOM=PMU
XW1902
SHORT-20L-0.05MM-SM
D
2
ROOM=PMU
ADJ.RANGE, LOW
LDO#
20% 6.3V 2 CERM-X5R 0402-9
OMIT
PMU_PRE_UVLO_DET
53 38 37 32 25 23
PP_VDD_MAIN
PP_VDD_BOOST 1
C1915 15UF 20%
6.3V 2 X5R 0402-1
ROOM=PMU
1
15UF 20%
C
R12 V11 R10 R16 V9 V10 R14 P19 R19 R9 V13 V16 T19 V17 V18 U19
18
C1913 2.2UF
20% 6.3V 2 X5R-CERM 0201-1
ROOM=PMU
ROOM=PMU
PP1V25_BUCK
VDD_LDO1 VDD_LDO2_15 VDD_LDO3_17 VDD_LDO4 VDD_LDO5 VDD_LDO6_BYP VDD_LDO7_8 VDD_LDO9 VDD_LDO10 VDD_LDO11_13 VDD_LDO14 VDD_LDO16 VDD_LDO18 VDD_LDO19 VDD_LDO19
U1801 D2333A1 WLCSP
A
VSS
NC
VLDO1 VLDO2 VLDO3 VLDO4 VLDO5_0 VLDO5_1 VLDO6
T12 U11 T10 T16 U9 U10 T14
VBYPASS
R15
VLDO7 VLDO8 VLDO9
T17 P18 R18
VLDO9_FB
P17
VLDO10 VLDO11 VLDO12 VLDO13 VLDO14 VLDO15 VLDO16 VLDO17 VLDO18 VLDO19
G15 VPP_OTP
G17 G4 H17 H18 H19 H4 J17 J4 J8 K1 K17 K2 K3 K4 K8 L17 L4 L8 M17 M4 N17 N18 N19 N4 P1 P2 P3 P4 P15 R17 R4 T5 T15 T4 T6 T7 T8 U15 T13 U8 V1 V12 V19 V8
ADJ.RANGE, HI
1.2-2.475V
2.4-3.675V
1.2-2.475V
2.4-3.675V
+/-1.4%
50mA
LDO2 (Ca)
1.2-2.475V
2.4-3.675V
+/-2.5%
50mA
LDO12 (E)
1.8V
LDO3 (Ca)
1.2-2.475V
2.4-3.675V
+/-2.5%
50mA
LDO13 (Cb)
1.2-2.475V
LDO4 (D)
0.7-1.2V
+/-2.5%
60mA
LDO14 (Gb)
0.7-1.4V
LDO5 (F)
2.5-3.6V(tbc)
+/-75mV
1000mA
LDO15 (Ca)
1.2-2.475V
+/-2.5%
(500/100mA in bypass)
LDO16 (Cb)
2.4-3.675V
1.2-2.475V
ACCURACY
MAX.CURRENT
+/-30mV
250mA
+/-5%
10mA
+/-30mV
250mA
+/-3.0%
400mA
2.4-3.675V
+/-2.5%
50mA
1.2-2.475V
2.4-3.675V
+/-30mV
250mA
LDO17 (Ca)
1.2-2.475V
2.4-3.675V
+/-2.5%
50mA
LDO18 (Gb)
0.7-1.4V
+/-3.0%
400mA
LDO19 (Gb)
0.7-1.4V
+/-3.0%
400mA
LDO_RTC
2.5V
+/-2.0%
10mA
BUF_1V2
1.2V
+/-5.0%
10mA
LDO11 (Cb)
2.4-3.675V
250mA
LDO7 (Cb)
1.2-2.475V
2.4-3.675V
+/-30mV
250mA
LDO8 (Cb)
1.2-2.475V
2.4-3.675V
+/-30mV
250mA
LDO9 (Cb)
1.2-2.475V
2.4-3.675V
+/-25mV
250mA
LDO10 (Ga)
0.7-1.2V
+/-4.5%
1150mA
J6 TP_DET
PP3V3_USB PP1V8_VA PP3V0_ALS_APS_CONVOY PP0V8_AOP PP3V0_NAND
P8
VPUMP
R5
2
1
C1918
1
2.2UF
2
20% 6.3V X5R-CERM 01005
PP0V9_NAND
17
C1916 20% 6.3V X5R-CERM 0201-1
ROOM=PMU
C1933
1
1.0UF
2
20% 6.3V X5R 0201-1
2
1
2
20% 6.3V X5R-CERM 0201-1
20% 2 6.3V X5R-CERM 0201-1
ROOM=PMU
20% 6.3V X5R-CERM 0201-1
C1922 2.2UF
ROOM=PMU
C1926
1
20% 6.3V X5R-CERM 0201-1
20% 2 6.3V X5R 0201-1
2.2UF
2
ROOM=PMU
C1921 2.2UF
1
2.2UF
ROOM=PMU
1
C1923
1.0UF
ROOM=PMU
1
C1925
ROOM=PMU
1
1.0UF
20% 2 6.3V X5R 0201-1
ROOM=PMU
C1935
1
C1930
2
20% 6.3V X5R 01005-1
29
LDO10 LDO11 LDO12 LDO13 LDO14 LDO15 LDO16 LDO17 LDO18 LDO19
16
VBUF_1V2
8 10 16 38 48
R1901 MF NOSTUFF 0.00 1 0201 2 25
ROOM=PMU
1
C1904
1
C1919
2
20% 6.3V X5R-CERM 0201-1
2
ROOM=PMU
20% 6.3V X5R-CERM 0201-1
ROOM=PMU
ROOM=PMU
ROOM=PMU
B
2.2UF
2.2UF
20% 6.3V X5R-CERM 0201-1
C
0.22UF
20% 2 6.3V X5R-CERM 0201-1
2.2UF
2
C1932
2.2UF
ROOM=PMU
C1927
1
44
38
1/20W 1%
LDO6 LDO7 LDO8 LDO9
29 40 41 53
20 21
PP1V2_REF
2.2UF
47NF
17 52
29
PP_LDO17 PP1V2_UT_DVDD PP1V2_NH_NV_DVDD
1
C1902
15
PP3V0_TRISTAR_ANT_PROX PP2V9_NH_AVDD PP1V8_HAWKING
#24989262
ROOM=PMU
1
25 29
27 40 46
PP1V8_ALWAYS PP3V0_MESA PP1V2_SOC PP1V8_MESA
20% 2 6.3V X5R-CERM 0201-1
PMU_VPUMP
32 33 34 35
PP_ACC_VAR
T9 U13NC P7 U14 U16 U12 T18NC T11 U17 U18
VBUF_1V2
LDO1 LDO2 LDO3 LDO4 LDO5
7
#24989262:OTP-AO LDO17 default off,50mA Iout_max
VPUMP: 10nF min. @4.6V
53 52 27 26 25 23 21 19 18 10 9 4 46 41 40 39 37 35 34 33 31 28
PP_VDD_MAIN
C1905
1
5% 2 16V NP0-C0G-CERM 01005
2
1
33PF
ROOM=PMU
PMU_VSS_RTC
C1909 220PF
5% 10V C0G-CERM 01005 ROOM=PMU
20
U15 = PMU XTAL GND
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
D
WLCSP
LDO
20% 6.3V 2 X5R-CERM 0201-1
1
ADJ.RANGE, LOW
D2333A1
ROOM=PMU
LDO INPUT
C1908 2.2UF
VSS
1
U1801
6.3V 2 X5R 0402-1
PP1V1_SDRAM 1
B
LDO#
MAX.CURRENT
C1912
SYM 1 OF 4
SYM 4 OF 4
ACCURACY
1
53 52 27 26 25 23 21 19 18 10 9 4 46 41 40 39 37 35 34 33 31 28
18 15
ADJ.RANGE, HI
LDO1 (Ca)
LDO6 (Cb)
A1 A11 A15 H8 A19 P13 A3 P14 A7 B11 B15 B19 B3 B7 C11 C15 C19 C3 C7 D11 D15 D19 D3 D7 E1 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E2 E3 E4 E5 E6 E7 E8 E9 F1 F17 F2 F3 F4
2
ADELYN LDO SPECS
ROOM=PMU NO_XNET_CONNECTION
20
3
PP_VDD_MAIN OMIT
18
5
New for ADELYN
53 52 27 26 25 23 21 19 18 10 9 4 46 41 40 39 37 35 34 33 31 28
6
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
1
PP
SM
3
2
1
BUTTON PULL-UP RESISTORS
PP2001
P2MM-NSM
ROOM=SOC
1
PP SM
PP1V8_SDRAM
PP2002 P2MM-NSM
1
ROOM=SOC
1
7
2 ROOM=PMU
40
NO_XNET_CONNECTION
11 13 7
1
C2001 1000PF
2
AP_TO_PMU_WDOG_RESET TRISTAR_TO_PMU_HOST_RESET AP_TO_PMU_SOCHOT_L PMU_TO_SYSTEM_COLD_RESET_L
P9 P10 P11 M5 NC P12
13 15 13
ROOM=PMU
13 40 37 13 7
AOP_TO_PMU_SLEEP1_REQUEST PMU_TO_AOP_SLEEP1_READY AOP_TO_PMU_ACTIVE_REQUEST PMU_TO_AOP_TRISTAR_ACTIVE_READY
R11 L11 L12 J12
PMU_TO_AOP_CLK32K
13
M9 NC M10
D101/D111 ONLY: TCXO_RF Supplies 32K 21 17 15 53 39 23 13
R2020 47
I2C1_AP_SDA
#24825674: Add R2020 to meet timing spec #26169957: R2020 to 100ohm (D10x only)
C
11
7 20
FOREHEAD NTC 1
39 37
100PF
5% 16V 2 NP0-C0G 01005 ROOM=PMU
10KOHM-1%
2
01005 ROOM=PMU
40 20 36
FOREHEAD_NTC_RETURN
4
1
2
1 1 C2008 100PF
5% 16V NP0-C0G 2 01005 ROOM=PMU
2
10% 10V X5R 01005
RCAM_NTC_RETURN 1
2 OMIT
ROOM=SOC
R2003 10KOHM-1% 2
01005 ROOM=PMU
1
PA_NTC_RETURN
10KOHM-1%
2
NC
1
R6 M6 P6 L5 L6 G16
TDEV1 TDEV2 TDEV3 TDEV4 TDEV5 TCAL
N9
XTAL1 XTAL2 VDD_RTC
C2002 0.22UF
20% 2 6.3V X5R 0201 ROOM=PMU
2
C2011 100PF
5% 16V 2 NP0-C0G 01005 ROOM=PMU
1
VDROOP0* G6 VDROOP1* G7
1
C2006 0.22UF
R2011 200K
PRE_UVLO_DET N8
PMU_PRE_UVLO_DET
1 11
16 18 20 21 32 36 37 40 41 47 48 52 53
NOSTUFF
R2015 220K
5% 1/32W MF 01005
12
2 ROOM=PMU
BUTTON_VOL_DOWN_L
44 20
11
14
NOTE:VDROOP_DET filtering is now inside Adelyn
14
19
IBAT VBAT BRICK_ID ADC_IN
L7 NC M7 NC H7 TRISTAR_TO_PMU_USB_BRICK_ID PMU_ADC_IN K7
BUTTON1 BUTTON2 BUTTON3 BUTTON4
M12 BUTTON_VOL_DOWN_L N12 BUTTON_POWER_KEY_L M11 BUTTON_RINGER_A N11 NC Reserved for MENU key on dev board
F16 F15 G14 F14 F13 G13 G12 H12 G11 G10 F9 G9 F8 G8 H9 H10 J9 J10 K9 K10 L9
PP1V8_SDRAM
2 ROOM=PMU
PMU_TO_AP_THROTTLE_CPU_L PMU_TO_AP_THROTTLE_GPU_L AP_VDD_CPU_SENSE AP_VDD_GPU_SENSE
GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21
R2007 220K
2 ROOM=PMU
BUTTON_POWER_KEY_L
44 20
1% 1/20W MF 201
PMU_TO_AP_PRE_UVLO_L
VDROOP0_DET F6 VDROOP1_DET F7
BUTTONO1 H11 BUTTONO2 J11 BUTTONO3 K11
NOSTUFF
PMU_TO_AP_BUF_VOL_DOWN_L PMU_TO_AP_BUF_POWER_KEY_L PMU_TO_AP_BUF_RINGER_A TIGRIS_TO_PMU_INT_L BB_TO_PMU_PCIE_HOST_WAKE_L PMU_TO_BBPMU_RESET_R_L WLAN_TO_PMU_HOST_WAKE NFC_TO_PMU_HOST_WAKE PMU_TO_NAND_LOW_BATT_BOOT_L
C 20 40 20
20 44 20 44 20 44
12
Button for two-finger reset: 20711463 and 21196187
12 12
21
R2000 1.00K
53
1
2
PMU_TO_BBPMU_RESET_L
53
5% 1/32W MF 01005 ROOM=PMU
53 53 17
NC_PMU_TO_GNSS_EN
PMUGPIO_TO_WLAN_CLK32K PMU_TO_BT_REG_ON
20 53 53
NC_GNSS_TO_PMU_HOST_WAKE
PMU_TO_WLAN_REG_ON BT_TO_PMU_HOST_WAKE PMU_TO_CODEC_DIGLDO_PULLDN PMU_TO_ACC_BUCK_SW_EN PMU_TO_BB_USB_VBUS_DETECT PMU_TO_NFC_EN PMU_TO_AP_FORCE_DFU_R PMU_TO_BOOST_EN PMU_TO_LCM_PANICB PMU_TO_HOMER_RESET_L
53 53
B
32 27 53
#24511807: Stuff for Carrier
R2009 0.00
53
1 23
RS
39
RS
PMU_TO_AP_FORCE_DFU 4
2
12
0% 1/32W MF 01005
36
I2C0_AP_SCL
37 47
RS
Sequencer controllable RS = requires sequencer
Y2001
32.768KHZ-20PPM-12.5PF 1
1 C2003 22PF
2
1.60X1.00-SM ROOM=PMU
5% 16V CERM 2 01005
AP_NTC_RETURN
PMU_VREF
D
19 20 21
CRITICAL
R2010 3.92K
0.1% 1/20W MF 0201 2 ROOM=PMU
ROOM=PMU
5% 1/32W MF 01005
GPIO21 = I2C SCL is for Chestnut dark current mitigation
ROOM=PMU
19
1
C2004 22PF
5% 16V 2 CERM 01005
PMU_VSS_RTC
ROOM=PMU
XW2001
SHORT-20L-0.05MM-SM
1
A
AMUX_B0 AMUX_B1 AMUX_B2 AMUX_B3 AMUX_B4 AMUX_B5 AMUX_B6 AMUX_B7 AMUX_BY
V14 V15
1
1
VREF J7
PRE_UVLO* N10
AMUX_A0 AMUX_A1 AMUX_A2 AMUX_A3 AMUX_A4 AMUX_A5 AMUX_A6 AMUX_A7 AMUX_AY
L14 L15 L16 M16 M15 M14 N16 N15 N14
PMU_VDD_RTC
2
SHORT-20L-0.05MM-SM ROOM=SOC
J14 J15 J16 K16 K15 K14 J13 K13 K12
PMU_XTAL1 PMU_XTAL2
R2004 01005 ROOM=PMU
PMU_AMUX_BY
XW2005
1
5% 16V 2 NP0-C0G 01005 ROOM=PMU
BBPMU_TO_PMU_AMUX3
OMIT
AP NTC
100PF
AP_TO_PMU_TEST_CLKOUT
2
1
C2010 1
4
CHESTNUT_TO_PMU_ADCMUX
XW2004 SHORT-20L-0.05MM-SM
1
5% 16V NP0-C0G 2 01005 ROOM=PMU
37
OMIT
RADIO PA NTC
C2009 100PF
1
PMUGPIO_TO_WLAN_CLK32K
53 20
PMU_TCAL
XW2003 SHORT-20L-0.05MM-SM
ROOM=SOC
NC
FOREHEAD_NTC REAR_CAMERA_NTC RADIO_PA_NTC AP_NTC
OMIT
ROOM=SOC
B
1
ACC_BUCK_TO_PMU_AMUX
53
XW2002 SHORT-20L-0.05MM-SM
01005 ROOM=PMU
SCLK MOSI MISO
NC
LCM_TO_CHESTNUT_PWR_EN TRISTAR_TO_PMU_USB_BRICK_ID PP1V2_MAGGIE PMU_AMUX_AY
27
7
ROOM=PMU PLACE_NEAR=U1801:2mm
R2002 10KOHM-1%
C2013
N6 N5 P5
NC
BBPMU_TO_PMU_AMUX1 BBPMU_TO_PMU_AMUX2
1000PF
REAR CAMERA NTC
SCL SDA
AP_TO_PMU_AMUX_OUT PMU_ADC_IN
53
53
TBD
N13 M13
NC
BUTTON_VOL_UP_L
44 12
R2001
SYS_ALIVE FORCE_SYNC CRASH* IRQ*
SPI_PMGR_TO_PMU_SCLK SPI_PMGR_TO_PMU_MOSI SPI_PMU_TO_PMGR_MISO
11
ROOM=PMU
11
C2007 1
PMU_IREF
ROOM=PMU
SLEEP_32K OUT_32K
H5 L13 L10 G5
HIGH=FORCE PWM MODE
I2C1_AP_SCL I2C_PMU_SDA_R
47
2
5% 1/32W MF 01005
SYSTEM_ALIVE LCM_TO_MANY_BSYNC PMU_TO_AOP_IRQ_L
13
100
IREF K6
20% 6.3V 2 X5R 0201
SLEEP1_REQ SLEEP1_RDY ACTIVE_REQ ACTIVE_RDY
5% 1/32W MF 01005
1
Active high with int 200k PD
10% 10V X5R 01005
1
RESET_IN1 RESET_IN2 RESET_IN3 RESET* SHDN
REFS
2 ROOM=PMU
COMPARATOR
2 ROOM=PMU
SYM 3 OF 4
R2008 100K
PP1V8_ALWAYS
D2333A1 WLCSP
5% 1/32W MF 01005
ADC
5% 1/32W MF 01005
5% 1/32W MF 01005
16 18 20 21 32 36 37 40 41 47 48 52 53
BUTTON_RINGER_A
44 20
U1801
R2012 10K
BUTTONS
R2005 100K
GPIO
R2006 100K
1
RESETS
1
2
PMGR
1
ROOM=PMU
19 20 21
AMUX
D
PP1V8_ALWAYS
PP2003 P2MM-NSM
NTC
PP1V8_SDRAM
SM
XTAL
47 41 40 37 36 32 21 20 18 16 53 52 48
PP
NOSTUFF
2
ROOM=PMU
OMIT
NOTE:100PF CAPS ARE THE SAMPLING CAPS FOR PMU ADC
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
TIGRIS CHARGER D
D
See Charger C2113 on Pg46
PP_VDD_MAIN 1
4 9 10 18 19 23 25 26 27 28 31 33 34 35 37 39 40 41 46 52 53
C2114 10UF
2
20% 6.3V CERM-X5R 0402-9 ROOM=CHARGER
TIGRIS_LDO
10% 16V 2 CER-X7R 01005
ROOM=CHARGER
C2109
1
4.2UF
10% 16V 2 X5R-CERM 0402-1
ROOM=CHARGER
1
C2111
1
4.2UF
10% 16V 2 X5R-CERM 0402-1
C2112 330PF
2
ROOM=CHARGER
10% 16V CER-X7R 01005
ROOM=CHARGER
1
220PF
2.2UF
5% 2 10V C0G-CERM 01005
2
ROOM=CHARGER
20% 6.3V X5R-CERM 0201-1
ROOM=CHARGER 28
NO_XNET_CONNECTION
40 4
PP5V0_USB
C2101
1 20 19
4.2UF
PP1V8_ALWAYS 1
R2101
10% 2 16V X5R-CERM 0402-1 ROOM=CHARGER
1
10% 2 16V CER-X7R 01005 ROOM=CHARGER 47
5% 1/32W MF 2 01005
47 20 17 15
ROOM=CHARGER
R2103 TIGRIS_TO_PMU_INT_L
C2110 330PF
100K
20
A5 B5 D5 C5 E5
1
100
5% 1/32W MF 01005
#24558610: Change to 100ohm
40
G3 E4
I2C1_AP_SDA I2C1_AP_SCL
E3
SYSTEM_ALIVE TRISTAR_TO_TIGRIS_VBUS_OFF
F4: 100 kOhm pullup to VLDO (regulated output voltage)
2 ROOM=CHARGER
TIGRIS_TO_PMU_INT_R_L TIGRIS_VBUS_DETECT
F3
1
30.1K 2 1% 1/32W MF 01005
VBUS VBUS VBUS VBUS VBUS
U2101 SN2400AB0 WCSP
ROOM=CHARGER
CRITICAL
SDA SCL SYS_ALIVE VBUS_OVP_OFF INT VBUS_DET TEST
LDO BOOT
G5
A4 BUCK_SW B4 BUCK_SW D4 BUCK_SW C4 BUCK_SW A1 BAT B1 BAT D1 BAT C1 BAT E1 BAT_SNS E2 ACT_DIODE G1 HDQ_HOST F2 HDQ_GAUGE
ROOM=CHARGER
TO TRINITY
A1
#25112685,Remove Snub
C2105
G4
C2106
0.047UF 1
TIGRIS_BOOT ROOM=CHARGER
C2102
1
330PF
2
10% 16V CER-X7R 01005 ROOM=CHARGER
10% 16V X5R 0201
Q2101
CSD68827W
BGA
G
ROOM=CHARGER
1
D
220PF
5% 10V 2 C0G-CERM 01005 ROOM=CHARGER
2
CRITICAL
S
TIGRIS_BUCK_LX
PP_BATT_VCC VBATT_SENSE
22
1
SWI_AP_BI_TIGRIS TIGRIS_TO_BATTERY_SWI_1V8
C2108
1
330PF
TIGRIS_ACTIVE_DIODE
R2102 1
48 47 41 40 37 36 32 20 18 16 53 52
C2118 2.2UF
20% 2 6.3V X5R-CERM 0201-1
ROOM=CHARGER
ROOM=CHARGER
5% 1/32W MF 01005 ROOM=CHARGER 2
PP1V8_SDRAM
1
4 22
1
20% 2 6.3V X5R-CERM 0201-1
ROOM=CHARGER
100K
C2117 2.2UF
10% 16V 2 CER-X7R 01005
NOSTUFF
12
A3 B3 D3 C3
B
USB_VBUS_DETECT
G2 F1
R2104 7
F4
PMID
PGND PGND PGND PGND
F5
C
C2115 A2 A3 B1 B2 B3
330PF
C2104
C1 C2 C3
C2103
A2 B2 D2 C2
1
1
VDD_MAIN VDD_MAIN VDD_MAIN VDD_MAIN
C
R2105
B
Q2102
40.2K
RV3C002UN DFN
D
S
2
G
1
1% 1/32W MF 2 01005
3
TIGRIS_PMID
TIGRIS_TO_BATTERY_SWI
22
SYM_VER_1
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
D
D
BATTERY CONNECTOR THIS ONE ON MLB
--->
516S00172 (matches d10 mlb MCO rev 27)
C
C XW2201
SHORT-20L-0.05MM-SM 1 2
J2201 RCPT-BATT-SHORT F-ST-SM
21
TIGRIS_TO_BATTERY_SWI
1
100
5% 1/32W MF 01005 ROOM=BATTERY_B2B
1 3 4
TIGRIS_BATTERY_SWI_CONN
2 1
C2201 56PF
9
5% 2 25V NP0-C0G-CERM 01005 ROOM=BATTERY_B2B
21
PLACE_NEAR=J2201:2mm NO_XNET_CONNECTION=1
11 8
7
R2201
VBATT_SENSE
ROOM=BATTERY_B2B
PP_BATT_VCC
5 2 6
1
C2202 56PF
5% 2 25V NP0-C0G-CERM 01005
10 12
ROOM=BATTERY_B2B
ROOM=BATTERY_B2B
1
C2203 100PF
5% 2 16V NP0-C0G 01005
ROOM=BATTERY_B2B
1
4 21
C2204 220PF
5% 10V 2 C0G-CERM 01005 ROOM=BATTERY_B2B
CRITICAL
ALLOW_APPLE_PREFIX
B
B
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
D
D
BOOST
C
C When VDD_MAIN < 3.4, boosts to 3.4 Otherwise tracks VDD_MAIN
PP_VDD_MAIN 1
C2309 10UF
20% 6.3V 2 CERM-X5R 0402-9
ROOM=BOOST
1
L2301 ROOM=BOOST
C2301
0.47UH-20%-4.2A-0.048OHM 1 2 SYS_BOOST_LX
4.7UF
20% 2 6.3V X5R-CERM1 402 ROOM=BOOST
20
PIUA20121T-SM
PMU_TO_BOOST_EN 1
R2301 511K
1% 1/32W MF 2 01005
A3 A4
VIN
C3 C4
SW SW
A1
VIN
EN
47
I2C0_AP_SCL
B2
47
I2C0_AP_SDA
C2
SDA
B1
VSEL
C1
BYP*
A2
GPIO
53 39 20 13
LCM_TO_MANY_BSYNC HIGH=FORCE PWM MODE
SCL
VOUT U2301 VOUT
SN61280D
B3 B4
PP_VDD_BOOST 1
ROOM=BOOST
C2302
2
20% 6.3V X5R 0402-1 ROOM=BOOST
D2 D3 D4
PGND
1
15UF
DSBGA
C2303
1
15UF
2
20% 6.3V X5R 0402-1
ROOM=BOOST
C2304
1
15UF
2
20% 6.3V X5R 0402-1
ROOM=BOOST
C2307
1
15UF
2
20% 6.3V X5R 0402-1 ROOM=BOOST
C2308
1
20% 6.3V X5R 0402-1
5% 2 10V C0G-CERM 01005
15UF
2
ROOM=BOOST
19 25 32 37 38 53
C2306 220PF
ROOM=BOOST
AGND D1
53 28 27 26 25 21 19 18 10 9 4 52 46 41 40 39 37 35 34 33 31
Control details from Radar 19634006
B
B
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
MAGNESIUM - COMPASS
CARBON - ACCEL & GYRO
D
INVENSENSE, MPU-6800: C2403=0.1UF
24
PP1V8_MAGGIE_IMU
BOMOPTION=CARBON_1
C2418
1
1
2.2UF
0.1UF
20% 6.3V 2 X5R-CERM 01005
20% 2 6.3V X5R-CERM 0201-1
PP1V8_MAGGIE_IMU
ROOM=CARBON
C2415
20% 6.3V 2 X5R-CERM 01005
ROOM=CARBON
2
R2401
VDD
100K
20% 2 6.3V X5R-CERM 0201-1
2.2UF
VDD
ROOM=MAGNESIUM
U2402
BOMOPTION: CARBON_1 #25765850:Update Carbon APN
HSCDTD601A-19A NC
VDDIO
U2401
NC NC NC
MPU-6900-21 LGA
ROOM=SOC
SPI_AOP_TO_ACCEL_GYRO_CS_L
13
5 8 14
GYRO_CHARGE_PUMP
SPC 2 SDI 3 SDO 4
CS FSYNC REGOUT
7
ACCEL_GYRO_TO_AOP_INT
13
DRDY
INT
SPI_AOP_TO_IMU_SCLK_R1 SPI_AOP_TO_IMU_MOSI SPI_IMU_TO_AOP_MISO
6
ACCEL_GYRO_TO_AOP_DATARDY
NC
13 24 13 24
24
BOMOPTION=CARBON_1
1
13 24
C2419
2
13
B1 B3 D1 D2
RSV RSV RSV RSV
SPI_IMU_TO_AOP_MISO
13 24
SDA/SDI A4
SPI_AOP_TO_IMU_MOSI
13 24
SCL/SCK A3
SPI_AOP_TO_IMU_SCLK_R1
13 24
SPI_AOP_TO_COMPASS_CS_L
13
CSB A2
D4 RST*
PP1V8_MAGGIE_IMU_FILT
1.09M INT PU
TRG/SE C3 NC DRDY A1
114K INT PD
ROOM=MAGNESIUM
+/-0.1PF 16V NP0-C0G 01005
COMPASS_TO_AOP_INT
13
CRITICAL VSS
ROOM=CARBON
PP2404 1 SM
C1
C2403
SDO B4
114K INT PU
CRITICAL
BOMOPTION=CARBON_1
LGA
C2 VPP
5PF
ROOM=CARBON
PP
ROOM=MAGNESIUM
15 GND
13 GND
12 GND
ROOM=CARBON
11 GND
9 GND
10% 6.3V 2 X6S 0201
10 GND
P2MM-NSM
0.1UF
C
20% 6.3V X5R-CERM 01005
BOMOPTION=CARBON_1
5% 1/32W MF 2 01005
1
1
ROOM=MAGNESIUM
ROOM=CARBON
C2408
C2401 0.1UF
0.1UF
BOMOPTION=CARBON_1
1
1
16
36 24 18
C2402
PP1V8_MAGGIE_IMU_FILT
BOMOPTION=CARBON_1
1
1
36 24 18
C4
D
PP2401 1 SM
C
PP
P2MM-NSM
ROOM=MAGNESIUM
PP2402 1
#25782019:Add 0ohm
36 24
1
0.00
2
24
0% 1/32W MF 01005
ROOM=BOT_CARBON
C2448
1
2.2UF
C2442 0.1UF
20% 2 6.3V X5R-CERM 0201-1
20% 2 6.3V X5R-CERM 01005
ROOM=BOT_CARBON
PP1V8_MAGGIE_IMU_R
PP
ROOM=BOT_CARBON
1
P2MM-NSM
C2445
ROOM=MAGNESIUM
0.1UF
#25740540:PP for South Carbon MOSI
20% 2 6.3V X5R-CERM 01005
1
ROOM=BOT_CARBON
1
R2441 100K
SM
PP2440
P2MM-NSM
1
VDD
VDDIO
U2404
5% 1/32W MF 2 01005
MPU-6900-21 LGA
ROOM=SOC
SPI_AOP_TO_BOT_ACCEL_GYRO_CS_L
13
PP
ROOM=HOMER
16
24
5 8 14
BOT_GYRO_CHARGE_PUMP
SPC 2 SDI 3 SDO 4
CS FSYNC REGOUT
SPI_AOP_TO_IMU_SCLK_R2 SPI_AOP_TO_IMU_MOSI SPI_IMU_TO_AOP_MISO
13
NOSTUFF
13 24
1
13 24
XW2404 SHORT-20L-0.05MM-SM ROOM=BOT_CARBON NO_XNET_CONNECTION=1
BOT_ACCEL_GYRO_TO_AOP_DATARDY
13
+/-0.1PF 2 16V NP0-C0G 01005
ROOM=BOT_CARBON
10% 6.3V 2 X6S 0201
ROOM=BOT_CARBON
B 15 GND
XW2404 to balance Via/Cu at INT pin
13 GND
CRITICAL 12 GND
0.1UF
6
ROOM=BOT_CARBON
10 GND
C2443
BOT_ACCEL_GYRO_TO_XW_INT
9 GND
1
2
DRDY
INT
11 GND
1
NC
7
C2449 5PF
OMIT
B
P2MM-NSM
PP2403 1 SM
PP1V8_MAGGIE_IMU_R 1
SM
ROOM=MAGNESIUM
R2404 PP1V8_MAGGIE_IMU 18
PP
PHOSPHORUS
#24593845, #25691124 BOSCH (APN:338S00188): nostuff C2420/C2421/C2422/C2423 and R2403 PU
R2422 24
1
PP1V8_MAGGIE_IMU_FILT 1
C2413
1
0.1UF
20% 2 6.3V X5R-CERM 01005
C2405
1
0.1UF
2
ROOM=PHOSPHORUS
C2420
NOSTUFF
1
4PF
20% 6.3V X5R-CERM 01005
2
ROOM=PHOSPHORUS
+/-0.1PF 16V NP0-C0G 01005
ROOM=PHOSPHORUS
C2421 20PF
2
5% 16V NP0-C0G-CERM 01005
ROOM=PHOSPHORUS
0.00
2
0% 1/32W MF 01005 ROOM=PHOSPHORUS
NOSTUFF
1
C2422
1
20PF
5% 2 16V NP0-C0G-CERM 01005
ROOM=PHOSPHORUS
PP1V8_MAGGIE_IMU
NOSTUFF
C2423
1
+/-0.1PF 16V NP0-C0G-CERM 01005
20% 2 6.3V X5R-CERM 0201-1
5.6PF
2
ROOM=PHOSPHORUS
18 24 36
C2414 2.2UF
ROOM=PHOSPHORUS
BOSCH: Internal PU
1
A 2
NOSTUFF
R2403 100K
5% 1/32W MF 01005
ROOM=SOC
6
PP1V8_MAGGIE_IMU_FILT 8
24
NOSTUFF
VDD
VDDIO
U2403
24 13 24 13
13
SPI_AOP_TO_IMU_MOSI SPI_AOP_TO_IMU_SCLK_R1 SPI_AOP_TO_PHOSPHORUS_CS_L
BMP284AA
3 SDI 4 SCK 2 CS*
LGA
SDO 5 IRQ 7
SPI_IMU_TO_AOP_MISO
SYNC_MASTER=Sync
13 24
SYNC_DATE=05/17/2016
PAGE TITLE
spare
PHOSPHORUS_TO_AOP_INT_L 13
GND
DRAWING NUMBER
1
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
THIS PAGE UNIQUE TO SMALL FORM FACTOR
UTAH POWER
IO FILTERS
TI:353S00015 ST:353S00889
NOTE: OUTPUT IMPDEANCE MUST BE >0.005-OHM IN ORDER TO MEET CAP ESR REQUIREMENT PER LDO SPEC. VENDOR ALSO RECOMMENDS CIN = COUT FOR STABILITY
U2501
D PP_VDD_BOOST 1
C2527
2
20% 6.3V X5R-CERM 0201-1
2.2UF
A1 B1
VEN
ROOM=RCAM_B2B
VOLTAGE=2.925V See Page46: D10x
PP2V9_UT_AVDD_CONN 1
C2531/C2507 are 2.2UF
C2502 0.22UF 10%
GND
6.3V 2 CER-X5R 01005
B2
53 38 37 32 23 19
FL2504
LP5907UVX2.925-S DSBGA VIN VOUT A2
ROOM=RCAM_B2B
ROOM=RCAM_B2B
1
45 46
9
AP_TO_UT_CLK
C2504
1
220PF
1
NOSTUFF
2
ROOM=RCAM_B2B
1
2 1
C2505
1
2.2UF
2
2
UT_AND_NV_TO_LED_DRIVER_STROBE_EN_CONN
45
ROOM=RCAM_B2B
150OHM-25%-200MA-0.7DCR 45
9
AP_TO_UT_SHUTDOWN_L
1
C2501
2 1
01005
ROOM=RCAM_B2B
220PF
20% 6.3V X5R-CERM 0201-1
2
ROOM=RCAM_B2B
5% 10V C0G-CERM 01005
C2514 220PF
5% 10V C0G-CERM 01005
2
ROOM=RCAM_B2B
ROOM=RCAM_B2B
FL2502
FL2503
33-OHM-25%-1500MA 1
45
5% 25V NP0-C0G-CERM 01005
ROOM=RCAM_B2B
PP2V8_UT_AF_VAR_CONN
ROOM=RCAM_B2B
PP3V0_ALS_APS_CONVOY
AP_TO_UT_SHUTDOWN_CONN_L
C2513
FL2501
0201
29 19
45
56PF
5% 16V NP0-C0G 01005
FL2500
PP2V8_UT_AF_VAR
1
ROOM=RCAM_B2B
100PF
5% 2 10V C0G-CERM 01005
AP_TO_UT_CLK_CONN
2 01005
C2512
33-OHM-25%-1500MA 18
D
150OHM-25%-200MA-0.7DCR
150OHM-25%-200MA-0.7DCR PP3V0_UT_SVDD_CONN
2 0201
C2519 2.2UF
1
ROOM=RCAM_B2B
20% 6.3V X5R-CERM 0201-1
2
C
1
2
ROOM=RCAM_B2B
26
45
UT_AND_NV_TO_STROBE_DRIVER_STROBE
1
C2518 220PF
2 1
01005
ROOM=RCAM_B2B
C2515 220PF
5% 10V C0G-CERM 01005
2
ROOM=RCAM_B2B
5% 10V C0G-CERM 01005
C
ROOM=RCAM_B2B
FL2505
33-OHM-25%-1500MA 19
PP1V2_UT_DVDD
1
PP1V2_UT_VDD_CONN
2 0201
1
ROOM=RCAM_B2B
2
C2506 2.2UF 20% 6.3V X5R-CERM 0201-1
ROOM=RCAM_B2B
1
2
C2508 2.2UF
20% 6.3V X5R-CERM 0201-1
C2510 2.2UF
1
20% 6.3V X5R-CERM 0201-1
2
ROOM=RCAM_B2B
1
2
ROOM=RCAM_B2B
C2503 220PF
5% 10V C0G-CERM 01005
1
2
ROOM=RCAM_B2B
45
C2521 15PF
5% 16V NP0-C0G-CERM 01005
ROOM=RCAM_B2B Desense for Wifi frequencies
FL2506
LPDP FILTERS
33-OHM-25%-1500MA 29 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39
1
PP1V8
2
PP1V8_UT_CONN
0201 ROOM=RCAM_B2B
1
C2509 1.0UF
20% 2 6.3V X5R 0201-1
ROOM=RCAM_B2B
1
45
C2511 220PF
53 28 27 26 23 21 19 18 10 9 4 52 46 41 40 39 37 35 34 33 31
5% 10V 2 C0G-CERM 01005
PP_VDD_MAIN 1
ROOM=RCAM_B2B
C2522
1
33PF
C2528
1
33PF
5% 2 16V NP0-C0G-CERM 01005
33PF
5% 2 16V NP0-C0G-CERM 01005
ROOM=RCAM_B2B
ROOM=RCAM_B2B
AC return path for LPDP
C2529
5% 2 16V NP0-C0G-CERM 01005
ROOM=RCAM_B2B
which is referenced to GND and VDD_MAIN
B
B
10
90_LPDP_UT_TO_AP_D0_P MAKE_BASE=TRUE
10
10
10
10
90_LPDP_UT_TO_AP_D0_N
90_LPDP_UT_TO_AP_D1_P 90_LPDP_UT_TO_AP_D1_N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
C2523
90_LPDP_UT_TO_AP_D0_P
1 20% X5R-CERM 1 ROOM=RCAM_B2B 20% X5R-CERM ROOM=RCAM_B2B
C2524
90_LPDP_UT_TO_AP_D0_N
C2525
90_LPDP_UT_TO_AP_D1_P
C2526
90_LPDP_UT_TO_AP_D1_N
C2530 0.1UF
LPDP_UT_BI_AP_AUX MAKE_BASE=TRUE
LPDP_UT_BI_AP_AUX
1 20% X5R-CERM 1 ROOM=RCAM_B2B 20% X5R-CERM ROOM=RCAM_B2B
1
2 6.3V 01005 2 6.3V 01005
0.1UF 90_LPDP_UT_TO_AP_D0_CONN_P
45
0.1UF 90_LPDP_UT_TO_AP_D0_CONN_N
45
2 6.3V 01005 2 6.3V 01005
0.1UF 90_LPDP_UT_TO_AP_D1_CONN_P
45
0.1UF 90_LPDP_UT_TO_AP_D1_CONN_N
45
LPDP_UT_BI_AP_AUX_CONN
2
20% 6.3V X5R-CERM 01005
ROOM=RCAM_B2B
1
45
C2520
56PF
5% 25V 2 NP0-C0G-CERM 01005
#24543254: Need to Scrub C2520 Value
ROOM=RCAM_B2B
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
STROBE DRIVERS INSIDE NEO SIP MODULE D10/sip_neo
D
D
M2600 53 52 27 26 25 23 21 19 18 10 9 4 46 41 40 39 37 35 34 33 31 28
PP_VDD_MAIN
C2609
NEO
C2610
1
10UF 20%
10UF 20%
6.3V CERM-X5R 2 0402-9 ROOM=STROBE
9 25
53 37
C2613
1
SIP
1
SYM 1 OF 3
220PF
B8 D2 D3
5% 10V C0G-CERM 2 01005
6.3V CERM-X5R 2 0402-9 ROOM=STROBE
ROOM=STROBE
C9
AP_TO_STROBE_DRIVER_HWEN
C8
UT_AND_NV_TO_STROBE_DRIVER_STROBE
D8
BB_TO_STROBE_DRIVER_GSM_BURST_IND 48
I2C_ISP_UT_SDA
48
I2C_ISP_UT_SCL
B9 B10
ROOM=STROBE
VDD VDD VDD
CRITICAL
HWEN1
D9 LED1 D10 LED1
PP_STROBE_DRIVER1_COOL_LED
44 45
D6 LED2 D7 LED2
PP_STROBE_DRIVER1_WARM_LED
44 45
STB1
C10
NTC
STROBE_MODULE_NTC
44
GSM1 SDA1 SCL1
C
C M2600
PP_VDD_MAIN
20% 6.3V CERM-X5R 2 0402-9 ROOM=STROBE2
C2612
1
10UF 20%
6.3V CERM-X5R 2 0402-9 ROOM=STROBE2
C2614
SIP
1
SYM 2 OF 3
220PF
5% 10V C0G-CERM 2 01005
B18 B19 D13
ROOM=STROBE
C12 C13
VDD VDD VDD
PP_STROBE_DRIVER2_COOL_LED
LED1 B11 LED1 B12
PP_STROBE_DRIVER2_WARM_LED
LED2 B14 LED2 B15
HWEN0
44 45
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B2 B3 B4 B5 B6 B7 B16 B17 B20 C1 C2 C3 C4 C5 C6 C7
44 45
STB0 NTC C11
B13
GSM0
46
I2C_ISP_NV_SDA
D12
SDA2
46
I2C_ISP_NV_SCL
D11
SCL2
B
53 52 27 26 25 23 21 19 18 10 9 4 46 41 40 39 37 35 34 33 31 28
PP_VDD_MAIN 1
C2617
1
5% 10V C0G-CERM 01005
2
220PF
2
ROOM=STROBE2
C2618 220PF
5% 10V C0G-CERM 01005
ROOM=STROBE2
NEO SIP
SYM 3 OF 3
A1 B1
AC return path for plane edge termination, which occurs near the Strobe modules.
M2600
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
A
GND2 GND2S
10UF
1
C14 C15 C16 C17 C18 C19 C20 D1 D4 D5 D14 D15 D16 D17 D18 D19 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
B
E20 D20
C2611
NEO
GND1 GND1S
53 52 27 26 25 23 21 19 18 10 9 4 46 41 40 39 37 35 34 33 31 28
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
ACCESSORY BUCK #25761020:Add Bypass 0ohm
NOSTUFF
R2711
1
D
0.00
2
D
1% 1/20W MF 0201
From PMU LDO6
ROOM=ACC_BUCK
U2710
1
A2 VIN WLCSP-COMBO VOUT A1
PP_VDD_MAIN
1
2.2UF
FPF1204UCX
53 28 26 25 23 21 19 18 10 9 4 52 46 41 40 39 37 35 34 33 31
C2704
2.2UF
20% 2 6.3V X5R-CERM 0201-1
PP_VDD_MAIN_ACC_BUCK_VIN
20% 2 6.3V X5R-CERM 0201-1
ROOM=PMU
B2 ON
1
ROOM=ACC_BUCK
2.2UF
GND
PMEG3002ESF
ROOM=ACC_BUCK
100K
A ROOM=ACC_BUCK
1% 1/32W MF 2 01005
FET Changes per #25687842 4/12/2016
ROOM=ACC_BUCK
Q2700
PMCM4401VPE
U2700 FAN53612-1.5V-1.9V
ACC_BUCK_EN
C
1
R2701 100K
5% 1/32W MF 2 01005 ROOM=ACC_BUCK
1
ACC_BUCK_SW
2
27
C2710 0.22UF 10%
B1
C2702
1
10UF
20% 6.3V 2 CERM-X5R 0402-9
2 6.3V CER-X5R 01005
R2705 10K
ROOM=ACC_BUCK
1
ROOM=ACC_BUCK
C2703
1
220PF
2
OMIT
C2701
XW2700
0.1UF
5% 10V C0G-CERM 01005
2
ROOM=ACC_BUCK
20% 6.3V X5R-CERM 01005
27
#25172498
SHORT-20L-0.05MM-SM 1 2
ACC_BUCK_FB
To Tristar on Pg40 ROOM=TRISTAR
PP_ACC_VAR
Q2701
ROOM=ACC_BUCK NO_XNET_CONNECTION=1 PLACE_NEAR=Q2700:2mm
ROOM=ACC_BUCK
5% 1/32W MF 01005 2 ROOM=ACC_BUCK
2 OMIT
R2702 200K
0.1% 1/32W TF 2 01005
B1
XW2707
A2 B2
2
20% 6.3V CER-X5R 0201
19 27 40 46
ROOM=TRISTAR
SHORT-20L-0.05MM-SM ROOM=TRISTAR
1 NO_XNET_CONNECTION=1
#25741319: Change to 4UF
ROOM=ACC_BUCK
ACC_BUCK_TO_PMU_AMUX
C2708
C
4UF
WLCSP
1
1
PMCM4401VPE
A1 G
20
A2 B2
ROOM=ACC_BUCK
1 1
PP_ACC_BUCK_VAR
PIGA1608-SM
C1 ACC_BUCK_FB
A1
AP_TO_ACC_BUCK_VSEL
From AP GPIO1
B1
C2
12
#25370332: For EMC #25919133: C2707 on P46 VOLTAGE=1.9V
0.47UH-20%-2.52A-0.08OHM
WLCSP
B2
WLCSP
L2700
CRITICAL
S
5% 1/32W MF 2 01005 ROOM=ACC_BUCK
R2710
S
100K
D2700 SOD962-2
A1 G
R2700
1
K
20% 2 6.3V X5R-CERM 0201-1
A2
1
C2700
D
From PMU GPIO14
ROOM=PMU
D
PMU_TO_ACC_BUCK_SW_EN
B1
20
C2705
PMU_AMUX_B3 FOR NOW
ACT_DIODE_TO_COMP_SENSE ROOM=TRISTAR
1
R2704 200K
ACT_DIODE_TO_COMP_OUT
0.1% 1/32W TF 2 01005
ROOM=ACC_BUCK
ACT_DIODE_TO_COMP_POS 46 40 27 19
PP_ACC_VAR
C2706
1
5
0.22UF
10% 6.3V 2 CER-X5R 01005
VCC
U2701
ROOM=ACC_BUCK
4 IN+
B
ACT_DIODE_TO_COMP_NEG
UDFN
B
VOUT 6
3 IN-
NC 2
#26434500: Divider to all 200kohm,0.1% #25987909: To Resistor Divider
NC
VEE
R2706
1
1
SCY992200A
200K
1
ROOM=ACC_BUCK
R2703 200K
0.1% 1/32W TF 2 01005
0.1% 1/32W TF 2 01005
ROOM=ACC_BUCK
ROOM=ACC_BUCK
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
THIS PAGE UNIQUE TO SMALL FORM FACTOR
D
D
M2800
M2800
TRINITY
TRINITY
SYM 1 OF 5
SYM 4 OF 5
SIP
TIGRIS_BUCK_LX
21
53 52 27 26 25 23 21 19 18 10 9 4 PP_VDD_MAIN 46 41 40 39 37 35 34 33 31 28
D2 D3 F2 G2 H2 J2
VDD VDD VDD VDD VDD VDD
F6 G6 H6 J6
BL_SW1_LX
BL2 B2 BL2 B3
BL_SW2_LX
BL1 BL1 BL1 BL1
37
A3 A4 A5 A6 A7 B1 B4 B7 C1 C2 C3 C4 C5 C6 C7 D1 D4 D7 E1 E2 E3 E4 E5 E6 E7 F1 F3 F4 F5 F7 G1 G3 G4 G5 G7
37
M2800
TRINITY SIP
SYM 2 OF 5
L2 L3
ARC N2 ARC N3
VDD VDD
ARC1_LX
35
SPEAKERAMP1_LX
34
M2800
TRINITY SIP L5 L6
M2800 TRINITY SIP
SYM 5 OF 5
A1 A2
GND1 GND1S
B
N5 N6
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
A
C GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
H1 H3 H4 H5 H7 J1 J3 J4 J5 J7 K1 K2 K3 K4 K5 K6 K7 L1 L4 L7 M1 M2 M3 M4 M5 M6 M7 N1 N4 N7 P1 P2 P3 P4 P5
B
GND2 GND2S
C
TIG B5 TIG B6
VDD VDD
P7 P6
D5 D6
53 52 27 26 25 23 21 19 18 10 9 4 PP_VDD_MAIN 46 41 40 39 37 35 34 33 31 28
SIP
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
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A
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7
6
5
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NEW HAMPSHIRE POWER 1
FL2913
2
0201
1
C2914
1
0.1UF 20%
1
PP3V0_ALS_APS_CONVOY
25 19
PP1V8_NH_IO_CONN
ROOM=FOREHEAD
45
2
PP3V0_ALS_CONVOY_CONN 45
01005
C2902
1
ROOM=FOREHEAD
C2917
1
20% 6.3V X5R-CERM 0201-1
2
2.2UF
220PF 5%
2
10V 2 C0G-CERM 01005
6.3V 2 X5R-CERM 01005
C2926 220PF
5% 10V C0G-CERM 01005
ROOM=FOREHEAD
ROOM=FOREHEAD
ROOM=FOREHEAD
ROOM=FOREHEAD
D
1
150OHM-25%-200MA-0.7DCR
33-OHM-25%-1500MA
PP1V8
2
PROX, ALS, & CONVOY POWER
FL2901
13 12 11 9 8 7 5 48 47 46 39 25 18
3
D
FL2902
33-OHM-25%-1500MA 19
PP1V2_NH_NV_DVDD
1
PP1V2_NH_DVDD_CONN
2 0201
1
ROOM=FOREHEAD
C2916 2.2UF
20% 6.3V 2 X5R-CERM 0201-1
1
C2915
1
0.1UF
C2903
FL2910
220PF
20% 6.3V 2 X5R-CERM 01005
ROOM=FOREHEAD
ROOM=FOREHEAD
45
150OHM-25%-200MA-0.7DCR
5% 2 10V C0G-CERM 01005
PP3V0_TRISTAR_ANT_PROX
53 41 40 19
ROOM=FOREHEAD
1
2
FL2903
1
PP2V9_NH_AVDD
2
PP2V9_NH_AVDD_CONN 1
ROOM=FOREHEAD
C2909 2.2UF
20% 2 6.3V X5R-CERM 0201-1 ROOM=FOREHEAD
1
C2901
1
0.1UF
2
2
220PF
20% 2 6.3V X5R-CERM 01005
5% 2 10V C0G-CERM 01005
ROOM=FOREHEAD
ROOM=FOREHEAD
NO_XNET_CONNECTION=1
SPEAKER2
2
AP_TO_NH_CLK_CONN
01005
1
2
ROOM=FOREHEAD
C2910
SPEAKERAMP2_TO_SPEAKER_OUT_POS
46 45 33
2
5% 10V C0G-CERM 01005
SPEAKERAMP2_TO_SPEAKER_OUT_NEG
AP_TO_NH_SHUTDOWN_CONN_L 1
C2935
ROOM=FOREHEAD
2 01005
1
220PF
150OHM-25%-200MA-0.7DCR ROOM=FOREHEAD
C
NO_XNET_CONNECTION=1
ROOM=FOREHEAD
1
5% 10V C0G-CERM 01005
45
56PF
FL2908
C2932 220PF
5% 25V 2 NP0-C0G-CERM 01005
AP_TO_NH_SHUTDOWN_L
5% 10V C0G-CERM 01005
ROOM=FOREHEAD
1
ROOM=FOREHEAD
9
C2908 220PF
ROOM=FOREHEAD
150OHM-25%-200MA-0.7DCR
C
20% 6.3V X5R-CERM 0201-1
C2904
FL2907
1
1
45
NEW HAMPSHIRE I/O AP_TO_NH_CLK
C2927 2.2UF
#24511567: Remove C2918
01005-1
9
1
ROOM=FOREHEAD
10-OHM-750MA 19
PP3V0_PROX_CONN
01005
33 45 46
C2911
NO_XNET_CONNECTION=1
C2931 1
220PF
220PF
5% 10V 2 C0G-CERM 01005
5% 10V 2 C0G-CERM 01005
ROOM=FOREHEAD
ROOM=FOREHEAD
R2903 SPEAKER_TO_SPEAKERAMP2_VSENSE_P
33
CONVOY I/O
1
PDM_ADARE_TO_CONVOY_CLK
100
PDM_ADARE_TO_CONVOY_CLK_CONN
2
1
SPEAKER_TO_SPEAKERAMP2_VSENSE_N
33
1
0.00
1
2
C2906 56PF
MIC3
FL2914
150OHM-25%-200MA-0.7DCR 1
PP_CODEC_TO_FRONTMIC3_BIAS
2 01005
PP_CODEC_TO_FRONTMIC3_BIAS_CONN 1
ROOM=FOREHEAD
45
DZ2905
6.8V-100PF
01005
2
#25170697: R2915 to 240ohm/C2921 to 220pF
R2915 1
240
2
1% 1/32W MF 01005
PROX_BI_AP_AOP_INT_PWM_L_CONN 1
FL2904
C2921
31
FRONTMIC3_TO_CODEC_AIN4_N
1
2 ROOM=FOREHEAD
1
2
FL2911
1 ROOM=FOREHEAD
DZ2906
6.8V-100PF
ROOM=FOREHEAD
01005
FRONTMIC3_TO_CODEC_AIN4_CONN_N 45
NO_XNET_CONNECTION=1
01005
5% 2 10V C0G-CERM 01005
150OHM-25%-200MA-0.7DCR 2 1 ALS_TO_AP_INT_CONN_L
ROOM=FOREHEAD
150OHM-25%-200MA-0.7DCR
45
220PF
ROOM=FOREHEAD
ALS_TO_AP_INT_L
B
45
32
12
5% 10V C0G-CERM 01005
ROOM=FOREHEAD
ROOM=FOREHEAD
A
C2934 220PF
ROOM=FOREHEAD
150OHM-25%-200MA-0.7DCR 1 2 PDM_CONVOY_TO_ADARE_DATA_CONN
45
NO_XNET_CONNECTION=1
1
ROOM=FOREHEAD
5% 2 25V NP0-C0G-CERM 01005
PROX_BI_AP_AOP_INT_PWM_L
SPEAKER_TO_SPEAKERAMP2_VSENSE_CONN_N
2
0% 1/32W MF 01005
5% 2 25V NP0-C0G-CERM 01005
ROOM=FOREHEAD
13 12
5% 10V C0G-CERM 01005
R2904
45
56PF
01005
PROX/ALS I/O
220PF
2
C2905
FL2906
PDM_CONVOY_TO_ADARE_DATA
C2933
ROOM=FOREHEAD
ROOM=FOREHEAD
33
1
#25657495: Update FL2905 to 100ohm 1
45
NO_XNET_CONNECTION=1
ROOM=FOREHEAD
5% 1/32W MF 01005
B
SPEAKER_TO_SPEAKERAMP2_VSENSE_CONN_P
2
0% 1/32W MF 01005
R2905 33
0.00
01005 ROOM=FOREHEAD
FL2909
150OHM-25%-200MA-0.7DCR 45
31
FRONTMIC3_TO_CODEC_AIN4_P
2
1 01005
C2924
ROOM=FOREHEAD
56PF
5% 2 25V NP0-C0G-CERM 01005 ROOM=FOREHEAD
FRONTMIC3_TO_CODEC_AIN4_CONN_P
NO_XNET_CONNECTION=1
1
DZ2907
45 SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare
6.8V-100PF 01005
2
ROOM=FOREHEAD
DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
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D
D
C
C
B
B
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
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CALTRA AUDIO CODEC (ANALOG INPUTS & OUTPUTS) D
D
CRITICAL ROOM=CODEC
U3101
41 41
41 41
44 44
For Borealis
29 29
LOWERMIC1_TO_CODEC_AIN1_P LOWERMIC1_TO_CODEC_AIN1_N
L2 AIN1+ L1 AIN1-
LOWERMIC4_TO_CODEC_AIN2_P LOWERMIC4_TO_CODEC_AIN2_N
K3 AIN2+ L3 AIN2-
REARMIC2_TO_CODEC_AIN3_P REARMIC2_TO_CODEC_AIN3_N
K2 AIN3+ K1 AIN3-
FRONTMIC3_TO_CODEC_AIN4_P FRONTMIC3_TO_CODEC_AIN4_N
J3 AIN4+ J4 AIN4-
C
WLCSP-1
SYM 1 OF 3
CS42L71
AOUT1+ AOUT1-
L9 NC M9NC
AOUT2+ AOUT2-
L8 NC M8NC
HPOUTA HPOUTB
K10NC K11NC
HS3
M5
HS4
M4
HS3_REF HS4_REF
HSIN+ HSIN-
WAS FOR RECEIVER; REPLACED BY SPEAKER IN D1xy
L10 M10
D1 NC E1 NC
C
HPDETECT J9 NC NC NC
F1 AIN5+ G1 AIN5-
NC NC
F2 AIN6+ F3 AIN6-
ROOM=CODEC
C3107 100PF 1
HAWKING_TO_CODEC_AIN7_P HAWKING_TO_CODEC_AIN7_N
44 44
B
33
A
53 27 26 25 23 21 19 18 10 9 4 52 46 41 40 39 37 35 34 33 28
1
NC NC
A4 DMIC1_CLK B4 DMIC1_DATA
DP DN
J12 H12
MBUS_REF
NC
C4 DMIC2_CLK C3 DMIC2_DATA
G10
NC NC
A3 DMIC3_CLK B3 DMIC3_DATA
NC NC
A2 DMIC4_CLK B2 DMIC4_DATA
PDM_CODEC_TO_SPKAMP2_CLK PDM_CODEC_TO_SPKAMP2_DATA
33
5% 16V NP0-C0G 01005
R3104 20.0
G2 AIN7+ G3 AIN7-
90_MIKEYBUS_CALTRA_DATA_P 90_MIKEYBUS_CALTRA_DATA_N MIKEYBUS_REFERENCE 41 1
R3101 100
2
90_MIKEYBUS_DATA_P 40
2
5% 1/32W MF 01005
ROOM=CODEC
R3103 20.0
1
90_MIKEYBUS_DATA_N 40
2
5% 1/32W MF 01005
ROOM=CODEC
C3106 100PF 1
5% 1/32W MF 01005 2ROOM=CODEC
2
5% 16V NP0-C0G 01005
A9 PDM_CLK B9 PDM_DATA
B
ROOM=CODEC
PP_VDD_MAIN 1
C3112 220PF
5% 2 10V C0G-CERM 01005
ROOM=CODEC
1
C3113
SYNC_MASTER=Sync
220PF
SYNC_DATE=05/17/2016
PAGE TITLE
spare
5% 2 10V C0G-CERM 01005
DRAWING NUMBER
ROOM=CODEC
Apple Inc.
AC return path for Mikeybus which is referenced to GND and VDD_MAIN
051-00419
REVISION
R
Radar 21203307
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
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6
5
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1
CALTRA AUDIO CODEC (POWER & I/O) 35 34 33 19
PP1V8_VA 1
C3209 2.2UF
D
20% 6.3V 2 X5R-CERM 0201-1
D
ROOM=CODEC
CODEC_AGND
PP_VDD_BOOST 1
C3212
1
0.1UF
1
20% 6.3V X5R-CERM 01005
2
0.1UF
20% 6.3V 2 X5R-CERM 01005
2
ROOM=CODEC
C3205 2.2UF
20% 6.3V X5R-CERM 0201-1
ROOM=CODEC
47 41 40 37 36 32 21 20 18 16 53 52 48
ROOM=CODEC
1
5% 1/32W MF 2 01005 ROOM=CODEC
0.1UF
2
20% 6.3V X5R-CERM 01005
R3202
PP1V2_VD_FILT
ROOM=CODEC
ROOM=CODEC
1
C3217
1
20% 6.3V X5R 0201-1
20% 6.3V 2 X5R 0201-1
1.0UF
2
1.0UF
ROOM=CODEC
C 4.7UF 1
LOWERMIC1_TO_CODEC_BIAS_FILT_RET
PP_CODEC_TO_LOWERMIC1_BIAS LOWERMIC1_BIAS_FILT_IN
41
2
M6 MIC1_BIAS K7 MIC1_BIAS_FILT
U3101
1
35 34 33 13
11
36 11
36 11
K12NC
36 11
11
CRITICAL
PP_CODEC_TO_LOWERMIC4_BIAS LOWERMIC4_BIAS_FILT_IN
41
36 35 34 33 11 36 35 34 33 11
L6 MIC2_BIAS J7 MIC2_BIAS_FILT
FLYC
36 35 34 33
L12NC
36 35 34 33
13
ROOM=CODEC
C3201
REARMIC2_TO_CODEC_BIAS_FILT_RET
1
13 44
2
PP_CODEC_TO_REARMIC2_BIAS REARMIC2_BIAS_FILT_IN
13
K6 MIC3_BIAS L5 MIC3_BIAS_FILT
13
20% 6.3V X5R-CERM1 402
FLYN
C3202
FRONTMIC3_TO_CODEC_BIAS_FILT_RET
1
29
PP_CODEC_TO_FRONTMIC3_BIAS FRONTMIC3_BIAS_FILT_IN
+VCP_FILT
J6 MIC4_BIAS K5 MIC4_BIAS_FILT 1
C3223
1
1.0UF
ROOM=CODEC
XW3203 SHORT-20L-0.05MM-SM
SPI_AP_TO_CODEC_MAGGIE_SCLK
C9 C8
CS* CCLK
SPI_AP_TO_CODEC_MAGGIE_MOSI SPI_CODEC_MAGGIE_TO_AP_MISO
B8 A8
MOSI MISO
C12
MCLK
CS42L71 ROOM=CODEC
CRITICAL
I2S_AP_TO_CODEC_MCLK
B11 C11 A11 A10
XSP_SCLK XSP_LRCK/FSYNC XSP_SDIN/DAC2B_MUTE XSP_SDOUT
11 20
PMU_TO_CODEC_DIGLDO_PULLDN
H5 J5
DIGLDO_PULLDN DIGLDO_PDN
C3224
20% 2 6.3V X5R 0201-1
ROOM=CODEC
1NO_XNET_CONNECTION
I2S_CODEC_XSP_TO_AOP_BCLK I2S_CODEC_XSP_TO_AOP_LRCLK I2S_AOP_TO_CODEC_XSP_DOUT I2S_CODEC_XSP_TO_AOP_DIN
ASP_SCLK ASP_LRCK/FSYNC ASP_SDIN ASP_SDOUT
1.0UF
20% 2 6.3V X5R 0201-1
ROOM=FOREHEAD
C6 C5 B5 B6
MSP_SCLK MSP_LRCK/FSYNC MSP_SDIN MSP_SDOUT
11
J10NC
I2S_MAGGIE_TO_AP_L26_CODEC_BCLK I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK I2S_MAGGIE_TO_L26_CODEC_DOUT I2S_L26_CODEC_TO_MAGGIE_DIN
B7 C7 D8 A7
11
20% 6.3V X5R-CERM1 402
2
B
2
INT*
WLCSP-1
SYM 3 OF 3
I2S_AP_TO_CODEC_MSP_BCLK I2S_AP_TO_CODEC_MSP_LRCLK I2S_AP_TO_CODEC_MSP_DOUT I2S_CODEC_TO_AP_MSP_DIN
11
M12NC
ROOM=CODEC
4.7UF
K9
AUDIO_TO_AOP_INT_L
SPI_AP_TO_CODEC_CS_L
20% 6.3V X5R-CERM1 402
45
WAKE*
JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO
ROOM=CODEC
2
4.7UF
K8
NC
ROOM=CODEC
CS42L71
C3204
LOWERMIC4_TO_CODEC_BIAS_FILT_RET
FLYP
U3101
SYM 2 OF 3
ROOM=CODEC
41
RESET*
WLCSP-1
20% 6.3V X5R-CERM1 402
4.7UF
H3
5% 1/32W MF 01005 2
C3221
ROOM=CODEC
C3203
CODEC_RESET_L
1
100K
VP_MBUS H10
20% 6.3V 2 X5R-CERM 01005
VA J1
ROOM=CODEC
0.1UF
C3215
VPROG_CP H11
20% 6.3V 2 CERM-X5R 0402-9
R3201 1.00K
VP M7
10UF
C3213
1
VL A5
C3211
1
VD_FILT C1 VD_FILT E12
1
41
PP1V8_SDRAM
PP1V8_SDRAM
VD D12 VD G12
47 41 40 37 36 32 21 20 18 16 53 52 48
C3214
VCP J11
53 38 37 25 23 19
32
GNDCP
ROOM=CODEC
L11
OMIT 1
C3222
1
1.0UF
20% 2 6.3V X5R 0201-1
ROOM=CODEC
C3225 1.0UF
2
20% 6.3V X5R 0201-1
ROOM=CODEC
-VCP_FILT LP_FILT+
M11NC F12
CALTRA_LP_FILTP 1
C3220 0.1UF
2
NC NC
M3 HS_BIAS_FILT M2 HS_BIAS_FILT_REF
20% 6.3V X5R-CERM 01005
H1
TSTO TSTO TSTO TSTO TSTO TSTO TSTO TSTO
D11 B10 D5 D6 E5 E6 E7 K4
TSTI TSTI TSTI TSTI TSTI TSTI TSTI TSTI TSTI
C10 D10 D7 D9 E8 E9 G11 H4 M1
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
A1 A12 B12 E2 E3 E4 E10 F4 F5 F6 F7 F8 F9 F10 G4 G5 G6 G7 G8 G9 H6 H7 H8 H9
NC NC NC NC NC NC NC NC
C
B
GND J8
ROOM=CODEC
FILT+
D3 NC D4 NC D2 NC C2 NC
CALTRA_FILTP 1
C3208 10UF
GNDD GNDD GNDD GNDD
GNDHS
GNDP
GNDA
L4
L7
J2
A
A6 B1 E11 F11
2
20% 6.3V CERM-X5R 0402-9
ROOM=CODEC
FILT-
H2 SYNC_MASTER=Sync
CODEC_AGND
SYNC_DATE=05/17/2016
PAGE TITLE
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32
DRAWING NUMBER
Apple Inc.
XW3202 SHORT-10L-0.1MM-SM 2
051-00419
REVISION
R
1
ROOM=CODEC
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
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D
D
SPEAKER AMPLIFIER 2
PP_VDD_MAIN
PP1V8_VA 10UF
20% 10V X5R-CERM 0402-8 ROOM=SPKAMP2
1
10UF
20% 6.3V 2 CERM-X5R 0402-9 ROOM=SPKAMP2
2
C3328
1
10UF
20% 6.3V 2 CERM-X5R 0402-9 ROOM=SPKAMP2
C3313
C3329
1
10UF
1
1
2.2UF 20%
20% 6.3V 2 CERM-X5R 0402-9
2
ROOM=SPKAMP2
L3302
VP
1.2UH-20%-3.0A-0.080OHM 1 2 SPEAKERAMP2_LX PIQA20161T-SM ROOM=SPKAMP2 47 47 35 34 32 13 12
I2C2_AP_SDA
R3301
34
100K
5% 1/32W MF 2 01005
29
PDM_ADARE_TO_CONVOY_CLK
MAKE_BASE=TRUE
1
ROOM=SPKAMP2
R3304 100K
SCL
AUDIO_TO_AOP_INT_L
A7
INT*
A6
RESET*
SPKAMP1_TO_SPKAMP2_SYNC
F6
ALIVE/SYNC
PDM_ADARE_TO_CONVOY_CLK
E5
AD0/PDM_CLK1
I2S_AOP_TO_MAGGIE_L26_MCLK
B7
MCLK
I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK
C6
LRCK/FSYNC
36 35 34 32
I2S_MAGGIE_TO_L26_CODEC_DOUT
D7
SDIN
36 35 34 32
I2S_L26_CODEC_TO_MAGGIE_DIN
B6
SDOUT
31
PDM_CODEC_TO_SPKAMP2_CLK
F7
PDM_CLK0
31
PDM_CODEC_TO_SPKAMP2_DATA
E7
PDM_DATA0
29
PDM_CONVOY_TO_ADARE_DATA
D5
PDM_DATA1
36 35 34 32 11
B
ROOM=SPKAMP2
PP_SPKR2_VBOOST 1
CRITICAL
C3312
5% 2 10V C0G-CERM 01005 ROOM=SPKAMP2
ISNS+ F1 ISNS- E1
VSNS+ E2 VSNS- E3
SCLK
1
220PF
VBST_A C1 VBST_A D1
ROOM=SPKAMP2
E6
C7
VBST_B A1 VBST_B B1
WLCSP
SDA
I2S_MAGGIE_TO_AP_L26_CODEC_BCLK
36 35 34 32 11
20% 2 6.3V X5R-CERM 0201-1
2.2UF
C
CS35L26-A1
C3311
1
0.1UF
C3325
1
10UF
10% 16V X5R-CERM 0201
2
C3324
2
ROOM=SPKAMP2
FILT+ F4 GNDP
GNDA
1
10UF
20% 10V X5R-CERM 0402-8
20% 10V X5R-CERM 0402-8
2
ROOM=SPKAMP2
1
SPEAKERAMP2_ISENSE_P SPEAKERAMP2_ISENSE_N
C3306
1
20% 10V X5R-CERM 0402-8
2
10UF
2
ROOM=SPKAMP2
ROOM=SPKAMP2
C3308 10UF
20% 10V X5R-CERM 0402-8
ROOM=SPKAMP2
C3319 0.01UF
2
10% 6.3V X5R 01005
ROOM=SPKAMP2 NO_XNET_CONNECTION
SPEAKER_TO_SPEAKERAMP2_VSENSE_P SPEAKER_TO_SPEAKERAMP2_VSENSE_N
29 29
SPEAKERAMP2_TO_SPEAKER_OUT_POS SPEAKERAMP2_TO_SPEAKER_OUT_NEG
OUT+ D2 OUT- C2
A3 A4 B3 B4 C3 C4 C5 D3 D4
5% 1/32W MF 2 01005 ROOM=SPKAMP2
36 35 34 13
D6
C3316
VA
U3301
SW SW
I2C2_AP_SCL
AP_TO_SPKAMP2_RESET_L 1
A2 B2
6.3V X5R-CERM 01005 ROOM=SPKAMP2
CRITICAL
C
1
0.1UF 20%
6.3V X5R-CERM 2 0201-1
ROOM=SPKAMP2
C3315
C3331 1
1
10% 10V 2 X5R 01005
2
1000PF
SPEAKERAMP2_FILT
AD1 F3
C3318
2
10% 10V X5R 402-1 ROOM=SPKAMP2
29 45 46 29 45 46
C3323 1000PF
ROOM=SPKAMP2
1
10% 10V X5R 01005
Pg46: Compass Compensation Coil
ROOM=SPKAMP2
1UF
B5 E4 F2
C3326
1
19 32 34 35
F5
C3327
A5
53 27 26 25 23 21 19 18 10 9 4 52 46 41 40 39 37 35 34 31 28
(North)
B
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
SPEAKER AMPLIFIER 1
2
1
(South) D
D
PP_VDD_MAIN
C3407
1
10UF
20% 10V X5R-CERM 2 0402-8
1
1
10UF
20% 6.3V CERM-X5R 2 0402-9
6.3V 2 X5R-CERM 01005
ROOM=SPKAMP1
48 48 35 33 32 13
PULLED LOW ON PG 35 35 13
A2 B2
SPEAKERAMP1_LX
D6
I2C_AOP_SDA
E6
I2C_AOP_SCL
A7
AUDIO_TO_AOP_INT_L
A6
AOP_TO_SPKAMP1_ARC_RESET_L 33
F6
SPKAMP1_TO_SPKAMP2_SYNC
E5
GND
MAKE_BASE=TRUE
36 35 33 13 36 35 33 32 11
I2S_MAGGIE_TO_AP_L26_CODEC_BCLK
36 35 33 32 11
I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK
36 35 33 32 36 35 33 32
B7
I2S_AOP_TO_MAGGIE_L26_MCLK
C7 C6 D7
I2S_MAGGIE_TO_L26_CODEC_DOUT
B6
I2S_L26_CODEC_TO_MAGGIE_DIN NC NC
E7 D5
A1 VBST_B B1 VBST_B C1 VBST_A D1 VBST_A
WLCSP
SDA
ROOM=SPKAMP1
CRITICAL
20% 6.3V X5R-CERM 0201-1 ROOM=SPKAMP1
PP_SPKR1_VBOOST 1
C3427
1
220PF
2
5% 10V C0G-CERM 01005 ROOM=SPKAMP1
INT*
C3428
1
10% 16V X5R-CERM 0201
20% 10V 2 X5R-CERM 0402-8
0.1UF
2
ROOM=SPKAMP1
C3403 10UF
ROOM=SPKAMP1
1
C3404 10UF
20% 10V 2 X5R-CERM 0402-8
F1 ISNS+ E1 ISNS-
ALIVE/SYNC AD0/PDM_CLK1 MCLK
E2 VSNS+ E3 VSNS-
SCLK
1
SPEAKERAMP1_ISENSE_P SPEAKERAMP1_ISENSE_N
1
C3431
1
10UF
20% 10V 2 X5R-CERM 0402-8
ROOM=SPKAMP1
RESET*
ROOM=SPKAMP1
C3432 10UF
2
20% 10V X5R-CERM 0402-8
ROOM=SPKAMP1
C3430 0.01UF
2
10% 6.3V X5R 01005
ROOM=SPKAMP1 NO_XNET_CONNECTION
SPEAKER_TO_SPEAKERAMP1_VSENSE_P SPEAKER_TO_SPEAKERAMP1_VSENSE_N
41 41
LRCK/FSYNC D2 OUT+ C2 OUT-
SDIN SDOUT
SPEAKERAMP1_TO_SPEAKER_OUT_POS SPEAKERAMP1_TO_SPEAKER_OUT_NEG
PDM_CLK0 FILT+
PDM_DATA0 PDM_DATA1
GNDP
A3 A4 B3 B4 C3 C4 C5 D3 D4
B
F7
2.2UF
C
CS35L26-A1
SCL
C3426
VA
U3402
SW SW
19 32 33 35
F5
VP
28
1
2
ROOM=SPKAMP1
C TO TRINITY
C3425 0.1UF 20%
A5
ROOM=SPKAMP1
C3405
PP1V8_VA
GNDA
AD1
F4
C3422
SPEAKERAMP1_FILT
1000PF
F3 1
1
10% 10V 2 X5R 01005
C3429 2.2UF
B5 E4 F2
53 27 26 25 23 21 19 18 10 9 4 52 46 41 40 39 37 35 33 31 28
#25112685,Remove C3414 See SPKAMP1 C3424 on Pg46
ROOM=SPKAMP1
20% 2 6.3V X5R-CERM 0201-1
1
41 41
C3434 1000PF
10% 2 10V X5R 01005
B
ROOM=SPKAMP1
ROOM=SPKAMP1
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
ARC DRIVER D
D
See ARC1 C3530 at Pg46 #25742582,Add back C3531 for D10x at Pg46 0201 C3525 is at Pg46 53 27 26 25 23 21 19 18 10 9 4 52 46 41 40 39 37 34 33 31 28
PP_VDD_MAIN
PP1V8_VA
C3532
1
1
10UF
C3527
1
0.1UF 20%
20% 6.3V CERM-X5R 2 0402-9
C3534 2.2UF
20% 6.3V 2 X5R-CERM 0201-1
6.3V 2 X5R-CERM 01005
ROOM=ARC1
ROOM=ARC1
19 32 33 34 35
ROOM=ARC1
C F5
A5
C VA
VP
28
48 48 34 33 32 13 34 13
A2 B2
ARC1_LX
D6
I2C_AOP_SDA
E6
I2C_AOP_SCL
A7
AUDIO_TO_AOP_INT_L
A6
AOP_TO_SPKAMP1_ARC_RESET_L 1
NC FROM HOMER PER #25452686
R3508 100K
35 34 33 32 19
5% 1/32W MF 2 01005 ROOM=ARC1
PP1V8_VA
MAKE_BASE=TRUE
36 34 33 13 36 34 33 32 11
NOSTUFF
C3501
1
36 34 33 32 11
5% 16V 2 CERM 01005
36 34 33 32
10PF
36 34 33 32
F6 NC
PP1V8_VA
B7
I2S_AOP_TO_MAGGIE_L26_MCLK
C7
I2S_MAGGIE_TO_AP_L26_CODEC_BCLK
C6
I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK
D7
I2S_MAGGIE_TO_L26_CODEC_DOUT
B6
I2S_L26_CODEC_TO_MAGGIE_DIN
ROOM=ARC1
NC
B
E5
E7 D5
VBST_B VBST_B
CS35L26-A1 WLCSP
SDA
VBST_A VBST_A
ROOM=SPKAMP2
SCL
CRITICAL
A1 B1 C1 D1
VOLTAGE=8.0V
PP_ARC1_VBOOST 1
C3526
1
5% 10V C0G-CERM 01005
10% 2 16V X5R-CERM 0201
220PF
2
C3535
1
0.1UF
ROOM=ARC1
INT*
ROOM=ARC1
C3537
1
20% 10V X5R-CERM 0402-8
20% 2 10V X5R-CERM 0402-8
10UF
2
C3524
ROOM=ARC1
ISNS+ ISNS-
ALIVE/SYNC AD0/PDM_CLK1 MCLK
VSNS+ VSNS-
SCLK
F1 E1
E2 E3
C3538
1
10UF
10UF
20% 2 10V X5R-CERM 0402-8
ROOM=ARC1
RESET* 1
ARC1_ISENSE_P ARC1_ISENSE_N
ROOM=ARC1
1
C3539 10UF
20% 2 10V X5R-CERM 0402-8 ROOM=ARC1
C3528 0.01UF
10% 2 6.3V X5R 01005
ROOM=ARC1 NO_XNET_CONNECTION
SOLENOID1_TO_ARC1_VSENSE_POS SOLENOID1_TO_ARC1_VSENSE_NEG
41 41
LRCK/FSYNC SDIN
OUT+ OUT-
SDOUT
D2 C2
VOLTAGE=8.0V
ARC1_TO_SOLENOID1_OUT_POS ARC1_TO_SOLENOID1_OUT_NEG
VOLTAGE=8.0V
41 41
PDM_CLK0 FILT+
PDM_DATA0 PDM_DATA1
GNDP
A3 A4 B3 B4 C3 C4 C5 D3 D4
NC
F7
U3502
SW SW
GNDA
AD1
F4
C3529
ARC1_FILT
F3 1
C3536 2.2UF
B5 E4 F2
TO TRINITY
20% 2 6.3V X5R-CERM 0201-1
1
1000PF
10% 10V 2 X5R 01005
ROOM=ARC1
1
C3542
B
1000PF
10% 2 10V X5R 01005
ROOM=ARC1
ROOM=ARC1
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
D
D
MAGGIE LDO
MAGGIE
APN: 353S00842
APN: 336S00020
U3603
47 41 40 37 36 32 21 20 18 16 53 52 48
PP1V8_SDRAM
LD39130S-1.2V/AP
A1
IN
B1
EN
OUT A2
CSP
PP1V2_MAGGIE 1
C3605
1
6.3V CER-X5R 0201
2
4UF 20%
GND B2
2
C3601 0.1UF
ROOM=ARC_CTRL
ROOM=ARC_CTRL
R3601 1
100
2
20% 6.3V X5R-CERM 01005
PP1V2_MAGGIE_PLL
5% 1/32W MF 01005
1
C3602 0.1UF
ROOM=ARC_CTRL
2
20% 6.3V X5R-CERM 01005
ROOM=ARC_CTRL
C
C
VPP_2V5 must be > 1.71V for SPI Slave programming
PP1V8_MAGGIE_IMU A5
D4
C3 SPI_VCCIO1
ROOM=ARC_CTRL
B3
20% 6.3V X5R-CERM 01005
VCC
2
VPP_2V5
ROOM=ARC_CTRL
0.1UF
VCCPLL
20% 6.3V 2 X5R-CERM 0201-1
C3606 C4
1
2.2UF
VCCIO_2
C3604
A4
1
VCCIO_0
36 24 18
ICE5LP4K-SWG36I
SPI_MAGGIE_TO_HOMER_POS_SCLK 47 41 40 37 36 32 21 20 18 16 53 52 48
PP1V8_SDRAM
C3603
1
2.2UF
13
20% 6.3V 2 X5R-CERM 0201-1 ROOM=HOMER
B
13
SPI_HOMER_TO_MAGGIE_POS_MISO AOP_TO_MAGGIE_EN MAGGIE_TO_AOP_INT
F6 E6 D6 NC D5 F5 E5
IOB_2A IOB_3B_G6 IOB_4A IOB_5B IOB_6A IOB_7B
BANK 0
MAGGIE_TO_HOMER_WAKE
IOB_10A WLCSP IOB_11B_G5 IOB_12A_G4_CDONE IOB_16A IOB_20A IOB_25B_G3 IOB_26A IOB_27B IOB_29B IOB_30A IOB_31B IOB_32A_SPI_SO IOB_33B_SPI_SI IOB_34A_SPI_SCK IOB_35B_SPI_CSN BANK 1
36
U3602
BANK 2
HOMER STM32L0 MICRO STM32L03 APN: 337S00231
A2 IRLED NC C6 RGB0 NC B6 RGB1 NC A6 RGB2 NC B5 IOT_46B_G0
R3604
B4 NC F4 E4 F3 E3 C2 B1 D2 E2 C1 B2 F2 D1 E1 F1
I2S_MAGGIE_TO_AP_L26_CODEC_BCLK_R MAGGIE_TO_AP_CDONE UART_AOP_TO_MAGGIE_TXD I2S_MAGGIE_TO_AP_DIN I2S_AOP_TO_MAGGIE_L26_MCLK I2S_MAGGIE_TO_L26_CODEC_DOUT I2S_L26_CODEC_TO_MAGGIE_DIN I2S_AP_TO_MAGGIE_DOUT I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK SPI_CODEC_MAGGIE_TO_AP_MISO SPI_AP_TO_CODEC_MAGGIE_MOSI SPI_AP_TO_CODEC_MAGGIE_SCLK SPI_AP_TO_MAGGIE_CS_L
1
VDD
VDDA
U3601
ROOM=HOMER
STM32L031E6Y6D
12 12
E5 PA0_CLK_INROOM=HOMER PB0 NC B4 PA1 PB1 WLCSP NC D4 PA2 PB3 E4 PA3 PB6 B3 PA4 PB7 D3 PA5 NC PC14_OSC32_IN E3 PA6 PC15_OSC32_OUT C3 PA7 NC C1 PA8 RST* B1 PA9 BOOT0 C2 PA10 A1 PA13 A2 PA14
UART_HOMER_TO_AP_RXD UART_AP_TO_HOMER_TXD 36 MAGGIE_TO_HOMER_WAKE
R3607 1
100
AP_BI_HOMER_BOOTLOADER_ALIVE_R
2
5% 1/32W MF 01005
13
ROOM=HOMER
47 41 47 41 13 53 17 13
HOMER_TO_AOP_WAKE_INT I2C_HOMER_SCL I2C_HOMER_SDA SWD_AP_BI_HOMER_SWDIO SWD_AP_TO_MANY_SWCLK
E1
VSSA
A
E2 D2 B2 A3 A4
GND GND
11
MAGGIE DRIVES TO ARC, SPKRS, AP, CODEC
I2S_MAGGIE_TO_AP_L26_CODEC_BCLK
11 32 33 34 35
1% 1/32W MF 01005 ROOM=ARC_CTRL
MAGGIE <-> AP (SDIN)
13 33 34 35 32 33 34 35
MAGGIE <-> ARC, SPKRS, CODEC (SDOUT)
32 33 34 35
MAGGIE <-> ARC, SPKRS, CODEC (SDIN)
11
MAGGIE <-> AP (SDOUT)
PP1V8_MAGGIE_IMU 1
R3605
11 32 33 34 35 11 32
5% 1/32W MF 2 01005
MAGGIE DRIVES TO ARC, SPKRS, AP, CODEC
1
1
18 24 36
R3602 10K
5% 1/32W MF 2 01005
11 32 11 32
B
9 12
R3603 511K
1% 1/32W MF 2 01005
SPI_MAGGIE_TO_HOMER_POS_MOSI
NC
B5 NC C5 NC NOTE: RESET HAS INTERNAL 65K PULLUP D5 PMU_TO_HOMER_RESET_L A5
CRITICAL
13
2
AP_TO_MAGGIE_CRESETB_L
ROOM=ARC_CTRL
C5 A3
SM PP
A1
D1
ROOM=HOMER
PP3602 P2MM-NSM
GND_LED
1
C4
SM PP
12
33.2
10K
CRESET_B D3
PP3601 P2MM-NSM
1
AP_BI_HOMER_BOOTLOADER_ALIVE 1
R3611 27K
5% 1/32W MF 2 01005
20 12
1
C3607 0.1UF
20% 2 6.3V X5R-CERM 01005 ROOM=HOMER
ROOM=HOMER
#24543115: Scrub Value
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
DISPLAY & TOUCH - POWER SUPPLIES CHESTNUT DISPLAY PMU
PP_CHESTNUT_CP 1
APN:338S1172
20% VOLTAGE=10V 2 X5R-CERM 0402-8
C3722 See Page46
PP_VDD_MAIN CRITICAL
C3710
1
6.3V CERM-X5R 0402-9
2
10UF 20%
L3704
1.0UH-20%-2.25A-0.15OHM PIXB2016FE-SM
D1 2
B2
CHESTNUT_LX
6.3V
A2 D3
I2C0_AP_SCL
47 20
D2
I2C0_AP_SDA
47
C3
LCM_TO_CHESTNUT_PWR_EN PMU_TO_AOP_TRISTAR_ACTIVE_READY
39 20 40 20 13 7
C2 E1
CHESTNUT_TO_PMU_ADCMUX
VIN
ROOM=CHESTNUT
2
B3 LCMBST B4 CPUMP
SYNC NO INT PULL
SCL SDA
VNEG
LCM_EN
VNEG(SUB)
200K INT PD
HVLDO1
RESET* NO INT PULL
ADCMUX
HVLDO2 HVLDO3
NOSTUFF C3727
D #24543286: Densense Cap for Chestnut Charge Pump
56PF
5% 25V NP0-C0G-CERM 01005
2
5% 25V NP0-C0G-CERM 01005
ROOM=CHESTNUT
PP6V0_LCM_BOOST
E3
PN5V7_LCM_MESON_AVDDN
39
PP5V7_MESON_AVDDH
39
PP5V7_LCM_AVDDH
39
PP5V1_TOUCH_VDDH
39
E2 A4 A3 A1 1
C3711
1
1UF 20%
2
C3712
1
10UF
16V CER-X5R 0201
C3713
1
20% 10V X5R-CERM 0402-8
20% 10V 2 X5R-CERM 0402-8
10UF
20% 10V X5R-CERM 0402-8
2
ROOM=CHESTNUT
2
ROOM=CHESTNUT
C3714
1
10UF
ROOM=CHESTNUT
ROOM=CHESTNUT
C3715
1
4.7UF
2
20% 10V X5R-CERM 0402 ROOM=CHESTNUT
C3716
1
20% 10V X5R-CERM 0402
5% 10V 2 C0G-CERM 01005
4.7UF
2
ROOM=CHESTNUT
C3717 220PF
ROOM=CHESTNUT
#26634069:D1x, C3715/C3716 to 138S0719 0402 4.7uF
LED BACKLIGHT DRIVER - 6LED
C
1
ROOM=CHESTNUT
CRITICAL
SW
NOSTUFF C3726 56PF
C4 CF1 E4 CF2
BGA
C1
20
1
U3703 TPS65730A0PYFF
ROOM=CHESTNUT
ROOM=CHESTNUT
PN_CHESTNUT_CN
ROOM=CHESTNUT
B1 PGND1 D4 PGND2
D
1
AGND
53 52 27 26 25 23 21 19 18 10 9 4 46 41 40 39 37 35 34 33 31 28
C3707 10UF
C
CRITICAL
D3701 DSN2
APN:353s00640 28
BL_SW2_LX
A
K
25V
NSR05F30NXT5G
ROOM=BACKLIGHT
TO TRINITY
CRITICAL
D3702
53 52 46 27 26 25 23 21 19 18 10 9 4 41 40 39 37 35 34 33 31 28
PP_VDD_MAIN
28
NSR0530P2T5G A
BL_SW1_LX
C3702 1
SOD-923-1
20% VOLTAGE=6.3V 2 CERM-X5R 0402-9
U3701
D4 IN
47 47 9 53 26
1
2% 50V C0G 0201
20% 2 35V X5R 0402
220PF
OUT
PP1V8_SDRAM
D3 VIO/HWEN
DWI_PMGR_TO_BACKLIGHT_DATA DWI_PMGR_TO_BACKLIGHT_CLK
C2 SDI C3 SCK
SW2_1 A3 SW2_2 A4
I2C0_AP_SDA I2C0_AP_SCL
B2 SDA A2 SCL
LED1 C1 LED2 B1
AP_TO_MUON_BL_STROBE_EN
D1 TRIG
BB_TO_STROBE_DRIVER_GSM_BURST_IND
D2 INHIBIT
2.2UF
ROOM=BACKLIGHT PLACE_NEAR=U3701:2MM
A1
C3725
1
C3704
1
2.2UF
20% 2 35V X5R 0402
C3706
1
20% 35V X5R 0402
20% 2 35V X5R 0402
2.2UF
2
C3705 2.2UF
1
39
C3721 2.2UF
20% 2 35V X5R 0402
SW1 C4
PP_LCM_BL_CAT1 39 PP_LCM_BL_CAT2 39
ROOM=BACKLIGHT
B
B3 B4
B
GND GND
11
DSBGA
CRITICAL
C3703
2
LM3539A1
ROOM=BACKLIGHT
11
1
ROOM=BACKLIGHT
10UF
48 47 41 40 36 32 21 20 18 16 53 52
PP_LCM_BL_ANODE
K
25V
1
2
MOJAVE MESA BOOST
R3701 200K
1% 1/32W MF 01005
ROOM=BACKLIGHT
APN:353S00671
L3703
1
10UF
CRITICAL
U3702
20% 6.3V CERM-X5R 2 0402-9
BGA
B1 SW
ROOM=MOJAVE 53 38 32 25 23 19
PP_VDD_BOOST
C3724
A
38 4
MESA_TO_BOOST_EN
B2 EN_M A3 EN_S
PP17V0_MOJAVE_LDOIN
C2 LDOIN
10UF
20% 6.3V 2 CERM-X5R 0402-9
C3708 100PF
5% 2 35V NP0-C0G 01005
VOUT C3
1
C3720 2.2UF
20% 2 35V X5R 0402
ROOM=MOJAVE
A1
ROOM=MOJAVE
1
CRITICAL
A2 VIN 1
PP16V0_MESA
LM3638A0 ROOM=MOJAVE
AGND
C3718
0403 ROOM=MOJAVE
ROOM=MOJAVE
PMID C1
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
1
C3709 100PF
B3
PP_VDD_MAIN
PGND
53 52 27 26 25 23 21 19 18 10 9 4 46 41 40 39 37 35 34 33 31 28
1.0UH-20%-0.4A-0.636OHM 1 2 POS18V0_MESA_LX
5% 2 35V NP0-C0G 01005
ROOM=MOJAVE
1
spare
C3719 2.2UF
DRAWING NUMBER
20% 35V 2 X5R 0402
Apple Inc.
ROOM=MOJAVE
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
MESA POWER 19
1
C3813
C3815
1
2.2UF
2.2UF
20% 6.3V 2 X5R-CERM 0201-1
1
C3822
1
0.1UF
20% 6.3V 2 X5R-CERM 0201-1
ROOM=MAMBA_MESA
PP3V0_MESA_CONN 38
0201 ROOM=MAMBA_MESA
2.2UF
20% 6.3V 2 X5R-CERM 0201-1
ROOM=MAMBA_MESA
C3821
1
2
ROOM=MAMBA_MESA
38
5% 10V 2 C0G-CERM 01005
ROOM=MAMBA_MESA
J3801
BB35C-RA24-3A F-ST-SM
C3804 220PF
20% 6.3V 2 X5R-CERM 01005
ROOM=MAMBA_MESA
PP3V0_MESA_CONN
38
PP16V0_MESA_CONN
38
MAMBA_TO_LCM_MDRIVE_CONN_MESA
GUARD
D
FL3801
150OHM-25%-200MA-0.7DCR 48 19
1
PP1V8_MESA 1
2
PP1V8_MESA_CONN
01005
C3814
ROOM=MAMBA_MESA
2.2UF
45
1
1
C3802
C3807
PP3801
5% 2 25V NP0-C0G-CERM 01005
5% 10V 2 C0G-CERM 01005
ROOM=MAMBA_MESA
P2MM-NSM SM PP 1
56PF
220PF
20% 2 6.3V X5R-CERM 0201-1
LCM_TO_MAMBA_MSYNC_CONN
38
45 39
47 47 38
AP_TO_TOUCH_MAMBA_RESET_CONN_L TP_MAMBA_HINT_L I2C_TOUCH_BI_MAMBA_SDA I2C_TOUCH_TO_MAMBA_SCL
PP1V8_TOUCH_TO_MAMBA_CONN
26
25
2 4 6 8 10 12 14 16 18 20 22 24
1 3 5 7 9 11 13 15 17 19 21 23
28
27
FL3802
PP16V0_MESA_CONN
01005 ROOM=MAMBA_MESA
1
53 37 32 25 23 19
C3803
C3828
MAMBA POWER
20% 6.3V 2 X5R-CERM 0201-1
MESA DIGITAL I/O FL3807
47 46 39 38 18
150OHM-25%-200MA-0.7DCR
C
1
R3807
LP5907SNX-2.75 X2SON 4 VIN VOUT 1
PP1V8_TOUCH
1
2
1
2
38
2
C3816
11
SPI_AP_TO_MESA_SCLK 1
511K
1% 1/32W MF 2 01005 ROOM=MAMBA_MESA
47 46 39 38 18
PP1V8_TOUCH
SPI_AP_TO_MESA_SCLK_CONN
2
38
1
56PF
5% 2 25V NP0-C0G-CERM 01005
ROOM=MAMBA_MESA
ROOM=MAMBA_MESA
1
33.2
45
SPI_MESA_TO_AP_MISO_CONN
2 1
38 38
38
C
0.00
PP1V8_TOUCH_TO_MAMBA_CONN
2 1
C3824
1
20% 6.3V X5R-CERM 0201-1
5% 10V 2 C0G-CERM 01005
2.2UF
ROOM=MAMBA_MESA
38
C3811 220PF
ROOM=MAMBA_MESA
FL3804
1
MAMBA_TO_LCM_MDRIVE 56PF
1% 1/32W MF 01005
38
150OHM-25%-200MA-0.7DCR
R3811 SPI_MESA_TO_AP_MISO
2
5% 10V C0G-CERM 01005
2
MAMBA DIGITAL I/O
C3817
C3805 11
C3812
ROOM=MAMBA_MESA
1
38 38
ROOM=MAMBA_MESA
0% 1/32W MF 01005
0% 1/32W MF 01005
R3808
38
220PF
20% 10V X5R-CERM 0402-8
R3809 0.00
38
R3805
ROOM=MAMBA_MESA
1
1
ROOM=MAMBA_MESA
5% 2 25V NP0-C0G-CERM 01005
1% 1/32W MF 2 01005 ROOM=MAMBA_MESA
C3823 10UF
GND EPAD
56PF
511K
D
48
PP2V75_MAMBA_CONN
ROOM=MAMBA_MESA
3 EN
MAMBA_LDO_EN
OMIT
SPI_AP_TO_MESA_MOSI_CONN 1
XW3801 SHORT-20L-0.05MM-SM ROOM=PMU
2 ROOM=MAMBA_MESA
48
U3801
ROOM=MAMBA_MESA
01005
38
TI:353S00576 ST:353S00932
NOTE: OUTPUT IMPDEANCE MUST BE >0.005-OHM IN ORDER TO MEET CAP ESR REQUIREMENT PER LDO SPEC. VENDOR ALSO RECOMMENDS CIN = COUT FOR STABILITY
1
2.2UF
ROOM=MAMBA_MESA
1
MESA_TO_AOP_FDINT_CONN I2C_MESA_TURTLE_SDA_CONN I2C_MESA_TURTLE_SCL_CONN MESA_TO_BOOST_EN_CONN MESA_TO_AP_INT_CONN SPI_AP_TO_MESA_SCLK_CONN SPI_AP_TO_MESA_MOSI_CONN AOP_TO_MESA_BLANKING_EN_CONN SPI_MESA_TO_AP_MISO_CONN PP2V75_MAMBA_CONN
PP_VDD_BOOST
5% 2 35V NP0-C0G 01005
SPI_AP_TO_MESA_MOSI
38
38
100PF
11
PP1V8_MESA_CONN
ROOM=MAMBA_MESA
2
5
PP16V0_MESA
Matches flex_x452_acf, schematic revision 1.5.0 pinout
30
150OHM-25%-200MA-0.7DCR 37 4
29
ROOM=MAMBA_MESA
ROOM=MAMBA_MESA
1
1
CRITICAL
MLB: 516S00141 (RCPT) FLEX: 516S00142 (PLUG)
80-OHM-25%-0.52A-0.17OHM 1
2
MAMBA AND MESA CONNECTOR
FL3803
PP3V0_MESA
3
1
2 01005 1
ROOM=MAMBA_MESA
2
ROOM=MAMBA_MESA
C3818
MAMBA_TO_LCM_MDRIVE_CONN_MESA
38
C3806 56PF
5% 25V NP0-C0G-CERM 2 01005
38
NOSTUFF
5% 25V NP0-C0G-CERM 01005 ROOM=MAMBA_MESA
56PF
5% 2 25V NP0-C0G-CERM 01005
ROOM=MAMBA_MESA
ROOM=MAMBA_MESA
R3801
B
11
MESA_TO_AP_INT
1
681
2
1% 1/32W MF 01005
1
MESA_TO_AP_INT_CONN
38
MESA_TO_BOOST_EN_CONN
38
B
C3819 100PF
5% 2 16V NP0-C0G 01005
ROOM=MAMBA_MESA
ROOM=MAMBA_MESA
R3802 37 4
MESA_TO_BOOST_EN
1
681
2
1% 1/32W MF 01005
1
FL3806
C3801
150OHM-25%-200MA-0.7DCR
100PF
13
5% 2 16V NP0-C0G 01005
ROOM=MAMBA_MESA
MESA_TO_AOP_FDINT
1
MESA_TO_AOP_FDINT_CONN
2 01005
ROOM=MAMBA_MESA
1
C3826
2
5% 16V NP0-C0G 01005
100PF
ROOM=MAMBA_MESA
FL3811
AOP_TO_MESA_BLANKING_EN
1
2
AOP_TO_MESA_BLANKING_EN_CONN
01005
#24543342: stuff 100pF
ROOM=MAMBA_MESA
150OHM-25%-200MA-0.7DCR 13
38
1
38
C3825 56PF
5% 2 25V NP0-C0G-CERM 01005 ROOM=MAMBA_MESA
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7 FL3912
DISPLAY POWER C3901
1
1
10UF
2
C3929
ROOM=DISPLAY_B2B
10UF 20%
20% 10V X5R-CERM 2 0402-8
10V 2 X5R-CERM 0402-8
ROOM=DISPLAY_B2B
PP5V7_LCM_AVDDH_CONN
1 0201
1
C3933
1
2.2UF 20%
C3913
ROOM=DISPLAY_B2B
5% 10V 2 C0G-CERM 01005
L3901
9
90_MIPI_AP_TO_LCM_CLK_P
9
90_MIPI_AP_TO_LCM_CLK_N
90_MIPI_AP_TO_LCM_CLK_CONN_P
45
90_MIPI_AP_TO_LCM_CLK_CONN_N
45
90_MIPI_AP_TO_LCM_DATA0_CONN_P
45
90_MIPI_AP_TO_LCM_DATA0_CONN_N
45
90_MIPI_AP_TO_LCM_DATA1_CONN_P
45
90_MIPI_AP_TO_LCM_DATA1_CONN_N
45
2 ROOM=DISPLAY_B2B
ROOM=DISPLAY_B2B
65OHM-0.7-2GHZ-3.4OHM TAM0605 CRITICAL
0201
PP1V8_LCM_CONN 1
AP/TOUCH INTERFACE
SYM_VER-1
1
ROOM=DISPLAY_B2B
C3934
1
2.2UF
45
ROOM=DISPLAY_B2B
9
4
90_MIPI_AP_TO_LCM_DATA0_P
C3914 220PF
20% 2 6.3V X5R-CERM 0201-1
9
5% 2 10V C0G-CERM 01005
1
3
90_MIPI_AP_TO_LCM_DATA0_N
2 ROOM=DISPLAY_B2B
D
L3903
ROOM=DISPLAY_B2B
65OHM-0.7-2GHZ-3.4OHM TAM0605 SYM_VER-1
9
90_MIPI_AP_TO_LCM_DATA1_P
9
90_MIPI_AP_TO_LCM_DATA1_N
4
1
3
2
CRITICAL
FL3904
ROOM=DISPLAY_B2B
150OHM-25%-200MA-0.7DCR 12
2
AP_TO_TOUCH_MAMBA_RESET_L
FL3913
37 20
2
LCM_TO_CHESTNUT_PWR_EN
LCM_TO_CHESTNUT_PWR_EN_CONN
FL3908
C3909 12
ROOM=DISPLAY_B2B
2
PP5V7_MESON_AVDDH
1 0201
1
C3932
ROOM=DISPLAY_B2B
2.2UF
20% 6.3V X5R-CERM 2 0201-1
ROOM=DISPLAY_B2B
1
2
1
45
C3917
C
220PF
ROOM=DISPLAY_B2B
2
ROOM=DISPLAY_B2B
20
PMU_TO_LCM_PANICB
10
1
PMU_TO_LCM_PANICB_CONN
2
5% 1/32W MF 01005
C3911
1
220PF
C3918
11
100PF
ROOM=DISPLAY_B2B
2
AOP/TOUCH INTERFACE
FL3922
150OHM-25%-200MA-0.7DCR
45
PP5V1_TOUCH_VDDH
1 0201
5% 16V NP0-C0G 01005
ROOM=DISPLAY_B2B
ROOM=DISPLAY_B2B
11
37
220PF
FL3916
2
LCM_TO_MANY_BSYNC
B
C3903
2
220PF
#26634069: nostuff C3903 to help desense
0201 ROOM=DISPLAY_B2B
13
1
UART_TOUCH_TO_AOP_RXD
PP_LCM_BL_CAT1_CONN 1
11
ROOM=DISPLAY_B2B
2
5% 25V NP0-C0G-CERM 01005
1 ROOM=DISPLAY_B2B
11
1
SPI_TOUCH_TO_AP_MISO
2
PP_LCM_BL_CAT2_CONN
1 1
ROOM=DISPLAY_B2B
2
ROOM=DISPLAY_B2B
150OHM-25%-200MA-0.7DCR 12
TOUCH_TO_AP_INT_L
2
1 01005
45
ROOM=DISPLAY_B2B
C3921
TOUCH_TO_AP_INT_L_CONN 45 1
C3927 100PF
5% 2 16V NP0-C0G 01005 ROOM=DISPLAY_B2B
5% 25V NP0-C0G-CERM 01005
R3908
ROOM=DISPLAY_B2B
ROOM=DISPLAY_B2B
C3926 56PF
56PF
100PF
SPI_TOUCH_TO_AP_MISO_CONN 45
FL3920
UART_AOP_TO_TOUCH_TXD_CONN
5% 2 35V NP0-C0G 01005
11
AP_TO_CUMULUS_CLK32K
2
33.2
AP_TO_CUMULUS_CLK_32K_CONN
1
1% 1/32W MF 01005 ROOM=DISPLAY_B2B
AC Coupling Caps A
B
5% 2 25V NP0-C0G-CERM 01005
ROOM=DISPLAY_B2B
01005
C3905
C3925 56PF
1
ROOM=DISPLAY_B2B
C3920
150OHM-25%-200MA-0.7DCR
UART_AOP_TO_TOUCH_TXD
1
1
56PF
FL3918
2
SPI_AP_TO_TOUCH_MOSI_CONN 45 5% 2 25V NP0-C0G-CERM 01005 ROOM=DISPLAY_B2B
01005
45
5% 2 25V NP0-C0G-CERM 01005
13
1
SPI_AP_TO_TOUCH_MOSI
01005
UART_TOUCH_TO_AOP_RXD_CONN
C3904 ROOM=DISPLAY_B2B
0201
1
100PF
2
ROOM=DISPLAY_B2B
FL3924
FL3919
ROOM=DISPLAY_B2B
5% 2 35V NP0-C0G 01005
FL3903
PP_LCM_BL_CAT2
2
56PF
5% 2 25V NP0-C0G-CERM 01005
150OHM-25%-200MA-0.7DCR
01005
33-OHM-25%-1500MA 37
C3919
150OHM-25%-200MA-0.7DCR
33-OHM-25%-1500MA
PP_LCM_BL_CAT1
ROOM=DISPLAY_B2B
C3923
150OHM-25%-200MA-0.7DCR
45
FL3917
FL3902
37
45
56PF
1
ROOM=DISPLAY_B2B
ROOM=DISPLAY_B2B
2
1
56PF
VOLTAGE=25.0V
2% 2 50V C0G 0201
1
1
PP_LCM_BL_ANODE_CONN
1
NOSTUFF C3922 ROOM=DISPLAY_B2B
LCM_TO_MANY_BSYNC_CONN
ROOM=DISPLAY_B2B
NOSTUFF
ROOM=DISPLAY_B2B
1 01005
33-OHM-25%-1500MA 0201
SPI_AP_TO_TOUCH_SCLK_CONN
C3924
0.00 2
0% 1/32W MF 01005
5% 25V NP0-C0G-CERM 2 01005
150OHM-25%-200MA-0.7DCR 53 23 20 13
2
1
56PF
FL3901
PP_LCM_BL_ANODE
SPI_AP_TO_TOUCH_SCLK
C3912
ROOM=DISPLAY_B2B
1
45
R3923
5% 2 10V C0G-CERM 01005
BACKLIGHT
1
SPI_AP_TO_TOUCH_CS_CONN_L 5% 2 25V NP0-C0G-CERM 01005 ROOM=DISPLAY_B2B
PP5V1_TOUCH_VDDH_CONN 1
ROOM=DISPLAY_B2B
1 01005
240-OHM-25%-0.42A-0.31DCR 37
2
SPI_AP_TO_TOUCH_CS_L
ROOM=DISPLAY_B2B
2
To Mamba/Mesa B2B
5% 2 10V C0G-CERM 01005
PP1V8_TOUCH_CONN 1
AP_TO_LCM_RESET_CONN_L
R3915
6.3V 2 X5R-CERM 0201-1
5% 2 10V C0G-CERM 01005
FL3911
ROOM=DISPLAY_B2B
5% 1/32W MF 01005
C3940
ROOM=DISPLAY_B2B
2 0201
1
ROOM=MAMBA_MESA
To Display B2B
1 R3901 100K
2.2UF 20%
5% 10V 2 C0G-CERM 01005
33-OHM-25%-1500MA
PP1V8_TOUCH
1
220PF
FL3910
47 46 38 18
C3910
01005
AP_TO_LCM_RESET_L
PP5V7_MESON_AVDDH_CONN 1
ROOM=DISPLAY_B2B
ROOM=DISPLAY_B2B
150OHM-25%-200MA-0.7DCR
240-OHM-25%-0.42A-0.31DCR 37
2
5% 10V C0G-CERM 01005
220PF
5% 10V C0G-CERM 01005
FL3915
5% 10V 2 C0G-CERM 01005
C
C3902
ROOM=DISPLAY_B2B
220PF
FL3909
2
45
1
1
45
C3928 100PF
5% 2 16V NP0-C0G 01005
ROOM=DISPLAY_B2B
PP_VDD_MAIN
SYNC_MASTER=Sync
28 27 26 25 23 21 19 18 10 9 4 53 52 46 41 40 37 35 34 33 31
SYNC_DATE=05/17/2016
PAGE TITLE
1
C3930 220PF
5% 2 10V C0G-CERM 01005 ROOM=DISPLAY_B2B
1
C3931 220PF
5% 2 10V C0G-CERM 01005 ROOM=DISPLAY_B2B
1
C3935 220PF
5% 2 10V C0G-CERM 01005 ROOM=DISPLAY_B2B
1
C3936
1
220PF
C3937
1
C3938
2
5% 10V C0G-CERM 01005
220PF
5% 2 10V C0G-CERM 01005
5% 2 10V C0G-CERM 01005 ROOM=DISPLAY_B2B
ROOM=DISPLAY_B2B
1
220PF
2
spare
C3939 220PF
DRAWING NUMBER
5% 10V C0G-CERM 01005
Apple Inc.
051-00419
REVISION
R
ROOM=DISPLAY_B2B
AC return path for LCM MIPI which is referenced to GND and VDD_MAIN
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
For placement "along the way" as we route from SOC to B2B.
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
45
PN5V7_LCM_MESON_AVDDN_CONN 1
ROOM=DISPLAY_B2B
220PF
5% 10V C0G-CERM 01005
240-OHM-25%-0.42A-0.31DCR 0201
C3915
220PF
2
1
1
C3916
1
ROOM=DISPLAY_B2B
2
AP_TO_TOUCH_MAMBA_RESET_CONN_L 38
ROOM=DISPLAY_B2B
1 01005
PN5V7_LCM_MESON_AVDDN
1 01005
150OHM-25%-200MA-0.7DCR
37
1
L3902
2
D
2
CRITICAL 1
3
240-OHM-25%-0.42A-0.31DCR 25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 29
3
SYM_VER-1
4
FL3906
PP1V8
4
65OHM-0.7-2GHZ-3.4OHM TAM0605
45
220PF
6.3V 2 X5R-CERM 0201-1
ROOM=DISPLAY_B2B
5
DISPLAY MIPI
240-OHM-25%-0.42A-0.31DCR
PP5V7_LCM_AVDDH
37
6
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
D
D
PP3V0_TRISTAR_ANT_PROX 1
PP_ACC_VAR
C4003
1
1.0UF
TRISTAR 2
20% 6.3V 2 X5R-CERM 01005
ROOM=TRISTAR
48 47 41 37 36 32 21 20 18 16 53 52
PP1V8_SDRAM 1
C4004
D
0.01UF 10%
ROOM=TRISTAR
2
z=0.45mm <rdar:/24285280> EVT: 343S00091 (P2:343S00078)
VDD_1V8 F3
1 1
6.34K 2 1% 1/32W MF 01005
C4001 0.01UF
31 31
ROOM=PMU
53 53
L4022
15NH-250MA 7
1
90_USB_AP_DATA_P
2 0201 ROOM=TRISTAR
L4021
12
15NH-250MA 7
1
90_USB_AP_DATA_N
12
ROOM=TRISTAR
12
90_MIKEYBUS_DATA_P 90_MIKEYBUS_DATA_N
C3 C4
90_USB_BB_DATA_P 90_USB_BB_DATA_N
A1 B1
TRISTAR_USB_BRICK_ID_R
C2
90_USB_AP_DATA_L_P 90_USB_AP_DATA_L_N
A3 B3
UART_AP_TO_ACCESSORY_TXD UART_ACCESSORY_TO_AP_RXD
E2 E1
UART_AP_DEBUG_TXD UART_AP_DEBUG_RXD
F2 F1
NC
PP_VDD_MAIN 1
C4007 220PF
5% 2 10V C0G-CERM 01005
1
7
C4008
7
220PF
SWD_DOCK_TO_AP_SWCLK SWD_DOCK_BI_AP_SWDIO
5% 2 10V C0G-CERM 01005
ROOM=SOC
DFN S
2
5% 1/32W MF 2 01005 ROOM=TRISTAR
ROOM=TRISTAR
Sm Footprint: 376S00135
D2 D1 A5 B5
CBTL1610A3BUK DIG_DP
WLCSP
DIG_DN USB1_DP USB1_DN BRICK_ID USB0_DP USB0_DN
P_IN F6 ACC1 C5 ACC2 E5
ROOM=SOC
4 41
DP2 A4 DN2 B4
90_TRISTAR_DP2_CONN_P 90_TRISTAR_DP2_CONN_N
CON_DET_L E3 D6 21 POW_GATE_EN*
UART1_TX UART1_RX
SWITCH_EN E4 HOST_RESET B6
UART2_TX UART2_RX
SDA SCL INT BYPASS
D3 D4 C6 E6
1
C4006 1UF
4 41
90_TRISTAR_DP1_CONN_P 90_TRISTAR_DP1_CONN_N
UART0_TX UART0_RX
JTAG_CLK JTAG_DIO
PP5V0_USB_RVP PP_TRISTAR_ACC1 PP_TRISTAR_ACC2
DP1 A2 DN1 B2
DVSS DVSS DVSS
53 27 26 25 23 21 19 18 10 9 4 52 46 41 39 37 35 34 33 31 28
R4002 10K
20% 2 16V CER-X5R 0201
4 41 4 41
ROOM=TRISTAR
4 41 4 41
TRISTAR_CON_DETECT_L
4 41
TRISTAR_TO_TIGRIS_VBUS_OFF POW_GATE_EN* is 6V-tolerant
PMU_TO_AOP_TRISTAR_ACTIVE_READY TRISTAR_TO_PMU_HOST_RESET
7 13 20 37 20
I2C0_AP_SDA I2C0_AP_SCL TRISTAR_TO_AOP_INT TRISTAR_BYPASS
PP4001 P2MM-NSM 1
#25714843: Remove R4003 Weak PD
SM
PP
47
B
47 13
1
C4005 1.0UF
F5 C1 A6
B
12
2 0201
1
C
RV3CA01ZP
G
U4001
ROOM=PMU
10% 2 6.3V X5R 01005
1
TRISTAR_REVERSE_GATE
ROOM=TRISTAR
TRISTAR_TO_PMU_USB_BRICK_ID
CRITICAL
Q4001
6.3V X5R 01005
R4001 20
4 21 41
3
ACC_PWR D5
C
C4002 0.1UF
20% 6.3V 2 X5R 0201-1
19 27 46
PP5V0_USB
VDD_3V0 F4
53 41 29 19
2
AC return path for USB pairs which is referenced to GND and VDD_MAIN
20% 6.3V X5R 0201-1 ROOM=TRISTAR
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
ANTENNA
2
LOWER MIC1/4
Please loop in Matt Mow (Antenna Team) when changing these components!
ARC CONTROL
31
LOWERMIC1_TO_CODEC_AIN1_P
FL4116
150OHM-25%-200MA-0.7DCR LOWERMIC1_TO_CODEC_AIN1_CONN_POS 2 1 01005
1
ROOM=DOCK_B2B
FL4103
2
PP3V0_LAT_CONN
1 01005
1
ROOM=DOCK_B2B
R4104
41
C4134
47 36
I2C_HOMER_SCL
1
10V 2 C0G-CERM 01005
2
47 36
I2C_HOMER_SDA
1
1
ROOM=DOCK_B2B
C4119
FL4108
1
ARC1 41 35
1
PP1V8_LAT_ARC_CONN
01005
1
ROOM=DOCK_B2B
ARC1_TO_SOLENOID1_OUT_POS
C
1
C4121
ROOM=DOCK_B2B
LOWERMIC4_TO_CODEC_AIN2_N
0% 1/32W MF 01005
1
53
2
BB_TO_LAT_GPO1
01005
C4122
41
C4110
32
2
5% 25V NP0-C0G-CERM 01005
2
SPEAKER1
1
BB_TO_LAT_GPO2_CONN
01005
41 34
ROOM=DOCK_B2B
1
C4111
220PF
ROOM=DOCK_B2B
FL4114
SPEAKER_TO_SPEAKERAMP1_VSENSE_P
01005
1
ROOM=DOCK_B2B
ROOM=DOCK_B2B
SPEAKER_TO_SPEAKERAMP1_VSENSE_N
ROOM=DOCK_B2B
150OHM-25%-200MA-0.7DCR 2 1 SPEAKER_TO_SPEAKERAMP1_VSENSE_CONN_NEG 01005
1
ROOM=DOCK_B2B
B
C4109
1
0.1UF
ROOM=DOCK_B2B
1
0.1UF
ROOM=DOCK_B2B
C4106
ROOM=DOCK_B2B
41 34 41 46 41 41 41
1
0.1UF
10% 25V X5R 2 0201
10% 25V X5R 2 0201
C4107
10% 25V 2 X5R 0201
ROOM=DOCK_B2B
1
330PF
C4108 330PF
10% 16V CER-X7R 2 01005
ROOM=DOCK_B2B
40 4
40 4 40 4
31 41 32
47
A
47
41 35 35 41 41
J4101
10% 16V CER-X7R 2 01005
41 34
53 49
1
5% 10V 2 C0G-CERM 01005
50
ROOM=DOCK_B2B
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47
90_TRISTAR_DP2_CONN_P 90_TRISTAR_DP2_CONN_N 90_TRISTAR_DP1_CONN_N 90_TRISTAR_DP1_CONN_P MIKEYBUS_REFERENCE LOWERMIC1_TO_CODEC_AIN1_CONN_POS LOWERMIC1_TO_CODEC_BIAS_FILT_RET I2C_MIC1_SDA_CONN I2C_MIC1_SCL_CONN ARC1_TO_SOLENOID1_OUT_POS SOLENOID1_TO_ARC1_VSENSE_POS PP3V0_LAT_CONN SPEAKER_TO_SPEAKERAMP1_VSENSE_CONN_POS
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48
41 34
#25429221:Carrier Dock flex to add +1 ACC2 pin
SPEAKERAMP1_TO_SPEAKER_OUT_POS
51
SPEAKERAMP1_TO_SPEAKER_OUT_NEG 1
PP_TRISTAR_ACC2_CONN BB_TO_LAT_GPO2_CONN LOWERMIC4_TO_CODEC_AIN2_CONN_POS LOWERMIC4_TO_CODEC_BIAS_FILT_RET BB_TO_LAT_GPO1_CONN BB_TO_LAT_ANT_SCLK_CONN BB_TO_LAT_ANT_DATA_CONN PP1V8_LAT_ARC_CONN PP3V0_LAT1_CONN
5% 2 10V C0G-CERM 01005
TRISTAR
41 41
ROOM=DOCK_B2B
32 41
R4102
41 41 40 4 41
TRISTAR_CON_DETECT_L
2
1.00K 1
TRISTAR_CON_DETECT_CONN_L 41
5% 1/32W MF 01005
41
1
10-OHM-1.1A
41 40 4 41
1
PP_TRISTAR_ACC1
ROOM=DOCK_B2B
ARC1_TO_SOLENOID1_OUT_NEG ARC1_TO_SOLENOID1_OUT_POS SOLENOID1_TO_ARC1_VSENSE_NEG I2C_HOMER_SDA_CONN I2C_HOMER_SCL_CONN
35 41
41
40 4
PP_TRISTAR_ACC2
1
C4117
SYNC_MASTER=Sync
1
C4118
SYNC_DATE=05/17/2016
PAGE TITLE
ROOM=DOCK_B2B
PP_TRISTAR_ACC2_CONN
ROOM=DOCK_B2B
ROOM=SOC
VOLTAGE=4.3V
100PF
2 0201
41
220PF
PP_TRISTAR_ACC1_CONN 41 1
spare
41
DRAWING NUMBER
VOLTAGE=4.3V
Apple Inc.
100PF
5% 2 16V NP0-C0G 01005
52
54
C4143
5% 2 10V C0G-CERM 01005
ROOM=DOCK_B2B
22-OHM-25%-1800MA
35
PP_VDD_MAIN 1
5% 2 16V NP0-C0G 01005
FL4106
35 41
53 27 26 25 23 21 19 18 10 9 4 52 46 40 39 37 35 34 33 31 28
C4116
2 01005
AC return path for USB pairs which is referenced to GND and VDD_MAIN
5% 2 16V NP0-C0G 01005
FL4105
41
USB AC Coupling
27PF
ROOM=DOCK_B2B
LOWERMIC1_TO_CODEC_AIN1_CONN_NEG PP_CODEC_TO_LOWERMIC1_BIAS_CONN TRISTAR_CON_DETECT_CONN_L
C4104 220PF
41
#25098110: Decrease DCR 41 34
C4103 220PF
F-ST-SM
ROOM=DOCK_B2B
SPEAKERAMP1_TO_SPEAKER_OUT_NEG SPEAKER_TO_SPEAKERAMP1_VSENSE_CONN_NEG BB_TO_LAT_GPO3_CONN LOWERMIC4_TO_CODEC_AIN2_CONN_NEG PP_CODEC_TO_LOWERMIC4_BIAS_CONN PP_TRISTAR_ACC1_CONN
B
SPEAKERAMP1_TO_SPEAKER_OUT_POS
245857
1
#22499940:Change Net Name to POS/NEG 40 4
C4127 220PF
PP5V0_USB
C4105
051-00419
REVISION
R
ROOM=DOCK_B2B
DOCK FLEX CONNECTOR
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
41
5% 2 10V C0G-CERM 01005
VOLTAGE=14.0V 40 21 4
C4126
5% 2 10V C0G-CERM 01005
FL4115
34
41
220PF
5% 25V NP0-C0G-CERM 01005
Per ANT Erdinc, change to cap
C4133
150OHM-25%-200MA-0.7DCR 2 1 SPEAKER_TO_SPEAKERAMP1_VSENSE_CONN_POS
56PF
2
1
41
5% 10V 2 C0G-CERM 01005
150OHM-25%-200MA-0.7DCR
BB_TO_LAT_GPO2
150OHM-25%-200MA-0.7DCR 2 1 PP_CODEC_TO_LOWERMIC4_BIAS_CONN ROOM=DOCK_B2B
FL4102
53
C
ROOM=DOCK_B2B
01005
ROOM=DOCK_B2B
ROOM=DOCK_B2B
PP_CODEC_TO_LOWERMIC4_BIAS
56PF
5% 2 16V NP0-C0G-CERM 01005
C4132 56PF
FL4121
BB_TO_LAT_GPO1_CONN 1
ROOM=DOCK_B2B
41
5% 25V 2 NP0-C0G-CERM 01005
1
33PF
ROOM=DOCK_B2B
1
ROOM=DOCK_B2B
150OHM-25%-200MA-0.7DCR 41
150OHM-25%-200MA-0.7DCR LOWERMIC4_TO_CODEC_AIN2_CONN_NEG 2 1 01005
FL4101
BB_TO_LAT_ANT_DATA_CONN
ROOM=DOCK_B2B
FL4120
Antenna GPIO
2
C4131 56PF
1
31
5% 16V 2 NP0-C0G-CERM 01005
1
41
5% 25V 2 NP0-C0G-CERM 01005
5% 10V C0G-CERM 2 01005
ROOM=DOCK_B2B
33PF
0.00
150OHM-25%-200MA-0.7DCR LOWERMIC4_TO_CODEC_AIN2_CONN_POS 2 1
220PF
5% 10V C0G-CERM 2 01005
R4110 BB_TO_LAT_ANT_DATA
C4102
1
220PF
ROOM=DOCK_B2B
53
LOWERMIC4_TO_CODEC_AIN2_P
ARC1_TO_SOLENOID1_OUT_NEG
BB_TO_LAT_ANT_SCLK_CONN 41
ROOM=DOCK_B2B
ROOM=DOCK_B2B
ROOM=DOCK_B2B
C4101
C4130 220PF
01005 41 35
41
5% 10V 2 C0G-CERM 01005
31
2 1
1
FL4119
R4109 0% 1/32W MF 01005
150OHM-25%-200MA-0.7DCR 2 1 PP_CODEC_TO_LOWERMIC1_BIAS_CONN
ROOM=DOCK_B2B
ROOM=DOCK_B2B
0.00
ROOM=DOCK_B2B
ROOM=DOCK_B2B
C4120 220PF
C4129 56PF
01005
41
5% 10V 2 C0G-CERM 01005
1
PP_CODEC_TO_LOWERMIC1_BIAS
ROOM=DOCK_B2B
2
BB_TO_LAT_ANT_SCLK
32
5% 25V NP0-C0G-CERM 01005
D
41
5% 25V 2 NP0-C0G-CERM 01005
FL4118
41
CKPLUS_WAIVE=I2C_PULLUP
C4136
2
150OHM-25%-200MA-0.7DCR
53
I2C_HOMER_SDA_CONN 56PF
10V 2 C0G-CERM 01005
1
ROOM=DOCK_B2B
2
VOLTAGE=3.0V
220PF 5%
150OHM-25%-200MA-0.7DCR LOWERMIC1_TO_CODEC_AIN1_CONN_NEG 2 1
ROOM=DOCK_B2B
01005
PP3V0_LAT1_CONN 41
ROOM=DOCK_B2B
01005
25V NP0-C0G-CERM 01005
FL4112
1 01005
PP1V8_SDRAM
LOWERMIC1_TO_CODEC_AIN1_N
150OHM-25%-200MA-0.7DCR
FL4107
53 52 32 21 20 18 16 48 47 40 37 36
31
56PF 5%
2
150OHM-25%-200MA-0.7DCR
PP3V0_TRISTAR_ANT_PROX
41
CKPLUS_WAIVE=I2C_PULLUP
C4135
ROOM=DOCK_B2B
ROOM=DOCK_B2B
53 40 29 19
2 1
C4128 56PF
FL4117
I2C_HOMER_SCL_CONN
1% 1/32W MF 01005
220PF 5%
D
49.9
41
5% 25V 2 NP0-C0G-CERM 01005
#26118161: Update FL4104 to 49.9ohm
150OHM-25%-200MA-0.7DCR
1
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
D
D
C
C
B
B
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
D
D
C
C
B
B
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
STROBE1
5
4
3
STROBE2
PP_STROBE_DRIVER1_WARM_LED
C4402
1
1
220PF
C4409
C4410
27PF
5% 10V C0G-CERM 2 01005
D
BUTTONS
PP_STROBE_DRIVER2_WARM_LED
26 45
26 45
1
1
220PF
5% 16V 2 NP0-C0G 01005
ROOM=RIGHT_BUTTON
2
100
1
C4401
27PF
ROOM=RIGHT_BUTTON
R4402
BUTTON_POWER_KEY_L
C4413
5% 6.3V NP0-C0G 2 0201 ROOM=RIGHT_BUTTON
ROOM=RIGHT_BUTTON
BUTTON_POWER_KEY_CONN_L
2
5% 1/32W MF 01005
1
27PF
5% 16V 2 NP0-C0G 01005
5% 10V C0G-CERM 2 01005
ROOM=RIGHT_BUTTON
20
1
1
0201
5.5V-6.2PF
ROOM=RIGHT_BUTTON
DZ4401 ROOM=RIGHT_BUTTON
2
D
CHASSIS_GND_BS401 PP_STROBE_DRIVER1_COOL_LED
PP_STROBE_DRIVER2_COOL_LED
26 45
C4406
1
1
220PF 5%
C4408
C4411
27PF
220PF 5%
5% 16V 2 NP0-C0G 01005
10V C0G-CERM 2 01005
C4412
120-OHM-0.220A
27PF 5%
10V C0G-CERM 2 01005
ROOM=RIGHT_BUTTON
ROOM=RIGHT_BUTTON
1
2
ROOM=RIGHT_BUTTON
20
1
BUTTON_RINGER_A
16V NP0-C0G 01005
C4418
1
27PF
ROOM=RIGHT_BUTTON
2
BUTTON_RINGER_A_CONN
ROOM=LEFT_BUTTON
1
5% 6.3V NP0-C0G 2 0201
0201
5.5V-6.2PF
ROOM=LEFT_BUTTON
FL4404
DZ4402 ROOM=LEFT_BUTTON
2
STROBE_MODULE_NTC
26
R4401 1 27K
CHASSIS_GND_BS401
2 1
ROOM=RIGHT_BUTTON
C4407 220PF
R4405
5% 2 10V C0G-CERM 01005
20
BUTTON_VOL_DOWN_L
1
C4419
ROOM=RIGHT_BUTTON
#24544474: Can R4401 be changed to 5%?
100
100PF
BUTTON_VOL_DOWN_CONN_L
2
5% 1/32W MF 01005
1
5% 16V NP0-C0G 2 01005
1
ROOM=LEFT_BUTTON
HAWKING
45
DZ4403
12V-33PF 01005-1
2
ROOM=LEFT_BUTTON
CHASSIS_GND_BS401
ROOM=LEFT_BUTTON
4 44
C
R4406 #24678255:DOE with 10% and/20% cap
20 12
BUTTON_VOL_UP_L 100PF
0.22UF 1
HAWKING_TO_CODEC_AIN7_N
1
C4420
C4417 31
4 44
STROBE_MODULE_NTC_CONN 45
01005
0.5% 1/32W MF 01005 2 ROOM=RIGHT_BUTTON
C
45
01005
150OHM-25%-200MA-0.7DCR 1
4 44
FL4407
26 45
1
45
2
HAWKING_TO_CODEC_AIN7_N_CONN
1
5% 16V 2 NP0-C0G 01005
45
20% 6.3V X5R 01005
ROOM=LEFT_BUTTON
100
BUTTON_VOL_UP_CONN_L
2
5% 1/32W MF 01005 ROOM=LEFT_BUTTON
1
45
DZ4404
12V-33PF 01005-1
2
ROOM=LEFT_BUTTON
CHASSIS_GND_BS401
4 44
ROOM=RIGHT_BUTTON
FL4405
C4421
150OHM-25%-200MA-0.7DCR 1 2 HAWKING_TO_CODEC_AIN7_C_P
0.22UF 1
HAWKING_TO_CODEC_AIN7_P
31
2
CKPLUS_WAIVE=MISS_N_DIFFPAIR
20% 6.3V X5R 01005
HAWKING_TO_CODEC_AIN7_P_CONN
01005 ROOM=RIGHT_BUTTON
1
C4415
1
5% 25V NP0-C0G-CERM 01005
2
56PF
ROOM=RIGHT_BUTTON
2
45
NOSTUFF
C4422 180PF
ROOM=RIGHT_BUTTON
10% 10V CERM 01005
ROOM=RIGHT_BUTTON
FL4406
150OHM-25%-200MA-0.7DCR
B
19
1
PP1V8_HAWKING
2 01005
PP1V8_HAWKING_CONN 1
ROOM=RIGHT_BUTTON
C4416
1
20% 6.3V X5R-CERM 0201-1
2
2.2UF
2
MIC2 (ANC REF)
ROOM=RIGHT_BUTTON
B
45
C4414 220PF
5% 10V C0G-CERM 01005
ROOM=RIGHT_BUTTON
FL4403
150OHM-25%-200MA-0.7DCR 32
PP_CODEC_TO_REARMIC2_BIAS
2
1
PP_CODEC_TO_REARMIC2_BIAS_CONN
01005 ROOM=RIGHT_BUTTON
1
45
C4403 220PF
5% 2 10V C0G-CERM 01005 ROOM=RIGHT_BUTTON
FL4401
150OHM-25%-200MA-0.7DCR 31
REARMIC2_TO_CODEC_AIN3_P
2
1
REARMIC2_TO_CODEC_AIN3_CONN_P
01005 ROOM=RIGHT_BUTTON
1
45
C4404 56PF
5% 2 25V NP0-C0G-CERM 01005
A
ROOM=RIGHT_BUTTON
FL4402
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare
150OHM-25%-200MA-0.7DCR 31
REARMIC2_TO_CODEC_AIN3_N
2
1
REARMIC2_TO_CODEC_AIN3_CONN_N
01005 ROOM=RIGHT_BUTTON
1
DRAWING NUMBER
45
Apple Inc.
C4405 56PF
051-00419
REVISION
R
5% 2 25V NP0-C0G-CERM 01005 ROOM=RIGHT_BUTTON
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
1
THIS PAGE UNIQUE TO SMALL FORM FACTOR
UTAH-C FLEX CONNECTOR THIS ONE --->
2
516S00152 RCPT (USED ON MLB) 516S00151 PLUG
J4501
AA26D-S022VA1 F-ST-SM
ROOM=RCAM_B2B 25
25
D
25 25 48 48
25 46 25
PP1V2_UT_VDD_CONN LPDP_UT_BI_AP_AUX_CONN AP_TO_UT_SHUTDOWN_CONN_L UT_AND_NV_TO_LED_DRIVER_STROBE_EN_CONN I2C_UT_SDA_CONN I2C_UT_SCL_CONN PP3V0_UT_SVDD_CONN PP2V9_UT_AVDD_CONN
24
23
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
25
PP1V8_UT_CONN
22
21
25
PP2V8_UT_AF_VAR_CONN
26
25
90_LPDP_UT_TO_AP_D0_CONN_N 90_LPDP_UT_TO_AP_D0_CONN_P
COMBINED BUTTON FLEX CONNECTOR
25
90_LPDP_UT_TO_AP_D1_CONN_N 90_LPDP_UT_TO_AP_D1_CONN_P
25
J4504
25
AA37D-S014SVA1
AP_TO_UT_CLK_CONN
F-ST-SM
25
516S00138 RCPT (USED ON MLB) 516S00137 PLUG
GND
MAKE_BASE=TRUE
PP_CODEC_TO_REARMIC2_BIAS_CONN 44 REARMIC2_TO_CODEC_AIN3_CONN_N 44 REARMIC2_TO_CODEC_AIN3_CONN_P 32 REARMIC2_TO_CODEC_BIAS_FILT_RET 47 I2C_MIC2_SDA_CONN 47 I2C_MIC2_SCL_CONN 44 BUTTON_POWER_KEY_CONN_L 44
DISPLAY / TOUCH FLEX CONNECTOR THIS ONE --->
D
MLB APN: 516S00150 FLEX APN: 516S00149
25
19
20
15
16
PP_STROBE_DRIVER2_COOL_LED
1
2
3
4
5
6
7
8
STROBE_MODULE_NTC_CONN PP1V8_HAWKING_CONN HAWKING_TO_CODEC_AIN7_P_CONN
9
10
11
12
13
14
44 26
PP_STROBE_DRIVER1_COOL_LED
17
18
44 26
PP_STROBE_DRIVER1_WARM_LED
21
22
BUTTON_RINGER_A_CONN BUTTON_VOL_UP_CONN_L BUTTON_VOL_DOWN_CONN_L PP_STROBE_DRIVER2_WARM_LED
26 44
44
XW4501
44 44
SHORT-20L-0.05MM-SM 1 2
HAWKING_TO_CODEC_AIN7_N_CONN
44
ROOM=RIGHT_BUTTON
44 44 44
26 44
J4502
BB35C-RA40-3A F-ST-SM
45
C
39 39 39 39 39
#24543369: Keep PP
PP4501 P2MM-NSM
SM PP
39 39
1
39
ROOM=TEST
39
PP5V7_LCM_AVDDH_CONN PP5V7_MESON_AVDDH_CONN PN5V7_LCM_MESON_AVDDN_CONN PP1V8_LCM_CONN PP1V8_TOUCH_CONN PP5V1_TOUCH_VDDH_CONN TOUCH_TO_AP_INT_L_CONN SPI_AP_TO_TOUCH_CS_CONN_L UART_AOP_TO_TOUCH_TXD_CONN
10MA 50MA 20MA 20MA 70MA 10MA
#25614112: Remove PP1V8_EEPROM Support 38
TP_LCM_PIFA
LCM_TO_MAMBA_MSYNC_CONN 1
C4507 56PF
5% 2 25V NP0-C0G-CERM 01005 ROOM=DISPLAY_B2B
39 39 39 38 39 39 4 39 4 39 4
PMU_TO_LCM_PANICB_CONN UART_TOUCH_TO_AOP_RXD_CONN LCM_TO_CHESTNUT_PWR_EN_CONN MAMBA_TO_LCM_MDRIVE AP_TO_LCM_RESET_CONN_L PP_LCM_BL_CAT1_CONN PP_LCM_BL_ANODE_CONN PP_LCM_BL_CAT2_CONN
100MA 200MA 100MA
41
42
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
43
44
I2C_DISP_EEPROM_SDA_CONN I2C_DISP_EEPROM_SCL_CONN I2C_TOUCH_BI_MAMBA_SDA I2C_TOUCH_SCL_CONN AP_TO_TOUCH_MAMBA_RESET_CONN_L SPI_TOUCH_TO_AP_MISO_CONN SPI_AP_TO_TOUCH_SCLK_CONN AP_TO_CUMULUS_CLK_32K_CONN SPI_AP_TO_TOUCH_MOSI_CONN LCM_TO_MANY_BSYNC_CONN
C
47 47 47
R4501 2
38 39 39 39
49.9
1
I2C_TOUCH_TO_MAMBA_SCL 47
1% 1/32W MF 01005
ROOM=DISPLAY_B2B
39 39 39
90_MIPI_AP_TO_LCM_DATA0_CONN_P 90_MIPI_AP_TO_LCM_DATA0_CONN_N
39 39
90_MIPI_AP_TO_LCM_DATA1_CONN_P 90_MIPI_AP_TO_LCM_DATA1_CONN_N
39 39
90_MIPI_AP_TO_LCM_CLK_CONN_P 90_MIPI_AP_TO_LCM_CLK_CONN_N
39 39
46
B
B
FOREHEAD516S00146 FLEX CONNECTOR RCPT (USED ON MLB)
THIS ONE --->
516S00145 PLUG
J4503
245858036201829 41
29 29
29 29 29 29 47 48 29 29
A
29 29 29 29
29
PP2V9_NH_AVDD_CONN PP1V8_NH_IO_CONN AP_TO_NH_SHUTDOWN_CONN_L AP_TO_NH_CLK_CONN SPEAKER_TO_SPEAKERAMP2_VSENSE_CONN_P PP3V0_ALS_CONVOY_CONN I2C_ALS_CONVOY_SCL_CONN I2C_PROX_SCL_CONN PROX_BI_AP_AOP_INT_PWM_L_CONN PDM_CONVOY_TO_ADARE_DATA_CONN FRONTMIC3_TO_CODEC_AIN4_CONN_N PP3V0_PROX_CONN PDM_ADARE_TO_CONVOY_CLK_CONN PP_CODEC_TO_FRONTMIC3_BIAS_CONN FRONTMIC3_TO_CODEC_AIN4_CONN_P
F-ST-SM
37
38
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
39
90_MIPI_NH_TO_AP_DATA0_P 90_MIPI_NH_TO_AP_DATA0_N
9 9
90_MIPI_NH_TO_AP_CLK_P 90_MIPI_NH_TO_AP_CLK_N
9 9
90_MIPI_NH_TO_AP_DATA1_P 90_MIPI_NH_TO_AP_DATA1_N
9 9
PP1V2_NH_DVDD_CONN I2C_NH_SCL_CONN I2C_NH_SDA_CONN SPEAKERAMP2_TO_SPEAKER_OUT_POS SPEAKERAMP2_TO_SPEAKER_OUT_NEG SPEAKER_TO_SPEAKERAMP2_VSENSE_CONN_N ALS_TO_AP_INT_CONN_L I2C_ALS_CONVOY_SDA_CONN I2C_PROX_SDA_CONN
29 48 48 SYNC_MASTER=Sync
29 33 46
SYNC_DATE=05/17/2016
PAGE TITLE
spare
29 33 46 29
DRAWING NUMBER
29
Apple Inc.
47 48
051-00419
REVISION
R
40
42
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
CRITICAL
II NOT TO REPRODUCE OR COPY IT
ROOM=FOREHEAD
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
THIS PAGE UNIQUE TO SMALL FORM FACTOR OTHER SMALL FORM FACTOR SPECIFIC PAGES: 4 - MECHANICAL #26682438:Move to Page 46
ISP I2C1
TOUCH I2C 47 39 38 18
D
25 18 17 16 13 12 11 9 8 7 5 52 48 47 39 29
PP1V8_TOUCH
PP1V8 1
R4603
1
2.2K
2
1
5% 1/32W MF 01005
5% 1/32W MF 2 01005 ROOM=MAMBA_MESA
2
ROOM=SOC
ROOM=SOC
I2C_ISP_NV_SCL 9 I2C_ISP_NV_SDA
I2C_TOUCH_TO_MAMBA_SCL
I2C_ISP_NV_SCL 26 I2C_ISP_NV_SDA 26
MAKE_BASE=TRUE
9
NC_AP_LPDP_AUX2
MAKE_BASE=TRUE
47
NC Nets in Small FF
UT B2B 45 25
NC_AP_LPDP_AUX2
10K
2.2K
5% 1/32W MF 01005
10
R4711
R4604
D
MAKE_BASE=TRUE
NOSTUFF
10
NC_90_LPDP_NV_TO_AP_D2_P
10
NC_90_LPDP_NV_TO_AP_D2_N
MAKE_BASE=TRUE
NC_90_LPDP_NV_TO_AP_D2_P NC_90_LPDP_NV_TO_AP_D2_N
MAKE_BASE=TRUE
PP2V9_UT_AVDD_CONN
10
1
C2531
MAKE_BASE=TRUE
C2507
1
2.2UF
2.2UF
20% 2 6.3V X5R-CERM 0201-1
10
NC_90_LPDP_NV_TO_AP_D3_N
20% 2 6.3V X5R-CERM 0201-1
ROOM=RCAM_B2B
NC_90_LPDP_NV_TO_AP_D3_P
NC_90_LPDP_NV_TO_AP_D3_P
MAKE_BASE=TRUE
NC_90_LPDP_NV_TO_AP_D3_N
ROOM=RCAM_B2B
C
C Top Speaker Compass Coil
VDD_MAIN Cap #26634069:D10x Only, 5x VDD_MAIN CAPS Change to 10UF/10V Pg21
PP_VDD_MAIN
53 28 27 26 25 23 21 19 18 10 9 4 52 46 41 40 39 37 35 34 33 31
C4601 1
Pg34
C2113
10UF
C3424
1
10UF
20% VOLTAGE=10V 2 X5R-CERM 0402-8
20% 10V X5R-CERM 2 0402-8
ROOM=BACKLIGHT
ROOM=CHARGER
Pg35 1
10UF
C3530
20% 10V X5R-CERM 2 0402-8
ROOM=SPKAMP1
SPEAKERAMP2_TO_SPEAKER_OUT_POS SPEAKERAMP2_TO_SPEAKER_OUT_NEG
Pg37
C3722
1
10UF
20% 10V X5R-CERM 2 0402-8 ROOM=ARC1
29 33 45 29 33 45
1
10UF
20% 10V X5R-CERM 2 0402-8
1
ROOM=CHESTNUT
R3332
1
910
R3333 910
1% 1/32W TK 2 01005
1% 1/32W TK 2 01005
ROOM=SPKAMP2
ROOM=SPKAMP2
NEG_COMPASS_COIL_COMP 1
POS_COMPASS_COIL_COMP
XW3333
SHORT-20L-0.05MM-SM
B
NO_XNET_CONNECTION
B
2
1
ROOM=MAMBA_MESA OMIT
C3332
1
220PF
53 52 27 26 25 23 21 19 18 10 9 4 46 41 40 39 37 35 34 33 31 28
PP_VDD_MAIN
C3531
53 52 27 26 25 23 21 19 18 10 9 4 46 41 40 39 37 35 34 33 31 28
220PF
5% 2 10V C0G-CERM 01005
#26104509:C3525 Change to 1UF 0201 in DVT
#25742582,Add back C3531 in layout at ARC
C3333
5% 2 10V C0G-CERM 01005
ROOM=SPKAMP2
ROOM=SPKAMP2
PP_VDD_MAIN
1
10UF
C3525
1
1.0UF 20%
20% 10V X5R-CERM 2 0402-8
6.3V X5R 2 0201-1
ROOM=ARC1
ROOM=ARC1
Dock B2B (Pg 41) FL4604
ACC Buck Caps
150OHM-25%-200MA-0.7DCR
A
53
BB_TO_LAT_GPO3
2
1 01005
BB_TO_LAT_GPO3_CONN 1
ROOM=DOCK_B2B
41
C4608
40 27 19
PP_ACC_VAR 1
56PF
5% 2 25V NP0-C0G-CERM 01005
SYNC_MASTER=Sync
C2707
SYNC_DATE=05/17/2016
PAGE TITLE
spare
2.2UF
20% 2 6.3V X5R-CERM 0201-1
ROOM=DOCK_B2B
DRAWING NUMBER
Apple Inc.
ROOM=TRISTAR
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
AP
3
2
TOUCH
25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39 29
I2C0
PP1V8
R4702
1
4.02K
1
1
4.02K
1% 1/32W MF 01005 2 ROOM=SOC
11
R4712
5% 1/32W MF 2 01005 ROOM=MAMBA_MESA
#26682438:Move to Page 46
MAKE_BASE=TRUE
NOSTUFF
C4701
1
1
C4702
5% 2 NP0-C0G-CERM 01005
2
25V
56PF 25V
ROOM=SOC
37
56PF
5% NP0-C0G-CERM 01005
I2C_TOUCH_TO_MAMBA_SCL I2C_TOUCH_BI_MAMBA_SDA
MAKE_BASE=TRUE MAKE_BASE=TRUE
NOSTUFF
37
C4709
I2C0_AP_SCL I2C0_AP_SDA
NOSTUFF
D
I2C_TOUCH_TO_MAMBA_SCL I2C_TOUCH_BI_MAMBA_SDA
46
I2C0_AP_SCL I2C0_AP_SDA
MAKE_BASE=TRUE
#24544434
NOTE:MAMBA I2C 2.2K PULL-UPS TO PP1V8_TOUCH INSIDE GALILEO ADDING R3803, R3804 AS OPTION FOR TWEAKING VALUE
NOSTUFF
10K
1% 1/32W MF 01005 2 ROOM=SOC
I2C0_AP_SCL I2C0_AP_SDA
11
PP1V8_TOUCH
46 39 38 18
R4701
D
1
5% 2 NP0-C0G-CERM 01005
23
25V
56PF
I2C_TOUCH_TO_MAMBA_SCL I2C_TOUCH_BI_MAMBA_SDA
C4711 1
37
PP1V8
25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39 29
1% 1/32W MF 01005 ROOM=SOC 2
1% 1/32W MF 01005 ROOM=SOC 2
1
I2C1_AP_SCL I2C1_AP_SDA
MAKE_BASE=TRUE MAKE_BASE=TRUE
NOSTUFF
C4703
1
5% 2 NP0-C0G-CERM 01005 25V
HOMER
D11/111 ONLY
NOSTUFF
C4704
1
56PF
2
5% 25V NP0-C0G-CERM 01005
20
1
20
1
R4713 1.00K
ROOM=PMU
ROOM=HOMER
1 R4705 2.2K
11
2
ROOM=SOC
R4716 2.2K
5% 1/32W MF 010052
ROOM=SOC
I2C5_SCL I2C5_SDA
36 41 36 41
11 11
21 21
1 R4706 2.2K 5% 1/32W MF 01005
C
1
5% 1/32W MF 01005 ROOM=SOC 2
5% 1/32W MF 2 01005
I2C_HOMER_SCL I2C_HOMER_SDA I2C1_AP_SCL I2C1_AP_SDA
PP1V8
R4715 2.2K
1.00K
5% 1/32W MF 2 01005
PP1V8
I2C2_AP_SCL I2C2_AP_SDA
ROOM=DISPLAY_B2B
1
R4714
I2C2
11
56PF
25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39 29
ROOM=HOMER
ROOM=SOC
C4712
I2C5
PP1V8_SDRAM
48 41 40 37 36 32 21 20 18 16 53 52
I2C1_AP_SCL I2C1_AP_SDA
56PF
ROOM=PMU
5% 1/32W MF 01005
45
4.02K
I2C1_AP_SCL 11 I2C1_AP_SDA
25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39 29
TO DISPLAY / TOUCH FLEX
5% 2 25V NP0-C0G-CERM 01005
ROOM=DISPLAY_B2B
11
#24544426
45
20 37
5% 2 NP0-C0G-CERM 01005
4.02K
25V
ROOM=MAMBA_MESA
25V
R4704 1
5% NP0-C0G-CERM 01005
2
56PF
R4703 1
38
40
ROOM=SOC
I2C0_AP_SCL I2C0_AP_SDA
TO MAMBA / MESA FLEX
C4710
1
ROOM=MAMBA_MESA
40
38
NOSTUFF
56PF
23
I2C0_AP_SCL I2C0_AP_SDA
I2C1
C
1
I2C3 25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39 29
2
I2C2_AP_SCL I2C2_AP_SDA
MAKE_BASE=TRUE MAKE_BASE=TRUE
PP1V8
1 R4709 2.2K
33
5% 1/32W MF 01005
33
ROOM=FOREHEAD
R4707
ROOM=SOC
0.00
1 0% 1/32W
I2C_ALS_CONVOY_SCL_CONN
2 MF 01005
45 11
I2C3_AP_SCL
B
ROOM=FOREHEAD
ROOM=SOC
ROOM=DOCK
2
FL4730
150OHM-25%-200MA-0.7DCR 2
ckplus_waive=I2C_PULLUP
I2C_MIC1_SCL_CONN
1
41
#26633265:mitigate MIC1 undershoot
0.00
2 MF 01005
5% 1/32W MF 01005
01005
R4708 1 0% 1/32W
2
1 R4710 2.2K
I2C_ALS_CONVOY_SDA_CONN
C4707 56PF
1
5% 25V 2 NP0-C0G-CERM 01005 ROOM=FOREHEAD
1
C4708
FL4729
45
TO FOREHEAD FLEX
11
I2C3_AP_SDA
2
100
I2C_MIC1_SDA_CONN
1
5% 1/32W MF 01005
56PF
5% 2 25V NP0-C0G-CERM 01005
TO DOCK FLEX
CKPLUS_WAIVE=I2C_PULLUP
C4730
1
1
56PF
ROOM=DOCK
C4729 56PF
5% 25V NP0-C0G-CERM 2 01005
ROOM=FOREHEAD
B
41
5% 25V 2 NP0-C0G-CERM 01005
ROOM=DOCK_B2B
ROOM=DOCK_B2B
ROOM=RIGHT_BUTTON
FL4732
150OHM-25%-200MA-0.7DCR 2
I2C_MIC2_SCL_CONN
1
CKPLUS_WAIVE=I2C_PULLUP
01005
FL4731
45
TO COMBINED BUTTON FLEX
150OHM-25%-200MA-0.7DCR 2
I2C_MIC2_SDA_CONN
1
CKPLUS_WAIVE=I2C_PULLUP
01005
ROOM=RIGHT_BUTTON
C4732
1
1
56PF
45
C4731 56PF
5% 25V 2 NP0-C0G-CERM 01005
5% 2 25V NP0-C0G-CERM 01005
ROOM=RIGHT_BUTTON
ROOM=RIGHT_BUTTON
FL4742
150OHM-25%-200MA-0.7DCR
A
2
1
I2C_DISP_EEPROM_SCL_CONN
45 SYNC_MASTER=Sync
01005
PAGE TITLE
ROOM=DISPLAY_B2B
FL4741
spare
TO DISPLAY FLEX
150OHM-25%-200MA-0.7DCR 2
SYNC_DATE=05/17/2016
DRAWING NUMBER
1
I2C_DISP_EEPROM_SDA_CONN
Apple Inc.
45
01005
ROOM=DISPLAY_B2B
1
C4742 56PF
2
5% 25V NP0-C0G-CERM 01005
ROOM=DISPLAY_B2B
1
C4741 56PF
5% 2 25V NP0-C0G-CERM 01005
ROOM=DISPLAY_B2B
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
AOP I2C
47 41 40 37 36 32 21 20 18 16 53 52 48
7 47 41 40 37 36 32 21 20 18 16 53 52 48
1
R4801 2.2K
5% 1/32W MF 01005
1
2
4
3
0.1UF 20%
6.3V X5R-CERM 01005 ROOM=SOC
5% 1/32W MF 01005
2
#24544699: Support 1MHz
U4802
PP1V8
25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39 29
1
MAX20312 WLP
13
I2C_AOP_SCL
MAKE_BASE=TRUE
A2 IOVCC1 ROOM=SOC
13
I2C_AOP_SDA
MAKE_BASE=TRUE
B2 IOVCC2
#24550735: ISP I2C0 PU 1
R4808 1.00K
A1 GND
9
ROOM=SOC
I2C_ISP_UT_SCL I2C_ISP_UT_SDA
MAKE_BASE=TRUE
0.00
1
I2C_UT_SCL_CONN 45
0% 1/32W MF 01005
1
35 35
ROOM=FOREHEAD
FL4815
150OHM-25%-200MA-0.7DCR
1
25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39 29
I2C_PROX_SCL_CONN
1
R4815
#24958320:Intentional R4815 Change Reduce undershoot when Prox Driving
2
33.2
1
I2C_PROX_SDA_CONN
1% 1/32W MF 01005
1
1
C4803 56PF
5% 25V 2 NP0-C0G-CERM 01005
ROOM=FOREHEAD
Intentional R4815 Change
ROOM=FOREHEAD
2
45
CKPLUS_WAIVE=I2C_PULLUP
9
C4804 56PF
9
R4810 2.2K
1
ROOM=SOC
2
5% 1/32W MF 01005
1
R4811 2.2K
CKPLUS_WAIVE=I2C_PULLUP
C4816 56PF
5% 25V 2 NP0-C0G-CERM 01005
ROOM=RCAM_B2B
5% 1/32W MF 01005
I2C_ISP_NH_SCL I2C_ISP_NH_SDA
56PF
5% 2 25V NP0-C0G-CERM 01005
I2C_UT_SDA_CONN 45
ROOM=RCAM_B2B
1
C4817 ROOM=RCAM_B2B
0% 1/32W MF 01005
45
CKPLUS_WAIVE=I2C_PULLUP
2
PP1V8
CKPLUS_WAIVE=I2C_PULLUP
01005
C
R4817 0.00
I2C2
TO FCAM FLEX
26
2
ROOM=RCAM_B2B
I2C_AOP_SCL I2C_AOP_SDA
26
R4816
See page 46
34
I2C_ISP_UT_SCL I2C_ISP_UT_SDA
MAKE_BASE=TRUE
I2C1 34
D
1.00K
ROOM=SOC
9
R4809
5% 1/32W MF 2 01005
5% 1/32W MF 2 01005
I2C_AOP_SCL I2C_AOP_SDA
2
1
ISP I2C0
C4807
2
R4802 2.2K
5
PP1V8_SDRAM 1
PP1V8_SDRAM
2
D
6
VCC B1
8
R4812
ROOM=SOC MAKE_BASE=TRUE
1
0.00 0% 1/32W MF 01005
MAKE_BASE=TRUE
5% 25V 2 NP0-C0G-CERM 01005
I2C_NH_SCL_CONN
2
1
ROOM=FOREHEAD
ROOM=FOREHEAD
CKPLUS_WAIVE=I2C_PULLUP
C4812
45
C
56PF
5% 2 25V NP0-C0G-CERM 01005 ROOM=FOREHEAD
38 19
PP1V8_SDRAM
16 18 20 21 32 36 37 40 41 47 48 52 53
5
1
R4803
4.7K
1% 1/32W MF 2 01005
VCC
U4805 6S 3 74LVC1G3157GX Y0 X2SON6 4Z Y1 1
NC
ROOM=MAMBA_MESA
I2C_AOP_SCL_ISO
GND
1
1
R4804
1% 1/32W MF 2 01005
ROOM=MAMBA_MESA
ROOM=FOREHEAD
R4806 0% MF
0.00
I2C_MESA_TURTLE_SCL_CONN
1/32W 01005
1% 1/32W MF 2 01005
CKPLUS_WAIVE=I2C_PULLUP
5% 25V 2 NP0-C0G-CERM 01005
38
C4809 56PF
PP1V8_SDRAM
511K
C4813 56PF
ROOM=MAMBA_MESA
1
R4805
1
45
ROOM=FOREHEAD
1
AOP_TO_MESA_I2C_ISO_EN 1
I2C_NH_SDA_CONN
2
0% 1/32W MF 01005
4.7K
2
2 13
R4813 0.00
PP1V8_MESA
5% NP0-C0G-CERM 01005
16 18 20 21 32 36 37 40 41 47 48 52 53
2 25V
5
TO MAMBA/MESA FLEX
ROOM=MAMBA_MESA
VCC
U4806 6S 3 74LVC1G3157GX Y0 X2SON6 4Z Y1 1 GND
R4807
NC
I2C_AOP_SDA_ISO
2 0% MF
2
0.00
I2C_MESA_TURTLE_SDA_CONN
1
1/32W 01005
38
ROOM=MAMBA_MESA
1
C4810 56PF
2
B
5% 25V NP0-C0G-CERM 01005
B
ROOM=MAMBA_MESA
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
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A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
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IV ALL RIGHTS RESERVED
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B
B
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
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C
C
B
B
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
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This page contains items which differ accross all MLB designs
PCIe lanes PP0801
D
P2MM-NSM
ROOM=SOC
SM
PP
D
90_AP_PCIE3_RXD_C_P 90_AP_PCIE3_RXD_C_N
PP0802 P2MM-NSM
ROOM=SOC
SM
C
1
PP
8 52
1
2 0.1UF 90_PCIE_BB_TO_AP_RXD_P GND_VOID=TRUE 6.3V X5R-CERM 01005
53
MAKE_BASE=TRUE
2 0.1UF 90_PCIE_BB_TO_AP_RXD_N 6.3V GND_VOID=TRUE X5R-CERM 01005
53
MAKE_BASE=TRUE
2 0.1UF 90_PCIE_AP_TO_BB_TXD_P 6.3V GND_VOID=TRUE X5R-CERM 01005
53
MAKE_BASE=TRUE
90_PCIE_AP_TO_BB_TXD_N
53
MAKE_BASE=TRUE
90_PCIE_WLAN_TO_AP_RXD_P
53
MAKE_BASE=TRUE
8
90_AP_PCIE2_RXD_C_P
1 C0816 ROOM=SOC 20%
8
90_AP_PCIE2_RXD_C_N
1 C0817 20% ROOM=SOC
8
90_AP_PCIE2_TXD_C_P
1 C0815 20% ROOM=SOC
8
90_AP_PCIE2_TXD_C_N
1 C0818 ROOM=SOC 20%
25 18 17 16 13 12 11 9 8 7 5 48 47 46 39 29
8 52
2 6.3V X5R-CERM 01005
0.1UF
C
GND_VOID=TRUE
PP1V8 1
R0807 100K
52
8
B
PCIE_WLAN_BI_AP_CLKREQ_L
5% 1/32W MF 2 01005 ROOM=SOC 1 C0811 20% ROOM=SOC
2 6.3V X5R-CERM 01005
90_AP_PCIE3_RXD_C_P
0.1UF
GND_VOID=TRUE
8
90_AP_PCIE3_RXD_C_N
1 C0812 20% ROOM=SOC
53
MAKE_BASE=TRUE
8
90_AP_PCIE3_TXD_C_P
1 C0814 20% ROOM=SOC
53
MAKE_BASE=TRUE
8
90_AP_PCIE3_TXD_C_N
1 C0813 20% ROOM=SOC
53
MAKE_BASE=TRUE
53
MAKE_BASE=TRUE
53
MAKE_BASE=TRUE
53
MAKE_BASE=TRUE
53
MAKE_BASE=TRUE
53
MAKE_BASE=TRUE
8 8 8 8 8 8 8 8
2 0.1UF 90_PCIE_WLAN_TO_AP_RXD_N 6.3V GND_VOID=TRUE X5R-CERM 01005
2 0.1UF 90_PCIE_AP_TO_WLAN_TXD_P GND_VOID=TRUE 6.3V X5R-CERM 01005 2 6.3V X5R-CERM 01005
90_PCIE_AP_TO_WLAN_REFCLK_P 90_PCIE_AP_TO_WLAN_REFCLK_N 90_PCIE_AP_TO_BB_REFCLK_P 90_PCIE_AP_TO_BB_REFCLK_N PCIE_AP_TO_WLAN_RESET_L PCIE_AP_TO_BB_RESET_L PCIE_WLAN_BI_AP_CLKREQ_L PCIE_BB_BI_AP_CLKREQ_L
0.1UF
90_PCIE_AP_TO_WLAN_TXD_N
B
GND_VOID=TRUE
90_PCIE_AP_TO_WLAN_REFCLK_P 90_PCIE_AP_TO_WLAN_REFCLK_N 90_PCIE_AP_TO_BB_REFCLK_P 90_PCIE_AP_TO_BB_REFCLK_N PCIE_AP_TO_WLAN_RESET_L PCIE_AP_TO_BB_RESET_L PCIE_WLAN_BI_AP_CLKREQ_L PCIE_BB_BI_AP_CLKREQ_L
53
MAKE_BASE=TRUE
52 53
MAKE_BASE=TRUE
52 53
MAKE_BASE=TRUE
47 41 40 37 36 32 21 20 18 16 53 48
R52061 100K
1% 1/32W MF 01005 2 ROOM=RADIO_BB 53 52
A
#24556007:Parallel to 100kohm R5906_RF(nostuff)
PCIE_BB_BI_AP_CLKREQ_L
#24535235: D10 EVT 1x Desense Cap (68pF) #24535276: D101 EVT 1x Desense Cap (220pF)
#25811920: D10 CRB: 2x 01005 Cap for Backlight Desense D101 CRB: No additional Cap 53 27 26 25 23 21 19 18 10 9 4 46 41 40 39 37 35 34 33 31 28
PP1V8_SDRAM
PP_VDD_MAIN
PP3V0_NAND 1
C2619 56PF
5% 2 25V NP0-C0G-CERM 01005 ROOM=STROBE
1
C2620
1
220PF
17 19
C1756
SYNC_MASTER=Sync
PAGE TITLE
68PF
5% 2 10V C0G-CERM 01005
2
ROOM=STROBE
SYNC_DATE=05/17/2016
spare
5% 16V NP0-C0G 01005
DRAWING NUMBER
ROOM=NAND
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
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77 58 55 53 52 27 26 25 23 21 19 18 10 9 4 46 41 40 39 37 35 34 33 31 28 47 41 40 37 36 32 21 20 18 16 68 60 58 55 53 52 48
55 20
55 20 55 20 55 20 55 12
55 52
D
55 52 55 52 55 52 55 52 55 52 55 52 55 52 55 20 55 12
6
PP_VDD_MAIN PP1V8_SDRAM
PP_VDD_MAIN
PMUGPIO_TO_WLAN_CLK32K
PMU_TO_WLAN_32K
4
Wifi/BT
PP1V8_SDRAM
PMU_TO_WLAN_REG_ON
5
3 27 26 25 41 40 39 47 41 40 37 68
77 23 37 36 60
58 21 35 32 58
55 19 34 21 55
53 18 33 20 53
52 10 31 18 52
65 38 37 32 25 23 19 65 20
PMU_TO_WLAN_REG_ON
PMU_TO_BT_REG_ON BT_TO_PMU_HOST_WAKE
65 20
PMU_TO_BT_REG_ON
69 20
BT_TO_PMU_HOST_WAKE
AP_TO_BT_WAKE
46 9 4 28 16 48
55 12 55 12 55 12
55 12 55 12 55 12 55 12
90_PCIE_AP_TO_WLAN_REFCLK_P 90_PCIE_AP_TO_WLAN_REFCLK_N 90_PCIE_AP_TO_WLAN_TXD_P 90_PCIE_AP_TO_WLAN_TXD_N 90_PCIE_WLAN_TO_AP_RXD_P 90_PCIE_WLAN_TO_AP_RXD_N PCIE_AP_TO_WLAN_RESET_L PCIE_WLAN_BI_AP_CLKREQ_L WLAN_TO_PMU_HOST_WAKE AP_TO_WLAN_DEVICE_WAKE
64 12
100_PCIE_AP_TO_WLAN_REFCLK_P
20 64 64 12
Opposite polarity on Karoo -->
100_PCIE_AP_TO_WLAN_REFCLK_N 100_PCIE_AP_TO_WLAN_TX_P
55 13
55 11 55 11 55 11 55 11
C
PP_VDD_MAIN
PP1V8_SDRAM
PP1V8_SDRAM
PP_VDD_BOOST
PP_VDD_BOOST_RF
BBPMU_TO_PMU_AMUX1 BBPMU_TO_PMU_AMUX2 BBPMU_TO_PMU_AMUX3
BBPMU_TO_PMU_AMUX1 BBPMU_TO_PMU_AMUX2
Cellular
BBPMU_TO_PMU_AMUX3
68 12
100_PCIE_WLAN_TO_AP_RX_P
68 37 26
100_PCIE_WLAN_TO_AP_RX_N
WIFI_MLB
PCIE_AP_TO_WLAN_PERST_L
68 12 68 12
PCIE_AP_BI_WLAN_CLKREQ_L
68 12
PCIE_WLAN_TO_PMU_WAKE
64 39 23 20 13
AP_TO_WLAN_DEV_WAKE
UART_AP_TO_WLAN_TXD UART_WLAN_TO_AP_RXD UART_AP_TO_WLAN_RTS_L UART_WLAN_TO_AP_CTS_L
AP_TO_BBPMU_RADIO_ON_L PMU_TO_BBPMU_RESET_L AP_TO_BB_RESET_L BB_TO_AP_RESET_DETECT_L BB_TO_STROBE_DRIVER_GSM_BURST_IND AP_TO_BB_MESA_ON AP_TO_BB_TIME_MARK
AP_TO_BB_COREDUMP LCM_TO_MANY_BSYNC AP_TO_BB_IPC_GPIO1
UART_WLAN_TO_AP_RXD
67 52
UART_AP_TO_WLAN_RTS_L
67 52
UART_WLAN_TO_AP_CTS_L
67 52 67 52
AOP_TO_WLAN_CONTEXT_A AOP_TO_WLAN_CONTEXT_B
PMU_TO_BBPMU_RESET_L
D
AP_TO_BB_RESET_L BB_TO_AP_RESET_DETECT_L
RADIO_MLB
BB_TO_AP_GSM_TXBURST AP_TO_BB_MESA_ON AP_TO_BB_TIME_MARK AP_TO_BB_COREDUMP_TRIG TOUCH_TO_BBPMU_FORCE_PWM AP_TO_BB_IPC_GPIO AP_TO_BB_IPC_GPIO2
UART_AP_TO_WLAN_TXD
UART_AP_TO_BT_TXD UART_BT_TO_AP_RXD UART_AP_TO_BT_RTS_L UART_BT_TO_AP_CTS_L
AP_TO_BBPMU_RADIO_ON_L
BB_TO_AP_RESET_ACT_L
100_PCIE_AP_TO_WLAN_TX_N
UART_AP_TO_BT_TXD
67 52
UART_BT_TO_AP_RXD
67 52
UART_AP_TO_BT_RTS_L
68 52
UART_BT_TO_AP_CTS_L
68 52 68 20
55 13
PP_VDD_MAIN
1
AP_TO_BT_WAKE
68 12 55 12
2
90_PCIE_AP_TO_BB_REFCLK_P 90_PCIE_AP_TO_BB_REFCLK_N 90_PCIE_AP_TO_BB_TXD_P 90_PCIE_AP_TO_BB_TXD_N 90_PCIE_BB_TO_AP_RXD_P 90_PCIE_BB_TO_AP_RXD_N PCIE_AP_TO_BB_RESET_L PCIE_BB_BI_AP_CLKREQ_L BB_TO_PMU_PCIE_HOST_WAKE_L
100_PCIE_AP_TO_BB_REFCLK_P 100_PCIE_AP_TO_BB_REFCLK_N 100_PCIE_AP_TO_BB_TX_P 100_PCIE_AP_TO_BB_TX_N 100_PCIE_BB_TO_AP_RX_P 100_PCIE_BB_TO_AP_RX_N PCIE_AP_TO_BB_PERST_L PCIE_AP_BI_BB_CLKREQ_L PCIE_BB_TO_PMU_WAKE_L
AOP_TO_WLAN_CONTEXT_A AOP_TO_WLAN_CONTEXT_B
I2S_AP_TO_BT_BCLK I2S_AP_TO_BT_LRCLK I2S_BT_TO_AP_DIN I2S_AP_TO_BT_DOUT
UART_AP_TO_BB_TXD UART_BB_TO_AP_RXD
I2S_AP_TO_BT_BCLK I2S_AP_TO_BT_LRCK
68 13
I2S_BT_TO_AP_DIN
68 13
UART_AOP_TO_BB_TXD UART_BB_TO_AOP_RXD
I2S_AP_TO_BT_DOUT
UART_AOP_TO_BB_TXD UART_BB_TO_AOP_RXD UART_AOP_TO_GNSS_TXD
C
UART_GNSS_TO_AOP_RXD
UART_BB_TO_WLAN_COEX 68 11
UART_WLAN_TO_BB_COEX
68 11 59 56
50_UAT_WLAN_5G_WEST 50_UAT_WLAN_2G_EAST 50_LAT_WLAN_5G_EAST 50_LAT_WLAN_G_1 50_LAT_WLAN_A_1 50_UAT2_M
68 11
50_UAT_WLAN_5G_WEST 50_UAT_WLAN_2G_EAST
68 11
50_UAT_WLAN_5G_EAST
68 55 68 55
50_WLAN_G_1
I2S_BB_TO_AP_BCLK I2S_BB_TO_AP_LRCLK I2S_AP_TO_BB_DOUT I2S_BB_TO_AP_DIN
I16 ieee ieee.std_logic_1164.all work.all TRUE
I2S_AP_TO_BB_BCLK I2S_AP_TO_BB_LRCLK I2S_AP_TO_BB_DOUT I2S_BB_TO_AP_DIN
UART_BB_TO_WLAN_COEX UART_WLAN_TO_BB_COEX
UART_BB_TO_WLAN_COEX
NFC_SWP
NFC_SWP
UART_WLAN_TO_BB_COEX
50_WLAN_A_1 50_UAT2_M 81 58 53
NFC_TO_BB_CLKREQ BB_TO_NFC_CLK 78 58 53
I15 12
50_UAT_WLAN_2G_WEST_PLEXER
50_WLAN_G_1
50_UUAT_LB_MLB_NORTH
50_UAT_WLAN_5G_EAST
50_UAT_MB_HB_SOUTH
50_UAT_WLAN_2G_EAST
50_UAT_LB_MLB_SOUTH
50_UAT_WLAN_5G_WEST
50_UAT1_WEST
AP_TO_ICEFALL_FW_DWLD_REQ
MAKE_BASE=TRUE
AP_TO_ICEFALL_FW_DWLD_REQ
78
AP_TO_ICEFALL_FW_DWLD SE2_PWR_REQ
81 58 53 78 58
50_UAT1_TUNER
50_UAT2_M
NFC_SWP_MUX SE2_READY
RADIO_MLB_FF 50_WLAN_A_1
NFC_SWP_MUX
PP3V0_TRISTAR_ANT_PROX PP1V8_SDRAM
PP3V0_TRISTAR_ARC_PROX VDD_TUNER_RFFE_VIO_1V8 UAT_TUNER_RFFE_CLK
36 17 13 67 67 13
19 29 40 41 60 16 18 20 21 32 36 37 40 41 47 48 52 53 55 58 60 68
64 20
UAT_TUNER_RFFE_DATA
67 40
BUFFER_GPO1
67 40
SE2_PRESENT ICEFALL_LDO_ENABLE SWD_AP_TO_MANY_SWCLK SWD_AOP_BI_BB_SWDIO PMU_TO_BB_USB_VBUS_DETECT 90_USB_BB_DATA_P 90_USB_BB_DATA_N
SE2_PRESENT ICEFALL_LDO_ENABLE
SWD_AP_TO_BB_CLK SWD_AP_BI_BB_IO USB_BB_VBUS 90_USB_BB_P 90_USB_BB_N
BUFFER_GPO2
B
BB_TO_LAT_ANT_SCLK BB_TO_LAT_ANT_SDATA
BB_TO_LAT_ANT_SCLK BB_TO_LAT_ANT_DATA
41 53 60 68 41 53 60 68
To UAT
75 59
50_UAT_WLAN_2G_WEST_PLEXER 50_UAT_LB_MLB_SOUTH 50_UAT_MB_HB_SOUTH 50_UUAT_LB_MLB_NORTH
75 59
50_UAT1_WEST
76 60
BB_TO_UAT_SCLK BB_TO_UAT_DATA 50_UAT1_TUNER BB_BUFFER_GPO1 BB_BUFFER_GPO2
76 59 73 59
P2MM-NSM
PP5304 PP PP5301 PP
1
P2MM-NSM
PP5302 PP
1
P2MM-NSM
PP5303 PP
1
SM ROOM=UAT_DEBUG
P2MM-NSM
SM ROOM=UAT_DEBUG
FF SPECIFIC 77 58 55 53 52 27 26 25 23 21 19 18 10 9 4 46 41 40 39 37 35 34 33 31 28 47 41 40 37 36 32 21 20 18 16 68 60 58 55 53 52 48
SM ROOM=UAT_DEBUG SM ROOM=UAT_DEBUG
PP_VDD_MAIN PP1V8_SDRAM
73 59
1
MAKE_BASE=TRUE MAKE_BASE=TRUE
I2
PP_VDD_MAIN
68 60
PP1V8_SDRAM
68 60
To LAT 68 60 53 41
58 20 64 58 64 58 58 12 58 12 58 20
58 12 58 12 58 12 58 12
A
B
50_UAT_WLAN_2G_WEST_PLEXER 50_UAT_LB_MLB_SOUTH 50_UAT_MB_HB_SOUTH 50_UUAT_LB_MLB_NORTH 50_UAT1_WEST
BB_TO_LAT_ANT_SCLK BB_TO_LAT_ANT_DATA
UAT_RFFE_CLK UAT_RFFE_DATA 50_UAT1_TUNER BUFFER_GPO1 BUFFER_GPO2
LAT_RFFE_CLK
PMU_TO_NFC_EN
PMU_TO_NFC_EN
BB_TO_NFC_CLK NFC_TO_BB_CLK_REQ
BB_TO_NFC_CLK
68 41
NFC_TO_BB_CLK_REQ
68 41
AP_TO_NFC_FW_DWLD_REQ AP_TO_NFC_DEV_WAKE NFC_TO_PMU_HOST_WAKE
AP_TO_NFC_FW_DWLD
UART_AP_TO_NFC_TXD UART_NFC_TO_AP_RXD UART_AP_TO_NFC_RTS_L UART_NFC_TO_AP_CTS_L
UART_AP_TO_NFC_TXD
UART_AP_TO_GNSS_RTS_L
UART_NFC_TO_AP_RXD
UART_GNSS_TO_AP_CTS_L
UART_AP_TO_NFC_RTS_L
GNSS_TO_PMU_HOST_WAKE
UART_NFC_TO_AP_CTS_L
AP_TO_GNSS_TIME_MARK
81 58 53 78 58 78 58 81 58 53
78 58 53
AP_TO_NFC_DEV_WAKE
68 60 53 41
LAT_RFFE_DATA
68 46
STOCKHOLM_MLB
BB_TO_LAT_GPO1 BB_TO_LAT_GPO2 BB_TO_LAT_GPO3
RFFE_GPO1 RFFE_GPO2 RFFE_GPO3
PMU_TO_GNSS_EN
NFC_TO_PMU_HOST_WAKE
UART_AP_TO_GNSS_TXD UART_GNSS_TO_AP_RXD
NFC_SWP SE2_READY SE2_PWR_REQ SE2_PRESENT
NFC_SWP
NFC
SE2_READY SE2_PWR_REQ SE2_PRESENT
NFC_SWP_MUX
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
NFC_SWP_MUX ICEFALL_LDO_ENABLE
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
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2
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
REV
1 ECN
CK APPD
DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
D
8
0006400877
ENGINEERING RELEASED
2016-06-14
D1X WIFI_MLB (PERENNIAL) FEBRUARY 1, 2016 PDF PAGE 2 3 TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
CSA PAGE 76 77
D
CONTENTS PERENNIAL WIFI FRONT-END
TABLE_TABLEOFCONTENTS_ITEM
BOM OPTIONS: D10_JP:
D11_JP: TRUE TABLE_5_HEAD
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
PART#
TRUE QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
CRITICAL
D11_JP
TABLE_5_ITEM
131S0648
1
CAP,CER,0.3PF,+/-0.05,01005
C7705_RF
CRITICAL
TABLE_5_ITEM
D10_JP
152S00273 TRUE 1
IND,0.6NH,UH-Q,01005
R7703_RF
TABLE_5_ITEM
152S00029
1
IND,1.1NH,UH-Q,01005
R7703_RF
CRITICAL
152S1976
1 TRUE
IND,0.7NH,UH-Q,01005
R7711_RF
CRITICAL
D11_JP
131S0400
1 TRUE
CAP,CER,3.5PF+/-0.1,01005
R7702_RF
CRITICAL
D11_JP
152S1986
1 TRUE
IND,FILM,2.2NH,UH-Q,01005
R7704_RF
CRITICAL
D11_JP
131S0648
1 TRUE
CAP,CER,0.3PF,+/-0.05PF,01005
C7708_RF
CRITICAL
D11_JP
TABLE_5_ITEM
1
CAP,CER,0.2PF,+/-0.05,01005
C7706_RF
CRITICAL
D10_JP
117S0161
1
RES,MF,0 OHM,1/32W,01005
R7711_RF
CRITICAL
D10_JP
117S0161
1
RES,MF,0 OHM,1/32W,01005
R7702_RF
CRITICAL
D10_JP
IND,1.0NH,UH-Q,01005
R7704_RF
CRITICAL
1
CAP,3.9PF,+/-1.0PF,01005
R6711_RF
CRITICAL
D10_JP
131S0593
1 TRUE
CAP,3.9PF,+/-1.0PF,0201,HI-Q
R6711_RF
CRITICAL
1
IND,7.5NH,UH-Q,01005
C6729_RF
CRITICAL
TABLE_5_ITEM
152S2055
D10_JP
1 TRUE
IND,7.5NH,UH-Q,0201
C6729_RF
CRITICAL
D11_JP
1
RES,MF,0 OHM,1/32W,01005
R7700_RF
CRITICAL
D10_JP
117S0161
1 TRUE
RES,MF,0 OHM,1/32W,01005
R7700_RF
CRITICAL
D11_JP
1
IND,6.2NH,UH-Q,01005
C7702_RF
CRITICAL
117S0161
D10_JP
1 TRUE
RES,MF,0 OHM,1/32W,01005
L7700_RF
CRITICAL
1
IND, 0.8NH,UH-Q,01005
L7700_RF
CRITICAL
1
IND,6.2NH,UH-Q,01005
L7701_RF
CRITICAL
D10_JP
152S1853
1 TRUE
IND,9.1NH,UH-Q,01005
L7701_RF
CRITICAL
1
RES,MF,0 OHM,1/32W,01005
R7701_RF
CRITICAL
53 IN
55
53 OUT
55
53 IN
55
53 IN
55
53 IN
55
53 IN
55
53 IN
55
53 OUT
TABLE_5_ITEM
D10_JP
117S0161
1 TRUE
RES,MF,0 OHM,1/32W,01005
R7701_RF
CRITICAL
D11_JP TABLE_5_ITEM
D10_JP
131S0893
1 TRUE
CAP,CER,0.2PF,+/-0.05PF,01005
C7705_RF
CRITICAL
D11_JP TABLE_5_ITEM
131S0893
D10_JP
NOSTUFF:C7729_RF,C7711_RF,C7709_RF,C7710_RF, C7707_RF, C7708_RF C7700_RF, C7703_RF,C7704_RF
1
CAP,CER,0.2PF,+/-0.05PF,01005
C7729_RF
CRITICAL
D11_JP
NOSTUFF:C7706_RF, C7711_RF,C7709_RF,C7710_RF, C7707_RF C7700_RF,C7702_RF, C7703_RF,C7704_RF
D10_ROW:
55
53 OUT
55
53 IN 2
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
D11_ROW:
TABLE_5_ITEM
131S0648
1
CAP,CER,0.3PF,+/-0.05,01005
C7705_RF
CRITICAL
D10_ROW
IO
55
53 OUT
55
53 IN
TABLE_5_HEAD
PART#
1
IND,1.1NH,UH-Q,01005
R7703_RF
CRITICAL
D10_ROW
1
CAP,CER,0.2PF,+/-0.05,01005
C7706_RF
CRITICAL
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
CRITICAL
D11_ROW
TABLE_5_ITEM
152S00273
TABLE_5_ITEM
131S0893
QTY
D10_ROW
1
IND,0.6NH,UH-Q,01005
R7703_RF
55
53 OUT
55
53 IN
TABLE_5_ITEM
152S1976
TABLE_5_ITEM
117S0161
TRUE 1
RES,MF,0 OHM,1/32W,01005
R7711_RF
CRITICAL
D10_ROW
1
IND,0.7NH,UH-Q,01005
R7711_RF
CRITICAL
D11_ROW TABLE_5_ITEM
TABLE_5_ITEM
117S0161
TRUE 1
RES,MF,0 OHM,1/32W,01005
R7702_RF
CRITICAL
D10_ROW TABLE_5_ITEM
152S1988
TRUE 1
IND,2.4NH,UH-Q,01005
R7704_RF
CRITICAL
D10_ROW TABLE_5_ITEM
B
117S0161
TRUE 1
RES,MF,0 OHM,1/32W,01005
R6711_RF
CRITICAL
D10_ROW TABLE_5_ITEM
152S1853
TRUE 1
IND,9.1NH,UH-Q,01005
C6729_RF
CRITICAL
D10_ROW
131S0400
1
CAP,CER,3.5PF+/-0.1,01005
R7702_RF
CRITICAL
D11_ROW
152S1986
TRUE 1
IND,FILM,2.2NH,UH-Q,01005
R7704_RF
CRITICAL
D11_ROW
118S0724
TRUE 1
152S2054
TRUE 1
55
53 OUT
55
53 IN
117S0161
TABLE_5_ITEM
TRUE 1
RES,MF,0 OHM,1/32W,01005
R7700_RF
CRITICAL
D10_ROW
1
UART_WLAN_TO_AP_RXD UART_AP_TO_WLAN_TXD UART_WLAN_TO_AP_CTS_L UART_AP_TO_WLAN_RTS_L
BLUETOOTH UART
TABLE_5_ITEM
TABLE_5_ITEM
RES,MF,0 OHM,1/20W,0201
R6711_RF
CRITICAL
D11_ROW
55 TABLE_5_ITEM
IND,9.1NH,UH-Q,0201
C6729_RF
CRITICAL
D11_ROW
RES,MF,0 OHM,1/32W,01005
R7700_RF
CRITICAL
D11_ROW
53 IN
55
53 OUT
55
53 IN
55
53 OUT
TABLE_5_ITEM
117S0161
90_PCIE_AP_TO_WLAN_REFCLK_P 90_PCIE_AP_TO_WLAN_REFCLK_N 90_PCIE_AP_TO_WLAN_TXD_P 90_PCIE_AP_TO_WLAN_TXD_N 90_PCIE_WLAN_TO_AP_RXD_P 90_PCIE_WLAN_TO_AP_RXD_N PCIE_AP_TO_WLAN_RESET_L PCIE_WLAN_BI_AP_CLKREQ_L WLAN_TO_PMU_HOST_WAKE AP_TO_WLAN_DEVICE_WAKE
WLAN UART
TABLE_5_HEAD
PART#
TABLE_5_ITEM
152S00029
C
PMU_TO_WLAN_REG_ON PMU_TO_BT_REG_ON BT_TO_PMU_HOST_WAKE AP_TO_BT_WAKE
WLAN PCIE
D11_JP
TABLE_5_ITEM
117S0161
55
TABLE_5_ITEM
TABLE_5_ITEM
152S2043
53 IN
D11_JP
TABLE_5_ITEM
152S1998
PMUGPIO_TO_WLAN_CLK32K
TABLE_5_ITEM
TABLE_5_ITEM
152S2043
55
TABLE_5_ITEM
TABLE_5_ITEM
117S0161
53 IN
CONTROL
D11_JP
TABLE_5_ITEM
152S2061
55
TABLE_5_ITEM
TABLE_5_ITEM
131S0404
53 IN
TABLE_5_ITEM
TABLE_5_ITEM
1
55
PP_VDD_MAIN PP1V8_SDRAM
CLOCKS
TABLE_5_ITEM
TABLE_5_ITEM
152S1980
53 IN
TABLE_5_ITEM
TABLE_5_ITEM
C
55
TABLE_5_ITEM
D10_JP
131S0893
POWER
TABLE_5_HEAD
UART_AP_TO_BT_TXD UART_BT_TO_AP_RXD UART_AP_TO_BT_RTS_L UART_BT_TO_AP_CTS_L
B
TABLE_5_ITEM
117S0161
TABLE_5_ITEM
152S2043
1
IND,6.2NH,UH-Q,01005
C7702_RF
CRITICAL
D10_ROW
1
L7700_RF
RES,MF,0 OHM,1/32W,01005
CRITICAL
AOP
D11_ROW TABLE_5_ITEM
152S1853
TABLE_5_ITEM
152S1998
1
IND, 0.8NH,UH-Q,01005
L7700_RF
CRITICAL
D10_ROW
1
L7701_RF
IND,9.1NH,UH-Q,01005
CRITICAL
D11_ROW TABLE_5_ITEM
TABLE_5_ITEM
152S2043
TRUE 1
IND,6.2NH,UH-Q,01005
L7701_RF
CRITICAL
D10_ROW
117S0161
1
RES,MF,0 OHM,1/32W,01005
R7701_RF
CRITICAL
D11_ROW
131S0893
1
CAP,CER,0.2PF,+/-0.05PF,01005
C7705_RF
CRITICAL
D11_ROW
55
53 IN
55
53 IN
AUDIO
TABLE_5_ITEM
TABLE_5_ITEM
117S0161
1
RES,MF,0 OHM,1/32W,01005
R7701_RF
CRITICAL
D10_ROW
AOP_TO_WLAN_CONTEXT_A AOP_TO_WLAN_CONTEXT_B
TABLE_5_ITEM
131S0893
NOSTUFF:C7729_RF,C7711_RF,C7709_RF,C7710_RF, C7707_RF, C7708_RF C7700_RF, C7703_RF,C7704_RF
1
CAP,CER,0.2PF,+/-0.05PF,01005
C7729_RF
CRITICAL
D11_ROW
NOSTUFF:C7706_RF,C7711_RF,C7709_RF,C7710_RF, C7707_RF, C7708_RF C7700_RF,C7702_RF, C7703_RF,C7704_RF
D101_WIFI: PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION TABLE_5_ITEM
131S0648
1
CAP,CER,0.3PF,+/-0.05,01005
C7705_RF
CRITICAL
D101
152S00029
1
IND,1.1NH,UH-Q,01005
R7703_RF
CRITICAL
D101
131S0893
1
CAP,CER,0.2PF,+/-0.05,01005
C7706_RF
CRITICAL
D101
117S0161
1
RES,MF,0 OHM,1/32W,01005
R7711_RF
CRITICAL
D101
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
TABLE_5_ITEM
1
IND,0.6NH,UH-Q,01005
R7703_RF
CRITICAL
D111
152S1976
1
IND,0.7NH,UH-Q,01005
R7711_RF
CRITICAL
D111
131S0400
1
CAP,CER,3.5PF+/-0.1,01005
R7702_RF
CRITICAL
D111
A
152S1988
TRUE 1
131S0648
TRUE 1
118S0724
TRUE 1
152S2054
TRUE 1
R7702_RF
CRITICAL
152S1986
TRUE 1
D101
118S0724
TRUE 1
152S2054
TRUE 1
117S0161
1
TABLE_5_ITEM
IND,2.4NH,UH-Q,01005
R7704_RF
CRITICAL
D101 TABLE_5_ITEM
CAP,CER,0.3PF,+/-0.05PF,01005
C7708_RF
CRITICAL
D101
TABLE_5_ITEM
IND,FILM,2.2NH,UH-Q,01005
R7704_RF
CRITICAL
D111
R6711_RF
CRITICAL
R6711_RF
CRITICAL
D111
C6729_RF
CRITICAL
IND,9.1NH,UH-Q,0201
C6729_RF
CRITICAL
D111
1
152S2043
TRUE 1
RES,MF,0 OHM,1/32W,01005
R7700_RF
CRITICAL
RES,MF,0 OHM,1/32W,01005
R7700_RF
CRITICAL
D111
C7702_RF
CRITICAL
117S0161 152S1853
CRITICAL
D101
152S2043
1
IND,6.2NH,UH-Q,01005
L7701_RF
CRITICAL
D101
IO
3
IO
3
IO
2
IO
2
IO
3
IO
50_UAT_WLAN_5G_WEST 50_UAT_WLAN_2G_EAST 50_LAT_WLAN_5G_EAST 50_LAT_WLAN_G_1 50_LAT_WLAN_A_1 50_UAT2_M
1
RES,MF,0 OHM,1/32W,01005
L7700_RF
CRITICAL
1
IND,9.1NH,UH-Q,01005
L7701_RF
CRITICAL
DRAWING NUMBER
D111
Apple Inc.
117S0161
1
RES,MF,0 OHM,1/32W,01005
R7701_RF
CRITICAL
D111
RES,MF,0 OHM,1/32W,01005
R7701_RF
CRITICAL
7
REVISION
R
131S0893
1
CAP,CER,0.2PF,+/-0.05PF,01005
C7705_RF
CRITICAL
D111
131S0893
1
CAP,CER,0.2PF,+/-0.05PF,01005
C7729_RF
CRITICAL
D111
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
8.0.0
TABLE_5_ITEM
NOSTUFF:C7706_RF,C7711_RF,C7709_RF,C7710_RF, C7707_RF, C7708_RF C7700_RF,C7702_RF, C7703_RF,C7704_RF
D101
NOSTUFF: C7729_RF,C7711_RF,C7709_RF,C7710_RF, C7707_RF C7700_RF, C7703_RF,C7704_RF
8
051-00419
TABLE_5_ITEM
TABLE_5_ITEM
1
spare
D111
TABLE_5_ITEM
117S0161
SYNC_DATE=05/17/2016
PAGE TITLE
TABLE_5_ITEM
L7700_RF
3
TABLE_5_ITEM
D101
IND, 0.8NH,UH-Q,01005
53 OUT
TABLE_5_ITEM
D101
1
53 IN
55
TABLE_5_ITEM
D101
152S1998
55
UART_BB_TO_WLAN_COEX UART_WLAN_TO_BB_COEX
SYNC_MASTER=Sync
TABLE_5_ITEM
IND,6.2NH,UH-Q,01005
53 IN
TABLE_5_ITEM
D101
TABLE_5_ITEM
117S0161
55
TABLE_5_ITEM
TABLE_5_ITEM
IND,9.1NH,UH-Q,0201
53 OUT
TABLE_5_ITEM
RES,MF, 0 OHM,1/20W, 0201
TABLE_5_ITEM
RES,MF, 0 OHM,1/20W, 0201
55
TABLE_5_ITEM
TABLE_5_ITEM
RES,MF,0 OHM,1/32W,01005
53 IN
I2S_AP_TO_BT_BCLK I2S_AP_TO_BT_LRCLK I2S_BT_TO_AP_DIN I2S_AP_TO_BT_DOUT
ANTENNA
TABLE_5_ITEM
TABLE_5_ITEM
1
55
TABLE_5_ITEM
152S00273 TABLE_5_ITEM
117S0161
53 IN
COEX
D111_WIFI:
TABLE_5_HEAD
55
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
6
5
4
3
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
2
1
6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
WIFI/BT PP1V8_SDRAM
PP_VDD_MAIN
C7600_RF 1 C7601_RF 27PF 0.01UF 5%
2 16V NP0-C0G
01005 WLAN
55
PMUGPIO_TO_WLAN_CLK32K
54 53
IN
54
53
IN
54
53
OUT
UART_BB_TO_WLAN_COEX UART_WLAN_TO_BB_COEX
1
10%
6.3V 2 X5R
2
01005 WLAN
54 LPO_IN 8 SECI_RX 7 SECI_TX
PP1V8_SDRAM 1
2
JTAG_WLAN_SEL
R7600_RF 10K
54 53 55
5% 1/32W MF 01005 2 WLAN NOSTUFF
55
IN
54 53
20% 6.3V CERM-X5R 0402-9
2 2 2 2
WLAN_RF
PMU_TO_WLAN_REG_ON
92 WL_REG_ON
LBEE5W11GJ-943
PMU_TO_BT_REG_ON
93 BT_REG_ON
SYM 1 OF 2
61 64 62 2
JTAG_WLAN_SEL JTAG_WLAN_TCK JTAG_WLAN_TMS JTAG_WLAN_TRST_L
JTAG_SEL JTAG_TCK JTAG_TMS JTAG_TRST*
C 55
54 53
OUT
55
54 53
IN
UART_WLAN_TO_AP_RXD UART_AP_TO_WLAN_TXD
11 FAST_UART_TX 10 FAST_UART_RX
53
OUT
UART_WLAN_TO_AP_CTS_L
54
53
IN
UART_AP_TO_WLAN_RTS_L
12 FAST_UART_CTS_IN
55
54 53
IN
AP_TO_WLAN_DEVICE_WAKE
13 WL_DEV_WAKE
55
54 53
OUT
BT_TO_PMU_HOST_WAKE
56 BT_HOST_WAKE
BI
56
IO
BI 1
AP_TO_BT_WAKE
IN
53 54
55
BT_UART_RXD BT_UART_TXD BT_UART_CTS* BT_UART_RTS*
41 42 44 43
UART_AP_TO_BT_TXD
IN
53 54
55
BT_PCM_CLK BT_PCM_SYNC BT_PCM_OUT BT_PCM_IN
38 37 40 39
I2S_AP_TO_BT_BCLK
WL_HOST_WAKE
14
WLAN_TO_PMU_HOST_WAKE
PCIE_CLKREQ* PCIE_PERST*
17 16
PCIE_WLAN_BI_AP_CLKREQ_L PCIE_AP_TO_WLAN_RESET_L
PCIE_RDP PCIE_RDN
19 20
90_PCIE_AP_TO_WLAN_TXD_P 90_PCIE_AP_TO_WLAN_TXD_N
IO
PCIE_TDP PCIE_TDN
22 23
90_PCIE_WLAN_TO_AP_RXD_P 90_PCIE_WLAN_TO_AP_RXD_N
PCIE_REFCLK_P PCIE_REFCLK_N
25 26
90_PCIE_AP_TO_WLAN_REFCLK_P 90_PCIE_AP_TO_WLAN_REFCLK_N
CXT_A/JTAG_TDI CXT_B/JTAG_TDO
63 3
AOP_TO_WLAN_CONTEXT_A AOP_TO_WLAN_CONTEXT_B
SR_VLX
33
SR_LVX
VIN_LDO
35
VIN_LDO
52 2G_ANT_CORE0 5 2G_ANT_CORE1
50_WLAN_G_0 50_LAT_WLAN_G_1
59 5G_ANT_CORE0 66 5G_ANT_CORE1
50_WLAN_A_0 50_LAT_WLAN_A_1
UART_BT_TO_AP_RXD UART_AP_TO_BT_RTS_L UART_BT_TO_AP_CTS_L
I2S_AP_TO_BT_LRCLK I2S_BT_TO_AP_DIN I2S_AP_TO_BT_DOUT
2
2 1
AOP_TO_WLAN_CONTEXT_A TDI
AOP_TO_WLAN_CONTEXT_B TDO
1
PP
2 1
PP7601_RF P2MM-NSM OMIT SM 1
PP
2 1
2 1
2 1
2 1
A
2
2
2
2 1
2 1
UART_WLAN_TO_AP_RXD
UART_AP_TO_WLAN_TXD
PP7603_RF P2MM-NSM OMIT SM 1
PP
2 1
PP7604_RF P2MM-NSM OMIT SM 1
PP
2 1
PP7605_RF P2MM-NSM OMIT SM 1
JTAG_WLAN_TCK
PP
2 1
PP7606_RF P2MM-NSM OMIT SM 1
JTAG_WLAN_TMS
JTAG_WLAN_TRST_L
AP_TO_WLAN_DEVICE_WAKE
BT_TO_PMU_HOST_WAKE
PP
2 1
PP7607_RF P2MM-NSM OMIT SM 1
PP
2
PP7608_RF P2MM-NSM OMIT SM 1
PP
2 1
PP7609_RF P2MM-NSM OMIT SM 1
PP
2 1
PMUGPIO_TO_WLAN_CLK32K
PP7610_RF P2MM-NSM OMIT SM 1
1
90_PCIE_AP_TO_WLAN_REFCLK_P
90_PCIE_AP_TO_WLAN_REFCLK_N
90_PCIE_AP_TO_WLAN_TXD_P
90_PCIE_AP_TO_WLAN_TXD_N
PCIE_AP_TO_WLAN_RESET_L
IN OUT
53 54
55
IN
53 54
IN
53 54
OUT
53 54
IN
53 54
OUT
53 54
BI IN
55
53 54 53 54
55
IN
53 54
55
IN
53 54
55
OUT
53 54
OUT
53 54
IN
53 54
55
IN
53 54
55
IN
53 54
55
IN
55
C7604_RF 7.5UF L7600_RF 2.2UH-20%-0.68A-0.25OHM 1
2
0806
SR_LVX_1
1
20% 4V CERM 0402
2
C7603_RF 100PF 5% 16V NP0-C0G 01005 WLAN
4
3
74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 94 95 96 97 98 99 100 101 102 103 104 105
SYM 2 OF 2
GND
THRM_PAD
THRM_PAD
D
C
B
PART NUMBER
ALTERNATE FOR PART NUMBER
BOM OPTION
REF DES
COMMENTS:
339S00201
339S00199
ALTERNATE
WLAN_RF
ALT WIFI/BT MODULE
PP
1
PP
PP7613_RF P2MM-NSM OMIT SM 1
PP
PP7614_RF P2MM-NSM OMIT SM 1
PP
PP7615_RF P2MM-NSM OMIT SM 1
PP
2 1
PP7616_RF P2MM-NSM OMIT SM 1
PP
2 1
PP
2 1
PP7618_RF P2MM-NSM OMIT SM 1
PP
2 1
PP7619_RF P2MM-NSM OMIT SM 1
PMU_TO_BT_REG_ON
55 55
LGA
PP7612_RF P2MM-NSM OMIT SM
1
PMU_TO_WLAN_REG_ON
53 54 53 54
LBEE5W11GJ-943
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163
TABLE_ALT_ITEM
PP7617_RF P2MM-NSM OMIT SM
JTAG_WLAN_SEL
OUT
WLAN_RF
TABLE_ALT_HEAD
PP
PP7611_RF P2MM-NSM OMIT SM
WLAN_TO_PMU_HOST_WAKE
5% 16V NP0-C0G 01005 WLAN
55
1
2 1
2
C7607_RF 27PF
BT_DEV_WAKE
B
PP7600_RF P2MM-NSM OMIT SM
10% 6.3V X5R 01005 WLAN
1
9 FAST_UART_RTS_OUT
54
1
2
C7606_RF 0.01UF
1
LGA
IN
56
1
C7602_RF 10UF
VBAT_RF_VCC 30 VBAT_RF_VCC 31
1
VBAT_VCC 28 VBAT_VCC 29
2 1
VDDIO_1P8V 15
D
1 4 6 18 21 24 27 32 34 36 45 46 47 48 49 50 51 53 57 58 60 65 67 68 69 70 71 72 73
PP
2 1
PP7620_RF P2MM-NSM OMIT SM 1
UART_AP_TO_BT_TXD
PP
PP7621_RF P2MM-NSM OMIT SM 1
UART_BT_TO_AP_RXD
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare
PP
PP7622_RF P2MM-NSM OMIT SM 1
UART_AP_TO_BT_RTS_L
DRAWING NUMBER
Apple Inc.
PP
1
PP
PP7624_RF P2MM-NSM OMIT SM 1
AP_TO_BT_WAKE
REVISION
R
PP7623_RF P2MM-NSM OMIT SM
UART_BT_TO_AP_CTS_L
051-00419
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
PP
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
WIFI UPPER ANTENNA FEEDS
D
D
OMIT_TABLE
R7704_RF
2.4NH+/-0.1NH-0.370A 55
BI
1
50_WLAN_G_0 1
2 01005
50_UAT_WLAN_2G_EAST 1
C7707_RF 0.2PF
+/-0.1PF 16V 01005 WLAN_UP_RFFE NOSTUFF
53 54
BI
2GHZ UAT
C7708_RF 0.6PF +/-0.05PF
16V 2 CERM
2 NP0-C0G
01005 WLAN_UP_RFFE OMIT_TABLE
OMIT_TABLE 55
BI
R7703_RF 0.00 2 1
50_WLAN_A_0 1
C7705_RF 0.2PF +/-0.1PF
0% 1/32W MF 01005
50_LAT_WLAN_5G_EAST 1
BI
53 54
C7706_RF 0.2PF
5GHZ UAT
+/-0.1PF
16V 2 NP0-C0G
2 16V NP0-C0G
01005 WLAN_UP_RFFE OMIT
01005 WLAN_UP_RFFE OMIT
C
C
JUAT2_RF MM8830-2600B
53
BI
50_UAT_WLAN_5G_WEST
0% 1/32W MF 1 C7729_RF 01005
50_UAT_WLAN_5G_BPF
2
54
1
0.2PF
+/-0.1PF
2 16V NP0-C0G
01005 WLAN_UP_RFFE OMIT
LFB185G53CGZE200 1 3
2
C7711_RF 0.2PF
+/-0.1PF 16V NP0-C0G 01005 WLAN_UP_RFFE OMIT
OMIT_TABLE
R7702_RF 0.00 2 1
50_UAT2_BPF 1
C7709_RF 0.2PF +/-0.1PF
2 16V NP0-C0G
01005 WLAN_UP_RFFE OMIT
0% 1/32W MF 01005
50_UAT2_TEST 1
C7710_RF 0.2PF
+/-0.1PF 16V 01005 WLAN_UP_RFFE OMIT
2 NP0-C0G
1
C
R
2
50_UAT2_M
1
GND 3
OMIT_TABLE
R7711_RF 0.00 2 1
F-RT-SM
W5BPF_RF 5.15-5.85GHZ-1.2DB
UP_RFFE
B
B
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2
1
REV
ECN
8
0006400877
CK APPD
DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
ENGINEERING RELEASED
D
D
STOCKHOLM_MLB JUNE 9, 2016 C
58
53
58
53 IN
58
53 IN
58
53 OUT
58
53 IN
58
53 IN
58
53 OUT
58
53 IN
58
53 IN
58
53 OUT
58
53 IN
58
53 OUT
PP_VDD_MAIN PP1V8_SDRAM PMU_TO_NFC_EN NFC_TO_PMU_HOST_WAKE AP_TO_NFC_DEV_WAKE AP_TO_NFC_FW_DWLD_REQ NFC_TO_BB_CLK_REQ BB_TO_NFC_CLK UART_AP_TO_NFC_TXD UART_NFC_TO_AP_RXD UART_AP_TO_NFC_RTS_L UART_NFC_TO_AP_CTS_L
58
53 IN
58
53 IN
58
53 IN
NFC_SWP SE2_READY SE2_PWR_REQ SE2_PRESENT
58
53 OUT
NFC_SWP_MUX
58
53 OUT
ICEFALL_LDO_ENABLE
2
C
IO
ALTERNATES PART NUMBER
B
ALTERNATE FOR PART NUMBER
132S0436
REFERENCE DESIGNATOR(S)
132S0400
C7504_RF
BOM OPTIONS PART#
QTY
DESCRIPTION
DESCRIPTION
BOM OPTION
B
?
0.22UF 20% 6.3V 01005
TABLE_5_HEAD
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_ITEM
131S0883
1
220PF, 0201 2% 50V
C7514_RF
D101
131S00055
1
22PF, 0201 2% 50V
C7512_RF
D101
131S00117
1
120PF, 0201 2% 50V
C7518_RF
D101
TABLE_5_ITEM
131S00081
1
270PF, 0201 2% 25V
C7514_RF
D111
131S00118
1
180PF, 0201 2% 50V
C7518_RF
D111
131S00033
1
680PF, 0201 2% 50V
C7516_RF
D111
131S00081
1
270PF, 0201 2% 25V
C7514_RF
D11_JP
131S0731
1
100PF, 0201 2% 50V
C7518_RF
D11_JP
131S00033
1
680PF, 0201 2% 50V
C7516_RF
D11_JP
131S00081
1
270PF, 0201 2% 25V
C7514_RF
D11_ROW
131S00118
1
180PF, 0201 2% 50V
C7518_RF
D11_ROW
131S00033
1
680PF, 0201 2% 50V
C7516_RF
D11_ROW
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
131S00026
1
820PF, 0201 2% 50V
C7516_RF
D101
131S0883
1
220PF, 0201 2% 50V
C7514_RF
D10_JP
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
131S00055
1
22PF, 0201 2% 50V
C7512_RF
D10_JP
131S00019
1
150PF, 0201 2% 50V
C7518_RF
D10_JP
131S0825
1
560PF, 0201 2% 50V
C7516_RF
D10_JP
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
131S0883
1
220PF, 0201 2% 50V
C7514_RF
D10_ROW
131S00055
1
22PF, 0201 2% 50V
C7512_RF
D10_ROW
131S00117
1
120PF, 0201 2% 50V
C7518_RF
D10_ROW
131S00026
1
820PF, 0201 2% 50V
C7516_RF
D10_ROW
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
5
4
3
STOCKHOLM
2
5V BOOSTER 2
D
NFC CONTROLLER
NFBST_RF WLCSP
A3 VIN
PP_VDD_MAIN_NFC 1 C7521_RF
1 C7511_RF
100PF 5% 16V 2 NP0-C0G 01005 NFC
15UF 20% 6.3V 2 X5R 0402-1 NFC
L7502_RF 1.8UH-0.7A 1
0603 NFC
1
2 NFC_BOOST_SW
B1 SW B2 SW
NFC_BOOST_EN
B3 EN
2
FAN48614BUC50X
6
VOUT A1 VOUT A2
C3 AGND
7
C1 PGND C2 PGND
8
VDD_NFC_5V
2
1 C7517_RF
1 C7522_RF
15UF 20% 6.3V 2 X5R 0402-1 NFC
100PF 5% 16V 2 NP0-C0G 01005 NFC
D
NFC
VDD_NFC_5V
2
1 C7520_RF
VDD_NFC_DVDD
VDD_NFC_ESE VOLTAGE=1.80V
58
57 53
OUT
57
53
57
53
IN
57
53
OUT
57
IN
53
IN
58
57 53
IN
58
57 53
OUT
58
57 53
IN
58
57 53
OUT
58
57 53
IN 2
D1 A5 B2 A2 A3 C1 B1 D2 A1 E1
NFC_TO_PMU_HOST_WAKE SE2_PRESENT AP_TO_NFC_FW_DWLD_REQ NFC_TO_BB_CLK_REQ BB_TO_NFC_CLK UART_AP_TO_NFC_TXD UART_NFC_TO_AP_RXD UART_AP_TO_NFC_RTS_L UART_NFC_TO_AP_CTS_L PMU_TO_NFC_EN VDD_NFC_ESE
NC 57
53
IN
57
53
OUT
57
53
OUT
SE2_READY ICEFALL_LDO_ENABLE NFC_SWP_MUX
IRQ SVDD_REQ DWL CLK_REQ NFC_CLK_XTAL1 RX TX CTS RTS VEN
F1 A4
IC00 SIM_SWIO GPIO0 A7 IC01 A6 TX_PWR_REQ D5
ESE_DWPM_DBG G7 ESE_DWPS_DBG G6
SMX_RST* SMX_CLK ESE_IO1 SE2_BUSY IC2 EXT_MUX
C3 XTAL2
NFC FRONT END C7507_RF 1000PF
1UF 20% 10V 2 X5R 0201 NFC
2
1
NFC_RXP
2
1
NFC_RXP_CAP
R7508_RF 560
2
1% 1/20W MF 201 NFC
2% 25V C0G-NP0 0201 NFC L7500_RF 160NH-10%-0.48A-0.33OHM
NFC_RF PN67VEU3-B001D004 UFLGA
E2 VSS
NC
E3 E4 F4 B3 B4 E6
2.2UF 20% 6.3V 2 X5R-CERM 0201-1
2
NC NFC_SWP NFC_TEST_OUT
2
NC NFC_BOOST_EN
2
NFC_RXP NFC_RXN
TX1 G3 TX2 G5
NFC_TXP NFC_TXN
VMID F7 SE2_ENABLE F2 SE2_SVDD_IN G1
B
0402 NFC
53 57
BI
1 C7509_RF
2 2 2
IN
53 57
58
2
1
NFC_TXN
2
0402 NFC
NFC_VMID SE2_PWR_REQ PP1V8_SDRAM
180 PHASE SHIFT INTRODUCED BY BALUN DONE FOR BEST ROUTING
L7501_RF 160NH-10%-0.48A-0.33OHM
2
AP_TO_NFC_DEV_WAKE
C
NFC_BALP 680PF 2% 25V 2 C0G-NP0 0201 NFC
OUT
53 57
58
IN
53 57
58
C7508_RF 1000PF 1 C7503_RF
2
1
NFC_RXN
0.1UF 20% 6.3V 2 X5R-CERM 01005 NFC
2 1
2
NC NC
RX+ F6 RX- F5
WKUP_REQ E5
1
NFC_TXP
BAL0 2 GND 1
C
0.22UF 20% 6.3V 2 X5R 01005 NFC
1 C7505_RF
1 C7527_RF
2.2UF 20% 6.3V 2 X5R-CERM 0201-1
3 BAL1 4 UNBAL
1UF 20% 10V 2 X5R 0201 NFC
1 C7504_RF
1 C7526_RF
2.2UF 20% 6.3V 2 X5R-CERM 0201-1
ATB161006F-20011 SM
1UF 20% 10V 2 X5R 0201 NFC
2
1 C7506_RF
BALUN_RF
1 C7502_RF
SVDD B7 ESE_VDD C5
1 C7500_RF
AVDD D7
0% 1/32W MF 01005 NFC
2
G4 TVSS C2 PVSS
2
VDD_NFC_AVDD VOLTAGE=1.80V
VUP G2 TVDD E7
1
VDD_NFC_AVDD
PP_VDD_MAIN_NFC
B6 DVSS C4 DVSS
2
R7502_RF 0.00
VDD_NFC_TVDD
C6 C7 B5 D3
2
PP1V8_SDRAM
VDD VBAT SIM_PMU_VCC PVDD
2 1
D4 AVSS D6 AVSS F3 AVSS
1UF 20% 10V 2 X5R 0201 NFC
2
NFC_BALN
2
1
R7509_RF 560
2
1% 1/20W MF 201 NFC
C7512_RF 22PF 1
TP7500_RF 1
NFC_ANT
2% 50V C0G 0201 OMIT_TABLE
680PF 2% 25V 2 C0G-NP0 0201 NFC
2% 25V C0G-NP0 0201 NFC
1
NFC_ANT_MATCH
1 C7510_RF
NFC_RXN_CAP
C7514_RF 220PF
1 C7515_RF
1 C7516_RF
1 C7518_RF
1000PF 2% 25V 2 C0G-NP0 0201 NFC
820PF 2% 25V 2 C0G-NP0 0201 NFC OMIT_TABLE
120PF 2% 50V 2 NP0-C0G 0201 OMIT_TABLE
2
2% 50V C0G-CERM 0201 OMIT
2
A
SM-TP1P25-TOP OMIT
TP7505_RF 1
NFC_TEST_OUT
TP-P55 NFC OMIT
SE2_PWR_REQ
A
B
1
R7599_RF 1.00K 5% 1/32W MF 2 01005
NFC LOAD SWITCH 2 1
2 1
A
2 1
UART_AP_TO_NFC_TXD
UART_NFC_TO_AP_RXD
OMIT PP7504_RF P2MM-NSM SM 1 PP
UART_AP_TO_NFC_RTS_L
OMIT PP7505_RF P2MM-NSM SM 1 PP
UART_NFC_TO_AP_CTS_L
OMIT PP7506_RF P2MM-NSM SM 1 PP
2 1
2 1
2 1
NFC_TO_PMU_HOST_WAKE
PP7507_RF P2MM-NSM SM 1 PP
PMU_TO_NFC_EN
OMIT PP7508_RF P2MM-NSM SM 1 PP
AP_TO_NFC_DEV_WAKE
OMIT PP7509_RF P2MM-NSM SM 1 PP
2 1
PP_VDD_MAIN
2 1
PP1V8_SDRAM
B2 ON
PP_VDD_MAIN_NFC
2
GND B1
2 1
PP7503_RF P2MM-NSM SM 1 PP
NFCSW_RF FPF1204UCX A2 VIN WLCSP-COMBOVOUT A1
OMIT 2 1
PP_VDD_MAIN
1
R7520_RF 0.00
2
PP_VDD_MAIN_NFC
2
1% 1/20W MF 0201 NOSTUFF
OMIT
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
1
REV
ECN
DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
8
0006400877
ENGINEERING RELEASED
2016-06-14
D10 RADIO_MLB_FF FEB 19, 2016
D
D
D10 NORTH-SOUTH METROCIRC 339S00086
D10 EAST-WEST METROCIRC 339S00110
C
EAST MLB
C
WEST MLB
MCEW_RF
FLTPSSL-382E
UPPER MLB 59
BI 1
53
IN
LOWER MLB
MCNS_RF
FLTPSSL-381E 6 2 4
50_UAT1_EAST 50_LAT_WLAN_NORTH 50_UUAT_LB_MLB_NORTH
1 3 5 8 10 12 21 22 23 24 25 26 27 28 29 30 31 32
B
SIGNAL1-U SIGNAL2-U SIGNAL3-U
SM
7 11 9
SIGNAL1-L SIGNAL2-L SIGNAL3-L
50_UAT_MB_HB_SOUTH 50_LAT_WLAN_SOUTH 50_UAT_LB_MLB_SOUTH
IO
INOUT IO
59 OUT
53
INOUT BI
3 1 5
50_UAT_WLAN_2G_EAST 50_LAT_WLAN_5G_EAST 50_UAT1_EAST
2 4 6 8 9 12 21 22
1 IO
33 34 35 36 37 38
GND
SIGNAL1-E SIGNAL2-E SIGNAL3-E
SM
SIGNAL1-W SIGNAL2-W SIGNAL3-W
GND GND
GND TRUE I11
7 10 11
50_UAT_WLAN_2G_WEST 50_UAT_WLAN_5G_WEST 50_UAT1_WEST
1 IO
INOUT
INOUT
IO
INOUT
23 24 25 26 27 28
INOUT
GND TRUE I12
GND
R6711_RF 3.9PF
1
1
50_UAT_WLAN_2G_WEST
2
50_UAT_WLAN_2G_WEST_PLEXER
+/-0.1PF 16V NP0-C0G 01005-1
INOUT
B
1
UP_RFFE OMIT
COAX
WIFI LOWER ANTENNA FEED
IO
INOUT
C6729_RF
7.5NH+/-3%-0.2A 01005
UP_RFFE OMIT 2
W2BPF_RF WLAN-BT-LTE 885118 LGA
TRUE
50_LAT_WLAN_G_1
0% 1/32W MF 01005 WLAN_RFFE OMIT
1
50_WLAN_G_1_BPF
1 INPUT
OUTPUT 4
C7701_RF 3.6PF
L7701_RF 9.1NH-3%-0.17A-1.7OHM
1
50_WLAN_G_1_M
GND
1
2 3 5
IO
L7700_RF 1 0.00 1 2
WLAN_RFFE
W25DI_RF LFD212G45MP2E013 4 P1
P3 2
2
50_LAT_WLAN_A_1 1
A
C7700_RF 0.2PF +/-0.1PF
16V 2 NP0-C0G
0% 1/32W MF 01005 WLAN_RFFE OMIT
50_LAT_WLAN_M 1
GND 1 3 5
IO
2
6 P2
2
R7700_RF 0.00 2 1
F-ST-SM
LGA
01005 WLAN_RFFE
01005 WLAN_RFFE
2
1
L7703_RF 4.0NH-+/-0.1NH-0.27A
L7702_RF 9.1NH-3%-0.17A-1.7OHM
JLAT3_RF MM7829-2700
50_WLAN_G_1_DPLX
+/-0.1PF 16V NP0-C0G 01005 WLAN_RFFE
1
01005 OMIT
2
C7703_RF 0.2PF +/-0.1PF
WLAN_RFFE
2 16V NP0-C0G
01005 WLAN_RFFE OMIT
50_WLAN_A_1_DPLX
R7701_RF 0.00 2 1 0% 1/32W MF 01005 WLAN_RFFE OMIT
50_LAT_WLAN_NORTH 1
1
1
50_LAT_WLAN_SOUTH
C7704_RF 0.2PF
3
+/-0.1PF 16V 01005 WLAN_RFFE OMIT
2 NP0-C0G
THROUGH METROCIRC
1
C7702_RF 4.3NH-3%-0.270A
01005 WLAN_RFFE OMIT
1
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
01005 WLAN_RFFE OMIT
spare DRAWING NUMBER
2
Apple Inc.
051-00419
REVISION
R
ADD REV ID FOR D10/D11 HERE 8
7
6
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
1
C5904_RF 120PF
10% 10V 2 CER-X7R 01005
D
150OHM-25%-200MA-0.7DCR BB_TO_UAT_DATA
2
53
1
1
PP1V8_SDRAM
IN
2
7
5% 2 16V NP0-C0G 01005 UAT
FL6701_RF 60
53
IO
1
BB_TO_UAT_DATA
2
0% 1/32W MF 01005
BB_TO_LAT_ANT_SCLK
IN 53
60
01005
8
1
2
27PF
3
4
5
6
2 16V NP0-C0G
9
UAT_TUNER_RFFE_DATA_FILT
5%
01005 UAT
10
2
2
BB_TO_UAT_SCLK
IN 53
60
0% 1/32W MF 01005
27PF
5% 16V 2 NP0-C0G 01005 UAT
2 16V NP0-C0G-CERM 01005
0.00
1 1 C6703_RF
27PF
C5908_RF
FL6702_RF
UAT_TUNER_RFFE_CLK_FILT
1 C6702_RF
33PF 5%
IN
PP3V0_TRISTAR_UAT_TUNER_B2B_FILT
2
1 C6705_RF
27PF
0.00
D
PP3V0_TRISTAR_ANT_PROX
1
505066-0620
1 C6701_RF
2% 2 6.3V NP0-C0G 01005
53
FL6703_RF
150OHM-25%-200MA-0.7DCR
F-ST-SM
68PF
1
TUNFX_RF
VDD_TUNER_RFFE_VIO_1V8_FILT
01005
C5905_RF
PLEASE CONTACT ANTENNA (MATT MOW) FOR ANY COMPONENT CHANGE.
UAT TUNER FLEX
FL6700_RF
IN
1
BB_TO_UAT_SCLK
2
53
2
5% 16V NP0-C0G 01005 UAT
BB_TO_LAT_ANT_DATA 1
C5909_RF
33PF 5%
C
2 16V NP0-C0G-CERM 01005
C
LB/MLB/GNSS/MB/HB STANDOFF PP3V0_TRISTAR_ANT_PROX 2
ALT UAT1 GND
C6720_RF 0.01UF
50_UAT1_TUNER
2.2NH+/-0.1NH-0.6A 50_UAT1_TUNER_M
4
1% 1/20W MF 0201 UP_RFFE
1
0201-1
1
5.6NH+/-3%-0.4A
1
0201
C6700_RF
1 6
USPDT2_RF
560NH-5%-2.80OHM
1
UP_RFFE
PP3V0_TRISTAR_ANT_PROX 2
C8007_RF 0.01UF
10% 2 6.3V X5R 01005
9.1NH+/-0.3%-0.3A 0201
UP_RFFE
B
VDD
L8008_RF
USPDT_RF RF1341
GNDA RFGND
5% 2 16V NP0-C0G-CERM 01005
2 0201
2
C6721_RF 33PF
1
USPDT_VDD
1
L6707_RF
1.2PF
+/-0.05PF 2 25V C0G-CERM 0201
2
2 50_UAT1_FEED
2% 25V C0H-CERM 0201 UP_RFFE
UP_RFFE
L8007_RF
SUAT1_RF STDOFF-2.56OD1.4ID.99H-SM
2
1
RF1
5
B
3 CB
BB_BUFFER_GPO2
IN
2 50_UAT1_NOTCH
C6714_RF
USPDT2_RF RF1341 53
1
1
VDD
WLCSP
C6716_RF 18PF
4
IO
C6704_RF 0.00 2 1
R6706_RF
53
IN
3 CB
BB_BUFFER_GPO1 1
C8005_RF 33PF
5% 16V 2 NP0-C0G-CERM 01005
WLCSP
RF1
3.0NH+/-0.1NH-0.6A 1 6
USPDT_RF
1
2
DC_BLOCK
0201
GNDA RFGND 2
10% 2 6.3V X5R 01005
5
1
1
C8008_RF
2
2% 25V C0H-CERM 0201
18PF
1
ALT_GND
C7731_RF IO
2
1
A
C6734_RF 100PF
5% 2 16V NP0-C0G 01005 UP_RFFE
1
C6735_RF 18PF
5% 2 16V CERM 01005 UP_RFFE
1
C6730_RF 220PF
5% 2 6.3V CERM 01005 UP_RFFE
1
C6731_RF 56PF
5% 2 16V NP0-C0G 01005 UP_RFFE
C6732_RF 4.0PF
+/-0.1PF 2 16V NP0-C0G 01005 UP_RFFE
2
1
1
C6733_RF 220PF
5% 2 6.3V CERM 01005 UP_RFFE
1
L8009_RF 9.1NH-0.4A
L6710_RF
03015
2
UP_RFFE
1
2
CHASSIS_GND
PP8000_RF P2MM-NSM SM 1 PP
NOSTUFF
C7730_RF
L7709_RF
0201
0201
1.8NH+/-0.1NH-0.8A
NOSTUFF
OMIT_TABLE
1
50_UAT2_FEED
+/-0.05PF 25V C0G-CERM 0201
CHASSIS_GND 1
1
1
SUAT2_RF STDOFF-2.56OD1.4ID.99H-SM
1.2PF
50_UAT2_M
3.0NH+/-0.1NH-0.6A SYNC_MASTER=Sync
4.3NH+/-3%-0.5A
2
0201
2
SGND_RF STDOFF-2.56OD1.4ID.99H-SM
SYNC_DATE=05/17/2016
PAGE TITLE
spare
1 2
DRAWING NUMBER
Apple Inc.
UP_RFFE
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
A
SM-TP1P25-TOP OMIT
5G WIFI STANDOFF
UAT GROUND RING
TP8000_RF
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
BOM LIST TABLE_5_HEAD
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION TABLE_5_ITEM
152S1860
1
LONGER PATH INDUCTOR
L8009_RF
CRITICAL
LMBRF
152S0570
1
3.0 NH,03015
L8009_RF
CRITICAL
NOLMBRF
D
D
C
C
B
B
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
81
6
5
4
3
2
1
ICEFALL, SIM, DEBUG_CONN
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
REV
ECN
CK APPD
DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
MAV16 RADIO_MLB
D
C
LAST_MODIFICATION=Wed Jun
8
SYNC <SYNC_MASTER1>
<SYNC_DATE1>
<SYNC_MASTER2>
<SYNC_DATE2>
<SYNC_MASTER3>
<SYNC_DATE3>
<SYNC_MASTER4>
<SYNC_DATE4>
<SYNC_MASTER5>
<SYNC_DATE5>
<SYNC_MASTER6>
<SYNC_DATE6>
<SYNC_MASTER7>
<SYNC_DATE7>
<SYNC_MASTER8>
<SYNC_DATE8>
<SYNC_MASTER9>
<SYNC_DATE9>
<SYNC_MASTER10>
<SYNC_DATE10>
<SYNC_MASTER11>
<SYNC_DATE11>
<SYNC_MASTER12>
<SYNC_DATE12>
<SYNC_MASTER13>
<SYNC_DATE13>
<SYNC_MASTER14>
<SYNC_DATE14>
<SYNC_MASTER15>
<SYNC_DATE15>
<SYNC_MASTER16>
<SYNC_DATE16>
<SYNC_MASTER17> <SYNC_MASTER18>
<SYNC_DATE18>
<SYNC_MASTER19> <SYNC_MASTER20>
<SYNC_DATE20>
<CSA_PAGE21>
<SYNC_MASTER21>
<SYNC_DATE21> <SYNC_DATE22>
<CSA_PAGE23>
<SYNC_MASTER23>
<SYNC_DATE23>
<CSA_PAGE24>
<SYNC_MASTER24>
<SYNC_DATE24>
<CSA_PAGE25>
<SYNC_MASTER25>
<SYNC_DATE25>
<CSA_PAGE26>
<SYNC_MASTER26>
<SYNC_DATE26>
<CSA_PAGE27>
<SYNC_MASTER27>
<SYNC_DATE27>
<SYNC_MASTER28>
<SYNC_DATE28>
<CSA_PAGE30>
65 OUT
81
78
64 53 IN
81
64 53 IN
78
68 53 OUT
78
68 53 OUT
78
53 IN
68 53 IN
78
64
53 IN
68
53 IN
78
67 53 IN 67 53 IN 67
53 IN
67
53 IN
67
53 OUT 53
68
64 53 IN
78
68 53 OUT
68
<SYNC_DATE29>
<SYNC_MASTER30>
<SYNC_DATE30>
IO
53 IN
68 53 OUT
SCH: 951-00964 BOM: 939-00826
68
53 IN
68
53 IN
68
53 OUT
I2S_BB_TO_AP_DIN
78 68 53 IN
81
78 68 53 OUT
UART_WLAN_TO_BB_COEX
81 53
IN
Y5501_RF
19P2 MHZ XTAL
197S0598
197S0593
ALTERNATE
Y5501_RF
19P2 MHZ XTAL
138S00101
138S00095
ALTERNATE
ALL
TRANSITION CAP
335S00013
335S0894
ALTERNATE
EPROM_RF
IC EEPROM
353S00253
353S00321
ALTERNATE
SWPMX_RF
IC SWITCH SPDT
155S00235
155S00234
ALTERNATE
UPPDI_RF
NOLMBRF
IO
81 78 53
IN
81 78 53
IN
81 78 53
IN
64 53 IN 64 53 OUT
IN
NFC
NFC_SWP NFC_SWP_MUX
SE2_READY AP_TO_ICEFALL_FW_DWLD_REQ SE2_PWR_REQ NFC_TO_BB_CLK_REQ BB_TO_NFC_CLK SE2_PRESENT ICEFALL_LDO_ENABLE
B
TUNER IO
BB_TO_UAT_SCLK BB_TO_UAT_DATA
IO
50_UAT1_TUNER
68
53 OUT
68
53 OUT
OUT IO
ALTERNATE
IO
14
C
MAKE_BASE=TRUE BB_TO_UAT_SCLK BB_TO_UAT_DATA MAKE_BASE=TRUE
BB_BUFFER_GPO1 BB_BUFFER_GPO2
7 14 7 14
DOCK MAKE_BASE=TRUE BB_TO_LAT_ANT_SCLK BB_TO_LAT_ANT_DATA MAKE_BASE=TRUE
BB_TO_LAT_ANT_SCLK BB_TO_LAT_ANT_DATA
TABLE_ALT_ITEM
197S0593
IO
12
WLAN
COMMENTS:
197S0565
IO
12
AUDIO
TABLE_ALT_HEAD
REF DES
14
UART_BB_TO_AOP_RXD
I2S_BB_TO_AP_BCLK I2S_BB_TO_AP_LRCLK I2S_AP_TO_BB_DOUT
81 53 OUT
ALTERNATES BOM OPTION
50_UAT_WLAN_2G_WEST_PLEXER 50_UAT1_WEST 50_UAT_LB_MLB_SOUTH 50_UAT_MB_HB_SOUTH 50_UUAT_LB_MLB_NORTH
IO
AOP
15
ALTERNATE FOR PART NUMBER
15
UART_AOP_TO_BB_TXD
OUT
PART NUMBER
ANTENNA
PCIE_AP_TO_BB_RESET_L PCIE_BB_BI_AP_CLKREQ_L BB_TO_PMU_PCIE_HOST_WAKE_L
53 IN
81 78 53
IO
90_PCIE_AP_TO_BB_REFCLK_P 90_PCIE_AP_TO_BB_REFCLK_N 90_PCIE_AP_TO_BB_TXD_P 90_PCIE_AP_TO_BB_TXD_N 90_PCIE_BB_TO_AP_RXD_P 90_PCIE_BB_TO_AP_RXD_N
81
78
IO
BB_TO_STROBE_DRIVER_GSM_BURST_IND AP_TO_BB_MESA_ON AP_TO_BB_TIME_MARK
68
81 78 53 OUT
B
20 17 6 20 17 6
AP_TO_BBPMU_RADIO_ON_L PMU_TO_BBPMU_RESET_L AP_TO_BB_RESET_L BB_TO_AP_RESET_DETECT_L
UART_BB_TO_WLAN_COEX
78
PMU_TO_BB_USB_VBUS_DETECT 90_USB_BB_DATA_P 90_USB_BB_DATA_N
PCIE
78
67
IO
78 64 53 IN
AP_TO_BB_COREDUMP LCM_TO_MANY_BSYNC AP_TO_BB_IPC_GPIO1
68 53 IN
SWD_AP_TO_MANY_SWCLK SWD_AOP_BI_BB_SWDIO
67 53 IN 20 6
81
78 64 53 IN
78
<SYNC_MASTER29>
81
BB CONTROL
7
<SYNC_MASTER22>
DEBUG
BBPMU_TO_PMU_AMUX1 BBPMU_TO_PMU_AMUX2 BBPMU_TO_PMU_AMUX3
65 OUT
4 20
MAKE_BASE=TRUE
AMUX
68
<CSA_PAGE20>
<CSA_PAGE29>
68 53 IN
65 OUT
<SYNC_DATE17>
PP_VDD_BOOST
PP_VDD_BOOST PP1V8_SDRAM
IN
81
D
PP_VDD_MAIN
77 65 64 53 IN
DATE
<SYNC_DATE19>
<CSA_PAGE28>
2016-06-14
POWER 81
<CSA_PAGE22>
ENGINEERING RELEASED
AP CONNECTIONS
8 12:54:09 2016
PAGE CSA CONTENTS <CSA_PAGE1> 62 page1 page1 <CSA_PAGE2> 63 BOM_OMIT_TABLE <CSA_PAGE3> PMU: CONTROL AND CLOCKS 64 <CSA_PAGE4> 65 PMU: SWITCHERS AND LDOS <CSA_PAGE5> 66 BASEBAND: POWER2 <CSA_PAGE6> 67 BASEBAND: CONTROL <CSA_PAGE7> 68 BASEBAND GPIOS <CSA_PAGE8> TRANSCEIVER0/1: POWER 69 <CSA_PAGE9> TRANSCEIVER0/1: TX PORTS 70 <CSA_PAGE10> 71 TRANSCEIVER0/1: PRX PORTS <CSA_PAGE11> RECEIVE MATCHING 72 <CSA_PAGE12> 73 LOWER ANTENNA & COUPLERS <CSA_PAGE13> 74 DIVERSITY RECEIVE ASM'S <CSA_PAGE14> 75 DIVERSITY RECEIVE LNA'S <CSA_PAGE15> 76 UPPER ANTENNA FEEDS <CSA_PAGE16> 77 PMU: ET MODULATOR <CSA_PAGE17> 78 TEST POINTS & BOOT CONFIG <CSA_PAGE18> TDD TRANSMIT 79 <CSA_PAGE19> FDD TRANSMIT 80
0006400877
7 17 7 17
TABLE_ALT_ITEM
68
53 OUT
BB_TO_LAT_GPO1
68
53 OUT
BB_TO_LAT_GPO2
68
53 OUT
BB_TO_LAT_GPO3
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
A
page1
SYNC_MASTER=Sync
ALL:C5616_RF-C5618_RF,C5632_RF-C5634_RF
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
BOM OPTIONS: LMBRF:
NOLMBRF: TABLE_5_HEAD
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
TABLE_5_ITEM
D
353S00723
1
MLB PAD
MLBPA_RF
CRITICAL
LMBRF
117S0002
1
MLB PAD LAT OUTPUT MATCH
R7105_RF
CRITICAL
LMBRF
152S2042
1
MLB PAD UAT OUTPUT MATCH
R7106_RF
CRITICAL
LMBRF
353S00627
1
MLB LNA
MLBLN_RF
CRITICAL
LMBRF
117S0002
1
MLB LNA OUTPUT MATCH
R6710_RF
CRITICAL
LMBRF
155S00139
1
PENTAPLEXER
PPLXR_RF
CRITICAL
LMBRF
118S0643
1
RES,MF,4.99K OHM,01005
R7506_RF
CRITICAL
LMBRF
155S00193
1
FLTR,DIPLEXER,LB-MB-HB,DPX,SHIELD,0805
UATDI_RF
CRITICAL
LMBRF
155S00158
1
FLTR,DIPLEXER,LB-MB/HB,MIRROR,0805
UPPDI_RF
CRITICAL
LMBRF
337S00284
1
IC,SECURE ELEMENT,BCM20211,WLBGA25
SE2_RF
CRITICAL
LMBRF
138S0739
1
CAP,1UF,0201
C7201_RF
CRITICAL
LMBRF
138S0739
1
CAP,1UF,0201
C7528_RF
CRITICAL
LMBRF
132S0316
1
CAP,0.1UF,01005
C7501_RF
CRITICAL
LMBRF
138S0739
1
CAP,1UF,0201
C7523_RF
CRITICAL
LMBRF
138S0739
1
CAP,1UF,0201
C7524_RF
CRITICAL
LMBRF
138S00032
1
CAP,2.2UF,0201
C7529_RF
CRITICAL
LMBRF
138S00032
1
CAP,2.2UF,0201
C7530_RF
CRITICAL
LMBRF
131S0217
1
CAP,100PF,01005
C7531_RF
CRITICAL
LMBRF
118S0627
1
RES,10KOHM,01005
R7512_RF
CRITICAL
LMBRF
CRITICAL
LMBRF
TABLE_5_ITEM
131S0444
1
DCS/PCS RX FILTER MATCH
R6301_RF
CRITICAL
NOLMBRF
152S2020
1
DCS/PCS RX FILTER MATCH
L6320_RF
CRITICAL
NOLMBRF
155S00149
1
DCS/PCS RX FILTER
GSMRX_RF
CRITICAL
NOLMBRF
152S2005
1
DCS/PCS RX MATCH (DCS)
L6318_RF
CRITICAL
NOLMBRF
131S0319
1
DCS/PCS RX MATCH (DCS)
C6332_RF
CRITICAL
NOLMBRF
131S0630
1
DCS/PCS RX MATCH (DCS)
C6340_RF
CRITICAL
NOLMBRF
152S2005
1
DCS/PCS RX MATCH (DCS)
L6319_RF
CRITICAL
NOLMBRF
131S0385
1
DCS/PCS RX MATCH (DCS)
C6333_RF
CRITICAL
NOLMBRF
131S0630
1
DCS/PCS RX MATCH (DCS)
C6341_RF
CRITICAL
NOLMBRF
155S00163
1
QUADPLEXER
PPLXR_RF
CRITICAL
NOLMBRF
155S00199
1
FLTR,DPX,PASS THRU,LB-MB-HB,SHLD,0805
UATDI_RF
CRITICAL
NOLMBRF
155S00234
1
FLTR,DPX,PASS THRU,LB-MB-HB,UNSHLD,0805
UPPDI_RF
CRITICAL
NOLMBRF
118S0724
1
RES,MF,0OHM,1/20W,0201
R6404_RF
CRITICAL
NOLMBRF
152S2044
1
IND,2.2NH,+/-0.1NH,600MA,0201
R7104_RF
CRITICAL
NOLMBRF
152S00157
1
1.2NH,+/-0.05NH,1.1A,UH-Q,0201
R6703_RF
CRITICAL
NOLMBRF
131S0549
1
18PF,0201,25V
R6708_RF
CRITICAL
NOLMBRF
131S0445
1
CAP,CER,12PF,5%,25V,0201,HI-Q
R6606_RF
CRITICAL
NOLMBRF
TABLE_5_ITEM
D
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
C
TABLE_5_ITEM
353S00026
1
SE2LDO_RF
LDO,BGA,2X2
D10 SPECIFIC:
TABLE_5_ITEM
131S0630
1
C6345_RF
CAP,CER,NPO/COG,27PF,2%,16V,01005
CRITICAL
C
LMBRF TABLE_5_HEAD
PART#
TABLE_5_ITEM
131S0341
1
C6348_RF
CAP,CER,COG,3.0PF,+/-0.05,25V,0201,HI-Q
CRITICAL
LMBRF
1
IND,FILM,6.2NH,3%,400MA,UH-Q,0201
L6322_RF
CRITICAL
LMBRF
131S0630
1
CAP,CER,NPO/COG,27PF,2%,16V,01005
C6315_RF
CRITICAL
LMBRF
152S2006
1
IND,FILM,6.2NH,3%,400MA,UH-Q,0201
L6305_RF
CRITICAL
LMBRF
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
CRITICAL
D10
CRITICAL
BOM OPTION
CRITICAL
D11
TABLE_5_ITEM
131S0278
TABLE_5_ITEM
152S2006
QTY
1
C7120_RF
CAP,CER,COG,1PF,+/-0.1PF,25V,0201,HI-Q
TABLE_5_ITEM
D11 SPECIFIC:
TABLE_5_ITEM
131S0341
1
C6306_RF
CAP,CER,COG,3.0PF,+/-0.05PF,25V,0201,HI-Q
CRITICAL
LMBRF TABLE_5_HEAD
PART#
TABLE_5_ITEM
131S0630
1
C6106_RF
CAP,CER,NPO/COG,27PF,2%,16V,01005
CRITICAL
LMBRF
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
131S0425
TABLE_5_ITEM
152S2051
1
IND,1.3NH,1.1A,0201
R6404_RF
CRITICAL
LMBRF
152S2000
1
IND,2.0NH,600MA,0201
R7104_RF
CRITICAL
LMBRF
131S00001
1
CAP,CER,0.1PF,25V,0201
C7119_RF
CRITICAL
LMBRF
118S0724
1
RES,MF,0OHM,1/20W,0201
R6703_RF
CRITICAL
LMBRF
118S0724
1
RES,MF,0OHM,1/20W,0201
R6708_RF
CRITICAL
LMBRF
131S0363
1
CAP,CER,C0G,HQ,0.6PF,+/-0.05PF,25V,0201
C7123_RF
CRITICAL
LMBRF
152S2002
1
IND,2.7NH,+/-0.1NH,600MA,0201,UH-Q
R6605_RF
CRITICAL
LMBRF
131S0337
1
CAP,1.5PF,+/-0.05PF,25V,0201,HQ
C6610_RF
CRITICAL
LMBRF
118S0724
1
RES,MF,0OHM,1/20W,0201
R6606_RF
CRITICAL
LMBRF
131S0275
1
CAP,CER,C0G,0.3PF,+/-0.1PF,25V,0201,HQ
C6416_RF
CRITICAL
LMBRF
1
C7120_RF
CAP,CER,COG,0.5PF,+/-0.05PF,25V,0201,HI-Q
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
B
B
TABLE_5_ITEM
TABLE_5_ITEM
118S0608
1
RES,MF,1K OHM,1%,1/32W,01005
R5911_RF
CRITICAL
LMBRF
152S1356
1
IND,10NH,3%,250MA,HI-Q,0201
C6613_RF
CRITICAL
LMBRF
TABLE_5_ITEM
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
PMU: CONTROL AND CLOCKS
1
RESET AND CONTROL: PMU
BBPMU_RF
D 81
HW_REV_ID
C
2
0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.00V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V
66 65 64
B
R5505 887K 422K 255K 180K 124K 102K 82.5K 63.4K 51.1K 51.1K 51.1K 50.0K 39.0K 14.7K 40.2K 6.34K
R5501 51.1K 51.1K 51.1K 51.1K 51.1K 51.1K 51.1K 51.1K 51.1K 63.4K 82.5K 100K 100K 51.1K 200K 51.1K
62 53
IN
AP_TO_BB_RESET_L
62 53 8178
1% MF 1/32W 01005 RADIO_PMIC
REVISION DEV1 DEV2 DEV 2.1 DEV 3 T181 PP/P1 DEV4 P2 DEV5 EVT EVT DOE
67
IN
IN
62 53 IN 78 78 67 OUT
R5504_RF 20.0K 2 1
PS_HOLD
BBPMU_RF
PMD9645
R5502_RF 1.00K 2 1
MF 5% 1/32W 01005 RADIO_PMIC
78 67
BI
78 67
BI
58 75 43 63 82 25 31
AP_TO_BBPMU_RADIO_ON_L PMU_TO_BBPMU_RESET_L PMIC_RESOUT_L PS_HOLD_PMIC SPMI_CLK SPMI_DATA
WLNSP
WLNSP CBL_PWR* PON_1 RESIN* PON_RST* PS_HOLD SPMI_CLK SPMI_DATA
SYM 1 OF 5 CONTROL
RADIO_PMIC
D
PMD9645
OPT_1 OPT_2 GND BAT_ID_THERM
52 42 98 53
PCIE PERST OPTION
NC PP_VDD_MAIN
PP_VDD_MAIN
36 46 57 62
1 4 16 20
MAKE_BASE=TRUE
GND 67
SYM 5 OF 5
GND GND RADIO_PMIC GND GND GND
MPPS AND GPIOS: PMU PP_1V8_LDO7
3 4 5
REV_ID 1
R5505_RF
C
40.2K
1% 1/32W MF 2 01005
EVT ALT/CARBON
DEV6 CARRIER DVT PVT
BBPMU_RF PMD9645
81
78 62 53
IN
66
OUT
67 OUT
1
PMU_TO_BB_USB_VBUS_DETECT HW_REV1_ID VDDPX_BIAS_UIM2 NC
VREF_DAC_BIAS
R5501_RF
NC
200K
1% 1/32W MF 2 01005
13 51 61 9 4 20 83 88
WLNSP MPP_01 MPP_02 MPP_03 MPP_04 MPP_05 MPP_06 PA_THERM1 PA_THERM2
SYM 3 OF 5 GPIO_MPP
RADIO_PMIC
GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06
26 15 21 37 32 38
NC NC
NFC_TO_BB_CLK_REQ
IN
62 53
R5511_RF 78
PCIE_AP_TO_BB_PERST_PMU_L SIM1_REMOVAL_ALARM LCM_TO_MANY_BSYNC
1 IN
68 78
IN
53 62
0.00
PCIE PERST OPTION
2 PCIE_AP_TO_BB_RESET_L
IN
53 62
68
1% 1/20W MF 0201
PP_1V8_LDO7
1
C5501_RF 0.1UF
20% 6.3V 2 X5R-CERM 01005 RADIO_PMIC
1
XTAL AND CLOCK: PMU R5503_RF 100K
1% 1/32W MF 01005 2 RADIO_PMIC
XTAL_19P2M_OUT
3 3
1
C5502_RF 1000PF
B
Y5501_RF 19.2MHZ-10PPM-7PF-80OHM
XO_THERM
2.0X1.6-SM 1 3
4
XTAL_19P2M_IN
3
BBPMU_RF
2
PMD9645
RADIO_PMIC 78 67
10% 6.3V 2 X5R-CERM 01005 RADIO_PMIC
XO_OUT_D0_EN
IN 3
3 3
XO_THERM
XTAL_19P2M_IN XTAL_19P2M_OUT
56
WLNSP SYM 2 OF 5
BB_CLK_EN
CLOCK
76 41
XO_THERM GND_XOADC
55 65 71
XTAL_19M_IN XTAL_19M_OUT GND_XO_CLK
RADIO_PMIC
LN_BB_CLK 45 BB_CLK 35
50_MDM_PCIE_CLK SHIELD_MDM_19P2M_CLK
OUT
67 78
OUT
67
RF_CLK1 66 RF_CLK2 77
SHIELD_WTR_19P2M_CLK BB_TO_NFC_CLK
OUT
70
OUT
53 62
SLEEP_CLK 72
SHIELD_SLEEP_CLK_32K
OUT
78
67 78
GND_XO_CLK: VIA DOWN TO GND PLANE
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
PMU: SWITCHERS AND LDOS SWITCHERS BULK CAPS 81
77 65 64 62 53
MAKE_BASE=TRUE PP_VDD_MAIN PP_VDD_MAIN
IN
D 1
C5620_RF 15UF 20%
2 6.3V CERM
0402 RADIO_PMIC
81 64 62 53 77 65
IN
1
PP_VDD_MAIN
4
L5601_RF 1UH-20%-0.054OHM-3.4A
C5621_RF 15UF
PP_VDD_MAIN
PP_VDD_MAIN
2.2UH-20%-0.14OHM-1.6A
4
PP_VSW_S2
C5622_RF 15UF MAKE_BASE=TRUE
5 16 6 17 28 33
PP_VDD_MAIN
4
PP_VDD_MAIN
4
PP_VDD_MAIN
4
C5623_RF 15UF
MAKE_BASE=TRUE 4
4
GND
1
20% 2 6.3V CERM 0402 RADIO_PMIC
4
81
77 65 64 62 53
IN
4 GND
B
GND
4
VDD_L5_6_15
23
VDD_L7_8
89
VDD_L9
90 47
VIN_VPH1 VIN_VPH2
73
VDD_OTP
IN
VDD_OTP OUT
MDM_VREF_LPDDR2
78
VREF_DDR
AVDD_BYP
74 79
AVDD_BYP REF_BYP
68
GND_REF
24
VDD_XO_RF
C5629_RF
0.47UF
10% 2 6.3V CERM-X5R 0201
1
C5601_RF 0.1UF
10% 2 6.3V CER-X5R 01005 RADIO_PMIC
OMIT
2
XW5616_RF SHORT-10L-0.1MM-SM
1
1
2
C5635_RF
1
R5601_RF 0.00
27PF
5% 16V NP0-C0G 01005
2% 16V CERM 01005
VREG_XO
VREG_L1 VREG_L2 VREG_L3 VREG_L4_16 VREG_L5 VREG_L6 VREG_L7 VREG_L8 VREG_L9 VREG_L10 VREG_L11 VREG_L12 VREG_L13 VREG_L14 VREG_L15
80 81 39 48 19 3 18 29 100 84 95 85 96 101 30
VREG_XO GND_XO VREG_RF GND_RF_CLK
34 40 60 50
4
L5604_RF
PP_VSW_S4
1
1.0UH-20%-2.7A-0.056OHM 1
1
XO_GND
A
4
1
BBPMU_TO_PMU_AMUX3
1.85V/1241MA
BBPMU_TO_PMU_AMUX3-53[I16] 69 65
OUT
C
C5633_RF
6.3V 2 X5R 0402
C5618_RF 25UF
4
CORE XO SHUTDOWN: ON 1
PP_1V0_SMPS5
1.01V/1059MA
66
OUT
C5634_RF 25UF
20% 6.3V X5R 0402
20% 2 6.3V X5R 0402
XO XO XO XO XO XO XO XO XO XO XO XO XO XO XO
4
SHUTDOWN: SHUTDOWN: SHUTDOWN: SHUTDOWN: SHUTDOWN: SHUTDOWN: SHUTDOWN: SHUTDOWN: SHUTDOWN: SHUTDOWN: SHUTDOWN: SHUTDOWN: SHUTDOWN: SHUTDOWN: SHUTDOWN:
OFF BYP OFF BYP ON BYP OFF OFF ON OFF ON OFF OFF OFF BYP
PP_1V5_LDO1 PP_1V2_LDO2 PP_0V9_LDO3 PP_0V95_LDO4 PP_1V7_LDO5 PP_1V8_LDO6 PP_1V8_LDO7 PP_1V8_LDO8 PP_1V0_LDO9 PP_3V075_LDO10 VDD_SIM1 PP_2V7_LDO12 VDD_SIM2 PP_1V8_LDO14 PP_1V8_LDO15
1.23V/124MA 1.20V/569MA 66 1.00V/610MA 69 1.00V/88MA 66 1.80V/52MA 66 1.80V/366MA 64 66 1.80V/15MA 1.80V/133MA 66 1.11V/1253MA 66 3.20V/15MA 66 81 1.80V/60MA 66 75 2.70V/62MA 73 74 1.80V/60MA 66 2.70V/5MA 71 68 1.80V/245MA 73 74 75 77 79 80 66
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
B 1
4
1
C5626_RF 1UF
C5604_RF 10UF 20%
20% 2 10V X5R 0201 RADIO_PMIC
2 6.3V CERM-X5R
0402 RADIO_PMIC
1
C5627_RF 10UF
1 1
C5605_RF 1UF
C5609_RF 1UF
20% 10V 2 X5R 0201 RADIO_PMIC
20% 2 10V X5R 0201 RADIO_PMIC 1
20% 6.3V 2 CERM-X5R 0402 RADIO_PMIC
2
1
1
C5630_RF
20UF
1
C5610_RF 1UF
20% 2 10V X5R 0201 RADIO_PMIC
20% 2 6.3V CERM-X5R 0402
20% 10V 2 X5R 0201 RADIO_PMIC
1
C5608_RF 4.7UF
1
C5611_RF 1UF
20% 2 10V X5R 0201 RADIO_PMIC
1
C5628_RF 1UF
20% 2 10V X5R 0201 RADIO_PMIC
20% 6.3V X5R-CERM1 402 RADIO_PMIC
C5613_RF 1UF
C5612_RF 1UF
20% 2 10V X5R 0201 RADIO_PMIC
C5607_RF 1UF
20% 10V 2 X5R 0201 RADIO_PMIC
OMIT
1
XW5614_RF SHORT-10L-0.1MM-SM
1.16V/1951MA
VREG_XO 4 VREG_XO_GND 4 VREG_RF_CLK 4 VREG_RF_CLK_GND
1
PLACE C5635 AND C5636 NEAR THE PMU
4
C5632_RF
HIGH VOLTAGE LDOS XO SHUTDOWN: ON
GPS LNA RFFE VIO
VREG_RF_CLK_GND
2
1
FRONT END SUPPLY UIM2
1
OMIT
MDM MEMORY, MDM USB XO SHUTDOWN: ON
25UF 20%
20% 6.3V X5R 0402
GND MDM LOW VOLTAGE ANALOG MDM EBI1, DDR CORE MDM CORE MDM PCIE MDM HIGH VOLTAGE ANALOG MDM 1.8V I/O, DDR, SHARED 1.8V VOLTAGE RAIL MDM PLL MDM LOW VOLTAGE USB MEMORY MDM HIGH VOLTAGE USB UIM1
VREG_RF_CLK
2
1
2
1UF
4
C5617_RF
2
RADIO_PMIC
BBPMU_TO_PMU_AMUX2
C5631_RF
20% 6.3V 2 X5R 0402
GND
0806
20% 2 10V X5R 0201 RADIO_PMIC
VREG_XO_GND
2
1.25V/693MA
25UF
20% 6.3V X5R 0402
25UF
L5605_RF
PP_VSW_S5
C5616_RF
GND 1
4
4
2
RADIO_PMIC
20% 2 10V X5R 0201 RADIO_PMIC
1UF
PLACE XW CLOSE TO PMU VIA XW DOWN TO THE GND PLANE
2
1
PP_1V225_SMPS2
20% 6.3V 2 CERM-X5R 0402
25UF
2.2UH-20%-0.14OHM-1.6A
1 C5603_RF
XW5617_RF SHORT-10L-0.1MM-SM
1
LOW VOLTAGE LDOS XO SHUTDOWN: ON
20UF
6.3V CERM-X5R 0402
1
RADIO_PMIC
1 C5602_RF
OMIT
2 0806
2
C5636_RF
100PF
2
1
0% 1/32W MF 2 01005
PP_VSW_S3
C5615_RF
GND
1.0UH-20%-2.7A-0.056OHM
VREG_S5 87 VSW_S5 99
VDD_S5 GND_S5
14
4 GND
PP_VDD_MAIN
VDD_S4 GND_S4 GND_S4
VREG_S4 12 VSW_S4 2
BBPMU_TO_PMU_AMUX3 65 BBPMU_TO_PMU_AMUX3-53[I16] IN
GND_REF
IN
VDD_S3 GND_S3 GND_S3
VREG_S3 69 VSW_S3 59 VSW_S3 64
2
0806
VDD_L3_4
REF_BYP
DESENSE CAPS
VDD_S2 VDD_S2 GND_S2
44
AVDD_BYP_GND
77 65 64 62 53
0.90V/2685MA
BBPMU_TO_PMU_AMUX1-53[I16] 66 65
OUT
4
20UF 20%
L5603_RF
10 11 22 27
VREG_S2 91 VSW_S2 97
BBPMU_TO_PMU_AMUX2
67
MAKE_BASE=TRUE
RADIO_PMIC
4
PP_VDD_BOOST PP_VDD_MAIN
VREG_S1 VSW_S1 VSW_S1 VSW_S1
POWER
VDD_L1_2_16
81
C5625_RF 15UF
VDD_S1 VDD_S1 GND_S1 GND_S1 GND_S1 GND_S1
4
77 65 64 62 53
4
WLNSP
86
1
81
1
RADIO_PMIC
SYM 4 OF 5
PP_1V225_SMPS2
IN
PP_VDD_MAIN
20% 2 6.3V CERM 0402 RADIO_PMIC
94 93
MAKE_BASE=TRUE
81 MAKE_BASE=TRUE PP_VDD_MAIN PP_VDD_MAIN
1
4
69
GND
8 1 7
PP_VDD_MAIN
4
4
C5624_RF 15UF
GND
70 49 54
PP_VDD_MAIN 4
PP_VDD_MAIN
GND
PP_VDD_MAIN
4
MAKE_BASE=TRUE PP_VDD_MAIN PP_VDD_MAIN
92 103 102
PP_VDD_MAIN
4
4
IN
GND
4
4
77 65 64 62 53
BBPMU_TO_PMU_AMUX1
4V X5R 0603
GND
PMD9645
20% 2 6.3V CERM 0402 RADIO_PMIC
C5614_RF
2 0806
BBPMU_RF
MAKE_BASE=TRUE
81
1
RADIO_PMIC
PP_VDD_MAIN
C
2
L5602_RF
4
4 GND
1
1
MDM MODEM XO SHUTDOWN: OFF
43UF 20%
20% 2 6.3V CERM 0402
IN
2
2520 RADIO_PMIC
MAKE_BASE=TRUE
PP_VDD_MAIN
81 64 62 53 77 65
1
PP_VSW_S1
20% 6.3V 2 CERM 0402 RADIO_PMIC GND MAKE_BASE=TRUE
1
D
4
XW5615_RF SHORT-10L-0.1MM-SM
RF_CLK_GND
PLACE XW CLOSE TO PMU VIA XW DOWN TO THE GND PLANE
5 4
BBPMU_TO_PMU_AMUX1 MAKE_BASE=TRUE
BBPMU_TO_PMU_AMUX1
OUT
62 SYNC_MASTER=Sync
4
BBPMU_TO_PMU_AMUX2 MAKE_BASE=TRUE
BBPMU_TO_PMU_AMUX2
8 4
BBPMU_TO_PMU_AMUX3 MAKE_BASE=TRUE
BBPMU_TO_PMU_AMUX3
SYNC_DATE=05/17/2016
PAGE TITLE OUT
62
OUT
62
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
8
7
6
5
4
3
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
BASEBAND: POWER BB_RF MDM9645
D 5 4
PP_1V0_SMPS5
C 5 4
PP_1V0_LDO9
B
5 4
V16 V17 F12 F13 F9 G11 G12 G16 G17 G8 G9 H15 H16 J18 J19 K15 L15 M15 M16 M17 P15 P16 R15 R16 U16 U7 U8
VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE
E19 F18 F19 G18 H10 H13 H14 H8 H9 J12 J13 J14 J15 J7 J8 K18 L17 L18 M12 M13 N12 N7 P6 P7 T12 T18 T6 U11 U12 U13 U18 U6 V18
VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM
C5705_RF 2.2UF
20% 2 4V X5R-CERM 0201 RADIO_BB BBPMU_TO_PMU_AMUX1
1
A
SYM 6 OF 8 PWR1
VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM
F7 BBPMU_TO_PMU_AMUX1 4 5 F8 G7 J11 K10 K11 K14 K6 K7 L10 L13 PP_1V2_LDO2 5 4 L14 L6 1 C5755_RF 1 C5729_RF L9 2.2UF 2.2UF M8 20% 20% 6.3V 2 X5R-CERM 2 6.3V M9 X5R-CERM 0201-1 0201-1 N11 RADIO_PMIC RADIO_PMIC N8 P10 P11 P14 20 17 7 6 5 4 PP_1V8_LDO6 R10 R13 20 17 7 6 5 4 PP_1V8_LDO6 R14 R8 1 C5730_RF R9 2.2UF 20% T13 6.3V 2 X5R-CERM T8 0201-1 RADIO_PMIC T9
BB_RF
MDM9645
1
1
C5733_RF 2.2UF
20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC
20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC
1
1
C5736_RF 2.2UF
1
C5734_RF 2.2UF
20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC
1
C5739_RF 2.2UF
20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC
1
C5737_RF 2.2UF
20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC
C22 D22 G22 H22 L22 M22 T22 U22 W2 Y2
VDD_P1 VDD_P1 VDD_P1 VDD_P1 VDD_P1 VDD_P1 VDD_P1 VDD_P1 VDD_P1 VDD_P1
R23
VDD_P2
AA23 AB16 E2 K2 P2
VDD_P3 VDD_P3 VDD_P3 VDD_P3 VDD_P3
C5742_RF 2.2UF
20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC
1
C5740_RF 2.2UF
20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC
C5704_RF 2.2UF
20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC NOSTUFF
SYM 7 OF 8 PWR2
VDD_SIM1 (PP_UIM1_LDO11)
AA21
VDD_P4
4
VDD_SIM2 (PP_UIM2_LDO13)
AA15
VDD_P5
PP_1V8_LDO6
AB11 M19
VDD_P7 VDD_P7
4 4
5 4
V9 VDD_USB_HS_1P8 AA10 VDD_USB_HS_3P3
PP_1V8_LDO8 PP_3V075_LDO10
AB3 NC W3 NC AA3 NC Y5 Y6 Y7
PP_0V95_LDO4
1
VDD_DDR_CORE_1P8 VDD_DDR_CORE_1P8 VDD_DDR_CORE_1P8 VDD_DDR_CORE_1P8
B23 E1 K23 U1
VDD_DDR_CORE_1P2 VDD_DDR_CORE_1P2 VDD_DDR_CORE_1P2 VDD_DDR_CORE_1P2 VDD_DDR_CORE_1P2
AA1 C23 D1 J23 W1
VDD_USB_SS_0P9 VDD_USB_SS_0P9 VDD_USB_SS_1P8 VDD_PCIE_0P9 VDD_PCIE_0P9 VDD_PCIE_1P8
20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC 5 4
1
20% 6.3V 2 X5R-CERM 0201-1 RADIO_PMIC
B12 B3 B15 B7 B18 B8
VDD_A1 B10 VDD_A1 E10 VDD_A2 VDD_A2 VDD_A2 VDD_A2
C18 C6 C7 E3
C5731_RF 2.2UF
20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC
1
C5732_RF 2.2UF
20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC
1
C5735_RF 2.2UF
20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC
1
C5738_RF 2.2UF
20% 2 6.3V 0201-1 RADIO_PMIC
1
1
C5741_RF 0.1UF
C5743_RF 2.2UF
20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC
20% 2 4V X5R 01005 RADIO_PMIC NOSTUFF
1
VDDPX_BIAS_UIM2
1
C5750_RF 0.1UF
20% 2 6.3V X5R-CERM 01005 RADIO_PMIC
1
C5747_RF 2.2UF
20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC
1
1
1
C5754_RF 2.2UF
C5752_RF 2.2UF
20% 6.3V 0201-1 RADIO_PMIC
2 X5R-CERM
20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC
PP_1V5_LDO1
1
4 5
4
20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC
4
C5748_RF 2.2UF
20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC PP_0V95_LDO4
VDD_ALWAYS_ON U14 NC VDD_PLL E13 VDD_PLL P19 VDD_QFPROM_PRG F10
C5749_RF 2.2UF
20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC NOSTUFF
20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC
PP_1V0_LDO9
3
C5751_RF 2.2UF
VDD_USB_HS_MX V11
C5744_RF 2.2UF
PP_1V2_LDO2
PP_1V7_LDO5
1
1
C5746_RF 2.2UF
VDD_A3 E7 VDD_A3 E17 VDD_A2 VDD_A1 VDD_A2 VDD_A1 VDD_A2 VDD_A1
4 5 6 7 17 20
C5745_RF 2.2UF
VREF_SDC U21 VREF_UIM Y20
VDD_A2 C12 VDD_A2 C15
20 4
20 17 7 6 5 4
PP_1V8_LDO6
BGA
1
4 5
PP_1V8_LDO7
3 4 5
PP_1V8_LDO7
3 4 5
C5753_RF 2.2UF
20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
BB_RF
MDM9645 BGA
SYM 8 OF 8 GND
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
H7 J10 J16 J17 J22 J6 J9 K1 K12 K13 K16 K17 K8 K9 L11 L12 L16 L23 L7 L8 M10 M11 M14 M18 M6 M7 N10 N13 N14 N15 N16 N17 N18 N6 N9 P1 P12 P13 P17 P18 P8 P9 R11 R12 R17 R18 R7 T10 T11 T14
GND GND GND GND GND GND GND GND GND GND GND GND GND GND
T15 T16 T17 T23 T7 U10 U15 U17 U23 U9 V1 V6 Y4 Y8
1
C5708_RF 2.2UF
20% 2 4V X5R-CERM 0201 RADIO_BB
1
C5711_RF 2.2UF
1
C5714_RF 2.2UF
1
C5717_RF 2.2UF
1
C5720_RF 2.2UF
1
C5723_RF 2.2UF
1
C5726_RF 2.2UF
1
B
C5701_RF 15UF
20% 4V 2 X5R-CERM 0201 RADIO_BB
20% 4V 2 X5R-CERM 0201 RADIO_BB
20% 2 4V X5R-CERM 0201 RADIO_BB
20% 2 4V X5R-CERM 0201 RADIO_BB
20% 4V 2 X5R-CERM 0201 RADIO_BB
20% 4V 2 X5R-CERM 0201 RADIO_BB
2 6.3V CERM
1
1
1
1
1
1
1
20%
0402 RADIO_BB
C5706_RF 2.2UF
1
C5709_RF 2.2UF
20% 2 4V X5R-CERM 0201 RADIO_BB
C5712_RF 2.2UF
20% 4V 2 X5R-CERM 0201 RADIO_BB
C5715_RF 2.2UF
20% 4V 2 X5R-CERM 0201 RADIO_BB
C5718_RF 2.2UF
20% 2 4V X5R-CERM 0201 RADIO_BB
C5721_RF 2.2UF
20% 2 4V X5R-CERM 0201 RADIO_BB
C5724_RF 2.2UF
20% 4V 2 X5R-CERM 0201 RADIO_BB
C5727_RF 2.2UF
20% 2 4V X5R-CERM 0201 RADIO_BB
C5702_RF 15UF
20% 2 6.3V CERM 0402 RADIO_BB
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
(MODEM SUB MEMORY)
PP_1V0_LDO9
1
C5707_RF 2.2UF
20% 2 4V X5R-CERM 0201 RADIO_BB
1
C5710_RF 2.2UF
20% 2 4V X5R-CERM 0201 RADIO_BB
Apple Inc. 1
C5713_RF 2.2UF
20% 2 4V X5R-CERM 0201 RADIO_BB
1
C5716_RF 2.2UF
20% 4V 2 X5R-CERM 0201 RADIO_BB
1
C5719_RF 2.2UF
20% 2 4V X5R-CERM 0201 RADIO_BB
1
C5722_RF 2.2UF
20% 2 4V X5R-CERM 0201 RADIO_BB
1
C5725_RF 2.2UF
20% 2 4V X5R-CERM 0201 RADIO_BB
1
C5728_RF 2.2UF
20% 2 4V X5R-CERM 0201 RADIO_BB
1
C5703_RF 15UF 20%
2 6.3V CERM
0402 RADIO_BB
6
REVISION
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
7
051-00419
R
II NOT TO REPRODUCE OR COPY IT
8
C
(MSM MODEM)
20% 4V 2 X5R-CERM 0201 RADIO_BB 5 4
D
(MSM CORE)
PP_1V0_SMPS5
1
5 4
BGA
A1 A11 A12 A15 A17 A2 A22 A23 A4 A6 A7 A9 AA5 AB1 AB10 AB15 AB21 AB23 AB5 AB7 AB9 B13 B19 B20 B21 B22 B5 C1 C11 C16 C2 C20 C21 C4 C9 D2 D21 D23 E14 E15 E16 E18 E21 E22 E23 E6 E8 E9 F11 F14 F15 F16 F17 F23 G10 G13 G14 G15 G19 G23 H11 H12 H17 H18 H19 H23 H6
5
4
3
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
BASEBAND: CONTROL AND INTERFACES BB_RF
MDM9645
D
BGA
D
BB_RF
SYM 1 OF 8 78 64
IN
78 64
OUT
64
IN
81 78 6 5 4 20
PP_1V8_LDO6 1
IN
NC NC
R5807_RF 1.00K
5% 1/32W MF 2 01005
17 6
20 1
R6 T3
SWD_AOP_BI_BB_SWDIO
MDM9645 BGA SYM 4 OF 8
RESOUT* V2 NC PS_HOLD PS_HOLD U2
SRST* RESIN* MODE_0 MODE_1
W23 U19 NC W22 V22 NC V21 NC
SWD_AP_TO_BB_CLK_BUFFER
CONTROL
SLEEP_CLK CXO_EN CXO
V19 V3
BB_JTAG_RST_L PMIC_RESOUT_L
IN
78 64
T2 U3 F2
SHIELD_SLEEP_CLK_32K XO_OUT_D0_EN SHIELD_MDM_19P2M_CLK
SDC1_CLK SDC1_CMD SDC1_DATA_0 SDC1_DATA_1 SDC1_DATA_2 SDC1_DATA_3
TCK TRST* TMS TDI TDO
R21 V23 T21 T19 R19 R22
OUT
4
64
1
NC NC NC
1% 1/32W MF 01005 2 RADIO_BB
NC NC NC
SPMI_CLK Y17 SPMI_DATA AB18
R5801_RF 240
PLACE CLOSE TO E1
SPMI_CLK SPMI_DATA
BI
64 78
BI
64 78
BDM_CAL EBI1_CAL MDM_VREF_LPDDR2
1
R5802_RF 240
1% 1/32W MF 01005 2 RADIO_BB
PLACE CLOSE TO T3
1
C5804_RF 0.1UF
2
10% 10V
D3 V5 K22 G21 K21 U5
BDM_ZQ EBI1_CAL VREF_DQ_BDM EBI1_VREF EBI1_VREF EBI1_VREF
MEMORY
X5R-CERM
0201
RADIO_BB
NOSTUFF AT CARRIER PP_1V8_LDO6
20 17 7 6 5 4
C
NOSTUFF
C
5
U5801_RF
SOT1226 SWD_AP_TO_BB_CLK_BUFFER 4
6 17
NC
1
3
NC
20 1
2
SWD_AP_TO_MANY_SWCLK
74AUP1G34GX
BB_RF
MDM9645 BGA SYM 2 OF 8 71
71
IN
IN
SHIELD_XCVR0_PRX_CA2_I SHIELD_XCVR0_PRX_CA2_Q
B9 A10
BBRX_IP_CH0 BBRX_QP_CH0
ANALOG_RF
BBRX_IP_FB C10 BBRX_QP_FB B11
SHIELD_XCVR0_TX_FB_RX_I SHIELD_XCVR0_TX_FB_RX_Q
IN
BB_RF
70 71
MDM9645 IN
BGA
70 71
SYM 5 OF 8 71
71
B
IN
IN
SHIELD_XCVR0_DRX_CA2_I SHIELD_XCVR0_DRX_CA2_Q
A8 C8
BBRX_IP_CH1 BBRX_QP_CH1
GNSS_BB_IP E11 GNSS_BB_QP E12
SHIELD_GPS_RX_I SHIELD_GPS_RX_Q
IN
IN
71 78 64
71
71
71
64
IN
IN
IN
IN
IN
SHIELD_XCVR1_DRX_I
C5
SHIELD_XCVR1_DRX_Q
B6 B4
SHIELD_XCVR1_PRX_I
A5
SHIELD_XCVR1_PRX_Q
C5801_RF
0.1UF
20% 2 6.3V X5R-CERM 01005
71
IN
71
IN
71
IN
71
IN
BBRX_QP_CH2 BBRX_IP_CH3 BBRX_QP_CH3
C13 C19
TX_DAC_VREF TX_DAC_VREF
SHIELD_XCVR0_PRX_CA1_I SHIELD_XCVR0_PRX_CA1_Q
A3 C3
BBRX_IP_CH5 BBRX_QP_CH5
SHIELD_XCVR0_DRX_CA1_I SHIELD_XCVR0_DRX_CA1_Q
B2 B1
BBRX_IP_CH6 BBRX_QP_CH6
VREF_DAC_BIAS 1
BBRX_IP_CH2
F21 NC F22 NC H21 NC J21 NC
NC NC NC NC
TX_DAC0_IP TX_DAC0_IM TX_DAC0_QP TX_DAC0_QM
C17 B17 A16 B16
TX_DAC1_IP TX_DAC1_IM TX_DAC1_QP TX_DAC1_QM
C14 NC B14 NC A13 NC A14 NC A20 A21 A18 NC A19 NC F1 NC F6 NC G1 NC G6 NC Y3 NC
ET_DAC0_P ET_DAC0_M ET_DAC1_P ET_DAC1_M DNC DNC DNC DNC DNC
SHIELD_XCVR0-1_TX_I_P SHIELD_XCVR0-1_TX_I_N SHIELD_XCVR0-1_TX_Q_P SHIELD_XCVR0-1_TX_Q_N
AA9 Y9
PCIE_USB_SYSCLK USB_HS_REXT
90_USB_BB_DATA_P 90_USB_BB_DATA_N
V10 Y10
USB_HS_DP USB_HS_DM
PCIE_TX_P AB6 PCIE_TX_M AA6
90_PCIE_BB_TO_AP_RXD_P 90_PCIE_BB_TO_AP_RXD_N
OUT
53 62
OUT
53 62
USB_SS_TX_P USB_SS_TX_M
PCIE_RX_P AA8 PCIE_RX_M AB8
90_PCIE_AP_TO_BB_TXD_P 90_PCIE_AP_TO_BB_TXD_N
IN
53 62
IN
53 62
USB_SS_RX_P USB_SS_RX_M
PCIE_REXT AA7
OUT
70
OUT
70
OUT
70
OUT
70
BI
78 62 53 81
1
AB2 NC AA2 NC AA4 NC AB4 NC
R5806_RF
4.02K
1% 1/32W MF 2 01005
PLACE CLOSE TO U12 SHIELD_ET_DAC_P SHIELD_ET_DAC_N
PCIE_REFCLK_P V8 PCIE_REFCLK_M V7
90_PCIE_AP_TO_BB_REFCLK_P 90_PCIE_AP_TO_BB_REFCLK_N
71 78 62 53 81
71
IN
USB_PCIE
50_MDM_PCIE_CLK BB_USB_TRXTUNE
OUT
77
OUT
77
NC
Y1
IN
53 62
78
IN
53 62
78
B
PCIE_CAL_RES 1
USB_SS_REXT
R5803_RF 1.43K
1% 1/32W MF 2 01005 RADIO_BB
PLACE CLOSE TO AA10
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
8
7
6
5
4
3
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
R5911_RF 1
MDM9645
3
2
1
BASEBAND: GPIOS PP_1V8_LDO6
R5912_RF 1
1.00K
1% 1/32W MF 01005
1.00K
1% 1/32W MF 01005
D
SKU R5911_RF ROW NOSTUFF JP 1.0 KOHM
R5912_RF NOSTUFF NOSTUFF
RADIO_BB
NOSTUFF
7 62
53
IN
62
53
IN
53 OUT
62 78
53
62 53 62
53
IN OUT IN
17
MAV13 = BB_LAT_0 RF_BB_LAT_1 RF_BB_LAT_2 RF_BB_LAT_3
79 78 OUT 80 19 18 17 80 73
V15 NC AA19 NC AB14 NC Y15 NC T1 R3 R2 NC R1 NC T5 NC P3 NC R5 P5 V13 AA12 Y13 AA13 V14 AA14 Y14 NC AB13 NC AB19 NC P21 NC P23 NC Y18 NC N19 P22 NC N3 N2 N1 N5 M3 NC M2 NC M1 NC M5 NC L5 NC L3 NC L2 L1 N22 F5
2
RADIO_BB OMIT_TABLE
SKU_ID
SKU_ID2
7
62
2
BB_RF
OUT 19 12
C
BB_EEPROM_I2C_SDA BB_EEPROM_I2C_SCL I2S_BB_TO_AP_LRCLK I2S_AP_TO_BB_DOUT I2S_BB_TO_AP_DIN I2S_BB_TO_AP_BCLK UART_BB_TO_AOP_RXD UART_AOP_TO_BB_TXD
FAST_BOOT_SELECT0 75_RFFE6_SCLK 75_RFFE6_SDATA 75_RFFE7_SCLK 75_RFFE7_SDATA
MAV13 = WDOG DIS
78
62 53
OUT
78 74
OUT
78 73
OUT
78 73
OUT
BB_TO_STROBE_DRIVER_GSM_BURST_IND RX-DSPDT_CTL2 FBRX-DSPDT_CTL1 FBRX-DSPDT_CTL2
BGA GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GPIO_16 GPIO_17 GPIO_18 GPIO_19 GPIO_20 GPIO_21 GPIO_22 GPIO_23 GPIO_24 GPIO_25 GPIO_26 GPIO_27 GPIO_28 GPIO_29 GPIO_30 GPIO_31 GPIO_32 GPIO_33 GPIO_34 GPIO_35 GPIO_36 GPIO_37 GPIO_38 GPIO_39
GPIO_40 GPIO_41 GPIO_42 GPIO_43 GPIO_44 GPIO_45 GPIO_46 GPIO_47 GPIO_48 GPIO_49 GPIO_50 GPIO_51 GPIO_52 GPIO_53 GPIO_54 GPIO_55 GPIO_56 GPIO_57 GPIO_58 GPIO_59 GPIO_60 GPIO_61 GPIO_62 GPIO_63 GPIO_64 GPIO_65 GPIO_66 GPIO_67 GPIO_68 GPIO_69 GPIO_70 GPIO_71 GPIO_72 GPIO_73 GPIO_74 GPIO_75 GPIO_76 GPIO_77 GPIO_78 GPIO_79
SYM 3 OF 8 GPIO
F3 NC K3 K5 NC J3 NC J2 J1 J5 H3 H2 H1 Y16 NC N23 AA16 V12 K19 NC Y23 L19 AA22 M23 NC AB22 NC Y12 NC AB17 Y22 NC M21 NC Y11 AA11 L21 W21 AA17 NC AA18 N21 NC AB12 NC H5 G3 G2 G5 Y21 Y19 AB20 AA20
SHIELD_GSM_TX_PHASE
OUT
1
75_RFFE3_SDATA 75_RFFE3_SCLK 75_RFFE4_SDATA 75_RFFE4_SCLK BB_TO_LAT_ANT_DATA BB_TO_LAT_ANT_SCLK
BI
74 78
OUT
74 78
BI
70 78
OUT
2
BUFFER ON RFFE5 SCLK/SDATA_A IS OUTPUT
70
C5902_RF 22PF PLACE CAP CLOSE TO MDM 2% 16V IMPROVES RXBN BY 4DB CERM
RF1352
01005
4 VIO
19 18 16 14 13 12 4 PP_1V8_LDO15
70 78
WLCSP
GPO1 1 GPO2 8
1 7 17 1 7 17 17 7 1
AP_TO_BB_TIME_MARK UART_BB_TO_WLAN_COEX UART_WLAN_TO_BB_COEX
IN OUT IN
53 62
17 7 1
78
53 62 WDOG 78 81 53 62 78 81
D
RFBUF_RF
BB_TO_LAT_ANT_SCLK
2 SCLK
BB_TO_LAT_ANT_DATA
3 SDATA
BB_BUFFER_GPO1 BB_BUFFER_GPO2
SCLK_A 5
BB_TO_UAT_SCLK
SDATA_A 6
BB_TO_AP_RESET_DETECT_L AP_TO_BB_COREDUMP AP_TO_BB_IPC_GPIO1
OUT
53 62
78
IN
53 62
78
BI
1 1 1 7 14
BB_TO_UAT_DATA
1 7 14
DIS CONFLICT GND
USID=0XF
7
20 17 7 6 5 4
53 62
RFCAL_QCN BB_TO_PMU_PCIE_HOST_WAKE_L
OUT
53 62
78
17 7 1
PCIE_BB_BI_AP_CLKREQ_L
BI
53 62
0.00
68
PCIE_AP_TO_BB_RESET_L AP_TO_BB_MESA_ON FAST_BOOT_SELECT1
BI
53 62
BI
64 78
R5909_RF 1 2
BB_TO_LAT_ANT_SCLK
IN
53 62
64
1
BI
75_RFFE1_SCLK SIM1_IO SIM1_DETECT SIM1_RST SIM1_CLK
77 78
BI
70 78
BI
70 78
BI
78 81
17 7 1
BB_TO_LAT_ANT_DATA
1
0.00 2
BB_TO_UAT_DATA
C
1 7 14
0% 1/32W MF 01005
RADIO_BB NOSTUFF 20 1
PP1V8_SDRAM
78 81 78 81
OUT
R5910_RF
5% 16V NP0-C0G 01005
77 78
OUT
IN
C5903_RF 100PF
2
75_RFFE2_SDATA 75_RFFE2_SCLK 75_RFFE1_SDATA
1 7 14
RADIO_BB NOSTUFF
17
SIM1_REMOVAL_ALARM
BB_TO_UAT_SCLK
0% 1/32W MF 01005
1
78 81
C5906_RF
1
C5907_RF
2
5% 16V NP0-C0G-CERM 01005
0.01UF
10% 2 6.3V X5R 01005
33PF
GPIO_RF QM18064 A3 VIO
RFFE USAGE TABLE B
R5906_RF 100K
1
PP_1V8_LDO6
1% 1/32W MF 01005 2 RADIO_BB NOSTUFF 7 1
BB_TO_LAT_ANT_DATA
A2 SDATA
BB_TO_LAT_GPO1 BB_TO_LAT_GPO2 BB_TO_LAT_GPO3
1 1 1
NC
GND
USID=0X8
B
1
1
R5907_RF 10K
1% 1/32W MF 2 01005 RADIO_BB
PCIE_BB_BI_AP_CLKREQ_L
C5901_RF 1UF
20% 2 10V X5R 0201 RADIO_BB
4 5 6 7 17 20
1
R5908_RF 10K
1% 1/32W MF 2 01005 RADIO_BB
VCC
PCIE PULL-UPS TO BB RAIL
EPROM_RF CAT24C08C4A 7
BB_EEPROM_I2C_SCL
B1 SCL
WLCSP RADIO_BB
SDA B2
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
BB_EEPROM_I2C_SDA
spare
7
DRAWING NUMBER
Apple Inc.
VSS
051-00419
REVISION
R
A2
A
17 7 1
A1 SCLK
A4 B1 B2 B4
BB EEPROM
PP_1V8_LDO6
A1
20 17 7 6 5 4
WTR3925 QFE3100 DIV MODULES WTR4905 TUNERS + ELNAS 2G PA,MLB PA,MB/HB TDD PA,MB/HB FDD PA LB PA, COUPLERS
BB_TO_LAT_ANT_SCLK
GPO1 GPO2 GPO3 GPO4
B3
RFFE1 RFFE2 RFFE3 RFFE4 RFFE5 RFFE6 RFFE7
17 7 1
WLCSP
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
8
7
6
5
4
3
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
TRANSCEIVER: POWER D
STAR ROUTING
D
DEFAULT_RESISTOR_0.001OHM_2_1
R6001_RF 69 65
IN
PP_0V9_LDO3 1 DEFAULT_CAPACITOR_1e+06pF_2_1
1
C6001_RF 10UF
20% 6.3V 2 CERM-X5R 0402 RADIO_TRANSCEIVER
0.00
2
0% 1/32W MF 01005
35MA
PP_VDD_XCVR0_RF1_TX_VCO
XCVR0_RF
DEFAULT_CAPACITOR_100000pF_2_1 DEFAULT_CAPACITOR_27.000000pF_2_1 1
RADIO_TRANSCEIVER
C6018_RF
0.1UF
20% 6.3V 2 X5R-CERM 01005
1
WTR3925-2-TR-03-1
C6010_RF
27PF
5% 16V 2 NP0-C0G 01005
RADIO_TRANSCEIVER
R6005_RF 1
0.00
2
0% 1/32W MF 01005
175MA
PP_VDD_XCVR0_RF1_TX
DEFAULT_CAPACITOR_100000pF_2_1 1
C6019_RF
1
0.1UF
20% 6.3V 2 X5R-CERM 01005 DEFAULT_RESISTOR_0.001OHM_2_1
XCVR0_RF
C6011_RF
WTR3925-2-TR-03-1
27PF 5%
WLPSP
16V 2 NP0-C0G 01005
88
0.00
2
0% 1/32W MF 01005
67
1
45
VDD_RF1_DIG
DEFAULT_CAPACITOR_100000pF_2_1 DEFAULT_CAPACITOR_27.000000pF_2_1 64
VDD_RF1_RX1
LDO_CAP 23
20% 2 6.3V X5R-CERM 0201-1
VDD_RF1_RX2
VDD_RF2 30
25MA
PP_VDD_XCVR0_RF1_DIG
1
VDD_XCVR0_RF2_LDO_BYPASS
SYM 4 OF 5 PWR
VDD_RF1_TVCO RADIO_TRANSCEIVER VDD_RF1_TSIG
RADIO_TRANSCEIVER
R6006_RF 1
C6380_RF CAN BE 0201 (TBD)
C6020_RF
0.1UF
20% 6.3V 2 X5R-CERM 01005 DEFAULT_RESISTOR_0.001OHM_2_1
1
C6012_RF
49
27PF
C6024_RF 2.2UF
5% 16V 2 NP0-C0G 01005
250MA
RADIO_TRANSCEIVER
BBPMU_TO_PMU_AMUX3
R6007_RF
C
1
0.00
2
1
DEFAULT_CAPACITOR_100000pF_2_1 DEFAULT_CAPACITOR_27.000000pF_2_1
0% 1/32W MF 01005
1
C6021_RF
0.1UF
20% 2 6.3V X5R-CERM 01005 DEFAULT_RESISTOR_0.001OHM_2_1
1
BBPMU_TO_PMU_AMUX3-53[I16] 65
GND
58 56 42 72
GND GND GND GND
28 84 21 91 20 90 19 89 102
GND GND GND GND GND GND GND GND GND
55
GND
GND 94 RADIO_TRANSCEIVER
GND GND GND GND GND GND GND
1
C6003_RF 0.47UF
20% 2 4V CERM-X5R-1 201 RADIO_TRANSCEIVER
C6013_RF
27PF
5% 2 16V NP0-C0G 01005
2
87 81 17 52 37 36 61
GND 53 GND 54 GND GND GND GND GND GND GND GND GND
69
DEFAULT_CAPACITOR_100000pF_2_1 DEFAULT_CAPACITOR_4700pF_2_1
40MA
PP_VDD_XCVR0_RF1_RX1
IN
3
C6005_RF 4700PF
57 82 83 26 27 71 63 41 48
C
GND 38 GND 25 GND 31
10% 6.3V X5R 01005 RADIO_TRANSCEIVER
RADIO_TRANSCEIVER
R6008_RF 1
0.00
2
0% 1/32W MF 01005
250MA
PP_VDD_XCVR0_RF1_RX2
DEFAULT_CAPACITOR_100000pF_2_1 DEFAULT_CAPACITOR_27.000000pF_2_1 1
C6022_RF
0.1UF
20% 2 6.3V X5R-CERM 01005
1
C6014_RF
27PF
5% 2 16V NP0-C0G 01005
RADIO_TRANSCEIVER
XCVR1_RF WTR4905 WLNSP 9 13 16 21 24 25 26 27 29 30
B STAR ROUTING
DEFAULT_RESISTOR_0.001OHM_2_1
R6002_RF 69 65
IN
PP_0V9_LDO3 1
1
20% 6.3V 0201-1 RADIO_TRANSCEIVER
2
0% 1/32W MF 01005
C6006_RF 2.2UF
0.00
PP_VDD_XCVR1_RF1_DIG 1
RADIO_TRANSCEIVER
C6007_RF
0.1UF
20% 2 6.3V X5R-CERM 01005
2 X5R-CERM
RADIO_TRANSCEIVER
0.00
2
0% 1/32W MF 01005
1
RADIO_TRANSCEIVER
C6008_RF
0.1UF
20% 2 6.3V X5R-CERM 01005
RADIO_TRANSCEIVER
RADIO_TRANSCEIVER
40MA
0.00 0% 1/32W MF 01005
2
C6009_RF
0.1UF
20% 2 6.3V X5R-CERM 01005
A
RADIO_TRANSCEIVER
VDD_RF1_DIG
PWR
IN
BBPMU_TO_PMU_AMUX3-53[I16] 65
69
1
C6004_RF 4700PF
GND GND GND GND GND GND GND GND GND
GND
32 35 37 39 40 42 45 48 52
B
10%
2 6.3V X5R
01005 RADIO_TRANSCEIVER
VDD_RF2 44 VDD_RF2_LDO 34
VDD_XCVR1_RF2_LDO_BYPASS 1
C6023_RF 2.2UF
C6016_RF
20% 6.3V 2 X5R-CERM 0201-1
27PF
5% 2 16V NP0-C0G 01005
175MA
PP_VDD_XCVR1_RF1_TX 1
50
33 VDD_RF1_RX 23 VDD_RF1_TX DEFAULT_CAPACITOR_27.000000pF_2_1
R6004_RF 1
WLNSP SRM 4 OF 5
C6002_RF 0.47UF
20% 2 4V CERM-X5R-1 201 RADIO_TRANSCEIVER
WTR4905
5% 2 16V NP0-C0G 01005
1
1
XCVR1_RF
C6015_RF
27PF
PP_VDD_XCVR1_RF1_RX 1
BBPMU_TO_PMU_AMUX3
DEFAULT_CAPACITOR_4700pF_2_1
R6003_RF 1
250MA
25MA
SYM 5 OF 5
GND GND GND GND GND GND GND GND GND GND
1
C6017_RF
27PF
5% 2 16V NP0-C0G 01005
SYNC_MASTER=Sync
RADIO_TRANSCEIVER
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
8
7
6
5
4
3
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
TRANSCEIVER: TX PORTS
2
1
OMIT_TABLE
C6106_RF 27PF
9
1
50_XCVR0_TX_HMB1_B11_B21
2
50_XCVR0_TX_B11_B21_PA_IN
DEFAULT_CAPACITOR_22.000000pF_2_1
L6110_RF
C6116_RF
2.8NH-+/-0.1NH-0.36A
XCVR0_RF
9
1
50_XCVR0_TX_HMB2_B38_B40_B41
01005 1
70 67
IN
70 67
IN
70 67
IN
70 67
IN
SHIELD_XCVR0-1_TX_I_P SHIELD_XCVR0-1_TX_I_N SHIELD_XCVR0-1_TX_Q_P SHIELD_XCVR0-1_TX_Q_N
71 67
OUT
71 67
OUT
78 68
IN
78 68
IN
9 1
SHIELD_XCVR0_TX_FB_RX_I SHIELD_XCVR0_TX_FB_RX_Q
47 62
75_RFFE1_SCLK 75_RFFE1_SDATA
DEFAULT_CAPACITOR_1000pF_2_1
TX_BB_IP TX TX_BB_IM RADIO_TRANSCEIVER TX_BB_QP TX_BB_QM
RFFE_CLK RFFE_DATA
70 64
IN
1
SHIELD_WTR_19P2M_CLK
46
2
1
C6112_RF 1.0PF
OUT
79
OUT
80
16V CERM 01005
+/-0.05PF 16V NP0-C0G-CERM 01005
9
C6107_RF 27PF
9 9 9
9
L6111_RF
1
2
1
50_XCVR0_TX_FBRX_IN_UNBAL
01005
C6118_RF
1
1.5PF
2
50_XCVR0_TX_FBRX_IN
C6117_RF
2
50_XCVR0_TX_B1_B3_B4_B25_PA_IN 1
2% 16V CERM 01005 RADIO_TRANSCEIVER IN
L6102_RF 10NH-3%-140MA
73
01005 NOSTUFF RADIO_TRANSCEIVER
2% 16V CERM 01005 RADIO_TRANSCEIVER
1.5PF
+/-0.1PF 16V 2 NP0-C0G 01005-1
2
1
50_XCVR0_TX_HMB3_B1_B3_B4_B25
C6105_RF 27PF
3.0NH+/-0.1NH-200MA
9
1
+/-0.1PF 16V 2 NP0-C0G 01005 NOSTUFF
2 50_XCVR0_TX_B38_B40_B41_PA_IN
DEFAULT_CAPACITOR_1.200000pF_2_15%
C6113_RF
2
100_XCVR0_TX_FBRX_IN_WTR TX_FBRX_P 8 16 TX_FBRX_M NC
XO_IN
SHIELD_XCVR0_19P2M_CLK_WTR_IN
10% 6.3V X5R-CERM 01005
66 NC 59 NC 51 NC 44 NC 101 50_XCVR0_TX_HMB1_B11_B21 100 50_XCVR0_TX_HMB2_B38_B40_B41 50_XCVR0_TX_HMB3_B1_B3_B4_B25 93 50_XCVR0_TX_HMB4_B7_B30 86
TX_HMLB1 80 NC 50_XCVR0_TX_HMLB2_B34_B39 TX_HMLB2 74
C6110_RF
1000PF
TX_LB1 TX_LB2 TX_LB3 TX_LB4 TX_MHB1 TX_MHB2 TX_MHB3 TX_MHB4
TX_FBRX_BBI TX_FBRX_BBQ
1
1.2PF
WLPSP SYM 3 OF 5
D
22PF
2 50_XCVR0_TX_HMB2_B38_B40_B41_MATCH
WTR3925-2-TR-03-1 76 75 68 60
80
2% 16V CERM 01005 RADIO_TRANSCEIVER
DEFAULT_INDUCTOR_2.800000nH_2_1
D
OUT
2
DEFAULT_INDUCTOR_2.800000nH_2_1
+/-0.1PF 16V NP0-C0G 01005-1
DEFAULT_CAPACITOR_22.000000pF_2_1
L6109_RF
C6115_RF
2.8NH-+/-0.1NH-0.36A 9
1
50_XCVR0_TX_HMB4_B7_B30
2
22PF
1
50_XCVR0_TX_HMB4_B7_B30_MATCH
01005 1
C
50_XCVR0_TX_B7_B30_PA_IN
OUT
80
DEFAULT_CAPACITOR_1.200000pF_2_1 5%
C6114_RF
16V CERM 01005
1.2PF
2
2
+/-0.05PF 16V NP0-C0G-CERM 01005
C
C6108_RF 27PF 9
1
50_XCVR0_TX_HMLB2_B34_B39
2
50_XCVR0_TX_B34_B39_PA_IN
OUT
79
2% 16V CERM 01005 RADIO_TRANSCEIVER
C6101_RF 27PF 9
50_XCVR1_TX_HMLB1_G1800_G1900
1
2
50_XCVR1_TX_G1800_G1900_PA_IN
2% 16V CERM 01005 RADIO_TRANSCEIVER
OUT
79
1
L6101_RF 10NH-3%-140MA
01005 NOSTUFF RADIO_TRANSCEIVER
2
B C6102_RF 27PF
XCVR1_RF
9
WTR4905
50_XCVR1_TX_HMLB2_B8_B20_B26_B27
70 67 70 67
IN IN
70 67
IN
70 67
IN
68
IN
78 68
IN
TX_BB_IP TX_BB_IM
SHIELD_XCVR0-1_TX_Q_P SHIELD_XCVR0-1_TX_Q_N
3 8
TX_BB_QP TX_BB_QM
57
SHIELD_GSM_TX_PHASE
56 51
75_RFFE4_SDATA 75_RFFE4_SCLK
78 68
DEFAULT_CAPACITOR_1000pF_2_1
55
C6109_RF 70 64
IN
SHIELD_WTR_19P2M_CLK
SYM 2 OF 5
14 19
GP_DATA
TX
TX_DA1 TX_DA2 TX_DA3 TX_DA4 TX_DA5
1 50_XCVR1_TX_HMLB1_G1800_G1900 18 50_XCVR1_TX_HMLB2_B8_B20_B26_B27 12 NC 2 50_XCVR1_TX_HMLB4_B12_B13_B28 7 50_XCVR1_TX_HMLB5_G850_G900
TX_FBRX 31
50_XCVR1_TX_FBRX_IN
9
50_XCVR1_TX_B8_B20_B26_B27_PA_IN
OUT
80
OUT
80
OUT
79
1
L6103_RF 10NH-3%-140MA
01005 NOSTUFF RADIO_TRANSCEIVER
9
2
9 12
C6103_RF 27PF
RFFE_DATA RFFE_CLK
9
50_XCVR1_TX_HMLB4_B12_B13_B28
1
2
50_XCVR1_TX_B12_B13_B28_PA_IN
2% 16V CERM 01005 RADIO_TRANSCEIVER
XO_IN
2 SHIELD_XCVR1_19P2M_CLK_WTR_IN
5% 6.3V CERM 01005
1
C6111_RF 68PF
5% 2 25V NP0-C0G-CERM 01005
A
2
9
100PF 1
1
2% 16V CERM 01005 RADIO_TRANSCEIVER
WLNSP SHIELD_XCVR0-1_TX_I_P SHIELD_XCVR0-1_TX_I_N
B
C6104_RF 27PF
NOSTUFF
9
50_XCVR1_TX_HMLB5_G850_G900
1
2
50_XCVR1_TX_G850_G900_PA_IN
SYNC_MASTER=Sync
2% 16V CERM 01005 RADIO_TRANSCEIVER
SYNC_DATE=05/17/2016
OFFPAGE=TRUE PAGE TITLE
1
spare DRAWING NUMBER
L6104_RF 10NH-3%-140MA
Apple Inc.
01005 NOSTUFF RADIO_TRANSCEIVER
051-00419
REVISION
R
2
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
8
7
6
5
4
3
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
TRANSCEIVER: PRX, DRX, & GPS PORTS D
WTR3925-2-TR-03-1
WTR3925-2-TR-03-1
WLPSP
WLPSP 104 NC 96 NC 103 NC 95 NC 11 11 11 11 11 11 11 11 11 11
SYM 1 OF 5 PRX
PRX_LB1 PRX_LB2 PRX_LB3 PRX_LB4
RADIO_TRANSCEIVER
50_XCVR0_PRX_PMB1_B4 50_XCVR0_PRX_PMB2_B1_B4 50_XCVR0_PRX_PMB3_B3 50_XCVR0_PRX_PMB4_B34_B39 50_XCVR0_PRX_PMB5_B25 50_XCVR0_PRX_PMLB6_B11_B21
99 92 106 98 105 97
PRX_MB1 PRX_MB2 PRX_MB3 PRX_MB4 PRX_MB5 PRX_MLB6
50_XCVR0_PRX_PHB1_B7 50_XCVR0_PRX_PHB2_B40_EXT
73 65 85 79
PRX_HB1 PRX_HB2 PRX_HB3 PRX_HB4
50_XCVR0_PRX_PHB3_B38_B40_B41 50_XCVR0_PRX_PHB4_B30
D
XCVR0_RF
XCVR0_RF
PRX_CA1_BBI 69
SHIELD_XCVR0_PRX_CA1_I
OUT
67
PRX_CA1_BBQ 77
SHIELD_XCVR0_PRX_CA1_Q
OUT
67
PRX_CA2_BBI 39
SHIELD_XCVR0_PRX_CA2_I
OUT
67
PRX_CA2_BBQ 33
SHIELD_XCVR0_PRX_CA2_Q
OUT
67
NC NC NC NC
72
IN
72
IN
72
IN
72
IN
72
IN
72
72
NC
50_XCVR0_DRX_DMB2_B34 50_XCVR0_DRX_DMB3_B1_B4 50_XCVR0_DRX_DMB4_B39 50_XCVR0_DRX_DMB5_B3_B25 50_XCVR0_DRX_DMLB6_B11_B21
NC
50_XCVR0_DRX_DHB2_B7_B38_B41
IN
NC
50_XCVR0_DRX_DHB4_B30_B40
IN
10
NC
50_GPS_RX
5 12 4 11
DRX_LB1 DRX_LB2 DRX_LB3 DRX_LB4
15 22 7 14 6 13
DRX_MB1 DRX_MB2 DRX_MB3 DRX_MB4 DRX_MB5 DRX_MLB6
43 50 29 35
DRX_HB1 DRX_HB2 DRX_HB3 DRX_HB4
2 10
DNC GNSS_L1
SYM 2 OF 5 DRX_GPS
DRX_CA1_BBI 78
SHIELD_XCVR0_DRX_CA1_I
OUT
67
DRX_CA1_BBQ 70
SHIELD_XCVR0_DRX_CA1_Q
OUT
67
DRX_CA2_BBI 34
SHIELD_XCVR0_DRX_CA2_I
OUT
67
DRX_CA2_BBQ 40
SHIELD_XCVR0_DRX_CA2_Q
OUT
67
GNSS_BBI 18
SHIELD_GPS_RX_I
OUT
67
GNSS_BBQ 32
SHIELD_GPS_RX_Q
OUT
67
RADIO_TRANSCEIVER
GP_DATA 24 NC
C
C
XCVR1_RF WTR4905 WLNSP 11
50_XCVR1_PRX_PLB1_B12_B13_B20_B28_B29
11
50_XCVR1_PRX_PLB2_B8_B26_B27
NC 11 11
SYM 3 OF 5
17 11 6
PRX_LB1 PRX_LB2 PRX_LB3
4 10 5
50_XCVR1_PRX_PMB1_G1800 50_XCVR1_PRX_PMB2_G1900
NC
PRX_BBI 15
SHIELD_XCVR1_PRX_I
PRX_BBQ 20
SHIELD_XCVR1_PRX_Q
OUT
67
OUT
67
XCVR1_RF WTR4905 WLNSP
PRX_MB1 PRX_MB2 PRX_MB3
28 22
NC NC
PRX
72
IN
72
IN
50_XCVR1_DRX_DLB1_B12_B13_B20_B28_B29 50_XCVR1_DRX_DLB2_B8_B26_B27 NC
PRX_HB1 PRX_HB2
NC
50_XCVR1_DRX_DMB2_B3
11
NC NC NC
B
1
4
2
0201 GNSS
49 54 60
DRX_LB1 DRX_LB2 DRX_LB3
59 53
DRX_MB1 DRX_MB2
38 43
DRX_HB1 DRX_HB2
58
GNSS_IN
DRX_GPS
DRX_BBI 47
SHIELD_XCVR1_DRX_I
OUT
67
DRX_BBQ 36
SHIELD_XCVR1_DRX_Q
OUT
67
GNSS_BBI 46 SHIELD_XCVR0_TX_FB_RX_I
OUT
67 70
GNSS_BBQ 41 SHIELD_XCVR0_TX_FB_RX_Q
OUT
67 70
B
GPS FILTER
L6200_RF
120NH-5%-40MA PP_1V8_LDO14
SYM 1 OF 5
PLACE NEAR U_WTR
1 C6201_RF
0.1UF 20% 6.3V 01005 GNSS
2 X5R-CERM
7
GFILT_RF DEFAULT_RESISTOR_0.001OHM_2_1
IN
50_GNSS
1 RFIN
LGA
3 LNA_EN
R6201_RF RFOUT 9
50_DRX_GPS_LNA_OUT 1
GND
2 4 5 6 8
A
76
GLNA_RF SKY65766-13
1
C6204_RF 2.0PF
GNSS
+/-0.1PF 2 16V NP0-C0G 01005
NOSTUFF
0.00
0% 1/32W MF 01005
2
50_DRX_GPS_LNA_MATCH 1
GPS-GNSS
1 UNBAL_PRT
C6205_RF 2.0PF
+/-0.1PF 2 16V NP0-C0G 01005
L6201_RF 10NH-3%-0.170A
SAFGB1G56XA0F57 LGA UNBAL_PRT 4 GND 2 3 5 6
VDD
50_GPS_FILTER_OUT 1
C6203_RF 1.6PF
1
2
50_GPS_RX
10
01005 SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
+/-0.1PF 2 16V NP0-C0G 01005
spare DRAWING NUMBER
NOSTUFF
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
8
7
6
5
4
3
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2 L6318_RF
PRIMARY & DIVERSITY RECEIVE MATCHING
GSMRX_RF
DC BLOCKING CAP VALUES CANNOT BE MORE THAN 33PF
NOSTUFF
27PF
80
50_LAT_MLB_G1800_G1900_PA_RX
IN
2
1 COMMON
50_XCVR1_G1800_G1900_DIPLEX_OUT 1
5% 6.3V NP0-C0G 0201
1
GSM1800 4
50_XCVR1_G1800_DIPLEX_IN
GSM1900 3
50_XCVR1_G1900_DIPLEX_IN
+/-0.1PF 25V C0G-CERM 0201
L6319_RF
1
GND
3.6NH+/-0.1NH-0.5A
RADIO_TRANSCEIVER
RADIO_TRANSCEIVER
1
C6333_RF 2.0PF
RADIO_TRANSCEIVER OMIT_TABLE
1
2
+/-0.1PF 16V NP0-C0G 01005
80
1
IN
L6304_RF
27PF
80
1
50_XCVR0_B25_PA_PRX
IN
2
1
50_XCVR0_PRX_PMB5_B25_MATCH
C6305_RF
2% 16V CERM 01005 RADIO_TRANSCEIVER
1
RADIO_TRANSCEIVER
1
OMIT_TABLE
2
1
C6307_RF
2
10
2% 16V CERM C6352_RF 01005 27PF RADIO_TRANSCEIVER 2%
NOSTUFF
16V CERM 01005
2
C
50_XCVR0_PRX_PMB3_B3 10
0201
RADIO_TRANSCEIVER
3.0NH+/-0.1NH-0.6A 1
10
50_XCVR1_PRX_PLB2_B8_B26_B27
2
L6306_RF
50_XCVR0_PRX_PMB3_B3_MATCH
2% 16V CERM 01005 RADIO_TRANSCEIVER
1
1
50_XCVR0_PRX_PMLB6_B11_B21
2
1.9NH-+/-0.1NH-0.6A-0.12OHM
RADIO_TRANSCEIVER
27PF
IN
2
RADIO_TRANSCEIVER
2% 16V CERM 01005 RADIO_TRANSCEIVER
+/-0.05PF 25V C0G-CERM 0201
C6316_RF 80
1
C6306_RF 1
1
IN
27PF
2 50_XCVR1_PRX_PLB2_B8_B26_B27_MATCH 0201
27PF
2 50_XCVR0_PRX_PMLB6_B11_B21_MATCH
50_XCVR0_B3_PRX-DSPDT_OUT
1
50_XCVR1_B8_B26_B27_PA_PRX
C6315_RF
3.0PF
C
80
OMIT_TABLE
0201
C6329_RF
15NH-3%-0.3A-0.7OHM
L6305_RF
50_XCVR0_B11_B21_PA_PRX
10
16V CERM 01005
L6313_RF
2
6.2NH-3%-0.4A IN
50_XCVR1_PRX_PLB1_B12_B13_B20_B28_B29
2
RADIO_TRANSCEIVER
0201
OMIT_TABLE
80
2
10
0201
3.1NH-+/-0.1NH-0.5A-0.17OHM
1
NOSTUFF
50_XCVR0_PRX_PMB5_B25
2
D
2% 16V CERM 1 C6351_RF 01005 27PF RADIO_TRANSCEIVER 2%
RADIO_TRANSCEIVER
1.6NH-+/-0.1NH-1A-0.05OHM
27PF
2 50_XCVR1_PRX_PLB1_B12_B13_B20_B28_B29_MATCH 0201
C6314_RF
10
C6328_RF
20NH-3%-0.25A-0.8OHM 50_XCVR1_B12_B13_B20_B28_B29_PA_PRX
50_XCVR1_PRX_PMB2_G1900
2
2% 16V CERM 01005 RADIO_TRANSCEIVER OMIT_TABLE
OMIT_TABLE
2
L6312_RF
10
C6341_RF 27PF
2 50_XCVR0_PRX_PMB2_G1900_MATCH 0201
6 5 2
0201
2
2% 16V CERM 01005 RADIO_TRANSCEIVER
2 OMIT_TABLE
5.1NH-3%-0.4A
L6320_RF
D
1
C6332_RF 2.0PF
RADIO_TRANSCEIVER
OMIT_TABLE
RADIO_TRANSCEIVER
2 50_XCVR0_PRX_PMB1_G1800_MATCH 0201
OMIT_TABLE
LGA
R6301_RF 1
1
C6340_RF OMIT_TABLE 27PF 50_XCVR1_PRX_PMB1_G1800
OMIT_TABLE
5.1NH-3%-0.4A
GSM1800-1900 B8856
1
2 0201
RADIO_TRANSCEIVER
L6307_RF
C6342_RF
4.3NH+/-3%-0.5A
C6308_RF
0201
RADIO_TRANSCEIVER
L6308_RF
80
1
IN
1.9NH-+/-0.1NH-0.6A-0.12OHM IN
1
50_XCVR0_B34_B39_PA_PRX
2
2
+/-0.1PF 25V C0G-CERM 0201
L6309_RF
0201
C6318_RF IN
1
50_XCVR0_B7_PA_PRX
2
1
C6310_RF 79
IN
1
0.00
2
1
0.00
1
2
RADIO_TRANSCEIVER
1% 1/20W MF 0201
10
1
C6311_RF
2 0201
50_XCVR0_PRX_PHB4_B30
2
IN
50_XCVR0_B11_B21_PA_DRX
1
2
C6348_RF
3.0PF 1
1
L6323_RF
IN
1
50_XCVR0_B3_B25_DRX-DSPDT_OUT
50_XCVR0_DRX_DMLB6_B11_B21
L6321_RF
4.3NH+/-3%-0.5A
2 80
IN
50_XCVR0_B40_PA_PRX_EXT_FIL
1
2
3.2NH+/-0.1NH-0.5A 2
RADIO_TRANSCEIVER
27PF
1
1
2
2
50_XCVR1_DRX_DMB2_B3 10
5% 6.3V NP0-C0G 0201
0201
0201
2
50_XCVR0_DRX_DMB5_B3_B25 10
2% 16V CERM 01005 RADIO_TRANSCEIVER
C6346_RF 27PF 1
50_XCVR0_PRX_PHB2_B40_EXT_MATCH
2
SYNC_MASTER=Sync
SHUNT COMPONENT WITH BAND 40 FILTER
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
50_XCVR0_PRX_PHB2_B40_EXT
051-00419
REVISION
R
10
2% 16V CERM 01005 RADIO_TRANSCEIVER
RADIO_TRANSCEIVER
RADIO_TRANSCEIVER OMIT_TABLE
L6325_RF
27PF
1
C6344_RF
0201
OMIT_TABLE
10
RADIO_TRANSCEIVER
10
0201
2 50_XCVR1_DRX_DMB2_B3_MATCH
10
C6349_RF
1
50_XCVR1_DRX_DLB2_B8_B26_B27
2
C6338_RF
3.2NH+/-0.1NH-0.5A 50_XCVR0_DRX_DMB4_B39
2
1
RADIO_TRANSCEIVER
2 50_XCVR0_DRX_DMB5_B3_B25_MATCH
RADIO_TRANSCEIVER
+/-0.05PF 25V C0G-CERM 0201
IN
50_XCVR1_B3_DRX-DSPDT_OUT
0201
2% 16V CERM 01005 RADIO_TRANSCEIVER
0201
2
74
2.4NH+/-0.1NH-0.6A
6.2NH-3%-0.4A
50_XCVR0_DRX_DMLB6_B11_B21_MATCH
2% 16V CERM 01005 RADIO_TRANSCEIVER OMIT_TABLE
IN
1
50_XCVR0_B39_MBHB-DRX-ASM_OUT
L6322_RF
27PF
80
74
10
74
C6345_RF
L6324_RF
2.4NH+/-0.1NH-0.6A
10
27PF
RADIO_TRANSCEIVER
A
IN
1
50_XCVR1_B8_B26_B27_LB-DRX-ASM_OUT
50_XCVR0_DRX_DMB3_B1_B4
2
C6325_RF
2% 16V CERM 01005 RADIO_TRANSCEIVER
2.1NH-+/-0.1NH-0.6A-0.12OHM 1
IN
1
50_XCVR0_B1_B4_MBHB-DRX-ASM_OUT
C6337_RF 2% 16V CERM 01005 RADIO_TRANSCEIVER
2% 16V CERM 01005 RADIO_TRANSCEIVER
27PF
RADIO_TRANSCEIVER
74
C6320_RF
50_XCVR_PRX_PHB4_B30_MATCH
74
10
27PF
50_XCVR0_PRX_PHB3_B38_B40_B41
2
10
27PF
50_XCVR0_DRX_DMB2_B34
2
C6324_RF
2% 16V CERM 01005 RADIO_TRANSCEIVER
2.5NH+/-0.1NH-0.6A
2
IN
1
50_XCVR0_B34_MBHB-DRX-ASM_OUT
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
8
7
6
SHEET
IV ALL RIGHTS RESERVED
5
B
50_XCVR1_DRX_DLB1_B12_B13_B20_B28_B29
2
2% 16V CERM 01005 RADIO_TRANSCEIVER
27PF
L6301_RF
L6311_RF
IN
2% 16V CERM 01005 RADIO_TRANSCEIVER
27PF
C6319_RF
0201
50_XCVR0_B30_PA_PRX
10
2
1
1
50_XCVR1_B12_B13_B20_B28_B29_LB-DRX-ASM_OUT
C6323_RF
50_XCVR0_PRX_PHB1_B7
2
74
RADIO_TRANSCEIVER 50_XCVR0_PRX_PHB3_B38_B40_B41_MATCH
1% 1/20W MF 0201
80
27PF
74
0201
+/-0.1PF 25V C0G 201
10
C6336_RF
1.0PF
RADIO_TRANSCEIVER
50_XCVR0_B38_B40_B41_PA_PRX
1
C6302_RF
2% 16V CERM 01005
10
3.9NH+/-0.1NH-0.5A
50_XCVR0_PRX_PHB1_B7_MATCH
50_XCVR0_DRX_DHB4_B30_B40
2
2% 16V CERM 01005 RADIO_TRANSCEIVER
L6310_RF
RADIO_TRANSCEIVER
27PF
80
27PF
1
50_XCVR0_PRX_PMB4_B34_B39
2
10
C6335_RF
50_XCVR0_B30_B40_MBHB-DRX-ASM_OUT
IN
50_XCVR0_DRX_DHB2_B7_B38_B41
2
2% 16V CERM 01005 RADIO_TRANSCEIVER
25V +/-0.1PF C0G-CERM 0201
74
2% 16V CERM 01005 RADIO_TRANSCEIVER
2
0201
RADIO_TRANSCEIVER
27PF
C6301_RF
B
DC BLOCKING CAP VALUES CANNOT BE MORE THAN 33PF
27PF
1
2.2PF
10
1
C6334_RF
2 50_XCVR0_DRX_DHB2_B7_B38_B41_MATCH
C6350_RF
C6317_RF
3.3NH+/-0.1NH-0.5A 1
IN
1
50_XCVR0_B7_B41_B38_MBHB-DRX-ASM_OUT
50_XCVR0_PRX_PMB2_B1_B4
2
50_XCVR0_PRX_PMB4_B34_B39_MATCH
0201
74
2% 16V CERM 01005 RADIO_TRANSCEIVER
1.2PF 1
L6328_RF
3.0NH+/-0.1NH-0.6A
27PF
1
C6309_RF
RADIO_TRANSCEIVER
10
C6343_RF
2 50_XCVR0_PRX_PMB2_B1_B4_MATCH 0201
79
2
+/-0.1PF 25V C0G-CERM 0201
4.3NH+/-3%-0.5A
50_XCVR0_PRX_PMB1_B4
2
2% 16V CERM 01005 RADIO_TRANSCEIVER
1.2PF 1
50_XCVR0_B1_B4_PA_PRX
1
1
IN
27PF
2 50_XCVR0_PRX_PMB1_B4_MATCH
2
80
1
50_XCVR0_B4_PA_PRX
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
LOWER ANTENNA AND COUPLER JLAT1_RF
MM7829-2700 14 13 12 4
1 C6407_RF
1 C6409_RF
18PF 2% 2 16V CERM 01005
0.1UF 20% 2 6.3V X5R-CERM 01005
LATDI_RF
1
80
BI
80
BI
50_LAT_LB_COMBINER_IN 50_LAT_MB_HB_COMBINER_IN
6 LB 0805-LGA 4 MB-HB
ANT
LATCP_RF
2NH+/-0.1NH-0.6A 2
50_LAT_LB_MB_HB_COMBINER_OUT
1
2
50_LAT_LB_MB_HB_CPL_IN
0201
1 3 5
GND
1 C6403_RF
1 C6402_RF
18PF 2% 2 25V C0H-CERM 0201 NOSTUFF
18PF 2% 2 25V C0H-CERM 0201 NOSTUFF
NC
FL6402_RF
1 RFIN1 13 RFIN2
80 73 68
BI
80 73 68
IN
1
PP_1V8_LDO15 75_RFFE7_SDATA 75_RFFE7_SCLK
IN
2
LGA
RFOUT1 RFOUT2
2 14
RF_CPL1 RF_CPL2
4 16
D
50_LAT1_ANT
1 3
C6411_RF
1 C6410_RF
1
18PF 2% 25V 2 C0H-CERM 0201 NOSTUFF
+/-0.05PF 25V 2 C0G-CERM 0201
0.7PF
NOSTUFF
50_LAT_LB_MB_HB_CPL_ANT
NC
6 USID
10-OHM-1.1A
80 79 77 75 74 73 68 65
SKY16705-21
2 0201
VDD
R6401_RF
LFD21829MMY1E339
2
1.3NH+/-0.1NH-1.1A
9
D
F-ST-SM
R6402_RF
PP_2V7_LDO12
5 VIO 12 SDATA 8 SCLK
PP_1V8_LDO15_LATCP
01005
50_XCVR0_LAT_CPLD 50_XCVR1_LAT_CPLD
12 12
PP_2V7_LDO12
14 13 12 4
1 C6419_RF
1 C6420_RF
1 C6401_RF
18PF 2% 16V 2 CERM 01005
18PF 2% 16V 2 CERM 01005
0.033UF 20% 4V 2 X5R-CERM 01005
3 7 10 11 15
GND
USID=0X6
1 C6414_RF
8
18PF 2% 16V 2 CERM 01005
VDD
C
SWLATCP_RF
C 70
OUT
70
OUT
6 10
50_XCVR0_TX_FBRX_IN 50_XCVR1_TX_FBRX_IN 17 7 17 7
7 9
FBRX-DSPDT_CTL1 FBRX-DSPDT_CTL2
CXA4439GC-E
RF1 RF2
LGA-1
VCTL1 VCTL2
RF1A RF1B
5 4
50_XCVR0_LAT_CPLD 50_XCVR0_UAT_CPLD
RF2A RF2B
2 1
50_XCVR1_UAT_CPLD 50_XCVR1_LAT_CPLD
12 12 12 12
3
GND
UPPER ANTENNA COUPLER PP_2V7_LDO12
1
9
14 13 12 4
VDD
LFD21829MMY1E339
80 80
BI
50_UAT_LB_COMBINER_IN 50_UAT_MLB_COMBINER_IN
0805-LGA 6 LB OMIT_TABLE 4 MB-HB
ANT
2
1
50_UAT_LB_MLB_COMBINE 1 C6405_RF
GND 1 3 5
18PF 2% 25V 2 C0H-CERM 0201 NOSTUFF
R6400_RF 0.00
50_UAT_LB_MLB_CPL_IN
2
1% 1/20W MF 0201
19
FL6401_RF
74 73 68 65 80 79 80 73 68
BI
80 73 68
IN
IN
PP_1V8_LDO15 75_RFFE7_SDATA 75_RFFE7_SCLK
1
2 01005
RFOUT1 RFOUT2
2 14
RF_CPL1 RF_CPL2
4 16
LGA
18PF 2% 16V 2 CERM 01005
0.1UF 20% 6.3V 2 X5R-CERM 01005
2
50_UAT_LB_MLB_SOUTH
1% 1/20W 1 C6417_RF MF 0201 18PF 2% 25V 2 C0H-CERM 0201 NOSTUFF
1
C6418_RF
NOSTUFF
B
50_UAT_LB_MLB_CPL_OUT 50_UAT_MB_HB_CPL_ANT
PP_1V8_LDO15_UATCP
5 VIO 12 SDATA 8 SCLK
50_XCVR0_UAT_CPLD 50_XCVR1_UAT_CPLD
R6404_RF
12
1.3NH+/-0.1NH-1.1A
12
1
GND 0.033UF 20% 4V 2 X5R-CERM 01005
53 62
18PF 5% 2 16V CERM 01005
2
50_UAT_MB_HB_SOUTH
0201 1 C6400_RF
OUT
6 USID
10-OHM-1.1A
1 C6404_RF
18PF 77 75 2% 25V 2 C0H-CERM 0201 NOSTUFF
50_UAT_MB_HB_CPL_IN
1 RFIN1 13 RFIN2
SKY16705-21
1 C6408_RF
3 7 10 11 15
B
UATCP_RF
UATDI_RF
1 C6406_RF
R6405_RF 0.00
USID=0X7
A
OUT
53 62
C6416_RF
1 C6415_RF OMIT_TABLE
1
18PF 2% 2 25V C0H-CERM 0201 NOSTUFF
+/-0.1PF 2 25V C0G-CERM 201
0.3PF
OMIT_TABLE
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
7
6
5
4
DIVERSITY RECEIVE
3
2
1
LB DRX ASM
D
14 13 12 4
D
PP_2V7_LDO12 1 C6501_RF
1 C6505_RF
0.1UF 20% 6.3V 2 X5R-CERM 01005
18PF 2% 16V 2 CERM 01005
9
8
R6501_RF
VDD
NC
50_XCVR1_B8_B26_B27_LB-DRX-ASM_OUT
80 79 77 75 74 73 68 65
IN
78 74 68 BI 78 74 68
IN
2 12 3 11
VLB_RX0 VLB_RX1 LB_RX0 LB_RX1
LBDSM_RF
ANT 16 50_LAT-UAT_LB-DRX-ASM_ANT
HFQSWEWUA LGA
1
GND 1 C6514_RF
1 C6503_RF
18PF 2% 2 16V CERM 01005
0.033UF 20% 2 4V X5R-CERM 01005
2
50_LB_DRX
0201
C6507_RF
1
2.0PF +/-0.1PF
5 VIO 7 SDATA 6 SCLK
PP_1V8_LDO15 75_RFFE3_SDATA 75_RFFE3_SCLK
1
IN
80
C6510_RF
2.0PF
25V 2 C0G-CERM 0201
+/-0.1PF 2 25V C0G-CERM 0201
NOSTUFF
NOSTUFF
EPAD 19 20 21
11
50_XCVR1_B12_B13_B20_B28_B29_LB-DRX-ASM_OUT
1 4 8 10 13 14 15 17 18
11
3.9NH+/-0.1NH-0.5A
USID=0X9
C
C
MB HB DRX ASM 14 13 12 4
PP_2V7_LDO12 1 C6504_RF
3
SWDSM_RF
B
CXA4430GC-E LGA
RFIN
2
CTRL 1
5
GND
11
RX-DSPDT_CTL2
7 17
1 C6513_RF
18PF 2% 2 16V CERM 01005
80 79 77 75 74 73 68 65
IN
78 74 68
BI
78 74 68
IN
2 3 15 16 13 14
MIPI_VDD B3_B25_RX B1_B4_RX MHBDSM_RF D5315 B30_B40_RX LGA B7_B38/B41B_B41_RX B34_RX B39_RX
22 MIPI_VIO 20 MIPI_SDATA 21 MIPI_SCLK
PP_1V8_LDO15 75_RFFE3_SDATA 75_RFFE3_SCLK
R6502_RF ANT1 10
1
ANT2 8 GND
1
50_LAT_MB-HB-DRX-ASM_ANT1
C6508_RF
2.0PF
+/-0.1PF 2 25V C0G-CERM 0201
THRM_PAD
0
2
5% 1/20W MF 201
50_LAT_MB_HB_DRX 1
18PF 2% 2 16V CERM 01005
IN
80
C6511_RF
B
2.0PF
+/-0.1PF 2 25V C0G-CERM 0201
NOSTUFF 1 C6515_RF
23 24 25 26
11
4 RF1 6 RF2
50_XCVR1_B3_DRX-DSPDT_OUT 50_XCVR0_B3_B25_DRX-DSPDT_OUT
18PF 2% 2 16V CERM 01005
50_XCVR0-1_B3_B25_MBHB-DRX-ASM_OUT 50_XCVR0_B1_B4_MBHB-DRX-ASM_OUT 11 50_XCVR0_B30_B40_MBHB-DRX-ASM_OUT 11 50_XCVR0_B7_B41_B38_MBHB-DRX-ASM_OUT 50_XCVR0_B34_MBHB-DRX-ASM_OUT 11 50_XCVR0_B39_MBHB-DRX-ASM_OUT 11
VDD
11
1 C6506_RF
0.1UF 20% 2 6.3V X5R-CERM 01005
18
18PF 2% 16V 2 CERM 01005
1 C6502_RF
1 4 5 6 7 9 11 12 17 19
14 13 12 4
PP_2V7_LDO12
NOSTUFF
R6503_RF 1
50_UAT_MB-HB-DRX-ASM_ANT2
USID=0XA
1
C6509_RF
2.0PF
+/-0.1PF 2 25V C0G-CERM 0201
NOSTUFF
A
0
5% 1/20W MF 201
2
50_UAT_MB-HB-DRX-LNA_OUT_RX 1
C6512_RF
2
+/-0.1PF 25V C0G-CERM 0201
IN
75
2.0PF
NOSTUFF
SYNC_DATE=04/17/2015
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
DIVERSITY RECEIVE LNAS
3
2
1
LB DRX LNA 14
D 10
D
PP_MHBLN_RF
VDD 14
3
50_UAT_LB-DRX-LNA_TX_RX
LBLN_RF
TX_RX
ANT
SKY13702-17
14 50_UAT_LB-DRX-LNA_ANT
15
LGA
75
68
75
68
VIO SDATA SCLK GND
1 C6617_RF 1 C6619_RF 1 C6620_RF
1
50_UAT_LB_SPLIT_OUT
BI
50_UUAT_LB_MLB_NORTH
1
2
1% 1/20W 0201
50_UAT_LB_MLB_SPLIT_IN
1 C6601_RFMF
1 C6602_RF
18PF 2% 2 25V C0H-CERM 0201 NOSTUFF
18PF 2% 2 25V C0H-CERM 0201 NOSTUFF
2
LGA ANT OMIT_TABLE
2
GND
50_UAT_LB-DRX-LNA_TX_RX
14 13 12 4
1
PP_2V7_LDO12
1 C6614_RF
14
1 C6629_RF
1 C6625_RF
0.1UF 20% 6.3V 2 X5R-CERM 01005
18PF 2% 16V 2 CERM 01005
PP_MHBLN_RF
VDD 1
2.7NH+/-0.1NH-0.6A 1
2 01005
R6605_RF
50_UAT_MLB_SPLIT_OUT
C
FL6602_RF
150OHM-25%-200MA-0.7DCR
14
18PF 2% 25V 2 C0H-CERM 0201 NOSTUFF
18PF 2% 2 25V C0H-CERM 0201 NOSTUFF
LB 4 MB-HB 6
5 3 1
53
R6601_RF 0.00
R6606_RF 0.00
1 C6611_RF
LFD21829MMP5E222
USID=0X2
MB/HB DRX LNA
1% 1/20W MF 0201 OMIT_TABLE
UPPDI_RF
0.033UF 20% 2 4V X5R-CERM 01005
20
C
18PF 2% 2 16V CERM 01005
1 2 4 5 6 11 12 13 15 16 17 18 19 20 21 22
18PF 2% 2 16V CERM 01005
EPAD 23 24 25
9 7 8
PP_1V8_LDO15 BB_TO_UAT_DATA 62 BB_TO_UAT_DATA-53[I16] BI BB_TO_UAT_SCLK 62 BB_TO_UAT_SCLK-53[I16] IN
80 79 77 75 74 73 68 65
2
13
50_UAT_MLB-DRX-LNA_TX_RX
4 2
50_UAT1_WEST 50_UAT_MB-HB-DRX-LNA_OUT_RX
MHBLN_RF
IN_TX OUT_RX
ANT 16 50_UAT_MB-HB-DRX-LNA_ANT
SKY13703-19
15
LGA
14
0201
OMIT_TABLE 1
1.5PF
+/-0.05PF 2 25V C0G-CERM 0201
OMIT_TABLE
C6613_RF
10NH-3%-250MA 0201
75
68 68
75
VIO SDATA SCLK GND
EPAD
2 OMIT_TABLE
25 26 27 28
C6610_RF
IN
1 3 5 6 7 8 9 10 11 12 13 14 15 17 18 19 24
1
21 23 22
PP_1V8_LDO15 BB_TO_UAT_DATA 62 BB_TO_UAT_DATA-53[I16] BI BB_TO_UAT_SCLK 62 BB_TO_UAT_SCLK-53[I16] IN
80 79 77 75 74 73 68 65
USID=0X3
MLB DRX LNA
B
B
FL6603_RF
150OHM-25%-200MA-0.7DCR 1
PP_2V7_LDO12
2 01005
PP_MLBLN_RF 1 C6627_RF
1 C6622_RF
0.1UF 20% 2 6.3V X5R-CERM 01005
18PF 2% 2 16V CERM 01005
1
14 13 12 4
VDD 14
50_UAT_MLB-DRX-LNA_TX_RX
MLBLN_RF
6 OUT_RX
ANT 13
LMRX2HJB-H68
50_UUAT_MLB
15
LGA OMIT_TABLE
75
68
2 4 3
VIO SDATA SCLK
GND
EPAD
5 7 8 9 10 11 12 14
75
68
IN
15 16
PP_1V8_LDO15 BB_TO_UAT_DATA 62 BB_TO_UAT_DATA-53[I16] BI BB_TO_UAT_SCLK 62 BB_TO_UAT_SCLK-53[I16] IN
80 79 77 75 74 73 68 65
USID=0X4
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
UPPER ANTENNA FEEDS D
D OMIT_TABLE R6708_RF 75
BI
50_UAT_LB-DRX-LNA_ANT
0.00
1
2
50_UUAT_LB_PLEXER
1% 1/20W MF 0201 UP_RFFE
1 C6726_RF
UAT1
18PF
2% 25V 0201 UP_RFFE NOSTUFF
2 C0H-CERM
OMIT_TABLE R6710_RF 1
2
1% 1/20W MF 0201 UP_RFFE
OMIT_TABLE R6703_RF 75
BI
50_UAT_MB-HB-DRX-LNA_ANT
1
0.00
2
1% 1/20W MF 0201 UP_RFFE
C
50_UUAT_MLB_PLEXER 1 C6728_RF
18PF
2% 25V 2 C0H-CERM 0201 UP_RFFE NOSTUFF
10 8 14 1 17
LB MLB MB-HB WIFI GNSS
F-RT-SM
PPLXR_RF
ACFM-W312-AP1
R6705_RF
LGA OMIT_TABLE
ANT 5
1
50_UAT1
2
R6715_RF
50_UAT1_MATCH
1
0.00
2
1
50_UAT1_TEST
1% 1/20W MF 0201 UP_RFFE
1% 1/20W MF 0201 UP_RFFE
50_UUAT_HB_PLEXER 1 C6711_RF
GND
18PF
2% 2 25V C0H-CERM 0201 UP_RFFE NOSTUFF
0.00
50_UAT1_TUNER
C
R
2
TO ANTENNA TUNER BI
53 62
GND UP_RFFE
3
50_UUAT_MLB
1
EPAD
1
C6713_RF
L6700_RF
18PF
19
BI
JUAT1_RF
MM8830-2600B
2 3 4 6 7 9 11 12 13 15 16 18
75
0.00
2% 2 25V C0H-CERM 0201
56NH-100MA-3.9OHM
C
0201
UP_RFFE NOSTUFF
NOSTUFF 2
62
53
50_UAT_WLAN_2G_WEST_PLEXER
BI
R6709_RF 71
50_GNSS
1
0.00
2
1% 1/20W MF 0201 UP_RFFE
50_GNSS_PLEXER 1 C6727_RF
18PF 2%
2 25V C0H-CERM
0201 UP_RFFE NOSTUFF
B
B
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
PMU: ET MODULATOR D
D
C
18
19 18
19 18
PP_VPA_APT
PP_1V8_LDO15
IN
PP_QPOET_VCC_PA PP_VDD_MAIN
PP_PA_VBATT
1
C6801_RF
IN
67
IN 17 7 17
75_RFFE2_SCLK 7 75_RFFE2_SDATA
2 3 17 16
AMP_IN+ AMP_IN-
20% 6.3V 2 X5R-CERM 0201-1
VDD_VBATT 12 VDD_VBATT 13
VDD_LDO 24 VDD_LDO 25
VDD_BUCK 20 VDD_BUCK 21
VDD_1P8 15
VCC_PA_GSM 7 VCC_PA_GSM 8
SHIELD_ET_DAC_P SHIELD_ET_DAC_N
VCC_PA_ET 5 VCC_PA_ET 6
PA_VBATT 10
2.2UF
67
C
65 68 73 74 75 79 80
TRIM_14 TRIM_18
26 23
USID_LSB
19
QPOET_RF
2103-601507-10
SCLK SDATA
LGA
1
C6802_RF
1
C6803_RF
2
20% 6.3V X5R-CERM 0201-1
C6804_RF
1
C6805_RF
2
20% 6.3V X5R-CERM 0201-1
2
20% 6.3V X5R-CERM 0201-1
81
2.2UF
2.2UF
2.2UF
2.2UF
20% 6.3V 2 X5R-CERM 0201-1
1
53 62 64 65 77
NC
4 11 18 27 28 29 30 31 32 1 9 14 22
GND
B
B
DESENSE CAPS 81
77 65 64 62 53
IN
PP_VDD_MAIN 1
C6806_RF
1
C6807_RF 27PF
100PF
2
5% 16V NP0-C0G 01005
2
2% 16V CERM 01005
PLACE C6806 AND C6807 NEAR THE QPOET
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
8
7
6
5
4
3
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
MLB TEST POINTS D
PP7000_RF SM
75_RFFE1_SDATA
7 9
PP
OMIT
1
7 9 PP
OMIT P2MM-NSM
1 3 20
75_RFFE2_SDATA
OMIT
PP
1
NFC_TO_BB_CLK_REQ
P2MM-NSM
PP
1 3
SM
7 16
OMIT
PP
1
PP
7 13
PP
P2MM-NSM PP
1
75_RFFE3_SCLK
7 13
SM
75_RFFE4_SDATA
7 9
SM
3 6 PP
3 6
PP
1
SM
UART_BB_TO_AOP_RXD
1 7 PP
BB_TO_LAT_ANT_DATA
PP
1 7
SHIELD_SLEEP_CLK_32K
P2MM-NSM
P2MM-NSM PP
3 6
AP_TO_BB_TIME_MARK
SM
PP
BB_TO_LAT_ANT_SCLK
PP
OMIT
PP
1
PP6935_RF
SM
1 7 PP
75_RFFE6_SCLK
PP
PP6917_RF
7 18 19
OMIT
1
1 7 PP
PP6936_RF
PP
90_USB_BB_DATA_N
1 6 20
SM
75_RFFE6_SDATA
PP6978_RF
PP7500_RF
SM
SM
P2MM-NSM
1 7 20
OMIT
P2MM-NSM 1
UART_BB_TO_WLAN_COEX
1
OMIT
SM
1
ICEFALL
SM
AP_TO_BB_COREDUMP
OMIT
P2MM-NSM
1 6 20
P2MM-NSM
SM
SM
90_USB_BB_DATA_P
PP6977_RF
P2MM-NSM
P2MM-NSM
1
OMIT
PP6931_RF
OMIT
7 20
P2MM-NSM
BB_TO_AP_RESET_DETECT_L
OMIT
BB_TO_STROBE_DRIVER_GSM_BURST_IND 1 7
SIM1_CLK
PP6974_RF
SM
SM
1 7
1
OMIT
P2MM-NSM 1
7 20
P2MM-NSM
1 7
OMIT
P2MM-NSM
SIM1_RST
PP6973_RF
SM
1
1
OMIT
PP6929_RF
PP6933_RF
SM
7 20
SM
PP6930_RF
PP6904_RF
SIM1_DETECT
P2MM-NSM
OMIT
OMIT
1
OMIT
PP
1
C
PP6972_RF
SM
SM
7 20
P2MM-NSM
1 3
P2MM-NSM
P2MM-NSM
SIM1_IO
PP6969_RF
OMIT
BB_TO_NFC_CLK
1
OMIT
P2MM-NSM
PP6914_RF
PP6903_RF
PP
P2MM-NSM
OMIT
7 9
OMIT
B
PP6953_RF
SPMI_DATA
SM
1
1 3
SIM
3 6
SM
75_RFFE4_SCLK
1
1
SM
PP
1
SPMI_CLK
P2MM-NSM
SM
1
1
PP6926_RF
XO_OUT_D0_EN
7
PMU_TO_BBPMU_RESET_L
PP
1
P2MM-NSM
AP_TO_ICEFALL_FW_DWLD_REQ
1 20
OMIT
7 18 19
PP6918_RF
OMIT
P2MM-NSM
PP6938_RF
SM
PP
1
UART_WLAN_TO_BB_COEX
SM
1 7 20
PP
1
RX-DSPDT_CTL2
PP7501_RF SM
1
SIM1_SWP
20
PCIE
PP
1
1
1
NFC_SWP_MUX
1 20
P2MM-NSM
SE2_SWP
20
SM
1
PP
OMIT
90_PCIE_AP_TO_BB_REFCLK_P
PP
PP7502_RF
SM
SM
B
OMIT
PP6980_RF PP
1 20
P2MM-NSM
P2MM-NSM
P2MM-NSM
SE2_READY
SM
OMIT
OMIT
1
PP6979_RF PP
7 13
PP
OMIT
P2MM-NSM
P2MM-NSM
OMIT
PP6915_RF
2
FAST_BOOT_SELECT1 FAST_BOOT_SELECT0
1 7
PP6913_RF
P2MM-NSM
PP
BB_TO_PMU_PCIE_HOST_WAKE_L
SM
PP
1
1
1% 1/32W MF 01005 RADIO_DEBUG
OMIT
7 12
P2MM-NSM
3 6
OMIT
PP6942_RF
PP
1
PP6912_RF PP
OMIT
1
50_MDM_PCIE_CLK
P2MM-NSM
P2MM-NSM
PP
FBRX-DSPDT_CTL2
OMIT
PP6941_RF 1
1
OMIT
OMIT
PP
PP
PP6925_RF
SM
SM
PP
SM
1% 1/32W MF 01005 RADIO_DEBUG
OMIT
PP6911_RF
P2MM-NSM
C
1
7
P2MM-NSM
SM
PP6940_RF
2
PP6900_RF
P2MM-NSM
OMIT
PP
OMIT
7 12
PP6924_RF
SM
75_RFFE3_SDATA
1 3 20
OMIT
3 7
P2MM-NSM 1
AP_TO_BBPMU_RADIO_ON_L
R6922_RF 10K
SM
OMIT
PP6939_RF
FBRX-DSPDT_CTL1
1
1
R6921_RF 10K
P2MM-NSM PP
SIM1_REMOVAL_ALARM
NOSTUFF 1
PP6923_RF
P2MM-NSM
75_RFFE2_SCLK
D
OMIT
PP6909_RF
SM
1
SM
OMIT
PP6944_RF
PP
P2MM-NSM
SM
PP_1V8_LDO6
SM
PP6921_RF
P2MM-NSM
7 16
20 7 6 5 4 3 6
P2MM-NSM
OMIT
PP6908_RF
SM
1
PMU_TO_BB_USB_VBUS_DETECT
PMIC_RESOUT_L
PP6905_RF
SM
PP
1
OMIT
6 20
P2MM-NSM
OMIT
PP6943_RF 1
1
BB_JTAG_RST_L
PP6920_RF
SM
75_RFFE1_SCLK
1
PP
OMIT
P2MM-NSM
SM
PP
6
PP6907_RF
P2MM-NSM
PP
SWD_AP_TO_BB_CLK_BUFFER
PP
OMIT
PP6952_RF PP
1
SM
SM
SM
1
P2MM-NSM
P2MM-NSM
P2MM-NSM
DEFAULT FAST_BOOT[2:0] USB = 0X2
PP6945_RF
PP6919_RF
PP6906_RF
P2MM-NSM PP
BOOT CONFIG
BBPMU
BASEBAND
1
SE2_PWR_REQ
1 20
OMIT
PP6981_RF
1 6
P2MM-NSM
OMIT
SM
PP
PP6916_RF
1
ICEFALL_LDO_ENABLE
1 20
OMIT
P2MM-NSM SM
PP
1
90_PCIE_AP_TO_BB_REFCLK_N
1 6
OMIT
PCIE GND PP6970_RF
PP6971_RF
SM
SM
P2MM-NSM
A
PP
OMIT
1
P2MM-NSM PP
1
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
OMIT
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
TDD TRANSMIT 2G PA
D
D
FL7001_RF 600-OHM-25%-0.1A
PP_PA_VBATT
1
19 16
2
PP_VPA_APT
2GPA_VBATT
16
0201-1
C7004_RF 1.0UF
C7005_RF
5% 16V 2 NP0-C0G 01005
VBATT
SKY77363 IN
50_XCVR1_TX_G850_G900_PA_IN
7 LBRFIN
70
IN
50_XCVR1_TX_G1800_G1900_PA_IN
12 HBRFIN
80 79 77 75 74 73 68 65
IN
80 79 78 68
BI
80 79 78 68
IN
11 VIO 9 SDATA 10 SCLK
C7017_RF
GND
2 4 5
1
LGA
27PF
1 C7008_RF 1 C7001_RF
20% 6.3V 2 X5R-CERM 0201-1
20% 6.3V 2 X5R-CERM 0201-1
18PF 2% 16V 2 CERM 01005
2.2UF
0.1UF 20% 6.3V 2 X5R-CERM 01005
C7011_RF 27PF 1
50_TX_G850_G900_PA_OUT
LBRFOUT
1
HBRFOUT
6
1 C7009_RF
18PF 2% 2 25V C0H-CERM 0201 NOSTUFF
5% 2 16V NP0-C0G 01005
5% 6.3V NP0-C0G 0201
1
50_TX_G1800_G1900_PA_OUT 1 C7010_RF
USID=0X5
2
C7012_RF 27PF
EPAD 13
70
C
1 C7007_RF
VCC
GSMPA_RF
PP_1V8_LDO15 75_RFFE6_SDATA 75_RFFE6_SCLK
1 C7006_RF
2.2UF
27PF
8
20% 6.3V 2 X5R 0201-1
1
3
1
18PF 2% 25V 2 C0H-CERM 0201 NOSTUFF
2
5% 6.3V NP0-C0G 0201
50_TX_G850_G900_PA_OUT_M OUT
80
1 C7013_RF
18PF 2% 2 25V C0H-CERM 0201 NOSTUFF
C
50_TX_G1800_G1900_PA_OUT_M OUT
MB HB TDD PA
80
1 C7014_RF
18PF 2% 25V 2 C0H-CERM 0201 NOSTUFF
PP_1V8_LDO15 75_RFFE6_SDATA 19 16
IN BI
65 68 73 74 75 77 79 80 68 78 79 80
PP_QPOET_VCC_PA
MLB_PA_VBATT
75_RFFE6_SCLK
IN
0.00
1
+/-0.1PF 16V NP0-C0G 01005
C7015_RF 5.6PF
+/-0.1PF 2 16V NP0-C0G 01005
SCLK 13
SDATA 12
VIO 14
VCC2 9
VCC1 8
VBATT 11 IN
3
RFIN_MB
IN
50_XCVR0_TX_B38_B40_B41_PA_IN
5
RFIN_HB
72
OUT
50_XCVR0_B38_B40_B41_PA_PRX
27
RX_B38_B40_B41
72
OUT
50_XCVR0_B34_B39_PA_PRX
25
RX_B34_B39
70
2
TDDPA_RF
50_XCVR0_TX_B34_B39_PA_IN
70
68 78 79 80
R7002_RF
TDD_PAD_VCC1
B
C7016_RF
5.6PF
1 1/32W
19
01005
20% MF
1
B
AFEM-8065-AP1 LGA-1 ANT
GND
16 50_TDD_PA_ANT_M
OUT
80
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
1 2 4 6 7 10 15 17 19 21 22 24 26 28 23 20 18
THRM_PAD
USID=0XF A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
7
6
0.00
0% 1/32W MF 01005
1
1.0UF
18PF 2% 16V 2 CERM 01005
70
IN IN
50_XCVR1_TX_B8_B20_B26_B27_PA_IN
2
50_XCVR1_TX_B12_B13_B28_PA_IN
3
LB_SNUBBER
1
C7130_RF
1
C7126_RF
1 C7127_RF
5% 16V 2 NP0-C0G-CERM 01005
0.033UF 20% 4V 2 X5R-CERM 01005 NOSTUFF
33PF
2% 6.3V 2 NP0-C0G 01005
NOSTUFF
NOSTUFF
1
C7101_RF
10% 10V 2 CERM 01005
2
1
1/32W MF 01005
74
72
IN
18
OUT
50_LB_DRX
12
LB_DIV
50_XCVR1_B8_B26_B27_PA_PRX
26
LB_RX0
25
LB_RX1
24
VLB_RX0
OUT
NC 72
OUT
50_XCVR1_B12_B13_B20_B28_B29_PA_PRX
NC
23
PP_1V8_LDO15 75_RFFE7_SDATA 75_RFFE7_SCLK
2 01005
0% 1
C7128_RF
1 C7129_RF
1 C7133_RF
5% 16V 2 NP0-C0G-CERM 01005
0.033UF 20% 4V 2 X5R-CERM 01005 NOSTUFF
0.033UF 20% 4V 2 X5R-CERM 01005
1
50_LAT_LB_PA_ANT
2
50_LAT_LB_COMBINER_IN
1
C7111_RF
2
IN
68 73
C7120_RF 824-915
+/-0.1PF 25V C0G 201
OMIT_TABLE
2
ANT2 14 1
50_UAT_LB_PA_ANT
VLB_RX1
R7102_RF 0.00
1 C7112_RF
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
50_UAT_LB_COMBINER_IN
BI
73
824-915
1 C7121_RF
18PF 2% 2 25V C0H-CERM 0201 NOSTUFF
18PF 2% 2 25V C0H-CERM 0201 NOSTUFF
THRM_PAD
1 4 5 6 11 13 15 17 19 20 21 22 27 28 29 30 31 32 33 34 35 36 37 38 39 42
2
1% 1/20W MF 0201
NOSTUFF
USID=0XD
R7131_RF 1.00
PP_QPOET_VCC_PA
19 18 16
1% 1/32W MF 2 01005
DEFAULT_RESISTOR_0.001OHM_2_1
MLB_TDD_SNUBBER
R7113_RF 0.00
2
18
0% 1/32W MF 01005
1
C7113_RF
1 C7114_RF
1.0UF
18PF 2% 16V 2 CERM 01005
20% 6.3V X5R 0201-1
RXFIL_RF BAW-B40F-RX
70
QM21140 LGA
IN
2
50_XCVR0_TX_B11_B21_PA_IN
C
C7131_RF
18PF 2% 16V 2 CERM 01005
2% 2 6.3V NP0-C0G 01005
68PF
PP_1V8_LDO15 75_RFFE6_SDATA 75_RFFE6_SCLK
NOSTUFF
VBATT 25
2
MLB_PA_VBATT
1
VIO 22
1
PP_PA_VBATT
1 C7117_RF
VCC2 27
19 18 16
VCC1 28
C
IN BI IN
65 68 73 74 75 77 79 80 68 78 79 80 68 78 79 80
MLBPA_RF HRPDAF025
RFIN_MLB
LGA
1 B40RXOUT
1
OMIT_TABLE
B40ANT 4
50_XCVR0_B40_PA_PRX_EXT_FIL
OUT
MLB PA
6 5 3 2
1
L7122_RF
L7123_RF 1.0PF
4.7NH-3%-0.270A
72
+/-0.1PF 2 16V NP0-C0G 01005
01005
R7105_RF 0.00
OUT
72
OUT
50_XCVR0_B11_B21_PA_PRX
20
50_XCVR0_B11_B21_PA_DRX
18
ANT1 14
50_LAT_MLB_PA_ANT
ANT2 12
50_UAT_MLB_PA_ANT
50_LAT_MLB_G1800_G1900_PA_RX
2
BI
1% 1/20W MF 0201 OMIT_TABLE
72
GND 1
68 73
BI
73
1.0PF
22NH-3%-0.25A
ANT1 16
BI
1
50_XCVR0_B40B_PA_PRX
65 68 73 74 75 77 79 80
D
2% 25V C0H-CERM 0201
1
GND
19
IN
18PF
LB PA
2G_TX
1
R7101_RF
LGA1
50_TX_G850_G900_PA_OUT_M
2
33PF
0201
79
0.00
NOSTUFF
SKY78100-14
RFIN1
0%
1/32W MF 01005
180PF
LBPA_RF RFIN0
0.00
1
68PF
LB_PAD_VCC1
VBATT 7
D
18PF 2% 16V 2 CERM 01005
0% 1/32W MF 2 01005
1 C7104_RF
C7103_RF
20% 6.3V 2 X5R 0201-1
70
1 C7105_RF
1
LB_PA_VBATT R7108_RF DEFAULT_CAPACITOR_1e+06pF_2_1 0.00
2
R7111_RF
SCLK 9
1
VIO 10
PP_PA_VBATT
VCC1 41
19 18 16
R7112_RF 1
PP_1V8_LDO15_PA 75_RFFE7_SDATA_PA 75_RFFE7_SCLK_PA
1% 1/32W MF 2 01005
DEFAULT_RESISTOR_0.001OHM_2_1
2
10-OHM-1.1A
1.00
DEFAULT_RESISTOR_0.001OHM_2_1
R7107_RF
R7130_RF
SDATA 8
PP_QPOET_VCC_PA
3
R7114_RF
NOSTUFF 1
VCC2 40
19 18 16
4
SCLK 23
FDD TRANSMIT
5
SDATA 24
8
1 C7122_RF
18PF 2% 2 25V C0H-CERM 0201 NOSTUFF
R7106_RF
PRX
1.8NH+/-0.1NH-0.8A
DRX
1
2
2
1428-1463
1428-1463 50_UAT_MLB_COMBINER_IN BI
73
0201
B
DEFAULT_RESISTOR_0.001OHM_2_1
MBHB_SNUBBER
R7109_RF
1 C7108_RF
1.0UF
18PF 2% 16V 2 CERM 01005
70
IN
70
IN
79 80 72
74
A
IN OUT
OUT 19
72
OUT
11 11 72
OUT
72
OUT
72
7 8
50_TDD_PA_ANT_M 50_LAT_MLB_G1800_G1900_PA_RX
RFIN_GSM RFIN_MB RFIN_HB
10 11
MB_HB_DRX DCS_PCS_RX
50_XCVR0_B1_B4_PA_PRX 50_XCVR0_B3_PRX-DSPDT_OUT 50_XCVR0_B7_PA_PRX
1 3 5 17 19 21
RX_B1 RX_B3 RX_B7 RX_B4 RX_B25 RX_B30
50_XCVR0_B4_PA_PRX 50_XCVR0_B25_PA_PRX 50_XCVR0_B30_PA_PRX
PP_1V8_LDO15 75_RFFE6_SDATA 75_RFFE6_SCLK
NOSTUFF
BI IN
65 68 73 74 75 77 79 80 68 78 79 80 68 78 79 80
27
28
IN
MBHBPA_RF
R7103_RF
1.8NH+/-0.1NH-0.8A
AFEM-8055-AP1 LGA
TRX2 TRX3
50_LAT_MB_HB_DRX 50_XCVR0_B40B_PA_PRX
2% 6.3V NP0-C0G 01005
SCLK
34 31 32
2
68PF
MBHB_FDD_PAD_VCC1
VBATT
50_TX_G1800_G1900_PA_OUT_M 50_XCVR0_TX_B1_B3_B4_B25_PA_IN 50_XCVR0_TX_B7_B30_PA_IN
IN
0% 1/32W MF 2 01005
C7132_RF
26
20% 6.3V X5R 0201-1
29
2
C7106_RF
0.00
18PF 2% 16V 2 CERM 01005
VIO
1
R7110_RF
1
38
0% 1/32W MF 01005
79
1
MBHB_FDD_PA_VBATT DEFAULT_CAPACITOR_1e+06pF_2_1
1 C7110_RF
VCC2
2
37
1
VCC1
PP_PA_VBATT
19 18 16
0.00
B
OMIT_TABLE
USID=0XB
1% 1/32W MF 2 01005
SDATA
PP_QPOET_VCC_PA
C7123_RF
+/-0.05PF 2 25V CERM 0201
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
1 3 4 5 6 7 8 9 10 11 13 15 16 17 19 21 26
R7132_RF 1.00
19 18 16
1
0.6PF
NOSTUFF 1
OMIT_TABLE
THRM_PAD
GND
1
50_LAT_MB_HB_PA_ANT
2 50_LAT_MB_HB_COMBINER_IN 0201
MB/HB PA
ANT1
14
ANT2
13
1 C7124_RF
2NH+/-0.1NH-0.6A 1
2
18PF 2% 2 25V C0H-CERM 0201 NOSTUFF
OMIT_TABLE
C7119_RF
2
OMIT_TABLE
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
2 4 12 15 16 18 20 22 23 24 25 30 33 35 36 39 40 41 42 6 9
EPAD
+/-0.05PF 25V C0G 0201
SYNC_DATE=05/17/2016
PAGE TITLE BI
spare
73
1710-2690
DRAWING NUMBER
1 C7125_RF
18PF 2% 25V 2 C0H-CERM 0201 NOSTUFF
0.1PF
SYNC_DATE=04/17/2015
SYNC_MASTER=Sync
50_UAT_MB_HB_CPL_IN
0201 1
73
BI
1710-2690
1 NOSTUFF C7118_RF 18PF 2% 2 25V C0H-CERM 0201 R7104_RF
50_UAT_MB_HB_PA_ANT
GND
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
USID=0XE 8
72 80
7
6
5
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A
8
7
6
5
4
3
2
1
SWP MUX
ICEFALL
D PP1V8_ICEFALL_LDO
20
20 7 1
1 C7501_RF
1 7 20
1
R7506_RF 4.99K 1% 1/32W MF 2 01005 NFC OMIT_TABLE 53
OUT
SE2_PRESENT
B3 A3 B1 A1 A2
NC NC NC NC NC 78
NC
62 53 78
1 C7524_RF
1UF 20% 10V 2 X5R 0201 SE2
IN
53
53 62
78
53 62
78
IN
NFC_SWP
1
2
IN
ICEFALL LDO
NC
SE2LDO_RF
SE2 OMIT_TABLE
17 1
1 C7530_RF
2.2UF
20% 2 6.3V X5R-CERM 0201-1 SE2 OMIT_TABLE
R7511_RF 68 62 53
IN
0.00
1
PP1V8_SDRAM
1% 1/20W MF 0201 NOSTUFF
2
PP1V8_ICEFALL_LDO
20
LP5907UVX-1.825-S DSBGA A1 VIN VOUT A2
PP_VDD_MAIN
20 16 4 3 1
OMIT_TABLE
81
17 20
OMIT_TABLE
B5 D5 C4 D1
1% 1/32W MF 2 01005
SIM1_SWP
NFC_SWP_R
VSS VSS VSS VSS
R7512_RF
B0 3
0% 1/32W MF 01005 NFC
17 20
SE2_PWR_REQ
17 20
VER 1
R7510_RF 0.00
NC NC SE2_SWP
SE2_SWP
GND 2
4 A
AP_TO_ICEFALL_FW_DWLD_REQ
TCAL_CLK B2
SWPMX_RF
NLAS3257CMX2TCG DFN 6 S B1 1 5 VCC
OMIT_TABLE
REG_PU D3
NFC_SWP_MUX
IN
0.1UF 20% 6.3V 2 X5R-CERM 01005 SE2
OMIT_TABLE
DWP E2 SWP E3
10K
C
1UF 20% 2 10V X5R 0201 SE2
DB_RX B4 DB_TX A4
WLBGA
C1 NC 1
1C7523_RF
VDDO_NFC E1
SE2_RF
PP1V8_SDRAM 1 C7525_RF
62
BCM20211CP
SPI_CLK SPI_CS SPI_INT SPI_MISO SPI_MOSI
E4 GPIO_0 D4 GPIO_1
SE2_READY
62 53
VDDO_HOST_2 A5
PP1V8_SDRAM
VDDC C5 VDDC E5
OMIT_TABLE
NOSTUFF
VDD1P8_BYP D2
1UF 20% 10V 2 X5R 0201 SE2
VDD1P2 C2
0.1UF 20% 2 6.3V X5R-CERM 01005 SE2 OMIT_TABLE
1UF 20% 10V 2 X5R 0201 SE2
VDD1P8 C3
1C7528_RF
1C7201_RF
VDD_SE2_1V8 VOLTAGE=1.80V VDD_SE2_1V2 VOLTAGE=1.20V
B1 VEN
ICEFALL_LDO_ENABLE
PP1V8_ICEFALL_LDO
20
C
GND
1 C7529_RF
B2
D
2.2UF
20% 6.3V 0201-1 SE2 OMIT_TABLE
2 X5R-CERM
1
C7531_RF
100PF
2
5% 6.3V CERM 01005
OMIT_TABLE
DEBUG CONNECTOR
SIM CARD CONNECTOR 20 17 7
SIM1_IO
20 17
SIM1_SWP J_DEBUG
20-5857-036-001-829 1
DZ6905_RF SG-WLL-2-2 9
SIM_DETECT 8
SIM_DETECT_GND
SIM1_DETECT
OUT
2 81 78 68
3
SIM1_CLK
IN
CLK
IO 7
J_SIM_RF
SIM1_IO
BI
DZ6902_RF SG-WLL-2-2
ESD202-B1-CSP01005
68 78 81
41
1
SIM
20 5 4
SIM1_RST
IN
1
VDD_SIM1 1 C6900_RF
B
F-RT-SM SIM
DZ6901_RF 2
SIM1_SWP 2
VCC
GND
1
2.2UF
20% 6.3V 2 X5R-CERM 0201-1 SIM
RESET
2
SIM
68 78 81
20 17 7
12V-33PF 01005-1
20 17 7
78
67 62 53
78
67 62 53 64 62 53
BI BI OUT
SIM
64
100PF
1
5% 2 16V NP0-C0G 01005 SIM
1
DZ6903_RF SG-WLL-2-2
ESD202-B1-CSP01005 SIM
67
DZ6904_RF SG-WLL-2-2
67
62 53 62 53 62 53
OUT OUT OUT
1% 1/32W MF 2 01005 SIM
2
4 1
6
7
8
9
10
11
12
13
14
15
16
AP_TO_BB_RESET_L
17
18
SWD_AP_TO_MANY_SWCLK SWD_AOP_BI_BB_SWDIO
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
39
40
PP_VDD_BOOST
VDD_SIM1 SIM1_RST SIM1_CLK SIM1_IO SIM1_SWP SIM1_DETECT
4 5 20
IN IN BI
68 78 81 68 78 81 68 78 81
17 20
OUT
68 78 81
B
BB_JTAG_RST_L UART_BB_TO_WLAN_COEX UART_WLAN_TO_BB_COEX
OUT IN IN
67 78 53 62 68
78
53 62 68
78
42
SIM1_IO
20 17 7
5
SIM
PP_1V8_LDO6
17 7 6 5 4
4
ESD202-B1-CSP01005
R6900_RF
15.00K
3
SIM1_CLK
1 C6901_RF
2 1
2
0201
1
SIM
SIM1_RST
1
PMU_TO_BB_USB_VBUS_DETECT 90_USB_BB_DATA_P 90_USB_BB_DATA_N AP_TO_BBPMU_RADIO_ON_L
17 3 1
78
DZ6900_RF
VDD_SIM1
20 5 4
17 20
5.5V-6.2PF
5 10 11 12 13 14 15 16
81 78 68
SWP 6
38
ESD202-B1-CSP01005
RCPT-WIDE-HSG-THICK-PIVOT 2
37
PP_VDD_MAIN
20 16 4 3 1
F-ST-SM
R6904_RF 100K
NOSTUFF
1
1% 1/32W MF 01005 2 SIM
SIM1_DETECT
7 17 20
A
SYNC_MASTER=Sync
SYNC_DATE=05/17/2016
PAGE TITLE
spare DRAWING NUMBER
Apple Inc.
051-00419
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
1
8.0.0 6 OF 53 6 OF 81
SIZE
D
A