VHDL For Engineers 1st Edition Short Solutions Manual Visit to download the full and correct content document: https://testbankdeal.com/dow nload/vhdl-for-engineers-1st-edition-short-solutions-manual/
Chapter 6 VHDL for Engineers Solutions October 26, 2008 5:18 pm 6.1 There are three common kinds of simulators for digital systems: time driven, event driven, and cycle based. Time-driven simulation is the slowest. Cycle-based simulation is the fastest. However, cycle-based simulation is only applicable to the functional simulation of synchronous sequential systems that have a single clock. 6.2 The VHDL LRM defines how an event-driven simulator that is compliant with the standard must execute the VHDL language. 6.3 For a time-based simulator to simulate a circuit to a resolution of 1 ns it has to evaluate the model every 1 ns, or 2 x 106 times for 2 ms of simulated time. For an event driven simulator, if the input changes only two times in 2 ms it has to evaluate the model only twice in 2 ms. 6.4 The three steps an event-driven simulator performs to accomplish a simulation are: elaboration, initialization, and repeated execution of simulation cycles. 6.5 (a1) library ieee; use ieee.std_logic_1164.all; entity andor is port( a, b, c : in std_logic; y : out std_logic ); end andor; architecture boolean_expr of andor is begin y <= (a and b) or c; end boolean_expr;
(a2) architecture selected of andor is begin with std_logic_vector'(a, b, c) select y <= '0' when "000" | "010" | "100", '1' when others; end selected;
1
(a3) architecture conditional of andor is begin y <= '1' when (a = '1' and b = '1') or c = '1' else '0'; end conditional;
(b1) process (a, b, c) begin y <= (a and b) or c; end process;
(b2) process (a, b, c) begin case std_logic_vector'(a, b, c) is when "000" | "010" | "100" => y <= '0'; when others => y <= '1'; end case; end process;
(b3) process (a, b, c) begin if a = '1' and b ='1' then y <= '1'; elsif c = '1' then y <= '1'; else y <= '0'; end if; end process;
6.6 Since the testbench was not described as selfchecking, f is not shown brought back to simulation process tb.
2
a
uut/u1 s2
s1 tb
b
uut/u0 uut/u2 c
6.7 (a) p1: process (a, b) begin sum <= a xor b; end process p1; p2: process (a, b) begin carry_out <= a and b;
(b)
sum
tb
uut/p1 a, b a, b
carry_out
uut/p2
(c) .
Signal
Current Value
<
Signal Driver Transaction Queue
a
<
‘U’ @ 0
b
<
‘U’ @ 0
After elaboration
3
f
Signal
Current Value
<
Signal Driver Transaction Queue
sum
<
‘U’ @ 0
carry_out
<
‘U’ @ 0
(d) Design: p06_07 TIME 0.000 0.000 0.000
Delta 0 1 2
a_tb U 0 0
b_tb U 0 0
sum_tb U U 0
uut/u1
s1
carry_out_tb U U 0
6.8 (a) u1: process (a, b) begin s1 <= a nand b; end process; u2: process (s1, c_bar) begin f <= s1 nand c_bar; end process;
(b)
a, b
c_bar
tb
uut/u2
f (c) Design: p06_08 TIME 0.000 0.000 0.000
4
Delta 0 1 2
a U 0 0
b U 0 0
c_bar U 0 0
f U U 1
6.9 (a) An assumption is made that the testbench is not selfchecking.
a, b
uut/u0
s1 uut/u1
tb c
uut/u2
f
s2
(b) u0: process (a, b) begin s1 <= a nand b; end process; u1: process (s1, s2) begin f <= s1 nand s2; end process; u2: process (c) begin s2 <= not c; end process;
Design: p06_09 TIME 0.000 0.000 0.000 50.000 ns 50.000 ns
Delta 0 1 3 1 3
a U 0 0 0 0
b U 0 0 0 0
c U 0 0 1 1
6.10 (a) and (b) library ieee; use ieee.std_logic_1164.all; entity fcn is port( a, b, c : in std_logic; f : out std_logic); end fcn; architecture mixed of fcn is signal s1, s2 : std_logic ;
5
f U U 0 0 1
begin u0: process (a, b) begin if a = '0' and b = '1' then s1 <= '1'; else s1 <= '0'; end if; end process; u1: process (a, c) begin case std_logic_vector'(a, c) is when "11" => s2 <= '1'; when others => s2 <= '0'; end case; end process; u2: process (s1, s2) begin f <= s1 or s2; end process;
(c)
a, b
uut/u0
s1 uut/u2
tb a,c
uut/u1
s2
f
6.11 If a design description has more than one simulation process that contains an assignment statement that assigns a value to the same signal it has multiple signal drivers. Each of these processes defines its own separate driver for that signal. For such a multiply driven signal, the simulator must create multiple driver queues for the same signal. Such a situation frequently occurs in a design with bused connections, a bus signal has multiple drivers. 6.12 During a simulation, each simulator process can be in one of three states: suspended, active, or running. The status of the simulation process in each state is: • Suspended: simulation process is not running or active • Active: simulation process is in the active processes queue waiting to be executed.
6
• Running: simulator is executing the simulation process. 6.13 At the beginning of the initialization phase, the current time (Tc) is set to 0. The kernel places all of the simulation processes in the active processes queue. Each simulation process is then taken from this queue and executed until it suspends. The order of execution of simulation processes during initialization is not important. The initial execution of each simulation process ensures that all initial transactions are scheduled, so that the simulation may continue. A simulation process is suspended either implicitly or explicitly. A process with a sensitivity list is suspended implicitly after its sequential statements have been executed to the end of the process. A process with one or more wait statements is suspended explicitly when its first wait statement is executed. 6.14 (a).
Signal
Current Value
<
Signal Driver Transaction Queue
a
<
‘U’ @ 0
b
<
‘U’ @ 0
sum
<
‘U’ @ 0
carry_out
<
‘U’ @ 0
After elaboration
(b) a
stim_a
uut/u0
sum
a b stim_b
(c) stim_b: process begin b_tb <= '0'; wait for 20 ns; b_tb <= '1'; wait for 20 ns; b_tb <= '0'; wait for 20 ns; b_tb <= '1'; wait;
7
b
uut/u1
carry_out
end process;
(d) Design: p06_14 TIME 0.000 0.000 0.000
Delta 0 1 2
a_tb U 0 0
b_tb U 0 0
sum_tb U U 0
carry_out_tb U U 0
6.15 (a) a b
p0
s1 f p2
c
(b) p0: process (a, b) begin s1 <= a and b; end process; p1: process (a, c) begin s2 <= a and c; end process; p2: process (s1, s2) begin f <= s1 or s2; end process;
(c)
8
p1
s2
tb0 a UUT/p0 s1
a
tb1
b
UUT/p2
UUT/p1
tb2
s2
c
(d)
(e)
9
time
delta
a
b
c
f
simulation processes
0
0
U
U
U
U
tb0, tb1, tb2, p0, p1, p2
0
1
0
0
0
U
p0, p1
0
2
0
0
0
U
p2
0
3
0
0
0
0
none
20
0
1
0
0
0
p0, p1
20
1
1
0
0
0
none
f
6.16 tb: process begin enable <= '0'; wait for 50 ns; enable <= '1'; wait; end process;
6.17 Increasing the delta cycle limit will not solve the problem because the number of cycles required is infinite. 6.18 library ieee; use ieee.std_logic_1164.all; entity norwfb is port( enable : in std_logic; sigout : out std_logic ); end norwfb; architecture dataflow of norwfb is signal s1: std_logic; begin s1 <= enable nor s1; sigout <= s1; end dataflow;
For the functional simulation, with the enable input starting at ‘1’ the output stays ‘0’ until the enable input is made ‘0’ at 40 ns. At that point a delta count overflow occurs and the simulation stops.
For the timing simulation, with the enable input starting at ‘1’ after a 20 ns delay the output becomes and stays ‘0’ until the enable input is made ‘0’ at 40 ns. At that point the output oscillates every 20 ns until the enable input is made ‘1’ at 160 ns, at which point the output becomes and remains ‘0’. The following waveform shows this relationship for a PLD with a 10 ns delay (not 20 ns).
10
6.19 The signal attributes transaction, quiet, active, and last_active can be categorized as transaction related. The signal attributes stable, delayed, event, last_event, and last_value can be categorized as event related. Attributes driving and driving_value can be categorized as general. 6.20 (a)
(b) sigx’last_event at 7 ns (7 ns - 0 ns) = 7 ns sigx’last_active at 7 ns (7 ns - 5 ns) = 2 ns sigx’last_value at 7 ns = ‘U’ 6.21
11
(a)
(b) sigy’last_event at 28 ns (28 ns - 10 ns) = 18 ns sigy’last_active at 28 ns (28 ns - 25 ns) = 3 ns sigy’last_value at 28 ns = ‘1’ 6.22 If the declaration of a variable was allowed in the declarative part of an architecture and two processes in the architecture body read and modify that variable, the variable’s modification is indeterminate if both processes contain the same signal in their sensitivity lists. This is because we cannot know which process is executed first in response to and event on that signal and the variable will immediately take its modified value.
12