Proceedings of INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION AND ENERGY SYSTEMS (ICCCES-16) In Association with IET, UK & Sponsored by TEQIP-II 29th -30th, Jan. 2016
Paper ID: E&TC02
ANALYSIS OF VEDIC MULTIPLIER Akshata R. Dept. of Electronics and Communication Gogte Institute of Technology Belagavi, India
Prof. V.P. Gejji Dept. of Electronics and Communication Gogte Institute of Technology Belagavi, India
Prof. B.R. Pandurangi Dept. of Electronics & Communication Engg., Gogte Institute of Technology Belagavi, India
power VLSI system design. There has been extensive Abstract - Multipliers are extensively used in FIR work on low power multipliers at technology, physical, filters, Microprocessors, DSP and communication circuit and logic levels. These low-level techniques are applications. For higher order multiplications, a not unique to multiplier modules and they are generally huge number of adders or compressors are to be applicable to other types of modules. The characteristics used to perform the partial product addition. The of arithmetic computation in multipliers are not need of low power and high speed Multiplier is considered well. Digital multipliers are the core increasing as the need of high speed processors are components of all the digital signal processors (DSPs) increasing. In this paper, a high performance, high and the speed of the DSP is largely determined by the throughput and area efficient architecture of a speed of its multipliers. Two most common multiplier for the Field Programmable Gate Array multiplication algorithms followed in the digital (FPGAs) is proposed. hardware are array multiplication algorithm and Booth The most significant aspect of the proposed method multiplication algorithm. The computation time taken is that, the developed multiplier architecture is by the array multiplier is comparatively less because the based on vertical and crosswise structure of Ancient partial products are calculated independently in parallel. Indian Vedic Mathematics. As per the proposed The delay associated with the array multiplier is the architecture, for two 8-bit numbers; the multiplier time taken by the signals to propagate through the gates and multiplicand, each are grouped as 4-bit that form the multiplication array. Booth multiplication numbers so 2 that it decomposes into 4×4 Department Communication Technology, isUniversity Collegemultiplication , City, Country another or important algorithm. Large multiplication modules. The of coding is done in verilog booth arrays are required for high speed multiplication and the FPGA synthesis is done using Xilinx library. and exponential operations which in turn require large (e-mail address) Keywords– FPGA, Multiplier, Xilinx. partial sum and partial carry registers. Multiplication of I. INTRODUCTION two n-bit operands using a radix-4 booth recording multiplier requires approximately n / (2m) clock cycles As the scale of integration keeps growing, more and to generate the least significant half of the final product, more sophisticated signal processing systems are being where m is the number of Booth recorder adder stages. implemented on a VLSI chip. These signal processing Thus, a large propagation delay is associated with this applications not only demand great computation case. Due to the importance of digital multipliers in capacity but also consume considerable amount of DSP, it has always been an active area of research and a energy. While performance and area remain to be two number of interesting multiplication algorithms have major design goals, power consumption has become a been reported in the literature. critical concern in today‟s system design. The need of low power VLSI systems arises from two main forces. In this thesis work, Nikhilam Sutra is first applied to the First, with the steady growth of operating frequency and binary number system and is used to develop digital processing capacity per chip, large current has to be multiplier architecture. Urdhva tiryakbhyam Sutra is delivered and the heat due to large power consumption also employed and it is very similar to the popular array must be removed by proper cooling techniques. Second, multiplier architecture. This Sutra also shows the battery life in portable electronic devices is limited. effectiveness of to reduce the NXN multiplier structure Low power design directly leads to prolonged operation into an efficient 4X4 multiplier. time in these portable devices. Multiplication is a fundamental operation in most signal processing II. DESCRIPTION AND ANALYSIS algorithms. Multipliers have large area, long latency and consume considerable power. Therefore, low power VEDIC mathematics is the ancient Indian system of multiplier design has been an important part in low mathematics which mainly deals with Vedic
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