Modern Test & Measure: April 2016

April 2016

Where

Innovation Meets

Quality Identifying PDN Sensitivities

∧ ∧

Gardien CEO Jason Fraser Talks Quality Assurance, Past and Present

Lowering Testing Costs with Boundary Scan

scopes learning center link

CONTENTS

Modern Test & Measure

EDITORIAL STAFF Content Editor Karissa Manske kmanske@aspencore.com Digital Content Manager Heather Hamilton hhamilton@aspencore.com Global Creative Director Nicolas Perner nperner@aspencore.com Graphic Designer Carol Smiley csmiley@aspencore.com Audience Development Claire Hellar chellar@aspencore.com Register at EEWeb http://www.eeweb.com/register/

TECH REPORT

4 10

Lowering the Cost of Test with Boundary Scan EEWEB FEATURE Wireless HVAC Clamp Meter TECH REPORT

12 24

Troubleshooting Clock Jitter and Identifying PDN Sensitivities TECH SERIES USB Type-C Cable Detection PRODUCT WATCH

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Accelerated Environmental Stress Screening with Qualmark’s AccESS Solutions INDUSTRY INTERVIEW

Published by AspenCore 950 West Bannock Suite 450 Boise, Idaho 83702 Tel | 208-639-6464

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Where Innovation Meets Quality Interview with Gardien CEO, Jason Fraser

X

12

Victor Alejandro Gao General Manager Executive Publisher Cody Miller Global Media Director Group Publisher

36 EEWeb

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Modern Test & Measure

Lowering the Cost of Test with

BOUNDARY SCAN

By Jun Balangue, Keysight Technologies, Inc.

PCBA Manufacturing Line

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TECH REPORT

Boundary Scan benchtop tester (in-line or debug)

The cost of manufacturing printed circuit board assemblies (PCBAs) has always been a concern for original equipment manufacturers (OEM) and contract manufacturers (CM). This is one of the reasons why electronics manufacturing has been shifting from one region to another region to stay competitive in this challenging environment.

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Modern Test & Measure

Testing the PCBA is an important part of the manufacturing process. The introductory illustration shows the different stages of PCBA manufacturing, starting from the bare printed circuit board undergoing solder pasting, after which components are placed one by one by an SMT machine at high speed. The PCBA then goes through the oven to melt the solder paste and create a connection between components and the PCB. Each stage of these manufacturing processes is an opportunity where a defect might be introduced by the process itself, by human error or by the equipment. One of the final stages of the PCBA fabrication is testing, to ensure that all components are correct and properly connected to the PCB. This is where the challenge starts, with a series of tests conducted on the PCBA to ensure defects are captured and corrected before the PCBA goes to another stage of the manufacturing stage.

The common PCBA testing stages consist of the following: 1. In Circuit Test (ICT) – Test the PCBA for opens and shorts, component value (resistor, capacitor, inductor, diode, transistor and FET), powered tests such as measuring voltage on board and checking the functionality of individual digital components.

Common defects arising from manufacturing faults include open, shorts, and wrong components.

2. Functional Test (FT) – PCBA is powered to enable checking of the

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functionality of the board. The defects are presented in a block of functions.

3. Repair Station (ICT and FT) – To repair the PCBA that failed during ICT and FT stage.

Design for Test: Introduce Boundary Scan Test at Prototype Phase Boundary scan or 1149.1 is an IEEE Standard that defines the test access port and boundary scan architecture of digital integrated circuits to allowed testing of devices in a PCBA. A boundary scan device is designed with shift registers known as boundary scan cells that are placed between pins of the devices and the internal logic (see Figure 2). These boundary scan cells allow control and observation of what happens at each input and output pin of the boundary device.

When these device pins are connected to other boundary scan devices, it will allow connectivity testing of each device.

Boundary scan has become an important limited access solution for PCBAs. Boundary scan usage has also expanded to include testing of non-boundary scan digital devices such as DDR and programming digital devices such as flash, EEPROM and serial peripheral interface (SPI) devices. Boundary scan also has the capability to execute other tests, as defined in the BSDL (Boundary Scan Description Language), including private instructions which support internal functions of a boundary scan device, such as built-in self-test (BIST).

TECH REPORT The success of boundary scan lies with the proper design of the board and verification of boundary scan at the early stage of the board design to ensure success during production implementation. Hence the printed circuit board assembly (PCBA) test strategy should start at the design stage of the board to ensure that maximum coverage is achieved during testing. Boundary scan can be used as part of the test strategy from the prototype stage, right to new product introduction (NPI) and production run stages to achieve the highest test coverage at every stage of the PCBA process, and at the same time lower the cost of test implementation.

BOUNDARY SCAN CAN BE USED AS PART OF THE TEST STRATEGY FROM THE PROTOTYPE STAGE, RIGHT TO NEW PRODUCT INTRODUCTION (NPI) AND PRODUCTION RUN STAGES TO ACHIEVE THE HIGHEST TEST COVERAGE AT EVERY STAGE OF THE PCBA PROCESS, AND AT THE SAME TIME LOWER THE COST OF TEST IMPLEMENTATION.

Figure 2 .

Boundary Scan on devices and interconnect test implementation

A BOUNDARY SCAN DEVICE IS DESIGNED WITH SHIFT REGISTERS KNOWN AS BOUNDARY SCAN CELLS THAT ARE PLACED BETWEEN PINS OF THE DEVICES AND THE INTERNAL LOGIC.

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Modern Test & Measure

Boundary Scan at Prototype Stage It will be very cost-effective if manufacturers can consider if their PCBA has proper design for boundary scan tests during the prototype design stage, before the board is actually assembled.

This can help assure the board designer that the PCBA will have maximum test coverage, without worrying for possible structural defects of the board. This will result in a shorter time to market for the PCBA to move to the next stages of the product cycle窶年PI and Production.

Another advantage of using boundary scan during the prototype phase is that the designer will be able to identify what nets of the board will not require testpoints. He can also determine early on which tests require boundary scan, while assigning other testpoints into nets that will only be tested during ICT.

Boundary Scan During NPI Successful boundary scan implementation during prototype build will ensure the

Figure 3:.

Boundary Scan implementation from Prototype (Design Stage) to New Product Introduction (NPI) and Production stages

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success of boundary scan at the next stage, which is the NPI phase. During NPI build, ICT is typically used as part of the test strategy, during which the ICT program will be developed and the ICT fixture will be built. Boundary scan implementation at this stage will have the following advantages: 1. Since the boundary scan test program is already created and debugged during the prototype phase, the ICT development time will be shorter.

2. During prototype, the nets that need to be tested with boundary scan have already been identified and separated from those that need ICT. This will mean fewer testpoints needing ICT translating to lower cost of ICT due to fewer analog/digital cards needed.

3. The cost of the ICT fixture is lowered since the PCBA has fewer testpoints.

4. The overall cost of ICT program development is cheaper since the boundary scan test program is already created during the prototype stage.

TECH REPORT Boundary Scan During Production Stage The same boundary scan test programs that are created during the prototype phase and integrated in ICT during the NPI stage can still be used in various stations during volume production (see Figure 4).

1. ICT Station – The boundary scan test developed during Prototype and NPI will be integrated in the ICT. 2. ICT Repair Station – The same boundary scan test can be used at the ICT repair station.

3. FT Station – The same boundary scan test can be used and integrated during functional testing of the PCBA. 4. FT Repair Station – The same boundary scan test can be used at the FT repair station.

Boundary scan implementation across all the product manufacturing and testing stages can lower the cost of test as the same hardware and software can be reused while simultaneously ensuring higher test coverage. The reuse of boundary scan test programs across test stations also ensure the quality of test is maintained at all the test stations.

This will help the production operator and technician become familiar with the defects being discovered at the various test stations, and help ease repair at all stages of production testing.

BOUNDARY SCAN IMPLEMENTATION ACROSS ALL THE PRODUCT MANUFACTURING AND TESTING STAGES CAN LOWER THE COST OF TEST AS THE SAME HARDWARE AND SOFTWARE CAN BE REUSED WHILE SIMULTANEOUSLY ENSURING HIGHER TEST COVERAGE.

Figure 4.

Boundary Scan implementation at different production stations

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Modern Test & Measure

Newswire

Wireless HVAC Clamp Meter Improving the Productivity of HVAC Technicians Fluke Corp. announced the release of Fluke速 902 FC True-rms HVAC Clamp Meter, a wireless Fluke Connect速-enabled meter that improves the productivity of HVAC technicians in the field.

With the Fluke 902 FC, technicians can document measurements, email results to customers, and collaborate with colleagues in real time directly from the job site.

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NEWSWIRE

T

he rugged CAT III 600V / CAT IV 300V rated meter performs the essential measurements of HVAC systems —microamps for testing pilot light sensors, resistance up to 60 kilohms, AC current, AC/DC voltage, capacitance and contact temperature—eliminating the need to carry multiple tools. Its small body is easy to hold and the jaw fits perfectly in tight work spaces.

As part of Fluke Connect—the industry’s largest system of software and more than 40 wireless test tools—the 902 FC can transmit measurements to a smartphone or tablet for later, detailed analysis. Those measurements can be uploaded to the cloud. Technicians can combine measurement data from

multiple Fluke Connect test tools to create and share reports from the job site via email and collaborate in real time with other colleagues with ShareLive™ video calls or email, increasing productivity in the field.

The clamp meter also decreases the frequency that technicians will need to wear personal protective equipment when working on high voltage/current panels. Simply turn off the panel, verify the panel is deenergized using standard safety procedures, place the clamp and sync it to a smartphone with the Fluke Connect app, close the panel, reenergize it, and take measurements from a safe distance.

Keysight TrueIR Thermal Imagers from Gap Wireless Find potential problems more quickly with the higher resolution and affordability of the U5850 series TrueIR thermal imagers. Get 320 x 240 pixels of in-camera fine resolution from its detector resolution of 160 x 120 pixels. With the built-in image logging capability, easily track performance of the system you monitor at a specific interval.

Plus, you can analyze temperature changes over time with trending graph.

Coupled with the powerful manual focus feature, users can focus on an object as close as 10 cm away - our solution provides clearer and sharper thermal images that reveal finer details.

info@gapwireless.com 1-855-826-3781

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gaplinkhere

Modern Test & Measure

Troubleshooting

Clock Jitter and Identifying

PDN Sensitivities Quickly identify PDN sensitivities, in-circuit, including clock jitter source locations, using a simple probe-based solution.

By Steve Sandler – Picotest

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TECH REPORT

P

ower distribution network (PDN) noise is one of the most common issues in low power applications.

Whether you are powering ADCs, clocks,

LNAs, digital data networks or sensitive RF applications, properly tuning your power supply is of the utmost importance. These sensitive circuits can be disrupted by just a few millivolts of power supply noise or even less. Due to this extreme sensitivity and the interaction between the power supply, distribution network, and load, power supply troubleshooting often becomes necessary.

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Modern Test & Measure

Due to the interactions between the source and load impedance, the troubleshooting must be performed in-circuit and there is often very limited physical access. As a result, this can be a time consuming process.

Even in a circuit that appears to be fully functional it’s generally a good idea to evaluate power supply sensitivities. It’s the best way to identify potential issues that could crop up as a result of operational and environmental tolerances.

In this sample application, we will demonstrate some simple test tools that couple with your spectrum and network analyzers that help support power supply noise source investigation.

Figure 1 shows the Picotest VRTS3 training demo board, which includes a variety of sample circuits, supporting many types of measurements.

One of these sample circuits is a 125MHz clock (OSC401), powered by a low dropout (LDO) voltage regulator (U301). Four different output capacitors can be connected or disconnected from the LDO using a four-position dipswitch (S301), altering the stability of the power supply.

The circuit schematic in Figure 2 shows the LDO linear regulator (LT1086) that powers the 125MHz clock oscillator, OSC401 through a slide switch (SEL1).

Of note is the 0.01uF decoupling capacitor C402 (on the right).

Figure 1. The Picotest VRTS3 training demo board showing the LDO and clock layout.

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TECH REPORT

Figure 2. The LDO and clock circuitry schematic.

Figure 3. Clock spurs at approximately 6 MHz offset are highlighted in this oscilloscope spectrum plot.

These spurs are used to demonstrate a simple and fast troubleshooting technique.

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Modern Test & Measure

Identifying a power supply noise sensitivity can be accomplished quickly and easily using a wide band harmonic comb generator and a 1-port passive transmission line probe.

The J2150A harmonic comb provides a wideband noise source with a 50Ω output impedance. It is contained in an ultra-portable USB “stick” form factor. The harmonic comb provides noise over a frequency range of 1kHz to more than 1GHz in three frequency ranges. The ranges are centered around 1kHz, 100kHz, and 8MHz. Harmonics are generated by time and frequency dithering of the output impulses. The comb can step through these ranges

automatically or be locked onto a single frequency range. While most instruments have several unused USB ports available, the comb can also be powered from the popular cell phone backup batteries for a portable solution.

A wideband DC block is generally included between the comb injector and the probe in order isolate the 50Ω DC impedance from the circuit being tested. The clock spectrum is viewed on an oscilloscope with a spectrum analyzer option, a signal source analyzer or a spectrum analyzer. The voltage regulator stability and distribution impedance are easily seen as sidebands or jitter in the clock spectrum.

Figure 4. Simple but effective tools support PDN interrogation and clock jitter assessment.

These include a J2150A harmonic comb broadband signal generator (left) along with 1-port (center) and 2-port bi-directional 50Ω passive probes and DC blockers (left).

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TECH REPORT The Picotest transmission line probes are unique, providing unity gain, bidirectional 50Ω connections to various instruments with a comfortable browser style head for probing the power distribution network.

This allows the probe to be used to inject signals, as in this example, or to measure noise using the same probe. The probe

connection is a generic 50Ω SMA connector, allowing connection to most instruments.

In this example, the harmonic comb injects a broadband signal into the clock’s decoupling cap (C402) using the 1-Port Probe, as seen in Figure 4. The clock’s spectrum is monitored at SMA connector, J3.

Figure 5.

The J2150A harmonic comb (inset and in Figure 3) is connected to the 1-Port probe via a P2130A DC Blocker and used to inject a signal into C402 (VDD of a 125MHz clock oscillator). The clock spectrum is monitored at SMA connector, J3.

http://www.siglentamerica.com

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Modern Test & Measure

Figure 6. The PDN interrogation using the comb’s search mode signal set reveals a resonance at approximately 7.5MHz as seen in the spectrum sidebands around the clock fundamental frequency.

Note the peaks are approximately -30dBc.

Moving the noise injection point to the linear regulator (same printed circuit board trace but downstream of the clock) we notice that the clock sideband noise is much smaller in Figure 7 at -45dBc. This information tells us that resonance is between the regulator and the clock. The resonance is comprised of the inductance of the printed circuit board trace and the decoupling capacitor, C402.

Figure 7. By injecting the noise at different locations within the PDN, the noise source is quickly located. Note the sidebands are about 15dB lower than in Figure 6. This tells us that the resonance is at the clock and not at the regulator.

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TECH REPORT Having located the resonance at the clock, we can calculate the characteristic impedance of the PCB connection using the value of the decoupling capacitor (10nF) and the 7.5MHz resonant frequency (7.5MHz). The characteristic impedance can be calculated as 1/(2*PI*7.5MHz*10nF), in this case 2.1â„Ś. Placing SEL1 switch in the center (OFF) position inserts a 2.4â„Ś resistor (R305) between the linear regulator and the clock, damping the resonance. The elimination of the 7MHz clock spectrum sidebands, seen in Figure 8 confirms that the resonance has been effectively damped by increasing the series resistance between the linear regulator and the clock.

Figure 8. The 7MHz clock sidebands have been eliminated by inserting the series resistor between the regulator and the clock, damping the PCB resonance.

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Modern Test & Measure

The resonance and the damping effectiveness can easily be confirmed by measuring the impedance at the clock’s decoupling capacitor with a vector network analyzer (VNA). Measurements are shown in Figure 9 for two different linear regulator output capacitors, as well as, the insertion of R305.

While the sidebands may not have seemed all that severe, they can significantly impact performance—much more so than they might otherwise appear. First, note that the sidebands in Figure 3 appear at 6MHz, while we determined the PCB resonance is at 7.5MHz. Second, the measurement in Figure 9 shows that at 6MHz the impedance is approximately 5dB lower than at the 7.5MHz peak and at 9MHz the impedance is approximately 15dB lower than the 7.5MHz peak.

Figure 9. The 7.5MHz resonance (red, blue traces) is clearly seen for two different linear regulator output capacitors, selected with switch S301. The insertion of the 2.4Ω resistor damps the resonance (green trace), reducing the impedance at 7.5MHz by approximately 15dB.

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So, what excited the resonance? There is a 2.8MHz switching point-of-load (POL) regulator also located on the VRTS3 demo board. The 2nd and 3rd harmonics are close enough to the resonant peak to impart clock noise. We can confirm the POL switching frequency as the noise generator, since an enable switch is included on the VRTS3 training board for this purpose. If we turn off the switching regulator the clock sidebands at 6MHz disappear. This also clearly demonstrates why we want to interrogate the circuit even if it appears to be functional.

The switching regulator operating frequency has a tolerance of 750kHz while the decoupling capacitor also has tolerances. These tolerances can easily shift the second harmonic of the switching regulator to occur exactly at the frequency of the impedance

TECH REPORT peak, increasing the clock noise significantly. While you would not likely see this frequency alignment occur in a nominal test, you are much more likely to know about its possibility via this PDN interrogation.

In summary, we quickly identified a PDN sensitivity that resulted in increased clock jitter. We identified the noise, determined its source and characteristic impedance, and easily corrected the issue by flattening the power rail impedance at the clock. This was all accomplished in just a few minutes using a highly portable harmonic comb generator (Picotest J2150A), a handheld 1-Port probe (Picotest P2100A) and an oscilloscope (Keysight Infiniium S).

Power Integrity Training Test Board The Picotest VRTS3 demonstration board is an excellent training tool for all levels of test and design engineers. It includes an example for this noise application, as well as many other basic power supply tests including Bode plots, non-invasive stability measurement, PSRR, TDR, and load step.

Picotest offers several bundled solutions for optimizing, testing, and troubleshooting power integrity issues, such as clock jitter, with support for various instruments and measurement domains. The recently introduced J2150A harmonic comb generator paired with a P2100A 1-port probe is only one, albeit powerful, solution.

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Modern Test & Measure

USB Type-C

Detection

By David Maliniak, Teledyne LeCroy

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TECH SERIES

USB 3.1 TYPE-C

T

he previous article examined the basics regarding the USB Type-C connector and the

Power Delivery 2.0 specification that complements the Type-C spec itself.

This article will turn our attention to the topic of USB Type-C cable detection.

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Modern Test & Measure

The Type-C connector is reversible, which is to say there are four ways a cable can be connected between upstream- and downstream-facing ports (Figure 1).

Not only that, but there are different types of Type-C cables. So how do the devices discern what’s between them?

To dig deeper into Type-C cable detection, let’s start with the simplest case, which is a source-only downstream-facing port (DFP) connected to an upstreamfacing port (UFP), or sink (Figure 2). Other connections are hidden for simplicity’s sake; both receptacles are powered and are continuously monitoring the configuration channel (CC1 and CC2) lines.

Figure 1. The four possible states of connection for a USB Type-C cable.

Figure 2. Shown are the terminating resistors used for USB Type-C cable detection.

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Let’s say the cable is being plugged in properly, i.e. in un-flipped straightthrough fashion as shown in Figure 1.

Upon cable plug-in, the DFP and UFP monitor the resistance levels on the CC pins. The DFP attaches pull-up resistors Rp, while the UFP attaches pull-down resistors Rd. In the case of the UFP, both CC pins are connected to ground and only sees this termination on the one CC line that’s connected, which would be CC1. Thus, it knows this is the line to use for Power Delivery communications.

Next, the DFP and UFP route the various other signals not shown here. If the cable were flipped over (flipped straight through

TECH SERIES as in Figure 1), they would see the same Rp and Rd terminations, only they would be on the CC2 line.

If there’s a twist in the cable, as in the bottom two examples in Figure 1, each receptacle needs to be smart enough to figure out which pins to use. Fortunately, they are, and will route signals to the correct pins.

All of the above assumes a non-Emarked cable. If we look at the same source-to-sink connection but with an E-marked cable, which carries a chip embedded in the CC line that enables the DFP to ping the cable and query it as to its capabilities, we’ll see a slightly different setup (Figure 3).

Figure 3. Source-to-sink connection using an E-marked USB Type-C cable.

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TECH SERIES

That chip embedded in the cable needs a small amount of power, so this is where the unused CC pin in the receptacle is used to provide it. A change of note in USB Type-C is a new differentiation between VBUS and VCONN power. The former is still used for powering or charging connected devices, while the latter is only for powering of E-marked cables and certain other devices.

VCONN provides 5V @ 200 mA and is initially sourced from the DFP. VCONN power does not pass through the cable to the UFP. With both linked partners monitoring the CC lines for Rp and Rd, the DFP is pulling up on both CC pins and again senses the pull-down resistance on the UFP end of the cable. E-marked cables present a load known as Ra. Thus, the receptacle senses another voltage divider; it knows it is

attached to an E-marked cable. That means VCONN must be sourced to power the cable’s electronics (Figure 4). Only after the two sides determine which line is to be the CC line does the DFP apply power to VCONN. After waiting for a required timing interval, the DFP can now send commands to the cable itself.

The end result of this process, in this case, is that the two CC1 pins become VCONN. It is possible that the cable may need VCONN at both ends if it has repeaters or other active components in the plug, so it’s up to the cable to propagate power to the far-end plug if necessary. Still, in all cases, VCONN is not passed through the cable but is terminated in the plug’s active electronics.

Figure 4. Deciding whether VCONN comes into play for an E-marked cable.

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Modern Test & Measure

Qualmark Accelerated

Environmental Stress Screening

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PRODUCT WATCH

Environmental Stress Screening (ESS) is critical for ensuring the reliability of electronic systems. The goal of ESS is to make a marginal product fail before shipment. Marginal products have one or more latent failure modes. These modes become apparent in a relatively short time in the form of warranty claims and dissatisfied customers.

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Modern Test & Measure

ESS utilizes a variety of stresses to exercise as many potential failure modes as possible.

INFANT MORTALITY RATE

ESS utilizes a variety of stresses to exercise as many potential failure modes as possible. The most important failure modes are: 1. Failures accelerated by high temperature dwell.

2. Failures accelerated by rapid thermal change rates—traditional ESS does not have rapid thermal change rates.

3. Failures accelerated by hot and cold dwells.

4. Failures accelerated by vibration— traditional ESS usually does not include vibration.

5. Failures only accelerated by a combined thermal and vibration stress environment—this is also something that traditional ESS does not include; AccESS does incorporate a combined environment.

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Each failure mode is a subset of the product’s infant mortality rate. Although in the past simple high temperature dwells were considered sufficient for ESS, modern electronic products are far more susceptible to stresses from thermal cycling and/or vibration.

Qualmark AccESS solutions, such as HawQ or Typhoon, save money by completing ESS in 1/5th the time. The combined stresses of rapid thermal and repetitive shock vibration increase infant mortality detection This means your product will undergo an ESS that meets or beats the most stringent screening requirements more rapidly than is possible with traditional equipment and gets your product on the truck and out the door in record time.

AccESS offers ramp rates up to 60°C per minute, far faster than the conventional

PRODUCT WATCH

AccESS offers ramp rates up to 60°C per minute, far faster than the conventional 5°C to 20°C per minute rates.

5°C to 20°C per minute rates. The benefits are twofold: first, faster ramp rates mean thermal cycles complete faster. Second, quicker temperature transitions induce more thermal stress and therefore fewer cycles are needed compared to an equivalent test with slower ramp rates Limit testing can be used to further accelerate ESS. By identifying and fixing product design issues, the temperature range between hot and cold dwells can be safely increased without causing hard fails. As a result, each temperature cycle induces relatively more thermal stress, which again saves screen time.

Qualmark AccESS solutions mean faster product validation through reduced ESS time . . . and time savings is cost savings. For more information, visit Qualmark.com.

Click this image to watch a video on Qualmark’s Accelerated Environmental Stress Screening process.

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MYLINK

MYLINK

Modern Test & Measure

Where

Innovation Meets

Quality Gardien CEO Jason Fraser Talks Quality Assurance, Past and Present Interview with Jason Fraser – CEO of Gardien

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INDUSTRY INTERVIEW

As the world’s largest synergistic PCB quality assurance company, Gardien handles every aspect of PCB quality—from electrical testing to process controls. By combining capital, time, labor, and knowledge, CEO Jason Fraser is confident that Gardien offers what competitors cannot.

EEWeb recently spoke with Fraser, who discussed the need for quality assurance, the state of the industry, and his predictions for the future of the company, the field, and the PCB industry.

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Modern Test & Measure

What is Gardien’s core offering?

Whether you’re a large or small fabricator, Gardien has a set of fully customizable QA solutions that allow customers to free up precious resources like, capital, time, labor, and knowledge. The customer can focus on what they do best, which is manufacturing class-leading boards, leaving us to do what we do best, which is to assure their quality. I know it’s a pretty big statement, but we have the experience to back it up. In one form or another, Gardien has been around since the advent of the personal computer and over half of the world’s largest PCB fabricators utilize our service, so we have some pretty unique solutions that we deliver into the marketplace.

To the best of my knowledge, we are the only tail end QA provider that has a global footprint. We operate in seven countries around the world and we have about 25 service centers employing 500 people. On average, Gardien does around 3,900 new jobs a month, 18,000 orders per month, and 24.5-million tests per month. For a QA business, we are a sizable operation.

Why do PCB fabricators utilize your service as opposed to doing the job themselves?

We offer a number of QA services, but we offer them in two solutions: our

OnDemand solution and our Integrate solution. To put it back into the context of the industry, OnDemand is essentially what most of the test industry delivers— when there is a test capacity constraint within manufacturing, the fabricator will put the excess work back into the local marketplace. We’ll typically undertake this type of work in one of our numerous service centers.

Our other solution, which is pretty unique in the industry, is what we call Integrate.

Integrate is where we sign a long-term agreement and take 100-percent of the responsibility of the QA needs of the fabricator. We’re able do this in any one of our global service centers or we can even come into the manufacturer’s facilities and integrate the QA floor.

For this offering, we can manage and work with existing QA personnel, or clients can release some of their personnel back into the value-add areas of their fabrication process and we supplement the additional headcount requirement.

Alternatively, we can fully staff the QA floor ourselves if needed. Similarly, If the client wishes for the QA staff to remain on their books, we will pay for their cost of employment, or we are equally happy to transfer them across to Gardien. It’s the beauty of Integrate, because it’s based on fully customizable and flexible solutions to address individual client needs.

Integrate is where we sign a long-term agreement and take 100-percent of the responsibility of the QA needs of the fabricator.

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INDUSTRY INTERVIEW When a client signs up with Integrate, it becomes our responsibility to ensure they have a fit-for-purpose test floor, which means we look at the existing and future needs of the customer, and if there’s a requirement to put in additional equipment, we will do so at our expense. Around half of Gardien’s revenue is generated from Integrate.

What are the fundamental differentiating factors of Gardien’s services?

What makes us unique is the fact that with Integrate we offer Partnership Pricing. If you look at the business model for the industry, you will see it’s based on overflow and outsourcing, which is charged on a per-board or area basis. This pricing model is completely at odds with a customer’s quality goals. Poor fabricator quality actually means increased revenue for a test company as they need to test more boards. We’ve changed that with Partnership Pricing; this model allows us to align ourselves completely with our clients. If they make a bad board, we don’t charge them for it—we only charge for what they ship. This means that if the customer is doing prototype work to gain additional business and they don’t charge for those prototypes, we don’t charge for them. This allows us to turn our relationship with the customer from a supplier to a partner because we have a vested interest in the company to get the quality to the best it can be because it is also to our advantage.

Our key differentiator is the nature of our global footprint. If the customer is using our facility in Toronto or Taipei, they’re going to get a globally consistent service.

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Modern Test & Measure

With all of the service centers Gardien has around the world, how are you able to keep everybody on the same page?

Our key differentiator is the nature of our global footprint. If the customer is using our facility in Toronto or Taipei, they’re going to get a globally consistent service.

We make good on that commitment by utilizing an enterprise resource planning (ERP) system that was developed inhouse, specifically for PCB quality assurance, which we call OnTrack. It quite literally drives our business. From an operational standpoint it handles tooling, production scheduling, process control, even pro-active equipment maintenance and calibration. It’s reporting capabilities are even more impressive. We capture a vast array of key performance information to drive efficiency, best practices, and for the generation of customer dashboards.

We created a new position last year of Vice President for Global Quality which includes the responsibility of making sure

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that best practices and skills we learn in one market are entered into OnTrack and rolled out to all our service centers . Given the segmentation of PCB fabrication—by geography, by technology, by volume etc. it’s of vital importance because we can take those technology lessons we learned in one territory and use them to assist our customers in another.

On the equipment side, you mentioned how the industry is constantly innovating. What challenge does that pose to Gardien as it has to QA the latest PCB technology?

I think this bodes well for companies like Gardien. The one thing to keep in mind is that if you can’t test it, you can’t make it. The industry today is around $60-billion and forecast to be $100-billion by 2020. Combine this with the continual onward march towards higher technology and tighter board parameters and I see a greater reliance on companies such as Gardien with its global QA experience and knowledgebase.

INDUSTRY INTERVIEW What do you foresee in industry in the next few years that is most exciting for Gardien?

From my point of view, what we are delivering to the customer is the most exciting aspect. When I first came on board, the biggest challenge was redefining the quality assurance aspect of the business. As a company, we were transactionally focused, looking at how we could save a bit of money for the customer in their test area. Given that test only accounts for a couple of percent of overall fabrication cost, it was hardly a game changing strategy. I felt that we could do better than that.

If you look at what we offer with the Integrate solution, it’s a very different conversation; one where we are helping to drive efficiencies for our customers, assisting them in improving throughput, and providing vital information and tools needed to perform better. What’s more, by changing the way that we charge for the service so that there’s an alignment of interest, we’ve taken what could so easily be dismissed as sales talk and transformed it into a service commitment; as we really do have skin in the game!

The one thing to keep in mind is that if you can’t test it, you can’t make it.

Technical image source: www.gardien.com

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