EEWeb Pulse - Volume 11

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Issue 11 September 13, 2011

Nick Such

AwesomeTouch

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TA B L E O F C O N T E N T S TABLE OF CONTENTS

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Nick Such CO-FOUNDER AND CEO, AWESOME TOUCH

Interview with Nick Such - Director of Awesome Labs at Awesome Inc.

8

AwesomeTouch: Wayfinding Applications for Public Multitouch Displays

BY NICK SUCH An introduction to AwesomeTouch’s new application, AwesomeMap.

Advantages of FPGA-Based Motor Control

11

BY MICHAEL PARKER WITH ALTERA A detailed look into how FPGA design tools can simplify motor control design.

Via Return Currents and the Path of Least Resistance

14

BY MICHAEL STEINBERGER WITH SISOFT Steinberger shares his knowledge of vias as mechanisms used to establish return current paths.

RTZ - Return to Zero Comic

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INTERVIEW

AwesomeTouch How did you get into electronics/engineering and when did you start?

I built my first circuits as a thirdgrade project with some help from my dad, who likely had some help from my uncle, who was an electrical engineer with AT&T, and worked on the New Jersey Relay Service.

I learned HTML in fourth grade, and built my first electric bicycle in middle school. These fed pretty well into my two loves: interaction design and electric vehicles.

What are your favorite hardware tools that you use?

Soldering iron, hot glue gun, and DMM.

What are your favorite software tools that you use?

Notepad++, Pro/E, Inkscape, GIMP, InSSIDer, 360 Panorama, and RedLaser.

What is the hardest/trickiest bug you have ever fixed?

While I started off in preschool playing games on a Commodore 64, my first “real” computer ran the original version of Windows 98. This version had minimal support for USB. When I received a new USB game controller for my birthday, I wanted to use it on my computer.

So I upgraded (one INF and DLL at a time) from Win98 First Edition to Win98 Second Edition.

Nick Such - Co-Founder and CEO at AwesomeTouch

What recommendations would you give to young students aspiring to be engineers?

Be curious and become a hacker.

I’m not talking about stealing passwords and credit card info, but rather, realize that you have the ability to change the world from the state in which it is presented to you into whatever state you envision.

There is so much technology floating around you that can be easily modified to suit the world’s needs. Poke around, and find ways to make new and better tools for humanity. Learn that failure is a key tool for engineers; how can we know what something is able to do until we push it to its limits?

And when you get to that limit, trace your steps back and use this newfound context to learn why things are the way they are.

What is on your bookshelf?

Here (www.shelfari.com/nicksuch/ shelf) is a list of my books, as well as books on leadership, and lots of Michael Crichton.

Do you have any tricks up your sleeve?

It has amazed me how the simple ability to “translate” between engineering-speak and normal human language can be a pivotal factor in the success of my projects.

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4

FEATURED INTERVIEW

Nick Such

INTERVIEW

What has been your favorite project?

I spent five years working with the University of Kentucky’s solar car team, and it was awesome.

Every two years, we design, build, and race a solar-powered car in track and cross-country races, competing against university teams from around the globe. I started off as a driver (finally, a good reason for being shorter than 6-foot!) and progressed to leading the team my final year. I had the opportunity to work with a super smart team of engineers (ME, EE, CS) and business people (we had to raise $200,000 for parts and race fees), as well as the fiercely collaborative solar car racing community. Our team frequently traveled to K-12 schools in Kentucky to promote engineering, and I loved meeting a generation of kids who have fully accepted that they will be driving electric or hybrid cars (or some other type of vehicle). And as one of our races traveled from Dallas, Texas to Calgary, Alberta, Canada, I am now officially an international race car driver (yet, sadly, that

pickup line has never worked for me)!

Do you have any note-worthy engineering experiences?

Our third-generation solar car used 162 lithium polymer batteries, which were carefully controlled by an active protection circuit in a ventilated, flame-retardant box. After seeing the YouTube videos of fires emitted from 6-cell laptop batteries, we decided that we wanted to do a destructive test on our Li-Po cells.

We wanted to better understand its

Be curious and become a hacker... realize that you have the ability to change the world from the state in which it is presented to you into whatever state you envision. limits for racing purposes, as well as the dangers to which we would potentially be subjecting our drivers (who share a vehicle compartment with the batteries). So, we imparted some mechanical damage to a cell and continued charging it at 20 amps, well after it had reached its 4.2V upper limit. Within 30 minutes, the cell failed, and emitted a six-inch flame that was incredibly difficult to extinguish. After seeing

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the destructive power of one cell, we took care to ensure that our pack of 192 was very well protected and monitored throughout the race.

What are you currently working on?

AwesomeMap is a wayfinding application for large-format touchscreens that’s used in the hospitality industry. In short, we make giant touchscreen maps that help visitors discover cities.

Our team was initially focused on hardware design, after developing a novel method for producing throughwindow multitouch displays, but shifted to software as our customer’s needs changed.

I’m also working with a local high school student who is developing a miniaturized R/C version of the University of Kentucky’s latest solarpowered car.

What direction do you see your business heading in the next few years?

The rate at which humanity is creating electronic data is staggering—nearly 2.5 exabytes per day (http://techcrunch. com/2010/08/04/schmidt-data/).

While there is a lot of great information in that stream, the amount of noise is incredible.

We are noticing, even for local place information, picking out the signal from the noise is a challenging task. Increasingly, we will be focusing on better methods for aggregating and managing this information, as well as effective ways to present it across tomorrow’s varying platforms.

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FEATURED INTERVIEW

My superpower: explaining really complex concepts in everyday terms. I can thank my grandmother for this. She recently received her first computer as a gift, and I was the family member in charge of teaching her how to use it. I hadn’t realized how my power-user habits have numbed me to the frustrations of a computing novice. For instance, trackpads create a non-intuitive disconnect between where a user is touching and where the on-screen interaction is occurring. This was, however, a very illustrative case of the superior ease-of-use of welldesigned touchscreen devices.

INTERVIEW FEATURED INTERVIEW

What challenges do you foresee in our industry?

Interaction with software and data will become a seamless part of our lives. Whether it’s on largeformat interactive displays or mobile devices, this data will be increasingly accessed through gesture-based input methods.

This requires a major change in the way we design interfaces, as well as choices for how much we allow technology to proliferate our daily lives. While the “Day Made of Glass” (http://www.youtube. com/watch?v=6Cf7IL_eZ38) from Corning provides an excellent proposition for the software that my company develops, I think there is a balance to be found among the connected world and the natural and human beauty on this planet.

And while electric vehicles are very cool, I’m more interested

University of Kentucky’s Solar Car (See Favorite Project)

in the system-level changes in transportation that can be facilitated through more intelligent software. Energy will be one key driver in our future transportation choices, but with the growing ubiquity of wireless connected devices, human productivity

is a far more significant factor.

Unless we want to continue to lose thousands of lives each year from distracted driving, we must find a better way to move people around while allowing them to efficiently communicate and perform their daily tasks. ■

Automotive, Medical, Telecom, POS LCD for Any Application

Microtips Technology QVGA Green w/LED Backlight 7” High Bright

From design to service, Microtips offers a variety of competitively priced Liquid Crystal Display modules which includes standard character and graphic monochrome, passive and active color displays with white LED as well as custom LCD modules and complete OEM services.

For your own design needs please contact

240 x 160 COG w/LED Backlight EEWeb | Electrical Engineering Community

Microtips Technology:

www.microtipsusa.com 1.888.499.8477

mtusainfo@microtipsusa.com

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Technology You Can Trust

Ultra Low Power Digital Optocouplers in Industrial Communication Interfaces 90% less power than standard optocouplers 40% lower power than alternative opto-isolators • Ultra low power • High temperature and supply voltage range • High noise immunity (35 kV/µs dynamic and static common mode rejection) • Certified for safe insulation (up to 1140 Vpeak continuous working voltage)

To request a free evaluation board go to: Avago Technologies new generation optocouplers, ACPL-x6xL series and www.avagotech.com/optocouplers ACNW261L, offer significant power efficiency improvements for industrial communication interfaces. With 35 years of experience in digital optocoupler design, Avago delivers quality you can count on.

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Controller

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Key Features

PROJECT

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wesome

ouch

Wayfinding Applications for Public Multitouch Displays

By Nick Such

About two years ago, my friends and I were running a tech/creative office space in downtown Lexington, Kentucky. The space was awesome (in fact, we named it “Awesome, Inc.”). By day it was full of some of the brightest, most creative people in the city, each working on turning his or her dreams into early-stage company reality. By night, the same space, with its brightlycolored walls, modern glass and metal fixtures, and open, flowing layout, was transformed into an art gallery and dance studio. The energy in that place was nearly boiling out the front door. That’s when we realized the problem. We had six, full-height windows exposed to Main Street, so passers-by could get a vague picture of what was going on inside our building, but they couldn’t get the full picture. What if they wanted to sign up for dance classes? What if they wanted to learn about the artist who created the painting on our wall? What if they had mad PHP skills and wanted to join one of our coding projects? We decided that the most logical conclusion was to turn the windows into a 30-foot touchscreen.

mounted touchscreens. From there, we started getting requests to do maps for indoor spaces, like hotels and eventually hospitals. And that’s where we discovered the true need for what we were doing: people get lost inside buildings.

AwesomeTouch has spent the past year developing an application called AwesomeMap that stays true to the core problem: How do we build a portal to help connect people to the extraordinarily useful metadata floating over the real world? This manifested itself as we took the local Visitors Bureau’s paper map of the city, and overlaid it with interactive trolley routes and 250 points of interest. And while we didn’t spring for the 30-foot version, we have deployed these maps on 50-inch wall-

A few weeks ago, we launched a project called BuildingLayer to allow anyone to contribute maps for any building in the world. Our goal is to build a database of maps of the inside of buildings, and overlay this onto the existing maps of outdoor spaces. Unlike the great outdoors, we can’t (yet) fly a plane through a building to capture geotagged imagery. For now, we’re relying on individuals to upload known floor plans, or to recreate the insides of buildings from memory, and the reference

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This problem seemed to have a simple solution at first.

The outdoor world has several wonderful, web-based mapping solutions such as Google, Bing, and even OpenStreetMap. Paired with a GPS receiver, these maps have done amazing things for society. My dad (and men everywhere) is no longer faced with the shame of stopping his car to ask for directions. Using locationbased check-in services like Foursquare, I can instantly find out where all my friends are. Farmers can automate the planting of crops, ensuring the most efficient use of land. But then it felt like 1492 all over again as we found the edge of the map: neither of these technologies, detailed maps nor accurate positioning systems, exists for the indoor world.

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FEATURED PROJECT

A

PROJECT FEATURED PROJECT

Figure 1: Maps Across Devices

shape of the building’s exterior. A few companies are working on this problem as well, and are making great progress for places like shopping malls where demand is high. But what about the local public library?

What about constantly-changing details at places like convention centers? That’s where we come in.

Indoor positioning is the other half of this problem, and there are some brilliant people working to solve it. Current GPS signals deteriorate once a receiver no longer has a clear view of the sky. Systems like A-GPS use the signals from cell towers to triangulate a user and

augment the data provided by GPS. Other technologies take into account the position relative to statically-located Wi-Fi and Bluetooth access points. Combining these systems with NFC, accelerometers, digital compasses, and advanced computer vision, we could see indoor positioning systems with precision within 1m. Until that’s ready, we’ll be busy filling in the map gaps where outdoors ends, and indoors begins. Success for us will be defined as solving our original problem: helping people feel less like outsiders when they’re inside a building. ■

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Get the Datasheet and Order Samples http://www.intersil.com

High Speed, Dual Channel, 6A, MOSFET Driver With Programmable Rising and Falling Edge Delay Timers ISL89367

Features

The ISL89367 is a high-speed, 6A, 2 channel MOSFET driver optimized for synchronous rectifier applications. Internal timers can be programmed with resistors to delay the rising and/or falling edges of the outputs. Logically ANDed dual inputs are also provided. One input is for the PWM signal and the second can be used as an enable. A third control input is used to optionally invert the logical polarity of the driver outputs.

• 2 outputs with 6A peak drive currents (sink and source) with output voltage range of 4.5V to 16V.

Comparator like logical inputs allows this driver to be configured for any logic level from 3.3V to 10 VDC. The precision logic thresholds provided by the comparators allow the use of external RC circuits to generate longer time delays than are possible with the internal timers. The comparators also allow the driver to be configured with a low output voltage that is negative relative to the logic ground if desired. This is useful for applications that require a negative turn-off gate drive voltage for driving FETs with logic thresholds.

At high switching frequencies, these MOSFET drivers use very little bias current. Separate, non-overlapping drive circuits are used to drive each CMOS output FET to prevent shoot-thru currents in the output stage.

• Typical ON-resistance ~1Ω.

• Specified Miller plateau drive currents.

• EPAD provides very low thermal impedance (θJC = 3°C/W).

• Dual logic inputs with hysteresis for high noise immunity.

• Rising and/or falling output edge delays programmed with resistors.

• ~ 20ns rise and fall time driving a 10nF load.

• Low operating bias currents

Applications • Synchronous Rectifier (SR) Driver • Switch mode power supplies • Motor Drives, Class D amplifiers, UPS, Inverters • Pulse Transformer Driver • Clock/Line Driver

An under voltage lockout (UV) insures that the driver outputs remain off (low) during turn-on until VDD is sufficiently high for correct logic control. This prevents unexpected behavior when VDD bias is being applied or removed.

3.3V ENABLE

VREF+

FDELA

INVA

RDELA /OUTA OUTB

PWM

GND INVB VREF-

RDELB FDELB

12V

RISING OR FALLING EDGE DELAY (ns)

350 300 +125°C (WORST CASE)

250 200 150

+25°C (TYPICAL) 100 50 0

-40°C (WORST CASE) 0

5

10

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RDT (2k to 20k)

FIGURE 1. TYPICAL APPLICATION

January 31, 2011 FN7727.0

FIGURE 2. PROGRAMMABLE TIME DELAYS

Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2011 All Rights Reserved. All other trademarks mentioned are the property of their respective owners.

Advantages of FPGA -based Motor Control Michael Parker

Sr Technical Manager, DSP

S

ystems operated by electric motors commonly utilize control loops that can monitor the position, velocity, current or other aspects to provide the desired operation. This is accomplished by comparing the actual measurements to a desired state, and creating an error signal from the difference, which is input to the control loop.

The output of the control loop drives the motor response. The classical approach is known as PID control or designating the proportional, integration and derivative aspects of the control loop.

The basic equation is:

d v^ t h = K P $ K I $ # e (t) dt + K D $ e (t) dt 0 t

Where v(t) is the controller output that stimulates the motor and the error signal e(t) = desired response(t) – actual response(t).

increases the motor drive as the error increases.

The integration term is present to eliminate a permanent lag in the actual response from the desired response. To accomplish this, the error is integrated over time, and the control loop will respond more forcefully if the error is persistent in one direction. The derivative term is used to allow the control loop to respond very quickly to changes in the error, as can occur if the desired response has a step or instantaneous change. The constant factors KP , KI and KD control the gains of these terms.

Most modern control loops are implemented digitally, necessitating the control loop equations to be converted into a discrete sampled digital form, as shown in the following equation:

v (k) = v (k - 1) + K P $ (e (k) - e (k - 1)) + K I $ e (k

The magnitude - 1response - e (time v (k) = v (ofk the ) + K P $of(eany (k)given k - 1)) + K I $ e (k) + K D $ (e (k) - 2e (k - 1) + e (k - 2)) is driven by the magnitude of the error signal. The KPeis(ksimply constant + K P constant - 1))a+proportional $ (e (k) K I $ e (k) + K D $ (ethat (k) - 2e (k - 1) + e (k - 2))

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TECHNICAL ARTICLE

Motion Control DSP

DSP Builder

IGBT Control I/F ADC I/F Position Encoder I/F

PHY PHY PWM ∑ ∆ A/D

Converters

Power Stage

TECHNICAL ARTICLE

Nios-II Processor

Industrial Ethernet

Motor

Encoder

SOPC Builder

Figure 1: FPGA-based Motor Control Block Diagram

FPGAs offer several advantages in motor control loop implementation compared to microprocessor or DSP implementation. A typical FPGA implementation is shown in Figure 1.

First, in many cases, an FPGA is already present in the system to provide interfacing to data convertors, to positioning encoders, and for real time Ethernet protocol implementations. With the control loop integrated into the FPGA, the use of an external processor can be eliminated, reducing BOM costs.

If a processor is required for non-control loop functions, it can be easily implemented as a soft core processor inside the FPGA. The Altera Nios II soft-core microcontroller is a good example, which can be implemented using less than 1000 logic elements, a very small fraction of the typical low cost FPGA logic resources. This provides an additional benefit of an obsolescence proof microcontroller architecture, as it can be seamlessly migrated to future FPGA device families.

Secondly, the stability of a motor control loop depends on several factors, such as the system gains, the numerical precision of the computations, and the processing time, or latency of the control loop. Use of an external processor nearly always increases the control loop latency, as both the error data and control loop response must pass through

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data convertors or encoders to the FPGA, then to the processor and back again. The control loop latency is the sum of these transfer times plus the processor interrupt response and main loop computational time.

Thirdly, a Simulink-based design flow is available which allows easy conversion of the simulation into FPGA implementation. This design tool is DSP Builder Advanced. It provides designers the ability to implement and verify their FPGA-based control circuits within the Simulink environment. DSP Builder also allows the designer to use either fixed or floating point FPGA implementation, or a mixture of the two. Given that control loops are iterative by nature, the high dynamic range of floating point can greatly simplify design verification and result in greater motor control stability and robustness.

Another unique feature of DSP Builder tool is the ability to control the degree of circuit “folding.” Most digital control loops have sample times far less than the FPGA clock rate. Therefore, it is possible to share common FPGA circuits to compute different parts of the control loop in a TDM fashion, using a technique known as “folding” or reusing the same circuits for different parts of the loop computation.

For a more detailed look at how FPGA design tools can simplify motor control design, comparison

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TECHNICAL ARTICLE

About the Author Michael Parker received his MSEE from Santa Clara University in California, and his BSEE from Rensselaer Polytechnic Institute in New York. He has over 20 years of DSP wireless engineering design experience with companies such as Alvarion, Soma Networks, TCSI, Stanford Telecom, and numerous startup companies. Michael joined Altera in January 2007, and is responsible for Altera’s entire digital

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signal processing (DSP) product planning.

Michael authored a book entitled Digital Signal Processing 101, published in 2010 and has written and published over 20 technical articles on DSP, floating point, and various other technology subjects. â–

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TECHNICAL ARTICLE

of fixed and floating point design resources, and how minimize the FPGA device resources through circuit folding, click here.

Via Return Currents and the Path of Least Resistance

Michael Steinberger

Lead Architect, Serial Channel Products

1.0 Conventional Wisdom A couple of months ago, I was discussing PC board via electrical behavior with a respected colleague, and he happened to mention that the ground return currents for the via would find the nearest ground via and follow that path. Five years ago, I would have said exactly the same thing. However, since then I’ve learned more about the electrical behavior of vias, and I now recognize nearby ground vias as only one of several mechanisms that ground currents can use to follow the signal current. I therefore thought others would find this new-found knowledge useful.

The point of this article is that ground currents will find the path of least resistance (impedance, actually). The path they take will affect the reflection coefficient seen by the signal, and will to a large extent determine the crosstalk in the system.

This article is solely about vias, that is, a planar piece of dielectric with ground planes on both

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sides, holes in the ground planes (antipads), and smaller holes through the dielectric and filled with metal to form signal conductors (via barrels). There are several other structures whose physics are similar, however they will not be addressed directly here.

2.0 A Fundamental Principle The following principle is based on fundamental electromagnetic analysis and explained in detail in [1]: At all frequencies for which the metal in the ground plane is more than a few skin depths thick, the sum of all the currents going through any given hole in the ground plane must be zero.

This means that for any hole in the ground plane, the total ground current flowing from one side of the ground plane to the other across the edge of the antipad is constrained to be equal and opposite to the total current flowing along any via barrels that

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TECHNICAL ARTICLE This at least lets us know where the ground currents are at some specific points in the ground return path.

The question, therefore, is how the ground currents get from the ground plane on one side of a dielectric layer to the ground plane on the opposite side of the dielectric. We’re already aware that one possible path is a ground via connecting to two ground planes, and we’ll get back to that mechanism. But let’s look at some other mechanisms first.

lines are separated by the dielectric disk. Thus, the dielectric disk, ground planes, and that portion of the center conductor passing through the disk form an isolated single ended via with no ground vias.

Magnitude S21 and S12

BLUE: Measured

RED: Calculated with Loss Tangent = 0.40

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???

It is evident from Figure 2 that at least at most frequencies, the ground currents found a return path, and a rather low impedance one at that.

4.5” Figure 1: Via test structure

a dielectric layer? Would that create an open circuit in the ground return path?

No. There are still capacitive and inductive coupling mechanisms that can be important.

Consider the via test structure [1] shown in Figure 1. This structure consists of a circular disk of dielectric (FR4) with gound planes on both sides.

Each ground plane is connected to a coaxial transmission line. The center conductors of the transmission lines are connected through a hole in the dielectric, thus forming one continuous center conductor. However, the shields of the transmission

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At low frequencies, the explanation is straightforward: The dielectric disk acts as an AC coupling capacitor. This model accurately matches the experimental data at low frequencies. At higher frequencies, the explanation is more complex. TEM waves propagate radially out to the edge of the disk and get reflected back to the center of the structure.

At most frequencies, these waves add up to create a low impedance ground path. However, at certain frequencies, the outgoing and incoming waves are exactly in phase at the center of the disk, causing a high impedance resonance in the ground return path. As shown in Figure 2, this radial TEM wave model matches the measured data very accurately across the entire range of measurement.

The radial TEM wave model also offers a different way to look at the capacitive coupling at low frequencies. DC is one of the resonant frequencies of the disk, and the coupling near DC is produced by this resonant mode.

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TECHNICAL ARTICLE

pass through the middle of the hole.

TECHNICAL ARTICLE

These radial waves can be compared to waves on the surface of a liquid. If you’re an impatient Ground Return Impedance - 0.04” Antipad diameter, 0.1” Thickness, Er=3.4

Impedance (Ohms)

BLUE: Zreal

RED: Zimag

100 90 80 70 60 50 40 30 20 10 0 0.0000E 1.0000E 2.0000E 3.0000E 4.0000E 5.0000E 6.0000E 7.0000E 8.0000E 9.0000E 10.0000E +00 +10 +09 +09 +09 +09 +09 +09 +09 +09 +09 Frequency (Hz)

Figure 3: Real and imaginary parts of the ground return impedance for a via on an infinite PC board

coffee drinker like myself, you’ve watched a drip coffee maker near the end of its cycle and noticed the waves caused by the last drips of coffee into the coffee pot. They go outward to the edge of the coffee pot, get reflected, and reconverge in the center of the pot. This is like the behavior of the disk test structure. The radial waves in a real PC board are more like the ripples in a pond. They propagate outward and get dispersed when they reach the shore.

The other extreme is an infinitely large board containing only a single via. The radial waves are only outgoing and there are no reflected waves.

This produces a real and imaginary impedance such as that shown in Figure 3. Note that the impedance is relatively low compared to a 50Ω load, and increases monotonically with frequency.

These results can be scaled to different dimensions for use in first order signal and crosstalk analyses.

The impedance is proportional to the thickness

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Figure 4: Ground currents on a ground plane in the vicinity of a via antipad

of the dielectric layer and the frequency scale is inversely proportional to the antipad diameter.

These impedances are, however, quite high compared to the impedances typically found in a power distribution network. This helps to explain why the vias in a power distribution network don’t share currents as much as one might have expected [2].

The resistive part of the impedance is caused by the fact that there is energy in the outgoing wave, and the energy is entirely dissipated in the surrounding board.

The reactive part of the impedance is a bit surprising at first glance, in that it’s inductive rather than capacitive. This reactance can be explained, however, by considering the pattern of ground currents, as shown by the solid lines in Figure 4.

The outward propagating currents generate a circular magnetic field such as that shown by the dotted lines in Figure 4. This magnetic field extends to the ground plane on the opposite side of the dielectric layer, where it induces currents in the opposite direction (into the antipad).

Further examination of the results of the simple via experiment [1] demonstrates that the capacitive coupling only occurs at frequencies that are just a little higher than a resonant frequency (such as near DC). Since the infinite PC board has no resonances, the coupling is inductive rather than capacitive.

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TECHNICAL ARTICLE

Most vias don’t have the symmetry of the test structure in Figure 1. Thus, if outgoing radial waves are reflected back to the originating via, they are not likely to converge the way the waves on a disk converge. Rather, they are more likely to get reflected into a number of different directions and become dispersed.

TECHNICAL ARTICLE

Insertion Loss with and without Ground Vias at 0.2” Radius BLUE: No Ground

rather than out of phase, as would be the case at lower frequencies. When waves are in phase, their voltages add and so the impedance presented to the external circuit is greater. Even at lower frequencies, the ground vias will present a nonzero impedance to the ground return currents, and that impedance will be a combination of inductance and resistance.

5.0 The Path of Least Impedance

RED: With Ground Vias

The ground vias therefore end up in parallel with the inductive coupling due to the radial TEM waves propagating between the ground planes. It is the parallel impedance of these two mechanisms that is presented to the ground return currents, and the ground return current is shared between these two mechanisms depending on the relative magnitudes of their impedances.

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Figure 5: Insertion loss with ground vias

and dielectric constant [3], and the proposed explanation was that the dielectric constant in the X/Y direction was greater than the dielectric constant in the Z direction. An inductive ground path would be another possible explanation.

4.0 The Role of Ground Vias Figure 5 shows the insertion loss of the via test structure when ground vias are added at a constant radius from the center conductor.

The ground vias certainly kill the resonance at DC, as expected. However, at frequencies for which the ground vias are more than a quarter wave from the center conductor, the ground vias are not at all helpful. The reason is that when the ground via is more than a quarter wave from the signal via, the round trip from the signal via to the ground via and back to the signal via is more than a half wave long, and so radial waves reflected from the ground vias can arrive in phase with the outgoing wave

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At frequencies for which there are ground vias closer than a quarter wave, the ground via conduction path will tend to dominate whereas at higher frequencies, the direct inductive coupling will be the only effective ground return mechanism.

Even at frequencies for which the ground vias are effective, the ground vias will not carry all of the ground return current, no matter how many ground vias there are. Rather, one should think about ground vias in the same way one thinks about the braided shield on a coaxial cable. For example, inexpensive RG59-U cable may have only 70% shield coverage.

In that sense, the shield coverage of the ground vias on most PC board designs is a lot lower than that.

6.0 References [1] Chong, Gopinath, Scearce, Steinberger, and White, “A Simple Via Experiment”, paper 5-TP2, DesignCon2009.

[2] James Weaver, Measuring Supply Currents in Printed Circuit Boards, Ph.D. dissertation, Stanford University, November 2007.

[3] Bogatin, Gupta, Resso, and Simonovich, “Practical Analysis of Backplane Vias for 5 Gbps and Above” paper 7-TA2, DesignCon2009.

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It should also be noted that if the ground return path is inductive, it will tend to increase both the apparent impedance and the apparent electrical length of the via. It has been observed that vias tend to have a longer electrical length than would be predicted based solely on the physical length

TECHNICAL ARTICLE Michael Steinberger, PhD, has over 30 years experience in the design and analysis of very high-speed electronic circuits. Dr. Steinberger began his career at Hughes Aircraft, designing microwave circuits. He then moved to Bell Labs, where he designed microwave systems that helped AT&T move from analog to digital longdistance transmission. He was instrumental in the

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development of high-speed digital backplanes used throughout Lucent’s transmission product line.

Prior to joining SiSoft, Dr. Steinberger led a group of over 20 design engineers at Cray, Inc. responsible for SerDes design, high-speed channel analysis, PCB design, and custom RAM design. â–

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