TECHNICAL ARTICLE 38 38 39 39 40 40 41 41 42 42 43 43 44 44 45 45 46 46 47 47 48 48 49 49 50 51 52 53 54 55 56 57 58 59 50 51 52 53 54 55 56 57 58 59 Verilog/SystemVerilog Verilog/SystemVerilog BEGIN BEGIN CASE current_state ISIS CASE current_state WHEN cars_go WHEN cars_go =>=> (walk_request ‘1’)THEN THEN IF IF (walk_request = = ‘1’) next_state cars_slow; next_state <=<= cars_slow; ELSEIF (walk_request ‘0’)THEN THEN ELSEIF (walk_request = =‘0’) next_state cars_go; next_state <=<= cars_go; ELSE ELSE next_state cars_go; next_state <=<= cars_go; ENDEND IF;IF; WHEN cars_slow WHEN cars_slow =>=> next_state cars_stop; next_state <=<= cars_stop; WHEN cars_stop => WHEN cars_stop => next_state people_go; next_state <=<= people_go; WHEN people_go => WHEN people_go => next_state <= people_slow; next_state <= people_slow; WHEN people_slow => WHEN people_slow => next_state <= cars_go; next_state <= cars_go; WHEN OTHERS => WHEN OTHERS => next_state <= cars_go; next_state <= cars_go; END CASE; END CASE; END PROCESS nextstate_proc; END PROCESS nextstate_proc; 3838 3939 4040 4141 4242 4343 4444 4545 4646 4747 4848 4949 50 50 51 51 52 52 53 53 54 54 55 55 56 56 57 57 58 58 59 59 60 60 61 61 TECHNICAL ARTICLE VHDL VHDL begin begin :: next_state_block_proc next_state_block_proc case case (current_state) (current_state) cars_go: begin begin cars_go: if (walk (walk request==0) request==0) if next_state == cars_go; cars_go; next_state else if if (walk (walk request==1) request==1) else next_state == cars_slow; cars_slow; next_state end end cars_slow: begin begin cars_slow: next_state == cars_stop; cars_stop; next_state end end cars_stop: begin begin cars_stop: next_state people_go; next_state == people_go; end end people_go: begin people_go: begin next_state = people_slow; next_state = people_slow; end end people_slow: begin people_slow: begin next_state = cars_go; next_state = cars_go; end end default: default: next_state = people_go; next_state = people_go; endcase endcase end // Next State Block end // Next State Block Figure 5 Today we looked at ways to create synthesis-friendly state machines that are easy to understand and reuse. In the next article, we will look at coding Mealy and Moore state machines and our options for dividing nextstate logic and output logic. since he joined Gateway Design Automation—the company that invented Verilog. Over the course of his career he has worked at Cadence, Sun Microsystems, and Mentor Graphics. Ray is currently an Applications Engineer Consultant with Mentor Graphics. ■ About the Author Ray Salemi is a veteran of the EDA industry and has been working with Hardware Description Languages EEWeb Electrical Engineering Community Join Today EEWeb | Electrical Engineering Community www.eeweb.com/register Visit www.eeweb.com 24