EEWeb Pulse - Volume 46

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Issue 46 May 15, 2012

Jean-Louis Malinge Kotura Electrical Engineering Community

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TA B L E O F C O N T E N T S TABLE OF CONTENTS

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Jean-Louis Malinge KOTURA Interview with Jean-Louis Malinge - CEO and President

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What is Silicon Photonics?

BY JEAN-LOUIS MALINGE The new optical communication technology that is revolutionizing the telecommunications industry.

Featured Products From PSPICE Netlist to Allegro Design Sub-Circuit

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BY DON LAFONTAINE WITH INTERSIL This step-by-step procedure enables the user to take any PSPICE netlist and convert it into a sub-circuit for insertion into their Cadence Allegro simulator.

Thermal Basics of Complex Devices

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BY ROGER STOUT WITH ON SEMICONDUCTOR Practical concerns and considerations for device level thermal management.

RTZ - Return to Zero Comic

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INTERVIEW

Malinge Kotura

How did you get into electronics/engineering and when did you start?

As you probably already noticed from my name, I am of French origin. I am a physicist by training and received my education in France in the 70s. When I was

initially searching for work, I was looking at industries or technologies that were at the very beginning of their life, and showed promise for success, which brought me to two areas. One was gallium arsenide devices because this was before the time that silicon was as available

Jean-Louis Malinge - CEO and President

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as it is today, and gallium arsenide was a good material system for fast electronics. The other area was optical fiber. I ended up randomly starting in optical fiber and photonics for communications and joined a company named Thompson CSF, a very large group in France. I started to work initially in the design and development of the first fiber optic communication line in France, which was in downtown Paris at the end of the 70s. I then migrated progressively to work on the design and realization of the first broadband network of what was one of the first Fiber to the Home (FTTH) demonstrations. At the end of the 1980s, I joined Corning Inc., which is a large fiber optics company headquartered in upstate New York. I started working for Corning in France, migrated to the US in the early 1990s. After that, I went through an executive MBA at Sloan School at MIT and joined the US side of Corning, working

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FEATURED INTERVIEW

Jean-Louis

INTERVIEW

In 2004 we started Kotura, where I am now, to focus on the next wave of photonics in the network using silicon as the material system of choice to design, develop and manufacture opto-electrical components.

How did you initially form your company? Was it yourself and other people?

Kotura is the restart of a startup that was created during the Internet bubble days in 2000. By 2003 and 2004, the original company was going nowhere, so the investors decided to restart the company at which time I joined as the CEO. At that point, Kotura had no product sales, but there was a base of technology and engineers. We restarted the company during the worst period of time for photonics because it was very difficult to talk about photonics and communication in the same sentence and be able to raise any money.

Can you tell us about the company—some of the products you guys have developed over time or areas of development that have gained traction?

The goal of Kotura is to build optical components on the same material and using the same platform that

we do to manufacture integrated circuits. Until recently, all of the photonics components that are used in telecommunication networks are based on a multitude of platforms and materials that are assembled together in modules to create a particular function, for example, an optical transmitter or an optical receiver. In a nutshell, our objective is to use the experience

The goal of Kotura is to build optical components on the same material and using the same platform that we do to manufacture integrated circuits. and the learning curve of the entire IC industry in silicon and reuse the materials base to manufacture photonics components. In 2006, we started to ship products in volume completely based on this silicon photonics platform. Currently, our products are used by three of the top five telecom companies and dozens of smaller companies running live voice and Internet traffic all over the world. Our devices have logged over 1 billion hours in the network, gaining us credibility with our customers and demonstrating the quality and reliability of our products.

Every few years, we are developing a new generation of those chips – some are enhancements of a

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previous design, but some are brand new devices that we are trying to bring to the market. We are currently working on a design that can transport 100GB of data over a single fiber for distances up to 10km while consuming less than five watts of power. These chips are quite complex; they integrate Wavelength Multiplexing and Demultiplexing on the chip, and they are much smaller than a postage stamp. They will enable high speed links between routers and servers in the data center, which is really where we are aiming our technology.

Do you have a fab or are you a fabless company?

We have a small fab that is doing two things for us: it provides quick turnaround on new designs, and it manufactures the products that we are sending to different OEMs. We start with bare CMOS wafers, then we fabricate all of the optoelectronic functions on them. Those wafers are diced and packaged by a contract manufacturer in Asia.

Our finished products are shipped to key customers around the world.

Besides the standard products that you are currently making, do you license your technology if people would like to include some of this photonic technology in an IC design they might be working on?

We are engaged in discussions about licensing technology. Since we founded the company, we have created a lot of patents. Kotura currently has around 140 patents on our silicon photonic products and design. Of those, there are 70 granted patents and 70 applications.

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FEATURED INTERVIEW

first in development, and migrating progressively to the business side.

By the end of the 1990s, I was running a large division of Corning focused on optical components.

When telecom collapsed in 2001, all of the companies in telecom and photonics experienced a very sudden large revenue decrease and had to restructure their assets.

INTERVIEW also inside

Our company actually looks like the Los Angeles area. We have a world class team and an extremely diverse set of people... this diversity is, I think, very important in creating the kind of technology we are developing... data centers. This demand has to be resolved by a new technology platform like silicon photonics, and we believe this will happen in the few years to come.

Any particular area or application you plan to target first?

What we are working very actively on right now are solutions for data centers, supercomputers and then eventually consumer electronics.

We are focusing a lot of our design and development power on what we call a 100G optical engine in silicon, where essentially from this very tiny chip we can push through the fiber 100G of information. Side by side, if we multiplied that by a large number of fibers, you can reach very quickly a large bandwidth of information transmittance. What we are developing today is mostly going

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into telecommunication networks, data centers and supercomputers.

How many people work for Kotura?

We currently have 60 to 65 highly technical employees based in Monterey Park, California, just outside of Los Angeles. Those people are mostly engineers and PhDs. In fact, we have 22 PhDs. Designing and fabricating optical chips in silicon is a big task with a huge impact for our customers.

Our packaging is done at a contract manufacturer in Asia. Last year, we opened an office in Shenzhen, China.

How would you describe the work culture in your company?

Our company actually looks like the Los Angeles area. We have a world class team and an extremely diverse set of people. The number of languages spoken here is amazing. This diversity is, I think, very important in creating the kind of technology we are developing as we are looking at doing things very differently, and we need to bring a lot of innovation and a lot of new ideas to this world. I speak of diversity of origin, but obviously we have diversity of skills and backgrounds too—those with IC backgrounds, process engineering backgrounds, optical design backgrounds. All those people are living in a close environment with each other, which is a good way to create innovation by mixing different skills and expertise close together to try to facilitate communication between those different groups of people.â–

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FEATURED INTERVIEW

So this is an area where we are generating intellectual property and discussing with interested parties about licensing some of the things we have done. We are at a turning point in this entire photonics industry that I will try to describe. All the way back to the 90s and early 2000s, after the collapse of the Internet bubble, optical fiber communication was mostly limited to the long distance transport of information. When you want to transport data from LA to NY or LA to Paris, that transmission is completely through optical fiber.

The metro area around major cities is also based upon fiber optics. But, up until a few years ago, for shorter distances when you were going a little further down in the layer of the network, everything was mostly copper with very limited optics.

The industry had not yet reached the need of optics at that level because the Internet was a smaller place, speeds were slower and power consumption was not a big issue. Today, the Internet is huge and growing fast. We are currently at a period of time in which we are accumulating and storing an unbelievable amount of data. There are numbers showing that every year we are accumulating and storing as much information as we did for the entire history known to mankind on this world. This is creating a huge stress in all those data centers and all the different boxes inside the data center that we are using to create and store the data. Social networking sites like YouTube and Facebook are all adding more video, images and data to be stored and transmitted. This is creating a huge bandwidth demand; not just on the long distance networks, but

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What Is Silicon Photonics?

Jean-Louis Malinge CEO and President at Kotura

Ever since the invention of the transistor more than 60 years ago, semiconductor chips have used electrons for communications.

Each new generation of devices offered more transistors in a smaller area, operating at faster speeds.

Today, the semiconductor industry exceeds $250B per year with a single CMOS chip containing as many as a billion or more transistors.

These complex circuits are still 100 percent electrical.

required exotic material systems for lasers, detectors, filters, isolators, modulators, and switches. Optical transceivers were hand assembled from hundreds of piece parts and, in many cases, still are today. Even though it was expensive, optical communication had the advantage of being able to transmit huge amounts of data over long distances.

The Internet was built using the back bone of telecommunications optical networks.

Meanwhile, during the 1980s, optical communications based on lasers and optical fiber was introduced for long distance telecommunication. Instead of lowcost silicon, optical communication

Silicon photonics brings optical communication into the semiconductor industry, enabling a whole new range of applications.

Opto-electronic functions are fabricated on the same CMOS

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wafers using the same equipment and methods as electronic chips.

The wafers are processed in the same fabs as those running electronics chips. The wafers are diced into chips just like electrical ones. Optical chips can be just as inexpensive as their electrical cousins. When mass volumes are needed, the wafer fab simply runs more wafers of the same recipe.

Silicon photonics eliminates the need for hand assembly of hundreds of parts. Silicon photonics chips are much, much smaller than the optical subassemblies they replace. A silicon photonics chip can support 100 gigabits per second transmission on a chip less than half

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PROJECT

Previously, optical solutions assembled from discrete components had to be packaged in expensive, hermetically sealed packages. A speck of dust between any of the components would

inhibit the light path and render the product useless. By contrast, silicon photonics devices are totally selfcontained within the layers of the chip. With no need for hermiticity, they can reuse low-cost industry standard electronics packaging.

Another huge advantage of optical communication is Wave Division Multiplexing (WDM). With WDM, four, eight or even 40 channels of light, each at a different frequency, can operate in parallel over a single strand of optical fiber. Fiber is cheap, especially when a single strand is replacing so many copper cables. On the computer board itself, optical buses consume far less space than electrical buses,

allowing more space for CPUs, memory and switching chips. For large pipes, optical interconnect is far less expensive than copper cabling.

We are in the early stage phases of silicon photonics. The capability to bring faster, smaller interconnects, which consume less power, offers the entire semiconductor industry a whole new world of opportunities.

Next generation data centers, high performance computers and eventually consumer video products will all benefit from optical interconnects built from silicon photonics. â–

Figure 1: Kotura’s optical engine is just two tiny silicon photonics chips that can transmit data at speeds of 100 Gb/s and more. Wafer scale integration eliminates hundreds of piece parts and cost effectively scales to millions of units.

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FEATURED PROJECT

the size of a postage stamp, which enables faster communications between the high speed CPU chips in supercomputers and the memory or other CPUs. This new technology allows high speed routers and switches in data centers to communicate with pipes of 100 Gb/s instead of 10 Gb/s. These chips can enable the backplanes in high performance computers to run at 100 Gb/s, 400 Gb/s or even one terabit per second.

F E AT U R E D P R O D U C T S Avago Technologies, a leading supplier of analog interface components for communications, industrial and consumer applications, announcedthe ACPL-M21L/021L/024L/W21L/K24Loptocouplerfamily.

These optocouplers consume less power as compared to other similar 5MBd optocouplers in the market. The ACPL-x2xLoptocouplers are designed to meet customer needs for lower power, higher isolation voltage, and better common-mode rejection (CMR) performance, thanks to the excellent performance of the new LED and detector IC design.

Avago Technologies’ digital optocouplers are used in a wide variety of isolation applications ranging from power supply and motor control circuits to data communications and digital logic interface circuits. All newoptocouplers are compliant to industrial safety standards such asIEC/EN/DIN EN 60747-5-5 approval for reinforced insulation, UL 1577 and CSA. The first available optocoupler, the ACPL-M21L is immediately available in sample quantities, and will sell for $0.88 apiece in lots of 10k units. For more information, please click here.

Broadband RF Mixer Linear Technology announces the LTC5567, a 300MHz to 4GHz downconverting mixer with outstanding IIP3 (Input Third Order Intercept) of 26.9dBm, low power consumption of 294mW, and wide IF bandwidth of 2.5GHz to support 4G wireless base stations and a wide range of high dynamic range receiver applications. The LTC5567’s wide 300MHz to 4GHz operating frequency range provides versatility in a single device, enabling operation in any of the cellular bands from 700MHz to 2.7GHz. The mixer features a conversion gain of 1.9dB and a noise figure of 11.8dB, providing excellent dynamic range for a wide variety of receiver applications. Additionally, the LTC5567’s IF output has a wide frequency range of 5MHz to 2500MHz, supporting wideband applications such as cable TV downlink transmitters and digital predistortion (DPD) receivers. Moreover, the LTC5567’s RF input is designed to withstand strong in-band blocking signals, while delivering a best-in-class noise figure of 16.5dB with a +5dBm blocker, ensuring enhanced receiver sensitivity in the presence of interference. For more information, please click here.

Contsant Power LED Controller Texas Instruments Incorporated introduced a new LED controller with constant power regulation. The LM3447 AC/DC LED driver includes a dimmer detect, phase decoder and adjustable hold current circuits to provide smooth and flicker-free dimming operation in off-line, isolated LED lighting applications, including A19, E26/27 and PAR30/38 bulbs, as well as can light retrofits. raditional drivers use constant current control to accurately regulate LED forward current. This approach produces consistent light output or intensity from LEDs in the same bin. However, once current is applied to the LED, its solder point temperature rises, leading to a decrease in forward voltage and a drop in efficacy. Conversely, by using the new LM3447 with constant power regulation, the LED forward voltage droop over temperature is offset by an increase in LED current to maintain constant LED power. The result is up to 10-percent improvement in efficacy across the expected operating temperature range of the fixture. For more information, please click here.

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FEATURED PRODUCTS

Low Power 5MBd Digital Optocouplers

From

PSPICE Netlist

to

Allegro Design SubCircuit Here is a common everyday scenario in the electronics industry: Designers who’ve found a good op-amp for their project want to run simulations on their design before they head into the lab to build up a prototype. They note that the device manufacturer offers a PSPICE model netlist in their data sheet, but remain unsure how to convert the PSPICE model netlist into a sub-circuit for the simulator. If the simulator is a Cadence Allegro simulator, then there is a step-bystep process to convert the data sheet netlist into a sub-circuit for simulations.

Intersil provides a PSPICE model

for all their low-speed and low power precision amps at the end of data sheets. The PSPICE model netlist and netlist schematics are included in the data sheet, along with simulation vs. characterization curves to highlight the accuracy of the PSPICE models. (To find out more details about the making of these PSPICE models, reference application note AN1556.)

Copying the PSPICE Netlist Download the data sheet or the PSPICE netlist from the web. The data sheet or netlist will be in .pdf format. Open the .pdf document and right-click to enable the select Don LaFontaine tool, if it is not already selected. This Senior Application Engineer

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Model Editor Open the Cadence model editor (Cadence SPB16.2\AMS Simulator\ Simulation Accessories\Model Editor). (Note: The version of Cadence software used in this example is SPB16.2.) The look and feel may change with different revisions of the Cadence software, but the procedure will be the same.

After selecting the Model Editor, the Select Design Entry Tool screen will appear. Choose the Default Design Entry tool “Capture” by clicking the radial button to the left of the word “Capture,” if the default has not already selected it, and click “DONE.” Click on “File” in the tool bar and select “New.” Click on “Model” in the tool bar and select “Import.” Then browse to the folder where you put the (your file name).MOD. Select the .MOD file and click “Open.” This will load the

netlist into the Model editor tool.

Click on “File” in the tool bar and select “Save As.” Then, type the part name as the file name to keep track of the project and click “Save.” The file with the complete netlist is now saved as a .lib library file. Click on “File” in the tool bar and select “Export to Capture Part Library.”

The Input Model Library path and the Output Part Library path will automatically be loaded. Verify that the file’s pathnames are the same with the only difference being the .lib and .olb extensions. Click “OK” and verify no “Error” messages or “Warning” messages occurred at the bottom of the screen (STATUS: 0 Errors messages, 0 Warning messages). Click on “File” in the tool bar and select Model Import Wizard [Capture]. Like before, both pathnames will load automatically and should have the same file paths with the only difference being the .lib and .olb extensions. Click “Next” and the screen shown in Figure 1 will appear.

This is the screen in which we will associate the pins of our PSPICE

model to the pins of the sub-circuit model. The symbol shown is a generic 5 pin device. We want our Op-amp symbol to look like an Op-amp. To do this, click on the Replace Symbol button and select from the list of symbols provided with the Cadence program. This list is located at the following location on your C drive (C:\Cadence\ SPB.16.2\tools\capture\libar y\ OPAmp.olb).

If the location of your Cadence software was loaded in a different location, then search for “Cadence\ SPB.” When selecting your symbol, all that matters is the pin count. The numbers assigned to the symbol pins can be changed later. Just scroll through the list to find a symbol that matches a desired pinout and pin count of your device.

In this example, we selected the TLC2201. Click “Next.” Then click on the row under the Symbol Pin column to activate pull down menu box under the symbol column. Now pick the associated pin to match the Model Terminal function in the Model Terminal column. Repeat for all Model Terminal pins as shown in Figure 2.

Click “Save Symbol” then finish and verify no “Error” messages or “Warning” messages (STATUS: 0 Errors messages, 0 Warning messages). Click “OK” and then close the Model Editor. You have now created the sub-circuit to import into your simulator.

Using the New Sub-circuit to Run Simulations Open

the

Cadence

Software

Figure 1: Replace Generic Symbol

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will enable you to then copy and paste the entire netlist into Notepad.

Name the file with the extension .MOD (not case sensitive). This file needs to be saved in a common directory with all the other files for this design.

TECHNICAL ARTICLE

Click “OK.” Click on .\(your file name) .dsn and then the SCHEMATIC1 to open the PAGE1 tab and then click on the PAGE1 tab. This is where the new subcircuit will be placed to run the simulations. Before we can place the new sub-circuit model and run a simulation, we need to set-up the simulation profile and add the library. Click on PSPICE in the tool bar and select “New Simulation Profile.” Then, type in any name that will help you keep track of the different simulations and click “Create.” Click the “Configuration Files” tab at the top. Then click on “Library” in the Category field on the left hand side. Browse to where you saved the Library file (.lib).

Then click the “Add to Design” button. The Simulation Settings screen should look like that shown in Figure 3 with the file path name being the location of the common directory.

Figure 2: All Pins Associated to Symbol

Click the “Apply” button.

Figure 3: Configuration File to Add Library

(Cadence SPB 16.2\Design Entry CSI). From the Cadence Product Choices screen, Select “Allegro Design Entry CIS” and click “OK.” Click on “File” in the tool bar and select “New,” and then “Project.”

Type in the name of the project and click on the radial button to the left of Analog of Mixed A/D. Browse to where you saved the Netlist in the common directory (you must have

all the files located in the same directory) and click “OK.” The user can select to base their new project on an existing project or start a new one. Selecting to base upon an existing project will carry over the existing project with all the simulation profiles and schematics.

This can be a real time saver if the new project is very similar to an old

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Now click the analysis tab (Figure 3) and configure the simulation for the simulation conditions desired.

In this example, we will setup the simulation as follows: Analysis Type = AC Sweep/Noise, Options = General Settings, Start frequency = 0.1Hz, End Frequency = 100Meg Hz, Points/Decade = 100.

The analysis selected for this example is an AC Sweep/Noise.

Other types of analysis are: Time Domain (Transient), DC Sweep and Bias Point. Just click the down arrow in the analysis type section to access the different Analysis options. When

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project. In this example, we will choose to create a new project.

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Adding the Sub-circuit to Your Simulation Schematic

Figure 4: Part Placement Tool

finished, click “OK.” The user will need to add the Library .olb to the simulator. To do this, click on “Place” in the tool bar and select “Part.” This will bring up the part placement tool at the far right of the simulator as shown

With the .lib file added to the simulation profile and the .olb file added to the part placement tool, you are now ready to place the Op-amp sub-circuit into your simulation schematic. Figure 4 shows the part placement tool after the .olb has been added to it. Under the Libraries section of Figure 4, find the new .olb symbol you added in the previous step (highlighted in blue). Double-click on the file to add the sub-circuit to the “Part” list section (also highlighted in blue).

Double click on the “Part” in the part list section and add the sub-circuit to the simulation schematic. You are now able to configure the Op-amp for simulations.

This step-by-step procedure enables the user to take any PSPICE netlist and convert it into a sub-circuit for insertion into their Cadence Allegro simulator. The straightforward PSPICE models offered by Intersil (reference AN1556) make it easy for the user to edit the netlist and run worst-case simulations for some of the Op-amp parameters.

About the Author Don LaFontaine is a Sr. Principal Application Engineer/Sr. Engineering Manager with Intersil’s Signal Path product line in Palm Bay, Florida. His focus is on precision analog products. He has been with Intersil Corp. for the last 30 years. He graduated from the University of South Florida with a BSEE in 1985. ■

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in Figure 4. To add the library, click on the tab where the arrow is pointing to in Figure 4. Browse to where you saved the Netlist in the common directory, select the .olb file and click “Open.” The new .olb file has been added to the library list (highlighted in blue Figure 4) Now you are ready to add the sub-circuit to your simulation schematic and start your simulations.

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TECH N IStout CAL ARTICLE Roger Senior Research Scientist

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Thermal Basics of Complex Devices Back in the days when most electronics components were packaged in metal cans (or manufactured as axial leaded devices with equipment housings generally spacious and un-crowded), matters of device level thermal management were relatively straightforward for design engineers. Sadly, thermal management has become much more of a challenge nowadays – both to understand and to tackle; with multi-pin plastic packaged devices in ever-shrinking formats being incorporated into high component density portable electronics with considerable pressure being placed on available space and overall power efficiency.

The following article details some of the key areas of concern in regard to device level thermal management in modern electronic products, with explanations of the fundamental theory behind it as well as some practical considerations.

First principles As we all know from basic thermodynamics, heat energy will flow from a higher temperature region to a lower temperature region (this being done through either

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conduction, convection, radiation or often a combination of these). Furthermore, the bigger the temperature difference witnessed, the greater the flow of heat will be.

Historically, for discrete devices, the ‘junction’ referred to in the term junction temperature (TJ) was the PN junction of the device. Though this is true for basic rectifiers, bipolar transistors, etc, the junction now generally refers to the hottest point within the device. As we move towards more complex device constructions where different parts of the silicon have different functions at different times, locating the precise position of this point can be very difficult.

A common misconception often held by engineers is that a device’s thermal resistance is an intrinsic property of the package in which it is enclosed. Among the reasons why this does not hold true is the fact that there is no isothermal surface, making it impossible to define a ‘case’ temperature. Though the metal can devices of the past had a relatively good approximation of an isothermal surface, modern plastic packages tend to exhibit quite large gradients. Furthermore, in modern package types

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Avoiding thermal runaway

Figure 1: Difficulties in defining thermal characteristics of modern device packages – due to gradients across package surface plus leads being at different temperatures

different leads will be at different temperatures, with multiple, parallel thermal paths leaving the package.

Probably the most common thermal parameter cited on a device’s datasheet is θJA. Unfortunately, when it comes to designing a device for a system to locate its TJ, this figure can often be misleading.

Many people unwisely think of θJA simply as the ratio of junction temperature rise above the ambient level to the power dissipated in the device. This suggests that as long as the ambient temperature for the application is known, it is possible to figure out how much power the device is going to dissipate in any specific scenario. From this, engineers assume they will be able to estimate the actual junction temperature of their device and come up with an upper limit for TJ, so they have a reasonable design margin to work with. Sometimes, device manufacturers will provide relatively thorough footnotes describing the test conditions under which the reported θJA was measured.

The simple truth is that θJA is not a measure of the device’s ability to dissipate heat on its own, but, in fact, is a measure of the entire system, including the device. In many applications, the device actually has the smallest direct contribution to its θJA value of all the system variables. Factors that prove to have a more profound effect are: area, air flow, board area/thickness, the number/density of power/ground planes, PCB

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Thermal runaway takes place if a semiconductor device reaches a point where it effectively has too much heat to sufficiently dissipate. The device’s temperature rises as a result and, as it is a function of temperature, further impinges on the device’s ability to dissipate heat.

Effectively, the device enters a condition, through an increase in its TJ, which changes its characteristics so that it is no longer possible to attain a nominally steadystate operating point. From there, the whole thing can rapidly snowball, with the device burning out. However, what is rarely recognized is the fact that this phenomenon can be initiated well below the maximum TJ value stated on the device’s datasheet.

If the thermal system around a given device has a steadystate thermal resistance, then it is possible to describe this steady-state condition using the following equation:

TJ = Q :iJx + Tx

(1)

With: TJ representing the junction temperature (in °C) Q representing the device’s power dissipation (in W) θJx representing the system’s steady state thermal resistance (in °C/W) Tx representing the thermal ground for runaway based on θJx (in °C).

Examining equation 1, it is clear that a slight alteration in power will result in a small change in the TJ level. If the power level briefly rises above the equilibrium value but then returns, TJ will also return to its equilibrium. From this equation, the following relationships can be derived:

Q = (TJ - Tx) /iJx

(2)

(dQ/dT) is the rate of change of system power dissipation with respect to changes in junction temperature.

Equations 2 or 3 show that for a small increase in TJ, the system can dissipate slightly more power than the original Q. Utilization of mathematical models allows the true nature of thermal runaway to be understood. It

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thickness, proximity/density other devices, etc. What device manufacturers cannot inform engineers about on the datasheets is the influence on θJA of the other heat sources within the overall thermal system.

TECHNICAL ARTICLE Q

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System Line As temperature rises, more heat may be dissipated Device Operating Line

With a decrease in temperature the system dissipates less power so that the temperature rises and equilibrium is restored

TX

TJ

T

Figure 2: Power dissipation versus temperature

also ensures that engineers give themselves adequate margins so that devices’ continued operation is ensured.

Figure 2 shows power dissipation on the vertical axis and temperature on the horizontal axis. The gently sloped red line is referred to as the ‘device operating line.’ This represents a device whose power dissipation increases with temperature. The blue diagonal line describes 1/ θJx as set out in equation 3. This is referred to as the ‘system line.’ It describes how increases in the device’s operating temperature go with increasing amounts of power that may be successfully dissipated from that device. The intersection of these two lines gives the nominal steady-state operating point. Thus, to the right of the steady-state operating point, more power leaves the system than the device produces, so it cools; to the left, less power leaves the system than is introduced, so it heats up. Either way, the imbalance in power causes TJ to move back toward the steady-state operating point.

Once this stability is lost, however, the device is at risk of thermal runaway. This will happen if the slope of the blue line is less than that of the red line In summary, the whole business of ensuring device level thermal management has become increasingly

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difficult with the advent of more compact, powerdense, functionally-complex devices enclosed in plastic packages. Inside the package, there are multiple heat paths that need to be taken into account; the idea that the package’s thermal properties can be represented by a single number is, at best, naive. Simultaneously, outside the package, specific boundary conditions dictate how heat flow from the device takes place. Engineers need to be fully aware of the thermal issues involved if their system designs are to achieve the reliability and performance levels they require.

About the Author Roger Stout received his BSE in Mechanical Engineering at ASU in 1977, and went on as a Hughes Fellow to earn his MSME at the California Institute of Technology in 1979.

He then joined Motorola in the equipment engineering side of the semiconductor business, which after about four years evolved into factory automation and control engineering. In about 1990, he took on the responsibility for thermal characterization of ASIC products. Roger holds six patents, and has been a registered Professional Engineer (Mechanical) in the state of Arizona since 1983.

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