EEWeb Pulse - Volume 48

EEWeb

PULSE

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Issue 48 May 29, 2012

Russ Croman Silicon Labs

Electrical Engineering Community

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TA B L E O F C O N T E N T S TABLE OF CONTENTS

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Russ Croman SILICON LABS Interview with Russ Croman - Director of Engineering, Broadcast Audio Products

Featured Products Illogical Logic - Part 2: Karnaugh Maps

BY PAUL CLARKE WITH EBM-PAPST This installment shows how K-Maps can clean up the messy task of creating logic gates.

NAND Evolution and the Future of Solid State Drives

9 11 15

BY ELI TIOMKIN WITH WESTERN DIGITAL With next-generation solid state media technologies, several evolutions loom on the horizon as future storage options are being put to the test by system manufacturers and storage vendors.

RTZ - Return to Zero Comic

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INTERVIEW

Croman Silicon Labs Russ Croman - Director of Engineering, Broadcast Audio Products

How did you get into engineering and when did you start?

I graduated from Washington State in 1993 with a Master of Science in Electrical Engineering. I studied under Dr. Terri Fiez, who is now

the department head at Oregon State University. I got my masters in Analog Circuit Design and did chips as a part of my thesis, which is becoming less and less common—to actually have the design fabricated and measured

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it in the lab. I eventually came to interview here in Austin at Crystal Semiconductor, which had just been acquired by Cirrus Logic, and was hired by them in May 1993.

I worked there in the hard disk drive read channel group for about seven years, which was an exciting field at the time. We revolutionized that area by applying some new signal processing techniques and also implementing the solutions in a single CMOS chip, which is a theme in everything I have worked on. CMOS mixed-signal design allows you to make a lot of system-level optimizations, such as implementing things in the digital domain that you previously implemented in the analog domain and vice versa. I then moved on to Silicon Labs in August of ’99 and started work right away on cell phone transceivers, which was a brand new product at that time. Silicon Labs had previously

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FEATURED INTERVIEW

Russ

INTERVIEW

How would you describe the culture at Silicon Labs?

Right off the bat, it was very dynamic and very driven to improve things.

Even if it’s something that has been done the same way for a long time, we would see if we could do things better: higher performance, lower power, less die area, etc..

That is a core part of the culture, I think. I came in before Silicon Labs went public, so it was very much a start-up company and since then, we’ve transitioned through that into a medium-sized going toward a larger company. That’s been an interesting journey. When you get past the start-up phase and you get closer to the “big company”

phase, there are challenges in keeping the design culture and innovative spirit alive. You start to have multiple product divisions within the company and you have to work to overcome organizational barriers that arise between groups of engineers and so forth. It was sometimes a struggle, but I think we’ve done a pretty good job of

I think the best advice I could give would be to remain constantly willing to step back from what you are doing and look at the big picture. It’s easy to bury yourself in the technical details of a task... keeping that innovative spirit and excitement alive. Now I’m a manager, and I feel it’s my job to ensure that it stays fun to come to work in the morning—I don’t want it to feel like drudgery or to feel like we are doing the same kind of chip that we’ve done before but just in a new process. We want to keep it innovative and fresh for our designers.

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In the design area where you work, how many engineers are there?

In my area, we do all of the broadcast radio tuner products. On the hardware side, I think there are around 18 engineers, both analog and digital. We have large systems and applications teams as well, about 15-20 engineers in total, who design the embedded firmware and applications circuits for our chips.

What architecture do you use for your microcontrollers and DSPs? For microcontrollers, we have mainly used the 8051 core. Silicon Labs acquired a company called Cygnal, which developed 8051based 8-bit microcontrollers with some high-end analog peripherals, so we started using that in our FM and AM tuners, which opened a whole new world of possibilities.

Instead of designing a tricky analog calibration circuit or a custom digital calibration engine, these things could be implemented much more flexibly in software. As far as the DSP goes, we developed our own, so that’s been an in-house operation.

Silicon Labs recently introduced the company’s first 32-bit microcontrollers – the Precision32™ family of ARM Cortex-M3 based MCUs. The advent of our 32-bit MCUs not only expands our served available market for embedded controllers, it also opens up many more possibilities to deliver innovative solutions based on ARM technology, such as wireless MCUs that combine a 32-bit MCU core with a high-performance RF transceiver.

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FEATURED INTERVIEW

been successful in building RF synthesizer chips for cell phones. I worked on the team that extended that basic technology to build a whole transceiver, and I mainly worked on the transmitter section of that project. A funny story about that was when I came to interview with the three founders of Silicon Labs, the CEO of the company was my original hiring manager at Crystal and so he and I already knew each other. We did the interview, and it all went fine and at the end of the day, he asked me what I wanted to work on. I told him if I had my choice, I’d work on RF circuitry, but I admitted to him that I didn’t really know anything about RF. He replied, “That’s okay, neither did we!” It was a very telling fact about Silicon Labs in that you didn’t have to necessarily be an expert in RF circuitry; you just had to know the fundamentals and principles, and you could derive everything else that you need to know. I appreciated that attitude!

INTERVIEW

What opportunities do you foresee for the industry that will change the designs you’ve been making 10 years from now?

I think that standard analog AM/ FM radio reception is kind of a done deal. I don’t think it’s possible to optimize a lot further than what we’ve already done. There are the emerging standards for digital broadcast radio, such as HD radio here in the U.S. and DAB radio over in Europe. I think the jury’s still out on whether those markets will really take off, but Silicon Labs definitely intends to either be there when that does happen, or in my view, to actually help make that happen by providing solutions that are compelling and that can help those markets actually succeed.

On another note, why don’t you tell us a little bit about your passion for astrophotography?

For people who know me, I don’t do anything halfway, and my hobbies become another profession in a sense. I have been very interested in astronomy since I was a kid when my dad showed me Saturn through a telescope. In college, I

had gotten into photography, doing primarily sports photography for the school newspaper. So I had experience with photography and cameras and how to make a decent photograph. I eventually bought a a small telescope that was on sale at the mall and spent about three months star-gazing with it out in the driveway. Then I thought it would be interesting to see if I could put a camera on the end of it and take some pictures, and then it was all downhill—or uphill—from there, depending on how you look at it. I guess my wife would say downhill, although I have to say she is very tolerant of my hobbies, for which I am very thankful.

After a while, I started to think that if I had a bigger telescope, I could see more, and if I had a better camera, then I could take better pictures, so I got a bigger telescope and then a better camera, and then another bigger telescope.

Eventually I built an all-robotic remotely-operated observatory in New Mexico. (My wife surely thought I had gone off the deep end after that!) The observatory is up high in the Sacramento Mountains to avoid all of the light pollution of the city, resulting in much better photos. Since it was all-robotic, I could automate it to take pictures all night while I went to sleep!

What’s the size of the aperture mirror in the telescope you built?

It has a 20-inch mirror and the optical design is called a Ritchey-Chrétien, which is the same optical design as the Hubble Space Telescope.

It’s got double hyperbolic surfaces on its mirrors, which are very

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hard to manufacture, but produce really great image quality. The camera is an 11-megapixel cooled astronomical CCD camera with filter wheels and guide cameras and the whole nine yards for getting really good images.

Were you able to get all of your images on a laptop or PC? I could put them anywhere, really.

In fact, most recently, I was running all of the imaging sessions from my iPad! The thing I loved about astrophotography, aside from the beauty of the final images, was all of the million little technical details that have to be right for an imaging session to work—all of the equipment has to be just right and sometimes you have to compensate for changing weather or changing atmospheric conditions, which maybe would influence which filters to use that night or how long to make the exposures. All of those factors kept it exciting for me. It really used all of my engineering skills!

What was your favorite thing you’ve been able to capture?

The one I’m most proud of is called, “The Orion Nebula in Mapped Color,” which is a super-colorful image of the Orion Nebula. It was taken through some special filters that isolate the emissions from individual chemical elements within the nebula—hydrogen, sulfur, oxygen—and it maps those emissions into new color space to show the structure and energy levels within the nebula in unique way. This photo was actually published in National Geographic,

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FEATURED INTERVIEW

What design tools do you use on a daily basis?

When I started working here, we started using this tool called SpectreRF developed by Cadence, which was a major innovation—a new way of looking at the performance specs of RF circuits and really an entirely new way of thinking about RF circuit theory. We still use that daily, that’s a staple for us.

INTERVIEW

Do you have any advice for the engineering community?

I think the best advice I could give would be to remain constantly willing to step back from what you are doing and look at the big picture. It’s easy to bury yourself in the technical details of a task, but does what you are working on make sense? Will it really contribute to the success of the product, and will that product really contribute to the success of whatever product it goes into? What is the end result of what you do? I think this applies at the subcircuit design level all the way up to the whole chip, and from the shipping clerk to the CEO.

Everybody on the team has to look at things from their viewpoint and make sure they make sense.

Sometimes this means challenging the assumptions that you are making, or even challenging the assumptions that your manager or your company’s executives are making. But if you don’t do that, it stops being your company and you’ll end up feeling like just a cog in the machine.

What direction do you see your business heading in the next few years? What challenges do you foresee in our industry?

We’re still in the midst of the CMOS revolution. CMOS is revolutionary: it started with digital circuits and

microprocessors, and then went on to analog functions of all kinds.

Now we’re well into the RF era of the revolution, and of course putting all of this together to make a whole system (and in some cases a whole product) on a chip. There are still plenty of opportunities for CMOS to revolutionize existing product areas and even help create new ones. The smartphone revolution, to name one, was made possible by really clever digital, analog, and RF CMOS design, implemented at scale. From where I sit, the future for Silicon Labs and the semiconductor industry as a whole is still very bright, as long as we keep finding new ways to apply this technology to problems that really matter. That is the challenge. ■

Figure 1: The Orion Nebula in Mapped Color, copyright © 2006 Russell Croman

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FEATURED INTERVIEW

which is the Holy Grail of sorts for a photographer (Figure 1).

©2011 Silicon Laboratories Inc. All rights reserved.

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F E AT U R E D P R O D U C T S LogiScope logic analyzer brought to you by Oscium transforms an iPhone, iPad or iPod into a 100MHz, 16 channel logic analyzer. Not only is it the most intuitive logic analyzer available, the triggering is so powerful you’ll be able to count the hair on your bug. Product highlights include a 100 MHz, 16 channel logic analyzer, a two logic harness, each with 8 digital and 1 ground, protocol decoding for 12c, SPI, UART and Parallel. The input voltage is -0.5v to +7v and has an advanced triggering system built in. It works with 2.0v, 2.5v, 3.3v & 5.0v systems and is entirely portable, so it can go wherever you go. The touchscreen makes navigating the interface a pleasure. It is interactive, responsive, and cutting edge. Changing the timescale is as easy as zooming into a picture on your smartphone. Adjusting the delay is as simple as a swipe across the top of the screen. The intuitive interface will also alert you to signals that are too fast for the timescale by changing the waveform to red (see image to the left). Protocol decoding does not depend on the timescale; it occurs live on the hardware so you can trigger in real time. For more information, please click here or watch Oscium’s video for the LogiScope here.

Xilinx Kintex-7 FPGA Embedded Kit Xilinx, Inc. today announced the Kintex™-7 FPGA Embedded Kit, providing a ready-to-use development platform for system designers to quickly and easily implement programmable system integration for applications where the processor needs to control different data streams, such as in video and Ethernet switching, motor control, and medical imaging. As a Xilinx® 7 series FPGA, Kintex-7 devices offer the flexibility to support changing standards, parallel processing and customizable interfaces with integrated functions like high performance DSP, memory, analog and I/O interfaces, making it easier for designers to embed soft processors to control dataflow and manage a number of interfaces in the system. Equipped with a combination of silicon, tools, IP cores, and MicroBlaze™ soft processor-based reference designs, both software and hardware developers alike can work on their designs in parallel. For more information, please click here.

SAR ADC with SPICE Model Texas Instruments Incorporated, today introduced a successiveapproximation-register (SAR) analog-to-digital converter (ADC) with a downloadable TINA TI SPICE model, enabling system designers to simulate and characterize the full analog signal chain in software for the first time. The model is available for the new 12-bit, 1-MSPS, 8-channel ADS8028, a highly-integrated SAR ADC featuring a low-drift internal voltage reference, wide external analog voltage reference range, wide analog and digital supply ranges, and an internal temperature sensor.

Designers could previously only simulate, model and test up to the SAR ADC, requiring them to invest time and resources building the ADC circuit in hardware. With a downloadable TINA-TI SPICE model available for all new SAR ADCs, designers will be able to fully verify ADC driving circuitry, enabling them to speed product development. This product offers low power consumption, wide temperature and supply ranges, and a high level of integration enable use in a wide variety of applications, including portable consumer electronics, wireless infrastructure and industrial equipment.

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LogiScope Logic Analyzer

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Illogical Logic

Part 2 - Karnaugh Maps Paul Clarke Electronics Design Engineer

C

0

0

1

I’ll first explain the simple idea of Karnaugh Maps (or K-Maps) before we start looking at bigger systems.

The idea is similar to Boolean Algebra in that we want as simple a system, which means reduced amounts of logic to perform a task.

K-Maps do this in a visual way in that you can see the like terms and link them together. So, starting with a simple OR gate we would have the following truth table.

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arrying on from my first article, Illogical Logic and Boolean Algebra , this article will look at Karnaugh Maps.

When I announced that I would be writing about this, I got lots of feedback and excitement. One person even commented that it’s “Sudoku for digital engineers.” So let’s have some fun!

AB 0 0 0 1 1 0 1 1

F 0 1 1 1

Figure 1

The K-Map for this would look like this (Figure 2).

As you can see, along each side you have one of our inputs, either A or B. EEWeb | Electrical Engineering Community

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TECHNICAL ARTICLE B

0

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Another example is as follows:

A

F = !A.B+A.!B+A.B This is messy because there are four gates and we know we only need one. Using Boolean Algebra would break this down to A+B. So how can the K-Map do the same?

The answer is: loops! The idea is to loop together like terms. For example, we can loop together !B.A with B.A. This loop then represents the common term in the loop, ignoring any element that changes.

Because B changes this loop simply represents A.

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• Loops can only go up or down – NOT diagonally.

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• Loops contain an EVEN number of terms, however, looping one item is allowed.

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Figure 4

With the loops in place, we can quickly see that the answer is A+!B. What makes K-Maps so useful is that you can quickly see the answers.

Now before we move on to bigger K-Maps we need some ground rules to follow!

• - So, only: 1, 2, 4 or 8 terms are allowed per loop!

• Loops only terms.

wrap

common

• Loops must always be square or rectangle – no funny blob shapes!

• Terms in the loops are AND’ed together.

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• All Loops are then OR’ed together for the final result.

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These aren’t the difficult rules you would expect but this is basically all you need to know!

The same can then be done with !A.B and A.B to give a loop that is equal to B. We now have two loops, A and B, so the final solution which

B

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Figure 3

C

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Figure 2

Then, like a truth table, you fill in when the output will be a logical 1 or 0. If we were to write down the Boolean Algebra for this in order to represent each square with a 1 in it, we would get:

D

So lets jump past three inputs to four inputs as you will hopefully figure out how to do three from this example. My truth table is as follows:

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TECHNICAL ARTICLE

A

we know to be true is: A+B

Figure 5

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Figure 6

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TECHNICAL ARTICLE

So back to our example – the loops in this example give the solution C.D+!A.C+A.!C.!D and from this you can see that the input B has no effect! You can also see in this example how the loops wrap around.

Are four inputs enough for your design however? As you can see, K-Maps at this level are only designed to work with four inputs,

so to add one or two more means adding a dimension. In effect for a five input system, you will have two K-Maps where one is when the fifth input is logic 0 and the other for when it’s logic 1. However, this can start to become a 3D jigsaw as now it’s possible to loop terms from one level to the next.

Next time I’ll be looking at some practical uses of K-Maps and Boolean Algebra in some basic logic circuits.

systems. At ebm-papst, he develops embedded electronics for thermal management control solutions for the air movement industry.

He is responsible for the entire development cycle, from working with customers on requirement specifications to circuit and PCB design, developing the software, release of drawings, and production support. ■

About the Author Paul Clarke is a digital electronics engineer with strong software skills in assembly and C for embedded

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TECHNICAL ARTICLE

To start you should note that the numbers along the top are not in the normal binary sequence. In fact you get a gray code sequence. This is so each row or column only have one term chance from one to the next.

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VOUT

VIN 10 VIN

VOUT 2

4 VBIAS

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1.0V VOUT

1 COUT 10µF

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GND 5

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IOUT = 0A

IOUT = 2A BIAS = 5V VIN = 3.3V VOUT = 2.5V COUT = 10µF 100

1k

IOUT = 3A

10k FREQUENCY (Hz)

100k

1M

FIGURE 3. VIN PSRR vs LOAD CURRENT (ISL80113) March 30, 2012 FN7841.0

ΔVADJ +25°C NORMALIZED (%)

PSRR (dB)

IOUT = 1A

60

0

3A

80 70

2A

60 50 40

1A

30 20 10 0

-40

25 85 TEMPERATURE (°C)

125

1.015

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FIGURE 2. DROPOUT VOLTAGE OVER-TEMP AND IOUT

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1.010 1.005 1.000 0.995 0.990 0.985

-40

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25 85 TEMPERATURE (°C)

125

FIGURE 4. ΔVADJ vs TEMPERATURE

Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2012 All Rights Reserved. All other trademarks mentioned are the property of their respective owners.

TECHNICAL ARTICLE

TECHNICAL ARTICLE

NAND Evolution and the Future of Solid State Drives Eli Tiomkin

Director Business Marketing

I

n the quest for achieving greater data storage capacity, lower prices, and smaller footprints, SSD evolution may be mired by unexpected pitfalls of quality and reliability.

Some technology luminaries have taken the position that the solid state drive (SSD) market will eclipse other electronic storage methods and eventually replace all types of storage with SSDs by the end of the decade. For such a forecast to be viable, the current state of the SSD market will have to undergo a hefty series of transitions and technological developments, many of which are still quite a few years out. In the meantime, leaving predictions to fend for themselves, SSDs are gaining greater acceptance in the storage market with their offering of high performance, relative low power, smaller footprints, wide range of capacities and the ability to withstand more physically-challenging installations, some notable advantages over traditional hard disk drives (HDDs).

Much like traditional rotating HDD technology is changing and evolving to keep pace with the ever-increasing demands for computer storage, so is NAND Flash, the

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TECHNICAL ARTICLE

Taking a look at next-generation solid state media technologies, several evolutions such as Vertical NAND or 3D Stackable NAND, Resistive RAM or (3D RRAM), Phase Change Memory (PCM) and Spin-Transfer Torque Magnetoresistive RAM (STT-MRAM) loom on the horizon as future storage options and are being put to the test by system manufacturers and storage vendors.

A Brief Look Back…

In the past five years or so, SSDs have begun to enter more of the mainstream storage market, mostly in the areas of security/surveillance, industrial, military and enterprise installations, where the budget delta between more costly SSDs could be better tolerated against the reliably trusted, less expensive choice of HDDs. Interest in SSDs has increased based on their high performance in IO-intensive applications: ability to withstand more rugged applications (better handling of shock, heat and vibration), their energy efficient nature and especially when there isn’t frequent and/or easy access to drives.

NAND = > Capacity, NOR = > Speed…

SSDs are built on NAND flash memory, a type of nonvolatile storage that does not require power to retain data. There are actually two main types of flash: NOR, which Intel introduced in 1988, followed by NAND, from Toshiba in 1989. NAND and NOR work differently; NAND has significantly higher storage capacity and NOR is faster but more costly to produce. NAND flash has been widely implemented in MP3 players, digital cameras and USB drives while NOR flash has often been used inside mobile phones. Some devices take advantage of both platforms—embedded NOR to boot up the operating system and a removable NAND card for storage inside the device.

While it is true that NAND flash has a finite number of write/erase cycles, the amount is sufficient for many years of life in most consumer applications. NAND memory cards, commonly referred to as flash memory cards, are

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easily replaceable when they wear out, but a consumer often replaces the digital device before surpassing the lifespan of its memory card. Device makers have found they can lower prices significantly by letting the consumer select the amount of expandable storage.

For SSDs, a primary concern is the limitation in the overall endurance (write limits) of the drives and thus it is important to understand a system’s usage model when choosing a solution, especially in 24/7 applications.

Flash-based SSDs are built on one of two types of NAND technology: single-level cell (SLC) or multi-level cell (MLC). The endurance and performance versus cost metrics vary greatly between the technologies, and for moderate to heavy workloads, SLC is often more suitable than MLC. Driven relentlessly to lower the cost-per-bit to accommodate the needs of next-generation electronic devices and mobile phone handsets, flash manufacturers are facing a myriad of challenges as they struggle in the development of new technologies, with chip size, maximum write/erase cycles and lowering voltage demands among them.

More Bits, Please…

NAND vendors have become very aggressive in their efforts to store more bits of data per NAND component at a lower cost per bit. They have attacked this issue in two ways.

First, is the effort to reduce the manufacturing process geometry, which shrinks the size and therefore the cost of the NAND cells (transistors) that actually store the data. The smaller the cells, the more of them that can be etched on a given area of a semiconductor wafer.

Process geometry shrinks, plus some additional solidstate physics issues (a separate topic), result in larger densities per NAND component.

Second, is the quest to offer components able to store multiple bits of data per cell in order to double, triple and eventually quadruple the number of bits of data that can be stored per each component. The trade-off for smaller process geometries and lower cost per bit is in component reliability. NAND flash components in their most common thin small outline packages (TSOPs) are getting bigger, faster and cheaper—but not necessarily “better.” Better in this case is defined as “more reliable”

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primary media in SSDs, currently at a rate never before seen in semiconductor technology. Comparing HDDs to SSDs is not really fair since it is akin to comparing an apple with an onion. However, one observation is certain: design engineers for both storage technologies are working overtime to offer greater capacity, faster speeds and smaller footprints at lower prices.

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Figure 1: Reliability vs. Cost Per Bit

in terms of endurance (the number of program/erase cycles) and data retention.

As NAND manufacturers work to bring next-generation SSDs to market, they face hurdles of achieving evermore write cycles and lowering voltage demands as well as additional roadblocks in their pursuit, not limited to: • Endurance and performance playing against each other • Usage model (workload) having the biggest impact on useful life • NAND media becoming more differentiated • The SSD quadrilemma: more capacity and lower $/ Gb = smaller cells, more bits/cell = less electrons/ cell = and ultimately, lower reliability

NAND cell stacking and basically picks up where current 2D NAND leaves off. Highly scalable and expected to reach the market by 2014, Vertical NAND may extend the usable life of fabrication equipment and serve as a bridge to revolutionary technologies in five to eight years.

2. Memristor/RRAM (Resistive RAM) may hold the best promise for post-NAND technology , as a replacement for flash, DRAM, and SRAM. Developers of the technology claim that energy usage, read and write speed, data retention, endurance, as well as price or memristors will be better than NAND.

As NAND flash approaches physical limits for lithographies below 20 nanometers or 1xnm, at least four new technologies are striving to extend MLC/SLCbased flash. Contending options include:

3. Phase Change Memory (PCM) may provide the best features of NAND, NOR and RAM in a single chip. Fast, bit-alterable (so it does not require a separate erase step like other types of flash) and a low power consumer, PCM could be an attractive, high-performance next step in flash evolution. PCM still has some engineering work needed to improve the important performance metric of latency.

1. Vertical NAND or 3D Stackable NAND is true vertical

4. Spin-Transfer Torque Magnetoresistive RAM (STT-

Forecast of Future Flash Technology

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And the Frontrunners in the Race?

• 3D NAND is predicted to hit the market between 2013 and 2014 • In Nov 2011, Samsung announced a 8Gb, 20nm phase-change memory (PCM) device • HP/Hynix has announced the commercial launch of a memristor product in mid-2013 For SSD technology to evolve to the next stages of development and replace current standards, the new technology must be on par or exceed in the critical areas of reliability, usable life span and ideally, cost. The keys to a successful technology transition will be marked by high volume production coupled with high yields of components available from multiple sources.

Looking forward Solid state drives are a complementary solution to hard drives, offering higher performance per unit of power, increased mechanical ruggedness, and smaller form factors. Hard drives and SSDs will continue to perform side by side or be integrated together in one form factor in many applications. Both the hard drive and solid state drive markets will continue to grow in the future just as we have seen in the last several years. SSDs and HDDs each offer compelling solutions on their own merits and will continue to differentiate to meet the needs of the markets they serve.

About the Author Eli Tiomkin is the Director, Business Development at Western Digital (WD) and previously held executive positions at Violin Memory (director of sales), STEC (director of OEM sales), and M-Systems (sales director). A dynamic, creative sales professional with extensive experience in the high-tech storage market, Tiomkin holds an MBA in International Business and Organizational Behavior and BS in Marketing, both from Oakland University. ■

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MRAM) uses magnetic elements to deliver ultra high-speed, low power consumption, and excellent reliability. Claimed by some developers to be the eventual ‘memory of the universe,’ STT-MRAM may play a key role when it begins to hit the market in 2013 to give embedded SRAM, DRAM, and NOR flash some heavy competition, provided it can improve its densities.

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