The merged tree shifter can be rearranged to do normalization without having to first compute how many bits to shift. To do this, we take advantage of the fact that the shift at each layer is a binary decision (either shift or don’t shift), and the fact that the ordering of the layers in a merged tree shifter is arbitrary. If the shift layers are ordered so that the largest shift comes first, then the shift decision at each stage is reduced to determining whether or not that shift operation will cause an overflow at that stage. An overflow will only occur if there is a significant bit in the top 2n bits before the shift by 2n. For unsigned data, if all of the top 2n bits are zero, then the data is shifted. Otherwise, the data is passed un-shifted to the next layer. The shift detection at each stage for unsigned data is then just the logical OR of the top 2n bits at the input to that stage, as shown in Figure 5. We have effectively decomposed the shift controls into a series of shift or don’t shift decisions matching the decomposition of the shift into power of two shifts. TECH ARTICLE with a handful of OR gates, and at the same time have arrived at an optimal normalizer architecture. Note also that if we leave the shifted output bits disconnected and prune the trees from the unused outputs back we arrive at an optimal merged tree implementation of a priority encoder. Two’s complement values can be normalized using this same technique. In that case, the shift is made if all the high bits match the sign bit instead of all being zero. The shift detection at the initial stages can sometimes be made faster by using the fast carry chain logic. Two’s complement is typically a little slower because more inputs feed into the decision. It is often better, smaller and faster to convert to sign-magnitude notation before doing the normalization. About the Author Raymond J. Andraka, P.E. earned a B.S.E.E. degree from Lehigh University, Bethlehem, PA, and an M.S.E.E. The sequence of the shift decisions forms a binary word degree from the University of Massachusetts, Lowell, indicating the total number of bit positions shifted. This in 1984 and 1992, respectively. He is the President of word can be directly interpreted as the change in the the Andraka Consulting Group, Inc., a digital hardware exponent due to normalization, thus this normalization design firm he founded in 1994. His company is focused circuit can also be used for fixed point to floating point exclusively on high-performance DSP designs using conversion by adding an appropriate offset to the FPGAs. He has applied FPGAs to signal processing shift value. By using a merged tree architecture for applications including radar processors, radar the shifter and paying attention to the overall goal, we environment simulators, sonar, Industrial ultrasound, have eliminated an ugly priority decode and replaced it HDTV, digital radio, spectrum analyzers, image processing, and communications test equipment. Ray’s prior signal 0 0 0 0 processor design experience Shifted Data In includes five years with Raytheon Data Out 1 1 1 1 <<1 <<2 <<4 <<8 Missile Systems designing radar signal processors and three years of signal detection and reconstruction algorithm development for the U.S. Shift by Priority ‘Exponent’ Air Force. He also spent two years Encoder Out developing image readers and Figure 5 Normalizer using priority encoder and merged tree shifter processors for G-Tech, where he set the company time-to-market record ‘Exponent’ for a new product. He also authored over 20 conference papers and articles dealing with various high8 msbs 4 msbs 2 msbs msb performance FPGA design and signal processing topics, and has been a 1 1 1 1 regular contributor to several on-line Normalized Data In forums dealing with FPGA and DSP Data Out design. 0 0 0 0 <<8 <<4 <<2 <<1 Figure 6 Merged tree normalizer eliminates the separate priority encode. Visit www.eeweb.com 19