4 minute read

References

[1] E. Suarez, N. Eicker and T. Lippert, Modular Supercomputing Architecture: from idea to production, Chapter 9 in

Contemporary High Performance Computing: from Petascale toward Exascale, vol. 3, J. S. Vetter, Ed., CRC Press, 2019, pp. 223-251. [2] E. Suarez, N. Eicker and T. Lippert, “Supercomputer Evolution at JSC,” in Proceedings of the 2018 NIC Symposium, 2018. [3] N. Eicker, T. Lippert, T. Moschny and E. Suarez, “The DEEP Project - An alternative approach to heterogeneous cluster-computing in the many-core era,” Concurrency and computation: Practice and Experience, vol. 28, pp. 2394–-2411, 2016. [4] A. Kreuzer, J. Amaya, N. Eicker, R. Léger and E. Suarez, “The DEEP-ER project: I/O and resiliency extensions for the

Advertisement

Cluster-Booster architecture,” in Proceedings of 2018 IEEE 20th International Conference on High Performance

Computing and Communications (HPCC), Exeter, United Kingdom, 2018. [5] E. Suarez, A. Kreuzer, N. Eicker and T. Lippert, The DEEP-EST project, Chapter 1 in Porting applications to a Modular

Supercomputer - Experiences from the DEEP-EST project, Forschungszentrum Jülich GmbH Zentralbibliothek,

Verlag, Schriften des Forschungszentrums Jülich IAS Series 48, 2021, pp. 9-25. [6] N. Eicker, A. Galonska and M. N. J. Hauke, Bridging the DEEP Gap – Implementation of an Efficient Forwarding

Protocol. In: Intel European Exascale Labs - Report 2013, 2014, p. 34–41. [7] E. Suarez, N. Eicker, T. Moschny and T. Lippert, Critical Analysis of the Modular Supercomputing Architecture.

Chapter 9 in Porting applications to a Modular Supercomputer - Experiences from the DEEP-EST project,

Forschungszentrum Jülich GmbH Zentralbibliothek, Verlag Jülich, IAS Series 48, 2021, pp. 233-245. [8] W. Gropp, “MPICH2: a new start for MPI implementations,” Recent Advances in Parallel Virtual Machine and

Message Passing Interface, vol. 2474, p. 7, 2002. [9] S. Pickartz, C. Clauss, S. Lankes, S. Krempel, T. Moschny and A. Monti, “Non- Intrusive Migration of MPI Processes in OS-bypass Networks,” in IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2016. [10] “InfiniBand (IB) architecture specification. Tech. rep., ITA,” 2016. [Online]. Available: https://www.infinibandta.org/ibta-specification/. [11] M. S. Birrittella, M. Debbage, R. Huggahalli, J. Kunz, T. Lovett, T. Rimmer, K. D. Underwood and R. C. Zak, “Intel®

Omni-path Architecture: Enabling Scalable, High Performance Fabrics,” in 2015 IEEE 23rd Annual Symposium on

High-Performance Interconnects, Santa Clara, CA, USA, 2015. [12] H. Fröning, M. Nüssle, H. Litz, C. Leber and U. Brüning, “On achieving high message rates,” in 13th IEEE/ACM

International Symposium on Cluster, Cloud, and Grid Computing, 2013. [13] A. Kreuzer, E. Suarez, N. Eicker and T. Lippert, Porting applications to a Modular Supercomputer - Experiences from the DEEP-EST project, Forschungszentrum Jülich GmbH Zentralbibliothek, Verlag Jülich, IAS Series 48, 2021, p. 254. [14] Jülich Supercomputing Centre, «JURECA: General-purpose supercomputer at Jülich Supercomputing Centre,»

Journal of large-scale research facilities, vol. 2, p. A62, 2016. [15] Jülich Supercomputing Centre, “JURECA: Modular supercomputer at Jülich Supercomputing Centre,” Journal of large-scale research facilities, vol. 4, p. A132, 2018. [16] Jülich Supercomputing Centre, “JURECA: Data Centric and Booster Modules implementing the Modular

Supercomputing Architecture at Jülich Supercomputing Centre,” Journal of large-scale research facilities, vol. 7, p.

A182, 2021. [17] Jülich Supercomputing Centre, “JUWELS Cluster and Booster: Exascale Pathfinder with Modular Supercomputing

Architecture at Jülich Supercomputing Centre,” Journal of large-scale research facilities, vol. 7, p. A183, 2021. [18] A. Herten, “JUWELS Booster - Early User Experiences,” in The 30th International Symposium on High-Performance

Parallel and Distributed Computing, PERMAVOST Workshop, HPDC21, Virtual, Sweden, 2021. [19] S. Kesselheim, A. Herten and K. Krajsek, “JUWELS Booster – A Supercomputer for Large-Scale AI Research, High

Performance Computing,” in ISC High Performance 2021, Digital, Germany, 2021.

Authors:

Estela Suarez is Senior Scientist at the JSC, leader of the DEEP project series, and Professor for High Performance Computing at the Rhenish Friedrich Wilhelm University of Bonn.

Norbert Eicker leads the research group on cluster computing at JSC, and is Professor for Parallel Hard- und Software-Systems at the Bergische Universität Wuppertal.

Thomas Moschny is CTO of ParTec AG, and lead-architect of the ParaStation Modulo software stack.

Simon Pickartz works as a Research Engineer at ParTec AG and is mainly involved in the development of ParaStation MPI, the communication stack of ParaStation Modulo.

Carsten Clauss is an MPI Developer and Research Engineer at ParTec AG. From 2018 to 2020, he was Professor for Computer Science at the IUBH Internationale Hochschule.

Valentin Plugaru is the Chief Technology Officer of LuxProvide, home of the MeluXina Luxembourg - EuroHPC supercomputer, where he leads strategic and operational planning.

Andreas Herten is Senior Scientist at the JSC, where he leads the research group ‘Accelerating Devices’. He is also the JSC-lead of the NVIDIA Application Lab at Jülich, a long-term collaboration between JSC and NVIDIA.

Kristel Michielsen leads the research group Quantum Information Processing (QIP) at the JSC and is Professor for QIP at RWTH Aachen University.

Thomas Lippert is Director of the Jülich Supercomputing Centre (JSC) from Forschungszentrum Jülich, and Professor for Modular Supercomputing und Quantum Computing at the Goethe-Universität Frankfurt.

Cite as: E. Suarez et al., Modular Supercomputing Architecture, ETP4HPC White Paper, 2022, doi 10.5281/zenodo.6508394

DOI: 10.5281/zenodo.6508394

© ETP4HPC 2022

This article is from: