Exam zone
USARTS
CS423 Dick Steflik
USART ●
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Universal Synchronous Asynchronous Receiver Transmitter used to send and receive small packets over a serial line
full or half duplex ● ● ●
typically asynchronously 5 – 8 bits of data 2 or 3 framing bits
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start bit
1 or 2 stop bits 0 or 1 parity bits
Data Format ●
Must be agreed on by sender and receiver before any exchanges can be made
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stop bit (1 to 0 transition)
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5 – 8 data bits
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0 or 1 parity bits (odd or even parity)
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1 or 2 stop bits (logic 0)
Parity ●
error detection mechanism
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odd parity
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even parity
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if an even number of data bits are 1 the parity bit is set to 1 to ensure an odd number of 1s if an off number of data bits are 1 the parity bit is set to 1 to ensure an even number of bits are 1s
calculated and set by transmitter
recalculated buy receiver and compared to transmitted value, if no match a bit was either picked or dropped in transmission.
Programming Model ●
Data input register
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Data output register
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Control register
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Status register
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speed, data bits, parity, stop bits, start, stop data ready, transmitting
interrupts
overflow, underflow, data ready, data sent
Sending data ●
Remember synchronization is on a character by character basis
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check status
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load data register
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start transmit
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wait for transmission complete status or for interrupt repeat
Receiving data ●
poll status register for data ready or wait for interrupt
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read data (save it)
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repeat
ATtiny2313 ●
UDR – Data Register
read / write (depending on context)
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UBRRL & UBRRH – Baud Rate Register
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UCSRB – Control Register
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writable
UCSRA – Status Register
readable
UCSRA ● ● ● ● ● ● ● ●
7 – RXC – Receive Complete 6 – TXC – Transmit Complete 5 – UDRE – Data Register Empty 4 – FE – Frame Error 3 – DOR – Data Overrun Error 2 – UPE – Parity Error 1 – U2X - Double the speed (Async mode only) 0 – MPCM – Multi-processor Communication Mode
UCSRB ●
7 – RXCIE – Rx Comp Interrupt Enable
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6 – TXCIE – Tx Comp Interrupt Enable
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5 – UDRIE – Dara Reg Empty Interrupt Enable
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4 – RXEN – Receiver Enable
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3 – TXEN – Transmitter Enable
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2 – UCSZ2 – Character size MSB
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1 – RXB8 – 9th bit if frame size is 9
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0 – TXB8 – 9th bit if frame size is 9
UCSRC ● ●
6 - UMSEL – (0-async, 1-sync) 5,4 – UPM1, UPM0 USART Parity Mode
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0 0 disabled 0 1 reserved 1 0 even parity enabled 1 1 odd parity enabled
3 – UCBS – Number of stop bits ( 0 – 1 bit , 1 – 2 bits) 2,1 – UCSZ1, UCSZ0 - USART Character Size used with UCSZ2 bit in UCSRB 0 – UCPOL – used in sync mode for clock polarity