PROCEEDINGS
ICCIET - 2014 INTERNATIONAL CONFERENCE ON CURRENT INNOVATIONS IN ENGINEERING AND TECHNOLOGY
Sponsored By INTERNATIONAL ASSOCIATION OF ENGINEERING & TECHNOLOGY FOR SKILL DEVELOPMENT ((Registered Under Indian Trust Act, 1882)
Technical Program 16TH October, 2014 Hotel La Hospin, Rajahmundry
Organized By INTERNATIONAL ASSOCIATION OF ENGINEERING & TECHNOLOGY FOR SKILL DEVELOPMENT
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Copyright Š 2014 by IAETSD All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of the publisher.
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About IAETSD: The International Association of Engineering and Technology for Skill Development (IAETSD) is a Professional and non-profit conference organizing company devoted to promoting social, economic, and technical advancements around the world by conducting international academic conferences in various Engineering fields around the world. IAETSD organizes multidisciplinary conferences for academics and professionals in the fields of Engineering. In order to strengthen the skill development of the students IAETSD has established. IAETSD is a meeting place where Engineering students can share their views, ideas, can improve their technical knowledge, can develop their skills and for presenting and discussing recent trends in advanced technologies, new educational environments and innovative technology learning ideas. The intention of IAETSD is to expand the knowledge beyond the boundaries by joining the hands with students, researchers, academics and industrialists etc, to explore the technical knowledge all over the world, to publish proceedings. IAETSD offers opportunities to learning professionals for the exploration of problems from many disciplines of various Engineering fields to discover innovative solutions to implement innovative ideas. IAETSD aimed to promote upcoming trends in Engineering.
About ICCIET: The aim objective of ICCIET is to present the latest research and results of scientists related to all engineering departments’ topics. This conference provides opportunities for the different areas delegates to exchange new ideas and application experiences face to face, to establish business or research relations and to find global partners for future collaboration. We hope that the conference results constituted significant contribution to the knowledge in these up to date scientific field. The organizing committee of conference is pleased to invite prospective authors to submit their original manuscripts to ICCIET 2014. All full paper submissions will be peer reviewed and evaluated based on originality, technical and/or research content/depth, correctness, relevance to conference, contributions, and readability. The conference will be held every year to make it an ideal platform for people to share views and experiences in current trending technologies in the related areas.
Conference Advisory Committee:
Dr. P Paramasivam, NUS, Singapore Dr. Ganapathy Kumar, Nanometrics, USA Mr. Vikram Subramanian, Oracle Public cloud Dr. Michal Wozniak, Wroclaw University of Technology, Dr. Saqib Saeed, Bahria University, Mr. Elamurugan Vaiyapuri, tarkaSys, California Mr. N M Bhaskar, Micron Asia, Singapore Dr. Mohammed Yeasin, University of Memphis Dr. Ahmed Zohaa, Brunel university Kenneth Sundarraj, University of Malaysia Dr. Heba Ahmed Hassan, Dhofar University, Dr. Mohammed Atiquzzaman, University of Oklahoma, Dr. Sattar Aboud, Middle East University, Dr. S Lakshmi, Oman University
Conference Chairs and Review committee:
Dr. Shanti Swaroop, Professor IIT Madras Dr. G Bhuvaneshwari, Professor, IIT, Delhi Dr. Krishna Vasudevan, Professor, IIT Madras Dr.G.V.Uma, Professor, Anna University Dr. S Muttan, Professor, Anna University Dr. R P Kumudini Devi, Professor, Anna University Dr. M Ramalingam, Director (IRS) Dr. N K Ambujam, Director (CWR), Anna University Dr. Bhaskaran, Professor, NIT, Trichy Dr. Pabitra Mohan Khilar, Associate Prof, NIT, Rourkela Dr. V Ramalingam, Professor, Dr.P.Mallikka, Professor, NITTTR, Taramani Dr. E S M Suresh, Professor, NITTTR, Chennai Dr. Gomathi Nayagam, Director CWET, Chennai Prof. S Karthikeyan, VIT, Vellore Dr. H C Nagaraj, Principal, NIMET, Bengaluru Dr. K Sivakumar, Associate Director, CTS. Dr. Tarun Chandroyadulu, Research Associate, NAS
ICCIET - 2014 CONTENTS 1
DESIGN AND IMPLEMENTATION OF PSEUDO RANDOM NUMBER GENERATOR USED IN AES ALGORITHM
1
2
GAME THEORY AND AUCTIONS FOR COOPERATION IN A WIRELESS NETWORK: A SURVEY
7
3
SURVEY ON COGNITIVE RADIO NETWORKS AND ITS ROUTING MECHANISM
14
4
DESIGN OF A LOW POWER MULTIBAND CLOCK DISTRIBUTION CIRCUIT USING SINGLE PHASE CLOCK
19
5
DESIGN AND IMPLEMENTATION OF MULTIPLE SIC VECTORS THEORY AND APPLICATION IN BIST SCHEMES
27
6
A NEW MULTILEVEL INVERTER TOPOLOGY FOR FOUR POLE INDUCTION MOTOR DRIVE
35
7
VLSI IMPLEMENTATION OF EFFICIENT CONVOLUTIONAL ENCODER AND MODIFIED VITERBI DECODER
42
8
A TRANSFORMER LESS SINGLE-STAGE AC-DC CONVERTER WITH CLOSED LOOP SYSTEM
48
9
AN INTERLEAVED BOOST CONVERTER INTEGRATING WITH SWITCHED CAPACITOR AND COUPLED INDUCTORS FOR RENEWABLE ENERGY SOURCES
53
10
SINGLE-PHASE SINGLE-STAGE MULTI-LEVEL AC–DC CONVERTER FOR POWER FACTOR CORRECTION
59
11
FUEL CELL BASED SINGLE-INPUT MULTIPLE-OUTPUT DC–DC CONVERTER FOR BLDC MOTOR
65
12
PIPELINED PARALLEL FFT ARCHITECTURE THROUGH FOLDING TRANSFORMATION
72
13
A DESIGN OF FPGA WITH LEDR ENCODING AND DUAL RAIL ARCHITECTURE
78
14
WAVELET TRANSFORM BASED LATENCY OPTIMIZED IMAGE COMPRESSION FOR LOW DENSE APPLICATIONS
83
15
POSITION CONTROL OF SERVO SYSTEMS USING PID CONTROLLER TUNING WITH SOFT COMPUTING OPTIMIZATION TECHNIQUE
88
16
VLSI IMPLEMENTATION OF SPATIAL MODULATION RECEIVER
93
17
A DECISIVE FUZZY CONTROLLED SINGLE SWITCH BASED CONVERTER FOR SRM DRIVE FOR WIDE SPEED RANGE OPERATION
105
18
ROBO CONTROL SYTSEM DESIGN USING ARM
111
19
DESIGN AND IMPLEMENTATION OF INTELLIGENT CONTROLLERS FOR A CONTINUOUS STIRRED TANK REACTOR SYSTEM
116
20
CLASSIFICATION OF LUNG TUMOUR USING GEOMETRICAL AND TEXTURE FEATURES OF CHEST X-RAY IMAGES
126
Proceedings of International Conference On Current Innovations In Engineering And Technology
ISBN : 978 - 1502851550
DESIGN AND IMPLEMENTATION OF PSEUDO RANDOM NUMBER GENERATOR USED IN AES ALGORITHM N.Madhavi (1) R.Viswanadham (2) N.Madhavi(1), M.TECH Student, DEPARTMENT of ECE, Shri Vishnu Engg college for women R.Viswanadham(2), ASST.PROFESSOR, DEPARTMENT of ECE, Shri Vishnu Engg college for women ABSTRACT This paper present a new Design for the generation of Advanced encryption of (bit) data. The Design opted to obtain this encrypted data is RMPRNG. This design also enhances the statistical properties of a chaos-based logistic map pseudo random number generator (PRNG) and extends the system period length. The reseeding method removes the short periods of the digitized logistic map and the mixing method extends the system period length to by “XOring” with a DX generator. This design also attains the throughput rate of 6.4 Gb/s. The mixing method extends the system period length by Xoring with ALG and the reseeding method removes the short periods which are occurred by CB-PRNG Index Terms- pseudo random number generator (PRNG), reseeding, Linear Congruential Generator (LCG), Carry-Look ahead Adder (CLA), Gate Equivalent (GE). 1. INTRODUCTION Pseudo random number generator (PRNG) is an algorithm for generating a sequence generator. PRNG has been widely find applications in Monte carlo generation, telecommunication systems, test pattern generation. A good PRNG should have characteristics of 1) Long-period random number sequence 2) Fit in statistical properties 3) A high throughput rate 4) Unpredictability
Linear PRNGs, such as linear feedback shift registers (LFSRs), linear congruential generators (LCGs), and multiple re- cursive generators (MRGs) can produce long-period random number sequences. Linear PRNGs when implemented gives efficient throughput rate and hardware cost, but the output of such Prng’s can be predictable due to the linear structure. Someone linear PRNGs in dealt with the predictability problem but incurred higher hardware cost and more process time . To overcome that predictability problem non linear chaos-based PRNG (CB-PRNG) is proposed. we propose a reseedingmixing PRNG (RM-PRNG) that consists of a CBPRNG and a long-period MRG. The reseeding method removes the disadvantages of short periods in CB-PRNG while the mixing of the CB-PRNG with an MRG pushes the overall system period length to a value (> 2253 in 32-b implementation ) based on simple theoretical calculation. By outputting multiple bits per iteration high throughput rate of (6.4 Gb/s) is achieved. So there is a need to implement a design which produce long periods and high throughput rate. Thus RM-PRNG is proposed. 2. EXISTING SYSTEM In general, mixing multiple CB-PRNGs results in higher hardware cost, lower throughput rate, and longer but unpredictable period length. Furthermore, one cannot be sure that the random numbers produced by these mixed PRNGs will have acceptable statistical properties. Since higher hardware cost is due to implementation of multiple CB-PRNG switch are more complex than linear PRNGs, mixing a CB-PRNG with a linear MRG instead of mixing two CB-PRNGs will reduced the hardware cost.
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EXISTING SYSTEM DRAWBACKS
Hardware cost. Lower Throughput Rate unpredictable period length It’s not sure that the random numbers produced by these mixed PRNGs will have acceptable statistical properties.
3. PROPOSED DESIGN (RM-PRNG) In our proposed RM-PRNG, which consists of a CB-PRNG and an MRG, the period length is considerably extended because the period length of the MRG is much longer than that of the CB-PRNG while the short periods of the CB-PRNG can be removed by our reseeding algorithm. We can analytically calculate the lower bound of the period length in RM-PRNG in terms of the period length of the CB-PRNG and that of the MRG. The enhancement of throughput rate is achieved by using a vector-mixing technique in the proposed RMPRNG. As the linear structure of the MRGs is broken by mixing with a CB-PRNG, the statistical properties will get improved. 4 .DESIGN APPROACH
ISBN : 978 - 1502851550
RM-PRNG is composed of three modules: Non linear module, Reseeding module, Vector mixing module. In a 32-b implementation , the Non linear Module has a controlled 32-b state register and a Next- state construction circuitry. The controlled register stores the state value Xi which can be set to seed 1 by the start command. The Next - state construction circuitry produces the next state value according to the recursive formula. For each state value generated, the reseeding control unit (RCU) in the Reseeding Module compares the values of and for checking the fixed point condition and increases the reseeding counter (RC) at the same time. The RC will be reset and the reseeding operation will be activated when either the fixed point condition is detected or the RC reaches the reseeding period. 4.1 NONLINEAR MODULE For Next state construction , LCM is used in the Non linear Module so that
with and as an initial seed. Choosing a value 4 for not only makes the LGM chaotic but also simplifies the implementation of equation to merely left-shifting the product of Xt and 1-Xt by 2 b. The state size decreases from 32 to 31 b, as the dynamics and in the equation are the same. This is equivalent to a degradation of resolution by 1 b. In addition, fixed points (at Xt=0 and 0.75) as well as short periods exist when the LGM is digitized. From exhaustive runs for all of the seeds, we obtain all other periods for the 32-b LGM without reseeding. The performance of a CB-PRNG using only the Nonlinear Module is unsatisfactory. So, to solve the fixed points and short-period problem, a new Reseeding Module is in proposed. 4.2 RESEEDING MODULE
Fig.1 Structure of the proposed RM-PRNG
Reseeding mechanism is obvious for the removal of the fixed points. When the reseeding period is reached or fixed point condition is detected, the value Zt+1 loaded to the state register will be perturbed away from Xt+1 in the RCU by the fixed pattern according to the formula
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4.3.1 DX GENERATOR
where subscripts i,j are the bit-index L is integer, and . Degradation of the statistical properties of chaos dynamics can be minimized by making the magnitude of the perturbation of the fixed pattern R small compared with Xt. Here, we set L=5 so that the maximum relative perturbation is only and the degradation can be ignored. The effectiveness in the removal of short periods depends on the reseeding pattern R and the reseeding period Tr. for suitable combination of Tr and R. First, the reseeding period should avoid being the values or the multiples of the short periods Ts of the unperturbed digitized LGM. Otherwise, if the 5 LSBs of Xt+1 equal to R when the reseeding procedure is activated, Zt+1 will be equal to Xt+1. Then no effective reseeding will be realized and the system will be trapped in the short period cycle. Hence, prime numbers should be used as the reseeding period candidate.
DX generator implementation is (the ALG) done by using 8-word registers, circular-left-shift (CLS), circular 3-2 counter and End Around Carrycarry look ahead adder (EAC-CLA). By using flipflops the eight-word register was implemented. For generating two partial products signal Yt-7 is circular-left-shifted 28 and 8 b, using the modules CLS-28 and CLS-8 respectively. To combine these three 31-b operands into two 31-b operands a circular 3-2 counter is used, which consumes 247 gates. To evaluate Yt+1 31-b EAC-CLA is used with 348 gates. The schematic design of the 31-b EAC-CLA [4], [9] is shown in the below Figure. The schematic design of the 31-b EAC-CLA includes four modules they are propagation and generation (PG) generators, endaround-carry (EAC) generator, internal carry (IC) generator, and CLAs .When EAC is generated by group of PGs, EAC is then fed to the IC generator and then to least-significant 8-b CLA. On CLAs, the final addition was performed. .
4.3 VECTOR MIXING MODULE The DX generator which is an efficient MRG serves as the ALG in Vector Mixing Module. Specifically, we choose the DX generator with the following recurrence equation: Yt+1= Yt+ BDX . Yt-7 mod M,
t>=7
Using an efficient search algorithm[8], we find that the particular choice of BDX =228+28and M=231-1 gives the maximum period of the DX generator. The LSBs of Yt+1 and that of Xt+1 are mixed in the Output Construction unit using a XOR operation to obtain the least significant bits of the output according to the equation
(a)
Fig.2 (a) Structure of the DX generator
OUTt+1[1:31] = Xt+1[1:31] (ex-or) Yt+1[1:31] Then, the most significant bit (MSB) of Xt+1 is attached to OUTt+1 [1:31] to form the full 32-b output vector OUTt+1.
(b)
(b) Structure of the 31-b EAC-CLA 5 . DIGITIZATION Digitization is the process of converting information into a digital format . In this format, information is organized into discrete units of data
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(called bit s) that can be separately addressed (usually in multiple-bit groups called byte s). This is the binary data that computers and many devices with computing capacity (such as digital camera s and digital hearing aid s) can process. Text and images can be digitized similarly: a scanner captures an image (which may be an image of text) and converts it to an image file, such as a bitmap . An optical character recognition ( OCR ) program analyzes a text image for light and dark areas in order to identify each alphabetic letter or numeric digit, and converts each character into an ASCII code. we make digitization of the logistic map as follows: Firstly, the chaotic sequence is generated through Equations, which has to be amplified by a scaling factor (10^4) and round to integer-sequence according to Equations Zk=round((xk *104)mod 256) This transformation implies that, when the randomly generated chaotic sequence (input values) is uniformly distributed, the output of the digitization process is also uniformly distributed Random numbers have been used extensively in many simulation applications like Monte Carlo Integration or computer modeling. But recently security applications have increased the need for strong (secure) random number generation like automatic password generation, encryption algorithms, on-line gambling etc. Thus random number generation has become a challenging and an interesting task. Most classical random number generators, generate sequences that are either linear or predictable hence not suitable for cryptographic and security applications. Others generate sequences that even though they are secure they are not cryptographically strong and above all are slow in execution. Also recent advances in random number generation like the construction of Multiple Recursive Generator (MRG) with large orders, Fast Multiple Recursive. Generator (FMRG) and DX (system of multiple recursive generators proposed by Deng and Xu generators does not generate a strong random
ISBN : 978 - 1502851550
number sequences. Though MRGs have extremely long period of length with good empirical performance, its recurrence equation can be solved given a small set of its generated sequence, this implies that MRGs and FMRGs are not strong cryptographic generators. We propose an algorithm that will transform linear sequences generated by both classical LCG, MRGs, FMRGs and DX generators and make them cryptographically strong generators by hiding the entire sequence generated by the generators, thus it will be difficult for cryptanalyst to predict or infer the generator sequence if even the partial sequence or the parameters or knowledge of the algorithm used in the transformation of the generators are known Experimental results and tests have shown that classical generators like LCGs that generate pseudorandom linear sequences are not suitable for cryptographic purposes, even though it is simple, efficient and easy to generate. Other classical generators like BBS, RSA, and BM etc that are thought to be secure are equally not good enough for cryptographic purposes as they are slow in generating the next random bit sequence. Also the recent advances in random number generation (MRGs and FMRGs) are fast and efficient in generating linear sequences with long periods and good empirical performance, but still they are not cryptographically strong as the linear system can be predicated using a system of unique k equations. Our proposed algorithm produces a strong pseudorandom sequence that is suitable for cryptographic purposes and difficult to predict/infer by transforming the linear sequences and breaking its linear structure. The transformation hides the linear bits of the generated linear sequence preventing the attacker from accessing the generated output sequence, even with the knowledge of the partial sequence, parameters of the generators and the algorithm used in transforming the generator sequence. Thus knowing the parameters and partial sequence of the generators does not pose any threat any longer as the prediction of the generator sequence will no longer be an easy one. PROPOSED SYSTEM ADVANTAGES:  High Throughput Rate  Less hardware cost
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6 . SIMULATION RESULTS RC (Reseeding counter )
ISBN : 978 - 1502851550
generator extends the period length to the theoretically calculated value greater than 2253 when it is get mixed with the CB_PRNG . Replacing a hardware-demanding CB-PRNG with a hardwareefficient MRG, the hardware cost is reduced and the hardware efficiency achieves 0.538 Mb/s-gate. Due to the generation of multiple random bits in an iteration by the RM-PRNG, the high throughput rate ( > 6.4 Gb/s) is attained. By improving the statiscal properties of the reseeding method the randomness will be enhanced. The generated random number sequences by the proposed RM-PRNG pass all the tests in NIST SP 800-22 test suite. Because of these benefits the proposed nonlinear RMPRNG can serve as a good technique in the cryptographic applications and telecommunication. FUTURE SCOPE
FINAL OUTPUT (Random number sequence)
Reseeding-Mixing method, proposed design supports higher throughput and lower hardware cost and generates a unpredictable random number sequence. So, that sequence can be used as a secret key in encryption and decryption circuits. REFERENCES [1] J. E. Gentle, Random Number Generation and Monte Carlo Methods, 2nd ed. New York: SpringerVerlag, 2003. [2] M. P. Kennedy, R. Rovatti, and G. Setti, Chaotic Electronics in Telecommunications. Boca Raton, FL: CRC, 2000. [3] D. Knuth, The Art of Computer Programming, 2nd ed. Reading, MA: Addison-Wesley, 1981. [4] A. Klapper and M. Goresky, “Feedback shift registers, 2-adic span, and combiners with memory,” J. Cryptology, vol. 10, pp. 111–147, 1997. [5] D. H. Lehmer, “Mathematical methods in largescale computing units,” in Proc. 2nd Symp. Large Scale Digital Comput. Machinery, Cambridge, MA, 1951, pp. 141–146, Harvard Univ. Press.
7. CONCLUSION The proposed reseeding mechanism solves the short-period problem originated from the digitization of the chaotic map. The long-period DX
[6] P. C. Wu, “Multiplicative, congruential randomnumber generators with multiplier and modulus ,” ACM Trans. Math. Software, vol. 23, pp. 255–265, 1997.
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[7] L. Y. Deng and H. Xu, “A system of highdimensional, efficient, longcycle and portable uniform random number generators,” ACM Trans.ModelComput. Simul., vol. 13, no. 4, pp. 299– 309, Oct. 1, 2003. [8] L. Y. Deng, “Efficient and portable multiple recursive generators of large order,” ACM Trans. Modeling Comput. Simul., vol. 15, no. 1, pp. 1–13, Jan. 2005. [9] L. Blum, M. Blum, and M. Shub, “A simple unpredictable pseudo- random number generator,” SIAM J. Comput., vol. 15, pp. 364–383, 1986. [10] B. M. Gammel, R. Goettfert, and O. Kniffler, “An NLFSR-based stream cipher,” in Proc. IEEE Int. Symp. Circuits Syst., 2006, pp. 2917–2920. [11]D.Mukhopadhyay,D.R.Chowdhury,andC.Rebeiro ,“Theory of composing non-linear machines with predictable cyclic structures,”inProc. 8th Int. Conf. Cellular Autom. Res. Ind., 2008, pp. 210–219, Springer. [12]D.Mukhopadhyay,“Grouppropertiesofnonlinearc ellularautomata,” J. Cellular Autom., vol. 5, no. 1, pp. 139–155, Oct. 2009.
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Game Theory and Auctions for Cooperation in a Wireless Network: A Survey Dr.R.Dhaya Associate Professor Dept of computer science and engineering Velammal Engineering College, Chennai, India. dhayavel2005@gmail.com
Abstract---Cooperative communication has great potential to amend the wireless channel capacity by exploiting the antennas on wireless contrivances for spatial diversity. However, applications of cooperative communication are marginally visually perceived in authenticity. A main obstruction blocking its wide applications is the lack of incentives for wireless nodes to participate in cooperative communication. We first survey the subsisting game theoretic solutions for providing cooperation incentives in cooperative communications. In this paper, we survey the most conspicuous works dwelling within the literature, and point towards paramount research directions. Keywords—cooperativecommunications, game theory, auction theory.
I. INTRODUCTION Today cooperative communication is an active area of research, and wireless devices are evolving into multipurpose systems with data extensive applications running on them, by this such applications require strong error protection and high speed connectivity. Those requirements, and along with the exploding growth of wireless networks and limited spectrum resources, have created capacity crunch and high interference in today’s wireless networks. This causes in situation that a move towards the development of new wireless techniques which can achieve a more efficient use of the available spectrum or energy consumption. An approach called cooperative communications promises to deliver some of the benefits of multiinput multi-output within the given constraints. Cooperative communication refers to the collaborative processing and retransmission of the overheard information at those stations surrounding the source. Because of the cooperation takes full advantage of the nature of the wireless channel and create diversity, in particular transmission diversity,
Anjana Devi.J PG Scholar Dept of computer science and engineering Velammal Engineering College, Chennai, India. anjanajavar@gmail.com
thereby achieving tremendous improvements in system robustness, capacity, delay, interference, and coverage range. II. COOPERATIVE COMMUNICATION In wireless networks, cooperative transmission is used as a means to combat channel fading (Fig.1). In cooperative communications, relays are assigned to help a source node to deliver its information to its destination node. Since transmission in the wireless channel is overheard by neighboring station which can process these signals and retransmit them in order to facilitate better reception. In these schemes, some overhearing nodes are also involved in the signal transmission by relaying the received signal from the source to the destination. Cooperative communications can achieve spatial diversity because signals bearing the same information go through uncorrelated channels introduced by cooperating nodes [1]. Each node in a cooperative communication transmits data of their own and acts a cooperative agent for other nodes (Fig. 2).
Fig. 1: cooperative communication.
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r2
r1
S
d
r3
rn
Fig3.b) one-to-many Fig. 2: Each mobile node is both a user and a relay. Cooperative transmission can obtain spatial diversity without using multiple antennas, thus achieving more reliable transmission or consuming less power. Since wireless channels vary with time, a source node may not always need help from a relay node, Therefore it is more sensible that cooperation is only initiated when it is necessary and beneficial and secondly, one or more appropriate relay nodes need to be selected among multiple potential helpers in the network. More generally a relay channel (RC) has many device nodes, but only one source and sink. The device nodes without sources and sinks are called relays and aid communication, perhaps generously, or through incentives, or competitively. Source node doesn’t use the relay nodes if it leads to the capacity lesser than its own direct transmission [9]. Cooperation among the nodes is required for achieving the cooperative communication. Not all the nodes will be willing to act as a relay node for it has to consume its own resources and energy. Game theory is used for analyzing and solving the problems in a cooperative network. Cooperative networks include three different topologies: a) one- to- one, b) one- to- many, c) many- to-one as depicted in Fig.3.
r
S
d Fig.3.a) One-to-one
s1
s2
r
d
s3 Fig 3.c) many-to-one Fig 3.Cooperative Communication topologies. The cooperative communication is better explained with one to one user model. Most cooperative transmission schemes involve two phases of transmission: a coordination phase, where users exchange their own source data and control messages with each other and/or the destination, and a cooperation phase, where the users cooperatively retransmit their messages to the destination. A basic cooperation system consists of two users transmitting to a common destination, as illustrated in Fig. 4. At any instant in time, one user acts as the source while the other user serves as the relay. In the coordination phase (i.e., Phase I), the source user broadcasts its data to both the relay and the destination and, in the cooperation phase (i.e., Phase II), the relay r forwards the source’s data (either by itself or by cooperating with the source) to enhance reception at the destination. The two users may interchange their roles as source and relay at different instants in time. To enable such cooperation among users, different relay technology can be employed.
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B. Amplify-and-Forward Relaying Scheme In amplify-and-forward (AF) relaying schemes, the relay amplifies the analog signal received from the source and forwards it to the destination (without explicitly decoding or demodulating the messages or symbols) . These schemes are also referred to as nonregenerative relaying schemes. Here, relays need not have knowledge of the encoding or modulation schemes employed at the source. Moreover, in addition to its low complexity, AF schemes are also desirable when the quality of the s-r link is not sufficient to guarantee reliable decoding at the relay. In this case, amplifying the analog signal preserves soft information that can be further exploited at the destination. The achievable capacity from s to d is Fig 4.Illustration of cooperative communication. C AF ( s, r , Pr , d )
Relaying Technology: There are several relaying techniques that can be employed by the cooperating relays. We compute the achievable capacity under cooperative communications. When node u transmits a signal to node v with power Pu, the signal-to-noise ratio (SNR) at node v, denoted by SNRuv, is
SNR uv
Pu N 0 || u , v ||
Where N0 is the ambient noise, ||u,v|| is the Euclidean distance between nodes u and v, and α is the path loss exponent which is between 2 and 4 in general, depending on the characteristics of the communication medium. A. Decode-and-Forward Relaying Scheme Decode-and-forward (DF) relaying schemes refer to cases where the relay explicitly decodes the message transmitted by the source s and forwards a newly generated signal to the destination d. These schemes are also known as regenerative relaying schemes. The achievable capacity from s to d is
SNRsr .SNRrd W log 2 1 SNRsd 2 SNRsr SNRrd 1
C. Coded cooperation Relaying Scheme In coded cooperation schemes different portions of the same message are transmitted in the two phases. Specifically, the source message is encoded in the first portion of the codeword that is transmitted by the source in Phase I and incremental redundancy (e.g., in the form of extra parity symbols) can be transmitted in the second portion of the codeword by either the source or the relay in Phase II. We adopt the cooperative communication model wth analog network coding [2], where each group of source nodes is assigned a single relay node. Denote by W the amount of bandwidth a relay node can utilize. Let Nrj be the white noise at relay node rj . Given the transmission power Prj of relay node rj , the channel capacity from source node si ∈ gk,where gk is the group agent to which the source node belongs. to destination node di through relay node rj can be calculated by a simplified channel capacity model as follows.
C(si , ri , di )
SNRsi,rj.SNRrj,di W log2 1 SNRsi,di | gk | 1 | gk | SNRrj,di SNRsi,rj si gk
W CDF(s, r, Pr ,d) minlog2 1SNRsr ,log21SNRsd SNRrd 2 Where 1
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| g k | 1N rj r2 N di
| g k | 1 r2
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III.
GAME THEORY
The essence of game theory is the formal study of interactions between several decision-makers who can have conflicting or common interests. By interactions, it is meant that what the others do has an impact on each decision-maker (called a player), and what he/she gets from an interactive situation does not only depend on his/her decisions. The mapping from the components in a game to the elements in cooperative communications is shown in Table I.
ISBN : 978 - 1502851550
which is actually the other source node. Each source node can decide to forward the packet to the destination of the other source (Forward) or drop it (Drop) (Fig.5) .
dst2
P1
P2
dst1
TABLE I COMPONENTS OF GAMES IN COOPERATIVE COMMUNICATIONS Components in the Game Players
Strategy
Utility/Payoff
Elements in Cooperative Communication Source nodes and/or relay nodes. Power control, Spectrum allocation, Relay nodes(s) or source node(s) selection, To cooperate or not Price.
Fig 5: The communication scenario under study: Each source node decides to forward the packet to destinations and has to go through to another source node. For this, each source node has to decide simultaneously either to forward or drop the received packets. The utility of each source is assumed to have the form “utility = benefit x cost” where the benefit is 1 if the packet is forwarded and 0 if it is dropped; the cost of transmitting is c > 0.This is shown in tabular form in Table II. TABLE II Forwarder’s dilemma in matrix form.
Data rate, Profit, e.g., revenue minus cost.
A strategic form game is an ordered triplet: G=(k, {Si}i∈k, ≥i) Where K is the set of players, Si is the set of strategies of player i, and ≥ i is a preference order over the set of action profiles for player i. The strategic form is the most used form, in both game theory and wireless literature. It is generally more convenient for mathematical analysis and is usable for both discrete and continuous strategy sets. In fact, the most common form relies on the existence of a cost/reward/payoff/utility function for each player. The utility of a player is the measurement function on the possible outcome determined by the strategies of all players and is denoted by ui. In wireless communications, the performance metrics (e.g., the quality of service) are generally known, which give the utility functions to be used directly [4]. Forwarder’s dilemma: Two source nodes want to send a packet to their respective destination nodes. To reach its destination, the packet has to go through an intermediate node
Classification of games: A. Dynamic vs static games Dynamic games generally assume that source nodes can extract some information from past moves, observations, and chosen strategies and take this into account to adjust current and future moves. In static games, source nodes have certain knowledge (information assumptions, behavior assumptions) and this does not change. B. Cooperative vs non-cooperative games In non-cooperative games, the individual goals and strategies can be distinguished, whereas in cooperative games this is not always possible. A key distinction between the two types of game is to know whether commitments are enforceable or not: in cooperative games commitments are fully binding
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and enforceable, while they are not in noncooperative games. Scope of a game theory includes the discussions on rationality, selfishness, interactions and the solution concepts.
Rationality:
For implementing advanced game theoretic algorithms in real systems, identifying the players plays an important role in modeling the strategic structure of the environment of a terminal. Additionally, wireless networks also have some specific features, which makes the problem of rationality even more complicated. In heterogeneous networks where players optimize different performance criteria, some players can be perceived as non-rational from a given other player’s point of view. Of course, this depends on the knowledge of the considered player.
Selfishness:
Modeling players as selfish decision-makers leads to incorrect predictions. But in wireless games selfish players are seems to be, in general, the most relevant assumption.
node i chooses the action D (Drop) the best-response of Source node -i is to drop. From this, the output of the global best-response correspondence BR (see 1.14) equals (D,D) for all the four possible action profiles. The unique fixed-point of this correspondence is clearly (D,D) i.e. (0,0), which is the unique Nash equilibrium of the game. Extensive-form game : An extensive-form game is a specification of a game in game theory, allowing (as the name suggests) explicit representation of a number of important aspects, like the sequencing of players' possible moves, their choices at every decision point, the (possibly imperfect) information each player has about the other player's moves when he makes a decision, and his payoffs for all possible game outcomes. Extensive-form games also allow representation of information. The Stackelberg game is an extensive form game, which is used to model the competition between one player, called the leader, and a set of players, called the followers. In this game, the leader takes action first and then the followers take actions. The leader knows ex ante that the followers observe its action and take actions accordingly. The NE in the Stackelberg game is called Stackelberg Equilibrium.
Interaction:
A game corresponds to a situation where (autonomous) decision-makers interact. The interaction in wireless networks depends on the scenario. Often interaction does exist because terminals share common resources. For example, when users exploit the same band at the same time, in the same geographical area, some multiuser interference occurs. Decisions made by the players are inter-dependent,in the sense that their performance metric depends on what the other players do:this is the interaction through actions. It is useful to know that there can be interaction between players even if the player’s utility does not directly depend on the actions of the others.
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Solution Concepts
The best response is the strategy which produces the most favorable outcome for a player, taking other players' strategies. The concept of a best response is central to John Nash's best-known contribution, the Nash equilibrium, the point at which each player in a game has selected the best response (or one of the best responses) to the other players' strategies .If Source node i chooses the action F (forward) the best-response of Source node -i is to drop. If Source
In a nut shell game theory states that it is common to be in situations where the outcome of a situation depends not only on what we do, but also on what other people do. This is clearly the case when participating in an auction. In cooperative network the players of the auction under consideration are base stations, laptops, mobile phones, routers, servers, and so on. Obviously, the engineers who design these machines are directed by the economic policy of their company or institution, which indicates that identifying the players is not always obvious in wireless communications. Nonetheless, there is a difference between considering a telecoms operator or a mobile phone to be a player – the nature of the action or decision to be taken is different. For an operator involved in a spectrum auction, the action to be taken may be a price, whereas the possible actions available to a mobile phone may be to decide which access points or base stations to be connected to [3]. Indeed, interaction between wireless terminals like mobile phones is naturally present in wireless networks, since interference often exists or/and common resources must be shared.
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IV. AUCTIONS IN COOPERATIVE NETWORK An auction is a process of trading resources by offering them up for bidding, and selling the items to the highest bidder. In economic terms, it is also a method to determine the value of a resource whose price is unknown. An auction is organized by an auctioneer, who distributes grid Market-Oriented Resource Management and Scheduling. The mechanism consists of determining the winner and setting the price. Auction schemes can be broadly classified into three categories: Pricing or credit based schemes Reputation based schemes ; and Commodity exchanged schemes. Credit-based schemes consider packet forwarding as a market model where nodes providing a service are remunerated, whilst nodes receiving a service are charged [5]. Hence, if a node wants to send its own packets, it must forward packets for the benefit of others. However, these schemes require tamperresistant hardware) or infrastructure-dependent credit clearance that other nodes can trust [7], [8]. The Reputation-based schemes discourage misbehavior by estimating the nodes reputation and punishing nodes with bad behavior .The scheme requires each node to rate every other node with which it communicates based on the service received or on observing the behavior of neighbors by listening to communications in the same transmission range. According to the collected information, the reputation system maintains a value for each observed node that represents a reputation of its behavior. The reputation mechanism allows avoiding sending packets through misbehaving nodes [10]. In commodity exchange mechanism, the source node takes other nodes as relays for cooperative communication. In return, the source node provides its own resource to help the relay nodes achieve certain objectives.[6] The auctions can be divided into three types based on participants and commodity exchanged: a) Single-sided auction, b) Double-sided auction, and c) Combinatorial auctions. A.Single-sided Auction: Single-sided auctions are mechanisms, where only buyers or sellers can submit bids or asks. Even though the single-sided auction is the most widely applied market model, it often leads to inefficient allocation. The most prominent single sided auctions are Vickrey Auction, Dutch Auction, First Price Sealed Bid (FPSB), and English Auction.
ISBN : 978 - 1502851550
English Auction: In the English auction, the auctioneer begins the auction with a reserve price (lowest acceptable price). Auction continues in rounds with increasing bid prices, until there is no price increase. The item is then sold to the highest bidder. Dutch Auction: In the Dutch auction the auctioneer begins with a high asking price which is lowered until some participant is willing to accept the auctioneer’s price or a predetermined minimum price is reached. That participant pays the last announced price. This type of auction is convenient when it is important to auction resources quickly, since a sale never requires more than one bid. Vickrey Auction: A Vickrey auction is a sealedbid auction, where bidders submit sealed bids. The highest bidder wins, paying the price of the second highest bid. This gives bidders incentives to bid their true value. When multiple identical units are auctioned, one obvious generalization is to have all bidders pay the amount of the highest non-winning bid. First Price Sealed Bid (FPSB) Auction: In this type of auction, all bidders simultaneously submit bids so that no bidder knows the bid of any other participant. The highest bidder says the price they submitted. In this case, the bid strategy is a function of one’s private value and the prior belief of other bidders’ valuations. The best strategy is bid less than its true valuation and it might still win the bid, but it all depends on what the others bid.
B.Double Sided Auction: In double auction, both providers and users submit bids which are then ranked highest to lowest to generate demand and supply profiles. From the profiles, the maximum quantity exchanged can be determined by matching selling offers (starting with the lowest price and moving up) with demand bids (starting with the highest price and moving down). This format allows users to make offers and providers to accept those offers at any particular moment. In double auction, the winner determination depends on different aspects such as aggregation, resource divisibility and if goods are homogeneous or are heterogeneous. Aggregation can come from the supplier side or from the buyer side. If no aggregation is allowed then each bid can be exactly matched to one ask. Divisible goods can be allocated partially. In the case that the bidder wants the entire good or nothing then its bid is considered indivisible.
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C. Combinatorial Auctions: Users may require a combination of multiple resources such as CPUs, memory and bandwidth. Combinatorial auction allows users and providers to trade a bundle of multiple resources. It is advantageous to users as they do not need to participate in multiple negotiations with providers for each resource required. Moreover, in some cases it also leads to cost benefits. In combinatorial auction, users express their preferences as bundles of resources that need to be matched. The providers submit their tasks and the auctioneer solves the optimization problem of allocation. The only drawback of combinatorial auction is the NPhardness of the matching problem which makes it inapplicable for large scale settings. Various variants of combinatorial auction are proposed in the literature to allocate computational resources among grid users. Main Issues to be focused in auction mechanism:
Truthfulness implies that the dominant strategy of each agent is to submit truthful valuations of the products. It can be achieved by unrelated bids of participating agents to their payments [11],[12]. Budget Balance means that the total payment received from the buyers is no less than the total payment to the sellers in an auction. Individual Rationality means that no winning buyer will be charged more than its bid, and no winning seller will be paid less than its ask.
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[3] J. Huang, Z. Han, M. Chiang, and H. Poor, “Auction-based resource allocation for cooperative communications,” IEEE JSAC, vol. 26, pp. 1226–1237, 2008. [4] M. Janzamin, M. Pakravan, and H. Sedghi, “A game-theoretic approach for power allocation in bidirectional cooperative communication,” in Proc. IEEE WCNC’10, pp. 1–6. 12 [5] N. Shastry and R. Adve, “Stimulating cooperative diversity in wireless ad hoc networks through pricing,” in Proc. IEEE ICC’06, pp. 3747–3752. [6] H. Wang, L. Gao, X. Gan, X. Wang, and E. Hossain, “Cooperative spectrum sharing in cognitive radio networks- a game-theoretic approach,” in Proc. IEEE ICC’10. [7] B. Wang, Z. Han, and K. Liu, “Distributed relay selection and power control for multiuser cooperative communication networks using stackelberg game,” IEEE Trans. Mobile Comput., vol. 8, pp. 975–990, 2009. [8] G. Zhang, L. Cong, L. Zhao, K. Yang, and H. Zhang, “Competitive resource sharing based on game theory in cooperative relay networks,” ETRI Journal, vol. 31, pp. 89–91, 2009. [9] D. Yang, X. Fang, and G. Xue, “HERA: An optimal relay assignment scheme for cooperative networks,” IEEE JSAC, accepted. [10] Y. Chen and S. Kishore, “A game-theoretic analysis of decode-and-forward user cooperation,” IEEE Trans. Wireless Commun., vol. 7, pp. 1941–1951, 2008. [11] D. Yang, X. Fang, and G. Xue, “Truthful auction for cooperative communications,” in Proc. ACM MOBIHOC’11, pp. 89–98. [12] D. Yang, X. Fang, and G. Xue, “Truthful auction for cooperative communications with revenue maximization,” in Proc. IEEE ICC’12, accepted.
V. CONCLUSION In this article, we have briefly surveyed on the game theory and auctions for the relay assignment in cooperative communications, with the fixate on designing cooperation incentive mechanisms. While game theory has been extensively applied to cooperative communications, there are still many challenges to be resolved with an extra effort from researchers. REFERENCES [1] J. Laneman, D. Tse, and G. Wornell, “Cooperative diversity in wireless networks: Efficient protocols and outage behavior,”IEEE Trans. Inf. Theory, vol. 50, pp. 3062–3080, 2004. [2] S. Sharma, Y. Shi, J. Liu, Y. T. Hou, and S. Kompella, “Is network coding always good for cooperative communications?” Proc. 2010 IEEE INFOCOM.
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ISBN : 978 - 1502851550
Survey on Cognitive Radio Networks and its Routing Mechanism Dr.R.Dhaya
C.Ambhika
Associate Professor, Dept. of Computer Science Velammal Eng. College Chennai dhayavel@gmail.com
PG scholar, Dept. of Computer Science Velammal Eng. College Chennai ambhidurai@gmail.com
Abstract—The
primary utilization activities and traffic characteristics in, the available spectrum resources will vary between mesh transmission endeavors, posing a challenge that the routing and resource allocation and have to deal with to assure timely distribution of the network traffic. COGNITIVE radio is a aiming at better utilization of available channel resources by the existence of licensed (or primary) and unlicensed (secondary or cognitive) radio nodes on the same bandwidth. The mesh nodes utilize cognitive overlay mode to share the spectrum with primary users.
from the fortification of network/infrastructure sides or just proceed in an ad hoc manner. Cognitive radio technology could additionally facilitate interoperability among different communication systems in which frequency bands and/or transmission formats differ.
Keywords— Cognitive, Spectrum, Mesh Architecture, Routing
I.
INTRODUCTION
Cognitive radios are an efficient technology for enabling unlicensed contrivances to efficiently utilize the spaces. Features of routing protocols in multi-hop networks are the routing metric used to cull the best route for forwarding packets. We survey the state-of-the-art routing metrics for cognitive radio networks. The listing of challenges that are addressed in designing a good routing metric for cognitive radio networks.
II.
COGNITIVE NETWORKS
Cognitive radios are software defined radios capable of sensing their environment and making authentic-time decisions, without any systems intervention [2]. This sanctions them to transmute their modulation schemes or protocols so as to habituate to the sensed environment. These radios dynamically identify portions of the spectrum that are not in utilization by primary users, and configure the radio to operate in the opportune space. The efficiency of the spectrum allocation determines both the network’s throughput as well as the overall spectrum utilization. The efficiency of the spectrum allocation determines both the network’s throughput as well as the overall spectrum utilization.
Cognitive Radio Hetrogeneity A cognitive radio terminal could additionally negotiate with other spectrum and/or network users to enable more efficient spectrum and network utilization[3]. The negotiation procedure may be facilitated
Figure 1. Ubiquitous Cognitive Radio Heterogeneous
A cognitive radio shall sense the environment (cognitive capability), analyze and learn sensed information (self-organized capability) and adjust to the environment (reconfigurable capabilities).
A. Cognitive Capability Spectrum Detection A cognitive radio can sense spectrum and detect “spectrum holes” which are those frequency bands not utilized by the licensed users or having constrained interference with them. Spectrum Sharing Waves may eventually be able to negotiate for spectrum use on an ad hoc or authentictime substructure, without the desideratum for prior acquiescent between all parties. Location Identification The ability to determine its location and the location of other transmitters, and then cull the congruous operating parameters such as the potency and frequency sanctioned at its location. Location technology may be a congruous method of eschewing interference because sensing technology would not be
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able to identify the locations of nearby receivers. Network/System Discovery Networks are reachable either via directed one hop communication or via multi-hop relay nodes. If there is no directed communication link between the terminal and the BTSs/APs but through other cognitive radio terminals some access networks are reachable, it can still make a call in this circumstance. Accommodation Discovery Network or system operators provide their accommodations through their access networks.
B. Reconfigurable Capability
Frequency Agility This ability customarily coalesces with a method to dynamically cull the opportune operating frequency predicated on the sensing of signals from other transmitters or on some other method. Dynamic Frequency Selection It dynamically detects signals from other radio frequency systems and evades cochannel operation. Adaptive Modulation/Coding A cognitive radio could cull the felicitous modulation type for use with a particular transmission system to sanction interoperability between systems. Transmit Power Control It sanctions transmission at the allowable limits when indispensable, but reduces the transmitter power to a lower caliber to sanction more preponderant sharing of spectrum when higher power operation is not obligatory. Dynamic System/Network Access For a cognitive radio terminal to access multiple communication systems/networks which run different protocols, the ability to reconfigure itself to be compatible with these systems is indispensable.
C. Self-Organized Capability Spectrum/Radio Resource Management To efficiently manage and organize spectrum apertures information among cognitive radios, good spectrum management scheme is indispensable.
ISBN : 978 - 1502851550
connection management can avail neighborhood revelation, detect available Internet access and support vertical handoffs, which avail cognitive radios to cull route and networks. Trust/Security Management Since CRNs are heterogeneous networks in nature, sundry heterogeneities (e.g. wireless access technologies, system/network operators) introduce lots of security issues. Trust is thus a requirement for securing operations in CRNs. III.
NETWORK ARCHITECTURE
The CRNs can be deployed in network-centric, disseminated, ad hoc, and mesh architectures, and accommodate the desiderata of both licensed and unlicensed applications [2]. The rudimentary components of CRNs are mobile station (MS), base station/access point (BSs/APs) and backbone/core networks.
A. Infrastructure Architecture MS can only access a BS/AP in the one-hop manner. MSs under the transmission range of the same BS/AP shall communicate with each other through the BS/AP. Communications between different cells are routed through backbone/core networks. The BS/AP may be able to execute one or multiple communication standards/protocols to consummate different demands from MSs.
Figure 2. Infrastructure Architecture
B. Ad-hoc Architecture There is no infrastructure support (or defined) in ad-hoc architecture. If an MS apperceives that there are some other MS nearby and are connectable through certain communication standards/protocols, they can establish a link and thus form an ad hoc network.
Mobility and Connection Management Due to the heterogeneousness of CRNs, routing and topology information is more and more involutes. Good mobility and
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Figure 3. Ad-hoc Architecture
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Proceedings of International Conference On Current Innovations In Engineering And Technology C. Mesh Architecture This architecture is an amalgamation of Infrastructure and Ad Hoc architectures by enabling the wireless connections between BSs/APs, which is akin to the Hybrid Wireless Mesh Networks. MSs can either access the BSs/APs directly or use other MSs as multi-hop relay nodes. Some BSs/APs may connect to the wired backbone/core networks and function as gateways. Since BSs/APs can be deployed without compulsorily connecting to wired backbone or core networks, it is more flexible and less costly in orchestrating the locations of BSs/APs. For BSs/APs having cognitive radio capabilities, they may use spectrum apertures to communicate each other. Due to potentially lots of spectrum apertures available, the capacity of wireless communication links among cognitive radio BSs/APs may be enough to accommodate as wireless backbone.
Figure 4. Mesh Architecture Networks
IV.
CHALLENGES OF ROUTING IN C OGNITIVE RADIO
The key challenge for routing in cognitive radio networks is the dynamical spectrum occupancies (or equivalently the dynamical transmission changes)[4]. When the channel being used by a secondary user is occupied by primary users, the corresponding link is broken; thus the data route no longer works[1]. Then, there are three possible actions the secondary user can take: • Wait: If the primary users will leave the channel soon, the secondary user can wait until the channel is cleared. • Switching channels: If there are multiple channels, the secondary user can also try to sense other channels and resume the transmission until an available channel is found. • Re-routing: If there is only one channel and the primary user does not leave quickly, a new path has to be found in order to resume the data traffic. Note that all the above actions incur cost. It incurs packet delay when waiting for the primary user to leave. In most wireless hardware, it takes time to switch to a new channel. It also incurs significant overhead to carry out re-routing since the secondary users need to exchange messages on the path information. Then, it is determined by the dominating factor to choose the corresponding action. This results in two type of routing schemes:
ISBN : 978 - 1502851550
• Stationary Routing: The data traffic has a fixed route. This type routing requires a quick channel switch mechanism or the primary user can leave quickly (that is, the spectrum is highly dynamical). Or when the spectrum is highly stationary (in this case, the network is similar to a traditional one), the route can also be stable, since the primary users seldom break the data path; however, in this case, a re-routing mechanism may be needed in case the emergence of primary users. • Dynamical Routing: In this case, the data traffic does not have a fixed route. The packet forwarding is adaptive to the spectrum situation or is random. The dynamical routing is suitable for the case in which the spectrum is moderately dynamical and the channel switching incurs significant overhead; otherwise, the secondary users can either wait for the leave of primary users or quickly switch to another channel. The change of routing strategy with respect to the level of dynamical spectrum. Hence, the selection of routing strategy should be highly dependent on the spectrum environment and the hardware specifications of the secondary users. A. Stationary Routing The routing can protect the primary users explicitly. There are two classes of secondary user services: class I assigns more significance to end-to-end latency under the constraint of primary user interference; class II puts more priority on the protection of primary users at the cost of certain performance loss for cognitive radio network. The routing algorithm must be scalable and takes the routing and spectrum selection into account jointly. B. Dynamic Routing It is assumed that the secondary user do not have prior information about the spectrum situation. The secondary users to learn how to carry out the routing. First, we describe how the MAC layers works in the network. Suppose that secondary user plans to send a packet to secondary user b. It first chooses a channel that is idle by carrying out spectrum sensing. Then, it sends a request-to-send (RTS) over these available channels. If no clear-to-send (CTS) from secondary user b is received in a predetermined period of time, a sends the RTS again until it receives the CTS. When b sends back the CTS, it also knows that a will transmit over this channel; thus, b will wait for the packets from a in this channel. Note that the RTS-CTS mechanism is the same as many traditional communications systems, such as the systems with CSMA-CA mechanism. However, the novelty of this approach is that the channel information is simplicity conveyed in the RTS message. C. Route Maintenance We assume that a route is broken due to the mobility of secondary users. For example, when a secondary user in a data path moves to an area with many primary users, this route may be damaged according to the protection of primary users. At this time, a new route should be found to resume the data traffic. In such a scheme, it is supposed that each secondary
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Proceedings of International Conference On Current Innovations In Engineering And Technology user knows its own location (e.g., using a GPS), as well as the locations of primary users. When a secondary user finds that it is close to primary users by comparing with a threshold, it signals its previous hop user that a new route discovery procedure should be initiated. Then, the previous hop user sends out RREQ packets and finds a new route.
D. Challenges in Cognitive Radio The main reason for packet drop is due to congestion. The congestion is determined by the drop of packets. However, this assumption is incorrect in wireless communication networks, where the packet drop can also be incurred by bad channel conditions (e.g., deep fading situation). For example, an intermediate communication link experiences a temporary deep fading and thus causes a packet drop. Actually, the bad channel condition may be recovered soon and there is no congestion; however, the source node will significantly decrease its traffic rate, thus causing the under utilization of the wireless spectrum. Hence, many approaches have been proposed to address the congestion control in wireless communication network.
ISBN : 978 - 1502851550
channel, all the neighboring SUs invalidate the routes that use this channel [5]. It filters the hop count to select between the candidate routes that have the same sequence number. A power-cognizant routing protocol was proposed utilizing five different metrics predicated on battery power consumption at nodes. These five metrics are the following: 1)Minimize energy consumed/packet: where energy consumed per packet is
Where T (a; b) is the energy consumed in transmitting (and receiving) one packet over one hop from a to b. 2) Maximize time to network partition: utilizing the max-flowmin-cut theorem, a minimal set of nodes (the cut-set) the abstraction of which will cause the network to partition can be found. This routing procedure balances the load over this set of nodes to maximize the life of the network. 3) Minimize Variance in node power levels: send packets to the neighbors with the least amount of data waiting to be transmitted. This metric is predicated on that all nodes in the network are equivalently consequential and endeavor to remain up all the nodes in the network. 4) Minimize cost/packet: where the node cost is the total energy consumed by this node so far. 5) Minimize maximum node cost.
Figure 5. Routing metric design challenges.
A modified version of the AODV protocol that avoids active primary users’ regions during both route information and packet forwarding without requiring a dedicated common control channel.
Figure 7: When a primary user becomes active, blocking the original route going through Node 2, Node 1 chooses to go through the combined route constructed by nodes 2 and 3 collaborating to null the interference at the primary user. This route is potentially better than choosing the alternate longer route that goes through Node 5.
Figure 6: Geographic forwarding on a given channel. The next hop is selected as the node nearest to the destination than the current node within the focus region.
During the route formation, channels that are currently used by PUs are excluded from the route discovery process. During forwarding, when a PU becomes active on a certain
Figure 7 shows a motivating scenario for DZP, in which Node 1 maintains the constructed route (1-2-4), even in the presence of a PU, by allowing nodes 2 and 3 to cooperatively send data packets to Node 4. This is better than using the alternate route that goes through Node 5. A distributed CR routing protocol that supports route maintenance, mobility, and do not require common control channel is considered one of the most suitable routing protocols to CRNs. However, designing such
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Proceedings of International Conference On Current Innovations In Engineering And Technology protocol while ensuring minimum end-to-end delay is not an easy task. E. Delay Routing approaches measures the quality of routing in terms of delays [6]. End-to-end delay along route is a traditional metric for routing algorithms, several different cases in multi-hop CRN. Delay-aware routing metrics are proposed in [7, 8, 9, 10], different delay components such as: 1. Switching Delay: occurs when a node in a path changes its frequency band. 2. Backoff Delay: MAC protocols result in backoff delay when trying to solve hidden-terminal and exposedterminal problems (while working on identical frequency band). 3. Queuing Delay: which depends on the transmission capacity of a node on a given frequency band.
V.
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CONCLUSION
Delay as a routing metric captures different aspects including channel switching time, end-to-end delay, and transmission delay, among others. It can be used as the main metric. Statistical model for the end-to-end delay in single path routing and then extends it to duplication-based and coding-aided multi-path routing schemes. The paper considers the impact of interference and dynamic spectrum access to derive the end-to-end delay using cognitive mesh networks. REFERENCES [1]
Youssef,M. ; Ibrahim,M.;AbdelatiM. ;LinChen ;Vasilakos,A.V."Routing Metrics of Cognitive Radio Networks:A Survey”,IEEE Communications Surveys & Tutorials, Volume: 16 Issue: 1 [2] K. –C. Chen, Y. –J. Peng N. Prasad Y. –C. Liang, S. Sun “ Cognitive Radio Network Architecture: Part I – General Structure.” [3] “Survey on performance analysis of cognitive radio networks” Pasi Lassila and Aleksi Penttinen COMNET Department, Helsinki University of Technology, Finland [4] F. Akyildiz, W. –Y. Lee, M. C. Vuran, S. Mohanty. NeXt generation/dynamic spectrum access/cognitive radio wireless networks: a survey. Computer Networks, Volume 50, Issue 13, 15 September 2006, Pages 2127-2159. [5] C. E. Perkins. Mobile IP. IEEE Communications Magazine, vol.40, no.5, pp.66-82, May 2002. [6] C. S. R. Murthy and B. S. Manoj. “Ad Hoc Wireless Networks: Architecture and Protocols”. Prentice Hall, 2004. [7] G. Cheng, W. Liu, Y. Li, and W. Cheng, “Spectrum aware on-demand routing in cognitive radio networks," 2nd IEEE International Symposium on New Frontiers in Dynamic Spectrum Access. [8] [8] G. Cheng, W. Liu, and Y. Li, “Joint on-demand routing and spectrum assignment in cognitive radio networks," IEEE International conference on Communications, pp. 6499{6503, 2007 [9] Z. Yang, G. Cheng, W. Liu, W. Yuan, and W. Cheng, “Local coordination based routing and spectrum assignment in multi-hop cognitive radio networks," Mobile Networks and Applications, pp. 67{81, 2008. [10] Z. Song, B. Shen, Z. Zhou, and K. S. Kwak, “Improved ant routing algorithm in cognitive radio networks," Communications and Information Technology, ISCIT 9th International Symposium,2009.
Delay-aware routing metrics are proposed in which consider different delay components including three delay components at a CR node. Node 2 relays flow 1 by receiving data on frequency band A and transmitting data on frequency band B. It uses the same spectrum band C for flow 2. On the other hand, node 5 relays all crossing flows on frequency band C. The delay at node 2 is dominated by switching delay, while the medium access delay is dominant in node 5. In addition to these delays, there exists also the queuing delay depending on the output capacity available on a given frequency band and on the number of flows sharing this capacity and on their workload.
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DESIGN OF A LOW POWER MULTIBAND CLOCK DISTRIBUTION CIRCUIT USING SINGLE PHASE CLOCK T.BhavyaBhavani (1), Dr.K.Seshadri Sastry (2), Dr.G.R.L.V.N Srinivas Raju (3) T.BhavyaBhavani (1), M.Tech student -VLSI Design, Dept of ECE, Shri Vishnu Engg College for Women Dr.K.Seshadri Sastry (2), Professor, Dept of ECE, Shri Vishnu Engineering College for Women Dr.G.R.L.V.N Srinivas Raju (3), Professor and H.O.D, Dept of ECE, Shri Vishnu Engg College for Women ABSTRACT: The clock distribution network consumes nearly 70% of the total power consumed by the integrated circuit since this is the only signal which has the highest switching activity. Normally for a multiband clock domain network we develop a multiple PLL to cater the need. This project aim for developing a low power true single phase clock(TSPC) multiband network which will supply for the multi clock domain network. In this paper, a wide band 2/3 prescaler is verified in the design of proposed wide band multimodulus 32/33/47/48 or 64/65/78/79 prescaler. A dynamic logic multiband flexible integer-n divider based on pulse swallow topology is proposed which uses a low power wide band 2/3 prescaler and a wide band multimodulus 32/33/47/48 or 64/65/78/79 prescaler. Since the multimodulus 32/33/47/48 or 64/65/78/79 prescaler has a maximum operating frequency of 6.2GHz, the values of P and S counters can actually be programmed to divide over the whole range of frequencies. However the P and S counter are programmed accordingly. The proposed multiband flexible divider also uses an improved loadable bit cell for swallow counter and consumes a power of 0.96 and 2.2mW. This project is highly useful and recommended for communication applications like Bluetooth, Zigbee, IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers which are proposed based on pulse swallow topology. This design is modelled using Verilog simulated tool ‘MODELSIM 6.4b’ and implemented and synthesized using ‘Xilinx ISE 10.1’. Keywords: True single phase clock (TSPC), Frequency synthesizer, Multimodulus prescaler, Phase locked loop (PLL)
1. INTRODUCTION Wireless LAN (WLAN) in the multi gigahertz bands, such as HIPER LAN II and Network standards like IEEE 802.11a/b/g are recognized as leading standards for high-rate data transmissions, and standards like Network protocol IEEE 802.15.4 are recognized for low-rate data transmissions. The integrated synthesizers for Wireless LAN applications at 5GHz reported in and consume up to 24 mw in CMOS realizations, where the first-stage divider is implemented using an Injection-locked divider which consumes large chip area and has a narrow locking range. The best published frequency synthesizer at 5GHz consumes 9.6 mw at 1-V supply, where its complete divider consumes power around 6 mw, where the first-stage divider is implemented using the source-coupled logic (SCL) circuit, which allows higher operating Frequencies but uses more power. Dynamic latches are faster and consume less power compared to static dividers. High speed divide-by- counter (also called prescaler) is a fundamental module for frequency synthesizers. Its design is crucial because it operates at a higher frequency and consumes higher power consumption. A divide-by- counter consists of flipflops (FF) and extra logic, which determines the terminal count. Conventional high speed FF based divide by counter designs use current-mode logic (CML) latches and suffer from the disadvantage of large load capacitance. This not only limits the maximum operating frequency and current-drive capabilities, but also increases the total power consumption. Alternatively, FF based divide-by designs adopt dynamic logic FFs such as true-singlephase clock (TSPC). The designs can be further enhanced by using extended true-single-phase-clock (E-TSPC) FFs for high speed and low power applications. E-TSPC designs remove the transistor
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stacked structure so that all the transistors are free of the body effect. They are thus more sustainable for high operating frequency operations in the face of low voltage supply. Past optimization efforts on prescaler designs focused on simplifying the logic part to reduce the circuit complexity and the critical path delay. For example, an E-TSPC design embedded with one extra P-MOS/N-MOS transistor can form an integrated function of FF and AND/OR logic. Moving part of the control logic to the first FF to reduce unnecessary FF toggling yields another version of prescaler design .These two classic designs each contains 16 transistors only and the mode control logic uses as few as 4 transistors. To achieve such circuit simplicity, it calls for a rationed structure in the FF design. Despite its distinct speed performance, the incurred static and short circuit power consumptions are significant. Latest designs presented in adopt a general TSPC logic family containing both rationed and ratio less inverter alternatives. Since the maximum height of transistor stacking is up to 5, these designs lose their performance advantages when working under a low scenario. In a power gating technique by inserting an extra PMOS between and the FF is employed in two novel divide-by-2/3 counter designs. The unused FF can be shut down when working in the divide-by-2 mode. Due to the increase in the number of transistor stacking (up to 4), these designs are not suitable for low operations. Due to the quadratic dependence of power consumption on supply voltage, lowering is a very effective measure to reduce the power at the expense of speed performance. .In particular, here focus on low operations for power saving without sacrificing the speed performance. In this design, rationed E-TSPC FFs are employed due to its circuit simplicity and speed performance. Only one pass transistor is needed to implement the mode control logic. The proposed design is capable of working at a maximum frequency of 531 MHz when the supply voltage is as low as 0.6 V.
ISBN : 978 - 1502851550
Fig 1: Proposed dynamic logic multiband flexible divider. The TSPC and E-TSPC designs are able to drive the dynamic latch with a single clock phase and avoid the skew problem. However, the adoption of singlephase clock latches in frequency dividers has been limited to PLLs with applications below 5GHZ. The frequency synthesizer reported in [6] uses an E-TSPC prescaler as the first-stage divider, but the divider consumes around 6.25 mw. Most Network protocol IEEE 802.11a/b/g frequency synthesizers employ SCL dividers as their first stage, while dynamic latches are not yet adopted for multiband synthesizers. In this paper, a dynamic logic multiband flexible integer-N divider based on pulse-swallow topology is proposed which uses a low-power wideband 2/3 prescaler and a wideband multi modulus 32/33/47/48 prescaler as shown in Fig. 1. The divider also uses an improved low power loadable bit-cell for the Swallow-counter. 2. DESIGN CONSIDERATIONS The key parameters of high-speed digital circuits are the propagation delay and power consumption. The maximum operating frequency of a digital circuit is calculated and is given by
f max = 1/(tpLH + tpH L) Where tpLH and tpHL are the propagation delays of gates respectively. The total power consumption of the CMOS digital circuits is determined by the switching and short circuit power.
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The switching power is linearly proportional to the operating frequency and is given by the sum of switching power at each output node as in
n P Switching=∑ fclkCLiVdd2 i=1 where n is the number of switching nodes fclk is the clock frequency CLi is the load capacitance at the output node of the stage, and Vdd is the supply voltage. Normally, the short-circuit power occurs in dynamic circuits when there exists direct paths from the supply to ground which is given by
Psc = Isc * Vdd where Isc is the short-circuit current. The analysis shows that the short-circuit power is much higher in E-TSPC logic circuits than in TSPC logic circuits. However, TSPC logic circuits exhibit higher switching power compared to that of E-TSPC logic circuits due to high load capacitance. For the E-TSPC logic circuit, the short-circuit power is the major problem. The E-TSPC circuit has the merit of higher operating frequency than that of the TSPC circuit due to the reduction in load capacitance, but it consumes significantly more power than the TSPC circuit does for a given transistor size. The following analysis is based on the latest design using the popular and lowcost 0.18 _m CMOS process. 3. WIDEBAND E-TSPC 2/3 PRESCALER The E-TSPC 2/3 prescaler consumes large short circuit power and has a higher frequency of operation than that of TSPC 2/3 prescaler. The wideband single-phase clock 2/3 prescaler used in this design consists of two D-flip-flops and two NOR gates embedded in the flip-flops. The first NOR gate is embedded in the output of DFF1, and the second NOR gate is embedded in the first stage of DFF2.
Fig 2: Wideband single-phase clock 2/3 prescaler
ISBN : 978 - 1502851550
When logic signal MC switches from "1" to "0", the logic value at the input of DFF1 is transferred to the input of DFF2 as one of the input of the NOR gate embedded in DFF1 is "0" and the wideband prescaler operates at the divide-by-3 mode. During the divide-by-2 operation, only DFF2 actively participates in the operation and contributes to the total power consumption since all the switching activities are blocked in DFF1. Thus, the wideband 2/3 prescaler has benefit of saving more than 50% of power during the divide-by-2 operation. The measured results shows that the wideband 2/3 prescaler has the maximum operating frequency of 6.5GHz. 4. MULTIMODULUS 32/33/47/48 or 64/65/78/79 PRESCALER The proposed wideband multimodulus prescaler which can divide the input frequency by 32, 33,47, and 48 or 64, 65,78 and 79 is shown in Fig. 3. It is similar to the 32/33 or 64/65 prescaler used in, but with an additional inverter and a multiplexer. The proposed prescaler performs additional divisions (divide-by-47 and divide-by-48 or divide-by-78 and divide-by-79) without any extra flip flop, thus saving a considerable amount of power and also reducing the complexity of multi band divider. The multimodulus prescaler consists of the wideband 2/3 (N1/(N1+1)) prescaler, four asynchronous TSPC divide-by-2 circuits ((AD)=16) and combinational logic circuits to achieve multiple division ratios.
Fig 3: Proposed Multimodulus 32/33/47/48 (or) 64/65/78/79 Prescaler
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Beside the usual MOD signal for controlling N/(N+l) divisions, the additional control signal sel is used to switch the prescaler between 32/33and 47/48 modes. 1) Case 1: sel='0' When sel='0', the output from the NAND2 gate is directly transferred to the input of 2/3 prescaler and the multimodulus prescaler operates as the normal 32/33 prescaler, where the division ratio is controlled by the logic signal MOD. If MC=1, the 2/3 prescaler operates in the divide-by-2 mode and when MC=O, the 2/3 prescaler operates in the divide-by-3 mode. If MOD=1, the NAND2 gate output switches to logic "I" (MC=1) and the wideband prescaler operates in the divide-by-2 mode for entire operation. The division ratio N performed by the multi modulus prescaler is N = (AD*N1) + (0*(N1+ 1)) = 32 Where N1=2 and AD=16 is fixed for the entire design. If MOD = 0 , for 30 input clock cycles MC remains at logic "1", where wideband prescaler operates in divide-by-2 mode and for three input clock cycles, MC remains at logic "0" where the wideband prescaler operates in the Divide-by-3 mode. The division ratio N+ 1 performed by the multi modulus prescaler is N+l = ((AD - l)*N1) + (1 * (N1 +1)) = 33 S2 switch to logic "0" and the bit-cell does not perform any function. The MOD signal goes logically high only when the S-counter finishes counting down to zero. If MOD and LD are logically low, the bit-cell acts as a divide-by-2 unit. If MOD is logically low and LD is logically high, the input bit PI is transferred to the output. In the initial state, MOD = 0, the multimodulus prescaler selects the divide-by-N+ 1 mode (divide-by-33 or32). 2) Case 2: sel =' l' When sel=' 1', the inverted output of the NAND2 gate is directly transferred to the input of 2/3 prescaler and the multimodulus prescaler operate as a 47/48 prescaler, where the division ratio is controlled by the logic signal MOD. If MC= 1, the 2/3 prescaler operates in divide-by- 3 mode and when MC=0, the 2/3 prescaler operates in divide-by-2 mode which is
ISBN : 978 - 1502851550
quite opposite to the operation performed when sel='0' If MOD=1, the division ratio N+ 1 performed by the multimodulus prescaler is same except that the wideband prescaler operates in the divide by-3 mode for the entire operation given by N + l = (AD * (N1+1)) + (0 * Nl) = 48 If MOD=1, the division ratio N performed by the multimodulus prescaler is N = ((AD - l ) * (N1 + 1)) + (1 * Nl)=47. In order to get 64/65/78/79 clock cycles we need to operate 4/5 prescaler by making the control signal sel of second MUX to ‘1’.To get 32/33/47/48 prescaler, the second MUX should be equal to ‘0’ means the control signal sel of the second MUX should be equal to ‘0’ and to get 64/65/78/79 prescaler, the second MUX should be equal to ‘1’ means the control signal sel of the second MUX should be equal to ‘1’. 1) Case 1: sel='0' When sel='0', the output from the NAND2 gate is directly transferred to the input of 4/5 prescaler and the multimodulus prescaler operates as the normal 64/65 prescaler, where the division ratio is controlled by the logic signal MOD. If MC=1, the 4/5 prescaler operates in the divide-by-2 mode and when MC = 0, the 4/5 prescaler operates in the divide-by-3 mode. If MOD=1, the NAND2 gate output switches to logic "1" (MC=1) and the wideband prescaler operates in the divide-by-2 mode for entire operation. The division ratio N performed by the multi modulus prescaler is N = (AD*N1) + (0*(N1+ 1)) = 64 Where N1=2 and AD=16 is fixed for the entire design. If MOD = 0 , for 62 input clock cycles MC remains at logic "1", where wideband prescaler operates in divide-by-2 mode and for three input clock cycles, MC remains at logic "0" where the wideband prescaler operates in the Divide-by-3 mode. The division ratio N+ 1 performed by the multi modulus prescaler is N+l = ((AD - l)*N1) + (1 * (N1 +1)) = 65
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S2 switch to logic "0" and the bit-cell does not perform any function. The MOD signal goes logically high only when the S-counter finishes counting down to zero. If MOD and LD are logically low, the bit-cell acts as a divide-by-2 unit. If MOD is logically low and LD is logically high, the input bit PI is transferred to the output. In the initial state, MOD=0, the multimodulus prescaler selects the divide-by-N+ 1 mode (divide-by-64 or 65) 2) Case 2: sel =' l' When sel=' 1', the inverted output of the NAND2 gate is directly transferred to the input of 4/5 prescaler and the multimodulus prescaler operate as a 64/65 prescaler, where the division ratio is controlled by the logic signal MOD. If MC= 1, the 4/5 prescaler operates in divide-by- 3 mode and when MC=0, the 4/5 prescaler operates in divide-by-2 mode which is quite opposite to the operation performed when sel='0' If MOD=1, the division ratio N+ 1 performed by the multimodulus prescaler is same except that the wideband prescaler operates in the divide by-3 mode for the entire operation given by
ISBN : 978 - 1502851550
uses two additional transistors M6 and M7whose inputs are controlled by the logic signal MOD. If MOD is logically high, nodes S1 (divide-by-48 or divide-by-79) and P, S counters start down counting the input clock cycles. When the S-counter finishes counting, MOD switches to logic "1" and the prescaler changes to the divide-by-n mode (divideby-32 or divide-47 or divide-by-64 or divide-78) for the remaining P-S clock cycles. During to a specified value from 0 to 31 for the lower band and 0 to 48 for the higher band of operation. this mode, since Scounter is idle, transistors M6 and M7 which are controlled by MOD, keep the nodes S1 and S2 at logic "0," thus saving the switching power in S counter for a period of (N*(P-S)) clock cycles. Here, the programmable input (PI) is used to load the counter.
N + l = (AD * (N1+1)) + (0 * Nl) = 79 If MOD=1, the division ratio N performed by the multimodulus prescaler is N = ((AD - l ) * (N1 + 1)) + (1 * Nl)=78. 5. MULTIBAND FLEXIBLE DIVIDER The single-phase clock multiband flexible divider which is shown in Fig 1 consists of the multi modulus 32/33/47/48or 64/65/78/79 prescaler, a 7-bit programmable (P) counter and a 6-bit swallow(S) counter. The control signal Sel decides whether the divider is operating in lower frequency band (2.4 GHz) or higher band (5-5.825 GHz). I .Swallow (S) Counter: The 6-bit s-counter shown in Fig.4 consists of six asynchronous loadable bit-cells, a NORembedded DFF and additional logic gates to allow it to be programmable from 0 to 31 or 0 to 63 for lowfrequency band and from 0 to 47 or 0 to 78 for the high-frequency band. The asynchronous bit cell used in this design .It is similar to the bit-cell except it
Fig 4: Swallow (S) Counter II. Programmable (P) Counter: The programmable P-counter is a 7-bit asynchronous down counter which consists of 7 loadable bit-cells and additional logic gates. Here, bit P7 is tied to the Sel signal of the multi modulus prescaler and bits P4 and P7 are always at logic "1." The remaining bits can be externally programmed from 75 to 78 for the lower frequency band and from 105 to 122 for the upper frequency band. When the P-counter finishes counting down to zero, LD switches to logic "1" during which the output of all the bit-cells in S-counter switches to logic "1" and output of the NOR embedded DFF switches to logic "0" (MOD = 0) where the programmable divider get
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reset to its initial state and thus a fixed division ratio is achieved. If a fixed 32/33 (N/(N+ 1)) dual-modulus prescaler is used, a 7 bit P counter is needed for the low-frequency band (2.4 GHz) while an 8-bit Scounter would be needed for the high frequency band(5-5.825 GHz) with a fixed 5-bit S counter. Thus, the multimodulus 32/33/47/48 prescaler eases the design complexity of the P-counter.
ISBN : 978 - 1502851550
cycles. Thus division ratio of 33(N+ 1) is performed. N and N+ 1 are given by N = (AD * N1) = 32 N + 1 = ((AD -1) * N1) + (1 * (N1 + 1)) = 33 2) When Sel=’l’: When Sel=l, the inverted output from NAND2 gate is given to the input of 2/3 prescaler and multimodulus prescaler operates in 47/48 mode. MOD signal controls the division ratio. When MOD=1 and MC=1 prescaler operated in divide-by-3 for the entire input cycles and division ratio of 48 (N+l) is performed. When MOD=1 and MC=0 divideby-2 is selected for entire input clock cycles for prescaler and the division ratio of 47(N) is performed. N and N+l are given by N = ((AD -1) * (N1 + 1)) + (1 * N1) = 47 N + 1 = (AD * (N1 + 1)) = 48
Fig 5: Programmable (P) Counter
6 .RESULTS AND CONCLUSION TABLE I PRESCALAR FREQUENCY DIVIDE RATIOS
1) When Sel='0': When Sel='0' the output from NAND2 gate is given to the prescaler and the multimodulus prescaler selects 32/33 mode and the division ratio is controlled by MOD signal. When MOD=1 the output from NAND2 gate switches to logic' 1 ' and the prescaler operates in divide-by-2 for entire operation. i.e., now division ratio of 32 (N) is performed. Similarly when MOD = 0, MC remains high for first 30 input clock cycles and goes low for 3 input clock
In order to get 64/65/78/79 clock cycles we need to operate 4/5 prescaler by making the control signal sel of second MUX to ‘1’.To get 32/33/47/48 prescaler, the second MUX should be equal to ‘0’ means the control signal sel of the second MUX should be equal to ‘0’ and to get 64/65/78/79 prescaler, the second MUX should be equal to ‘1’ means the control signal sel of the second MUX should be equal to ‘1’ 3) When Sel='0': When Sel='0' the output from NAND2 gate is given to the prescaler and the multimodulus prescaler selects 64/65 mode and the division ratio is controlled by MOD signal. When MOD=1 the output from NAND2 gate switches to logic' 1 ' and the prescaler operates in divide-by-2 for entire operation. i.e., now division ratio of 64 (N) is performed. Similarly when MOD = 0, MC remains high for first 62 input clock cycles and goes low for 3 input clock cycles. Thus division ratio of 65(N+ 1) is performed. N and N+ 1 are given by N = (AD * N1) = 64 N + 1 = ((AD -1) * N1) + (1 * (N1 + 1)) = 65
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ISBN : 978 - 1502851550
4) When Sel=’l’: When Sel=l, the inverted output from NAND2 gate is given to the input of 2/3 prescaler and multimodal’s prescaler operates in 78/79 mode. MOD signal controls the division ratio. When MOD=1 and MC=1 prescaler operated in divide-by-3 for the entire input cycles and division ratio of 79 (N+l) is performed. When MOD=1 and MC = 0 divideby-2 is selected for entire input clock cycles for prescaler and the division ratio of 78(N) is performed. N and N+l are given by N = (( AD -1) * (N1 + 1)) + (1 * N1) = 78 N + 1 = (AD * (N1 + 1)) = 79 The results are shown below: DIVIDE BY 32/33/47/48
PRESCALER 2/3
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DIVIDE BY 64/65/78/79
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Proceedings of International Conference On Current Innovations In Engineering And Technology
ISBN : 978 - 1502851550
7. CONCLUSION In this paper a simple approach for the low power multiband clock distribution using single phase clock distribution for Wireless Local Area Networks frequency synthesizer is presented. In this project, a wideband 2/3 or 4/5 prescaler is verified by the design of modified wide band multimodulus 32/33/47/48 or 64/65/78/79 prescaler. A dynamic logic multiband flexible integer N divider is designed which uses the wide band 2/3 prescaler, multimodulus 32/33/47/48 or 64/65/78/79 prescaler. The technique for low power fully programmable divider using design of reloadable bit cells for P and S Counter is given. P and S counters can be programmed accordingly for the required bands of frequencies, so that it provides solution to the low power PLL synthesizers for Bluetooth, Zigbee, IEEE 802.15.4 and IEEE 802.11 a/b/g WLAN applications with variable channel spacing. In this paper we worked on the four modes like 32/33, 47/48, 64/65 and 78/79 prescaler. The future work will be combining wide band 2/3 prescaler, 4/5 prescaler and 8/9 prescaler to provide six modes of operations like 32/33, 47/48, 64/65, 78/79, 128/129 and 143/144. This means a wide band 2/3 or 4/5 or 8/9 prescaler is verified by the design of multimodulus 32/33/47/48 or 64/65/78/79 or 128/129/143/144 prescaler in future work. So future flexible divider controls more number of frequency bands. REFERENCES
[4] L. Lai Kan Leung et al., “A 1-V 9.7-mW CMOS Frequency synthesizer for IEEE 802.11a transceivers,” IEEE Trans. Microwind. Theory Tech., vol. 56, no. I, pp. 39-48, Jan. 2008. [5] M. Alioto and G. Palumbo, Model and Design of Bipolar and MOS Current-Mode Logic Digital Circuits. New York: Springer, 2005. [6] Y. Jorgen etc all, "A true single-phase-clock Dynamic CMOS circuit technique," IEEE J. SolidState Circuits, vol. 24, no. 2, pp. 62-70, Feb. 1989. [7] S. Pellerano etc, “A 13.5-mW 5 GHz frequency synthesizer with dynamic-logic frequency divider,” IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 378383, Feb. 2004 [8] V. K. Manthena et al., “A low power fully programmable J MHz resolution 2.4 GHz CMOS PLL frequency synthesizer,” in Proc. IEEE Biomed. Circuits Syst. Conf, Nov. 2007.pp 187-19. [9] X.P.Y u et al., “Design and optimization of the extended true single phase clock based prescaler”, IEEE Trans. Microw. Theory Tech., vol.56, no. 11, pp.3828-3835, Nov.2006. [10] X.P.Y u et al., “Design of a low power wideband high resolution programmable frequency divider”, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.13, no. 9, pp.1098-1103, Sep.2005.
[1] Vamshi Krishna Manthena, Manh Anh Do, Chirn Chye Boon, and Kiat Seng Yeo “A Low-Power Single-Phase Clock Multiband Flexible Divider” , IEEE transactions on very large scale integration (VLSI) systems, vol. 20, no. 2, February 2012. [2] H.R.Rategh et al., “A CMOS frequency synthesizer with an injected locked frequency divider for 5-GHz wireless LAN receiver,” IEEE J. SolidState Circuits, vol. 35, no. 5, pp. 780-787, May 2000. [3] P. Y. Deng et al., “A 5GHz frequency synthesizer with an injection locked frequency divider and differential switched capacitors,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 2, pp. 320326, Feb. 2009.
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ISBN : 978 - 1502851550
DESIGN AND IMPLEMENTATION OF MULTIPLE SIC VECTORS THEORY AND APPLICATION IN BIST SCHEMES N.Seethamma 1, V.Srinivasarao 2 1
2
M.Tech Student, Department of ECE, Shri Vishnu Engineering College for women, Bhimavaram Associate Professor, Department of ECE, Shri Vishnu Engineering College for women, Bhimavaram 1 Mail id: sitanelluri@gmail.com
ABSTRACT Test pattern generators are the vital blocks in Built-in self-test. In this paper a new approach which is multiple single input changes (MSIC) is used to generate the random patterns for applying it to CUT for testing applications. A reconfigurable Johnson counter and a scalable SIC counter are developed to generate a class of minimum transition sequences. The proposed TPG is flexible to both the test-perclock and the test-per-scan schemes. The generated patterns based on this approach are applied to the ISCAS benchmark designs. Control unit is used to control all the operations. Mainly control unit will do configuration of CUT in test mode/Normal mode, feed seed value to TPG and TRA. Simulation results show the functionality of the pattern generator. The synthesis is carried out on XILINX ISE and the simulation is performed on the ISE simulator. The obtained test results are comparing with the primary one to demonstrate the target fault coverage. Index Terms—Built-in self-test (BIST), low power, single-input change (SIC), test pattern generator (TPG).
applications require low power dissipation VLSI circuits. The power dissipation during test mode is 200% P more than in normal mode. Hence it is important aspect to optimize power during testing. Power optimization is one of the main challenges. To reduce the power consumption generates the test vectors with less number of transitions. Generally the random sequence at the output of the flip-flops can be used as a test pattern. Flip-flop’s connected in series with feedback taps defined by the generator polynomial. The seed value is loaded into the outputs of the flip-flops. The only input required to generate a random sequence is an external clock where each clock pulse can produce a unique pattern at the output of the flip-flops. This test pattern is run on the circuit under test for desired fault coverage. The number of inputs required by the circuit under test must match with the number of flip-flop outputs. The power consumed by the chip under test is a measure of the switching activity of the logic inside the chip which depends largely on the randomness of the applied input
I.INTRODUCTION
stimulus. Reduced correlation between the successive
The main challenging areas in VLSI are
vectors of the applied stimulus into the circuit under
performance, cost, and power dissipation. The
test can result in much higher power consumption by
demand
and
the device than the budgeted power. A new low
communications system are increasing rapidly. These
power pattern generation technique is implemented
for
portable
computing
devices
using a multiple single input change method.
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A) Need for using BIST technique
ISBN : 978 - 1502851550
II. PROPOSED MSIC-TPG SCHEME
Today’s highly integrated multi-layer boards with fine-pitch ICs are virtually impossible to be accessed physically for testing. Traditional board test methods which include functional test, only accesses the board's primary I/Os, providing limited coverage and poor diagnostics for board-network fault. In circuit testing, another traditional test method works by physically accessing each wire on the board via costly "bed of nails" probes and testers. To identify reliable testing methods which will reduce the cost of test equipment, a research to verify each
This section discuss about the introduction of MSIC and how the test patterns are generated using this scheme. First, the SIC vector is decompressed to its multiple code words. Meanwhile, the generated code words will bit-XOR with a same seed vector in turn. Hence, a test pattern with similar test vectors will be applied to all scan chains. The proposed MSIC-TPG consists of an SIC generator, a seed generator, an XOR gate network, and a clock and control block.
VLSI testing problems has been conducted. The major problems detected so far are as follows:
Test generation problems Gate to I/O pin ratio
B)
Test Generation Problems
The large number of gates in VLSI circuits has pushed computer automatic-test-generation times to weeks or months of computation. The numbers of test patterns are becoming too large to be handled by an external tester and this has resulted in high computation
costs and has
outstripped reasonable available time for production testing. C)
The Gate to I/O Pin Ratio Problem As ICs grow in gate counts, it is no longer
true that most gate nodes are directly accessible by one of the pins on the package. This makes testing of internal nodes more difficult as they could neither no longer be easily controlled by signal from an input pin (controllability) nor easily observed at an output pin (observe ability). Pin counts go at a much slower rate
than
gate
counts,
which
worsens
the
Fig.1(a) Symbolic simulation of an MSIC pattern for scan chains. (b) Symbolic representation of an MSIC pattern.
controllability and observe ability of internal gate nodes.
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generate an SIC sequence in time domain.As shown
A) Test Pattern Generation Method
in Fig. 2(a), it can operate in three modes. Assume there are m primary inputs (PIs) and M scan chains in a full scan design, and each scan chain
1) Initialization: When RJ_Mode is set to 1 and Init is
has l scan cells. Fig. 1(a) shows the symbolic
set to logic 0, the reconfigurable Johnson counter will
simulation for one generated pattern. The vector
be initialized to all zero states by clocking CLK2
generated by an m-bit LFSR with the primitive
more than l times.
polynomial
can
be
expressed
as
S(t)
=
S0(t)S1(t)S2(t), . . . , Sm−1(t) (hereinafter referred to as the seed), and the vector generated by an l-bit Johnson counter can be expressed as J (t) =
2) Circular shift register mode: When RJ_Mode and Init are set to logic 1, each stage of the Johnson counter will output a Johnson codeword by clocking CLK2 l times.
J0(t)J1(t)J2(t), . . . , Jl−1(t).In the first clock cycle, J = J0 J1 J2, . . . , Jl−1 will bit-XOR with S = S0S1S2, . .
3) Normal mode: When RJ_Mode is set to logic 0,
. , SM−1, and the results X1Xl+1X2l+1, . . . ,
the reconfigurable Johnson counter will generate 2l
X(M−1)l+1 will be shifted into M scan chains,
unique SIC vectors by clocking CLK2 2l times.
respectively. In the second clock cycle, J = J0 J1 J2, . . . , Jl−1 will be circularly shifted as J =Jl−1 J0 J1, . . . , Jl−2, which will also bit-XOR with the seed S = S0S1S2, . . . , SM−1. The resulting X2Xl+2X2l+2, . . . , X(M−1)l+2 will be shifted into M scan chains, respectively. After l clocks, each scan chain will be fully loaded with a unique Johnson codeword, and seed S0S1S2, . . . , Sm−1 will be applied to m PIs. Since the circular Johnson counter can generate l unique Johnson codewords through circular shifting a Johnson vector, the circular Johnson counter and XOR gates in Fig. 1 actually constitute a linear sequential decompressor.
B) Reconfigurable Johnson Counter
C) Scalable SIC Counter When the maximal scan chain length l is much larger than the scan chain number M, we develop an SIC counter named the “scalable SIC counter.” As shown in Fig. 2(b), it contains a k-bit adder clocked by the rising SE signal, a k-bit subtractor clocked by test clock CLK2, an M-bit shift register clocked by test clock CLK2, and k multiplexers. The value of k is the integer of log2(l − M). The waveforms of the scalable SIC counter are shown in Fig. 2(c). The k-bit adder is clocked by the falling SE signal, and generates a new count that is the number of 1s (0s) to fill into the shift register. As shown in Fig. 2(b), it can operate in three modes.
According to the different scenarios of scan length, this paper develops two kinds of SIC generators to generate Johnson vectors and Johnson codewords, i.e., the reconfigurable Johnson counter and the scalable SIC counter.For a short scan length,
1) If SE = 0, the count from the adder is stored to the k-bit subtractor. During SE = 1, the contents of the kbit subtractor will be decreased from the stored count to all zeros gradually.
we develop a reconfigurable Johnson counter to
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2) If SE = 1 and the contents of the k-bit subtractor
stage conventional LFSR, and operates at low
are not all zeros, M-Johnson will be kept at logic 1
frequency CLK1. The test procedure is as follows.
(0). 1) The seed generator generates a new seed by 3) Otherwise, it will be kept at logic 0 (1). Thus, the
clocking CLK1 one time.
needed 1s (0s) will be shifted into the M-bit shift register by clocking CLK2 l times, and unique Johnson codewords will be applied into different scan chains.
2) The Johnson counter generates a new vector by clocking CLK2 one time. 3) Repeat 2 until 2l Johnson vectors are generated. 4) Repeat 1–3 until the expected fault coverage or test length is achieved.
E) MSIC-TPGs for Test-per-Scan Schemes The MSIC-TPG for test-per-scan schemes is illustrated in Fig. 3(b). The stage of the SIC generator is the same as the maximum scan length, and the width of a seed generator is not smaller than the scan chain number. The inputs of the XOR gates come from the seed generator and the SIC counter and their outputs are applied to M scan chains, respectively. The outputs of the seed generator and XOR gates are applied to the CUT’s PIs, respectively. The test procedure is as follows. 1) The seed circuit generates a new seed by clocking Fig.2. SIC generators. (a) Reconfigurable Johnson counter (b) Scalable SIC counter (c) Waveforms of the scalable SIC counter.
CLK1 one time. 2) RJ_Mode is set to 0. The Reconfigurable Johnson counter will operate in the Johnson counter mode and
D) MSIC-TPGs for Test-per-Clock Schemes The MSIC-TPG for test-per-clock schemes is
generate a Johnson vector by clocking CLK2 one time.
illustrated in Fig. 3(a). The CUT’s PIs X1 − Xmn are
3) After a new Johnson vector is generated, RJ_Mode
arranged as an n ×m SRAM-like grid structure. Each
and Init are set to 1. The reconfigurable Johnson
grid has a two-input XOR gate whose inputs are
counter operates as a circular shift register, and
tapped from a seed output and an output of the
generates l codewords by clocking CLK2 l times.
Johnson counter. The outputs of the XOR gates are
Then, a capture operation is inserted.
applied to the CUT’s PIs. A seed generator is an m-
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4) Repeat 2–3 until 2l Johnson vectors are generated. 5) Repeat 1–4 until the expected fault coverage or test length is achieved.
ISBN : 978 - 1502851550
error. Tapping can be taken according to the specification but as per taping change the TPG output generate will also change and as we change in number of flip-flop the probability of repetition of random number will reduce. The initial value loading to the TPG is known as seed value. Classification of test strategies: 1. Weighted Pseudorandom: Testing: In weighted pseudorandom testing, pseudorandom patterns are applied with certain 0s and 1s distribution in order to handle the random pattern resistant fault undetectable by the pseudorandom testing. Thus, the test length can be effectively shortened. 2. Pseudo exhaustive Testing: Pseudo exhaustive testing divides the CUT into several smaller sub circuits and tests each of them exhaustively. All detectable flaws within the sub circuits can be detected. However, such a method involves extra design effort to partition the circuits and deliver the test patterns and test responses. BIST is a set of structured-test techniques for combinational and sequential logic, memories, multipliers, and other embedded logic blocks. BIST is the commonly used design technique for self testing of circuits.
Fig 3. MSIC-TPGs for (a) test-per-clock and (b) test-per-scan schemes.
III. STRATEGY DESCRIPTION
3. Pseudorandom Testing: Pseudorandom testing involves the application of certain length of test patterns that have certain randomness property. The test patterns are sequenced in a deterministic order.
The MSIC Test pattern generator architecture internally consists of a control circuit, seed circuit,
The test length and the contents of the patterns are used to impart fault coverage.
SIC counter, scan chain and MISR modules. Here the control unit is used to initiate the seed value and
4. Exhaustive Testing: Exhaustive testing involves
enable the counter and to control the scan design.
the application of all possible input combinations to
CUT is the circuit or chip in which we are going to
the circuit under test (CUT). It guarantees that all
apply BIST for testing stuck at zero or stuck at one
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detectable faults that divert from the sequential behavior will be detected. The strategies are often
IV.RESULTS
applied to complex and well isolated small modules such as PLAs.
WAVEFORM FOR 4BIT MISC
5. Stored Patterns: Stored-pattern approach tracks the pre generated test patterns to achieve certain test goals. It is used to enhance system level testing such as the power-on self test of a computer and microprocessor
functional
testing
using
micro
programs. BIST is a design for testability (DFT) technique in which testing is carried out using built – in hardware features. Since testing is built into the hardware, it is faster and efficient. The BIST architecture needs three additional hardware blocks such as a pattern generator, a response analyzer and a
WAVEFORM FOR 8 BIT LOW POWER LFSR
test controller to a digital circuit. For pattern generators, we can use either a ROM with stored patterns, or a counter or a linear feedback shift register (LFSR).A response analyzer is a compactor with stored responses or an LFSR used as a signature analyzer. A controller provides a control signal to activate all the blocks.The circuit introduces more switching activities in the circuit under test (CUT)during
test
than
that
during
normal
operation[5].It causes excessive power dissipation and results in delay penalty into the design[6].
WAVEFORM FOR 8 BIT MSIC
Using BIST Technique the portability can be achieved very easily than the Automatic Test pattern generator. Generally the Automatic Test pattern generators are used externally while a BIST uses internally. Due to advantages of BIST the concept of ATPG is vanishes but it also has its own advantages.
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Schematics:
ISBN : 978 - 1502851550
between the successive bits. The simulation results shows that how the patterns are generated for the applied seed vector. This paper presents the implementation of MSIC approach based pattern generator
with
regard
to
verilog
language.
Synthesizing and implementation (i.e. Translate, Map and Place and Route) of the code is carried out on Xilinx - Project Navigator, ISE suite. The power reports shows that the proposed low power lfsr consumes less power during testing by taking the benchmark circuit. In future there is a chance to RTL Schematics:
reduce the power somewhat more by doing modifications in the proposed architecture.
REFERENCES [1] Feng Liang, Luwen Zhang, Shaochong Lei, Guohe Zhang, Kaile Gao, and Bin Liang “Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes” in IEEE transactions on very large scale integration (vlsi) systems, Vol. 21, No. 4, April 2013 Technology schematics:
[2] Y. Zorian, “A distributed BIST control scheme for complex VLSI devices,” in 11th Annu. IEEE VLSI Test Symp. Dig. Papers, Apr. 1993,pp. 4–9. [3] A. Abu-Issa and S. Quigley, “Bit-swapping LFSR and scan-chain ordering: A novel technique for peak- and average-power reduction in scan-based BIST,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 28, no. 5, pp. 755–759, May 2009. [4] P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, J. Figueras,S. Manich, P. Teixeira, and M. Santos, “Low-energy BIST design: Impact of the LFSR TPG parameters on the weighted switching activity,”in Proc. IEEE Int. Symp. Circuits Syst., vol. 1. Jul. 1999, pp.110–113.
V. CONCLUSION The proposed approach shows the concept of reducing the transitions in the test pattern generated.
[5] S. Wang and S. Gupta, “DS-LFSR: A BIST TPG for low switching activity,” IEEE Trans. Comput.Aided Design Integr. Circuits Syst.,vol. 21, no. 7, pp. 842–851, Jul. 2002.
The transition is reduced by increasing the correlation
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[6] F. Corno, M. Rebaudengo, M. Reorda, G. Squillero, and M. Violante,“Low power BIST via non-linear hybrid cellular automata,”in Proc. 18th IEEE VLSI Test Symp., Apr.–May 2000, pp.29–34. [7] P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, and H. Wunderlich,“A modified clock scheme for a low power BIST test pattern generator,” in Proc. 19th IEEE VTS VLSI Test Symp., Mar.–Apr. 2001,pp. 306–311. [8] D. Gizopoulos, N. Krantitis, A. Paschalis, M. Psarakis, and Y. Zorian, “Low power/energy BIST scheme for datapaths,” in Proc. 18th IEEE VLSI Test Symp., Apr.–May 2000, pp. 23–28. [9] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch,“A gated clock scheme for low power scan testing of logic ICs or embedded cores,” in Proc. 10th Asian Test Symp., Nov. 2001, pp.253–258.
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A New Multilevel Inverter Topology for Four pole Induction motor Drive P.JAYANTH
D.SRINIVASA RAO
PG Scholar Department of Electrical and Electronics Engineering, Gudlavalleru Engineering college, JNTU K Gudlavalleru, A.P, India. e-mail: mr.p.jayanth@gmail.com
Associate Professor Department of Electrical & Electronics Engineering, Gudlavalleru Engineering college, JNTU K Gudlavalleru, A.P, India. e-mail: dsrinivasarao1993@gmail.com
Abstract- In this paper a new multilevel inverter topology
is proposed for the control of the induction motor. This multilevel inverter uses a single DC link. The identical voltage profile windings in induction motor stator are disconnected and each winding is separated into two parts. These parts are fed with two two-level inverters from both sides. In order to generate five level voltages in induction motor stator windings two two two-level inverters are required. All the inverters are fed with single DC link with magnitude . The problem with the use of common DC link for all the inverters is, common mode currents will pass through the induction motor stator windings. To avoid this problem sine triangular pulse width modulation is applied to all two level inverters. All the harmonics are shifted to switching frequency which will have less impact on the motor stator windings. Total harmonic distortion is also reduced by using this multilevel inverter topology. Due to fewer harmonics, it gives near sinusoidal output voltage. The efficiency of the system is also improved. In this paper the proposed multilevel inverter, its operation, modulation method, simulation results with SIMULINK/MATLAB are shown. Keywords- Sine triangular pulse width modulation method, Total harmonic distortion (THD).
I.
INTRODUCTION
From the past few decades multilevel inverters are widely used for the control of the induction motor drives. Because of the lower harmonics, reduced stresses on the power electronic devices, improved efficiency of the drive and etc [1]-[3].conventional multilevel inverter configurations are diode clamped [4], flying capacitor [5] and cascade H-bridge [6]. The disadvantages of using these conventional structures are, more number of diodes are required in diode clamped inverter, voltage balancing problem in flying capacitor inverter and more number of DC sources in cascade Hbridge structure. These structures are advantageous up to 3levels only. Increasing the number of levels increase circuit complexity, cost and size. The alternative for this is open end winding induction motor fed with 2 level inverters [7].
In the open end winding scheme of induction motor, windings are fed with two level inverters to get three level inverter topology. In the open end winding scheme as the number of levels increase, conventional multilevel inverters have to be used or the inverters have to be cascaded on both sides of the induction motor drive [8]. In this paper a new multilevel inverter topology is proposed for the control of the induction motor. This topology produces five level voltages at the output by using four conventional two level inverters. In this topology the windings are separated and each part of the winding is fed with two two-level inverters from both sides of the parts. So in order to generate five level voltages on motor phase windings four two level inverters are used. These inverters use common DC link voltage with magnitude 4 . Sine triangular pulse width modulation is used in this inverter topology. II.
INDUCTION MOTOR
The three phase induction motor is the most widely used alternating current (AC) motor in industry. Induction motors are popular because of their simplicity, good power factor, rugged construction, reliability and simple operation. Its characteristics are also similar to direct current shunt motor. For a given output rating the physical size of the induction motor is relatively small as compared to other types of motors. The efficiency of the induction motor is also high as there are no frictional losses and maintenance is simple. Induction motor mainly consists of stator and rotor. Even though it is equipped with stator and rotor it is a singly excited machine. In this machine there is no electrical connection between stator and rotor. Construction: In this proposed scheme the three phase stator winding is connected and each phase winding is separated into two halves. This scheme is known as open ended winding of induction motor. These separated windings are supplied from the multilevel inverters to produce rotating magnetic field.
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The rotor can be either squirrel cage or slip ring. The rotor consists of a cylindrical laminated iron core with slots around the core. These slots carry the rotor bars. Most of the motors uses squirrel cage rotor because of its robust and simple construction. In the proposed scheme stator three phase winding is disconnected and each winding is separated into two parts. But operating principle of this motor is same as that of the conventional induction motor. As supply is given to the stator windings currents will flow through stator windings and alternating flux will be produced. This alternating flux will revolve at synchronous speed. As the rotor conductors are short circuited, this flux will cut the short circuited rotor conductors and electromagnetic force (EMF) will be induced. This EMF causes currents will flow in the rotor. This induced currents causes alternating flux is generated and lags the stator flux. The interaction between two magnetic fields creates mechanical which is necessary to run the rotor.
ISBN : 978 - 1502851550
mechanical load applied to the motor is increased, at full load, then there will be drop in speed until the developed torque matches with the load torque. And the motor runs at constant speed when both the torque are equal. The motor will be stop whenever the load torque exceeds the breakdown torque of the motor. Depending upon the design of the motor the breakdown torque varies but it is in the range of 200 to 300 percent of full load torque in standard squirrel cage motors. In the operating region the speed torque characteristics of induction motors are similar to DC shunt motors. III.
DYNAMIC MODELLING OF INDUCTION MOTOR
There are two sets of identical voltage profile windings in the conventional four pole induction motor. These windings are connected in series which is shown in fig. 2.
Speed-torque characteristics: The speed-torque characteristics of the induction motor are shown in fig 3. For any load torque there are two operating points B and D. The operating point B is unstable.
Fig. 2. Induction motor stator winding general arrangement
For the proposed inverter these windings are disconnected and each winding is separated into two parts as shown the fig. 3.
Fig. 1. Speed-torque characteristics of induction motor
Because if there is any requirement of speed rise causes the developed torque increases then the load torque which further raises speed. So, at this point the operation of the induction motor is not good. The operating point D is stable because at this point any tendency of speed rise will be opposed by decrease in developed torque. Similarly if there is any fall in speed then there will be increase in developed torque to bring the motor to operating point D. The maximum torque at point D is called breakdown torque or pull in torque. Thus the region AC is called unstable region and CE is called as stable region. If the
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Fig. 3.Arrangement for the proposed inverter
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The stator resistance, magnetizing inductance and stator leakage inductance of each part is equal to half of the stator winding because of the separated equal windings. The voltage equations for the stator winding is given by −
=
∗
+
∗
∗ −
=
∗
−
∗
∗
∗
+
− (1)
∗
−
∗
∗
−
∗ ∗ (2) The sum of the voltage across the two separated parts is equal to the total voltage across the winding and is given by )+( ) =( − − (3) The motor voltage can be obtained by substituting equations (1) and (2) in equation (3) 1 1 = ∗ + ∗ − ∗ ∗ − ∗ ∗ 2 2 (4) Similarly the voltage equations for the remaining two phases of induction motor is given by 1 1 = ∗ + ∗ − ∗ ∗ − ∗ ∗ 2 2 (5) 1 1 = ∗ + ∗ − ∗ ∗ − ∗ ∗ 2 2 (6) In order to solve the voltage equations in dq0 frame basic equations of induction motor can be used. = ∗ + ∗ + ∗ (7) =
∗
+
∗
+
∗
(8)
=
∗
−
∗
+
∗
(9)
= =
=
∗
∗
+( −
∗ =
+
∗ )∗
−( − ∗
+
(10)
)
∗
+ ∗ +
∗
∗
(11) (12) (13)
Flux linkage equations of induction motor are given by =
∗
+
∗
(14)
=
∗
+
∗
(15)
= =
∗ ∗
(16) +
∗
(17)
=
∗
ISBN : 978 - 1502851550
+
∗
(18)
= ∗ (19) In terms of dq0 axis currents the expression for the electromagnetic torque is given by = ∗ ∗ ∗ ∗ + ∗ (20) In terms of torque rotor speed of the motor is given by =
∗
∗(
−
)
(21)
Where d : direct axis, q : quadrature axis, s : stator variable, r : rotor variable, Vqs,Vds : q and d-axis stator voltages, Vqr,Vdr : q and d-axis rotor voltages, rr : rotor resistance, rs : stator resistance, Lls : stator leakage inductance, Llr : rotor leakage inductance, iqs,ids : q and d-axis stator currents, iqr,idr : q qnd d-axis rotor currents, p : number of pole, J : moment of inertia, Te : electrical output torque, TL : load torque. There is no difference between normal induction motor and disconnected induction motor which can be observed from the equations (4), (5) and (6). IV.
PROPOSED FIVE LEVEL INVERTER
For the four pole induction motor drive five level inverter topology is proposed. By using four two-level inverters the available four terminals which are the result of the disconnection of two identical voltage profile winding coils are supplied and it is shown in fig. 4. A single DC link with magnitude 4 supplies all two-level inverters. In the fig 3 the first inverter are S11 to S16 , the second inverter switches are S21 to S26, the third inverter switches are S31 to S36 and the fourth inverter switches are S41 to S46. These switches have blocking voltage of Vdc⁄4. The complementary switches of the first inverter are (S11, S12), (S13, S14), (S15, S16). The complementary switches of the second inverter are (S21, S22) , (S23, S24), (S25, S26). The complementary switches of the third inverter are (S31, S32), (S33, S34), (S35, S36). The complementary switches of the fourth inverter are (S41, S42), (S43, S44), (S45, S46). During the voltage levels , 0,− in order to isolate the middle inverters inverter-2 and inverter-3 the auxiliary switches S1 to S6 are required
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TABLE I SWITCHING COMBINATIONS FOR GENERATING FIVE VOLTAGE LEVELS
TABLE II COMPARISON BETWEEN CONVENTIONAL AND PROPOSED INVERTER
Fig. 4. Proposed inverter
The unequal voltage will be distributed across the motor phase winding if the switches S1 to S6 are short circuited ,which results in unequal flux distribution. The table-I shows the possible switching combinations which are used to generate five voltage levels across motor phase-A winding. The table-II shows the comparison between proposed and conventional multilevel inverter topologies in terms of power electronic switches, clamping diodes, isolated voltage sources, capacitor banks and bi-directional switching devices. Same numbers of switching devices are required for all the topologies.
From the table II it is observed that clamping diodes are not required in proposed inverter whereas 18 diodes are required for neutral point converter (NPC). It requires single isolated voltage source whereas cascade H-bridge requires 6 isolated voltage source. 4 capacitor banks are required for NPC and 18 for flying capacitor (FC). The proposed converter does not require a capacitor bank.
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V.
MODULATION STRATEGY
Multi carrier based pulse width modulation techniques are applied to multi level inverters. The most popular and easiest multi carrier pulse width modulation technique is sine triangular PWM. In this PWM triangular waves are used as carrier waves and sinusoidal wave is used as reference wave. The number of carrier waves depends upon the number levels at the output. The relation between voltage levels at the output and carrier waves is given by No.of carrier waves= no.of levels at the output-1 In this proposed inverter five levels appear at the output. so the number of carrier waves used are 4. Fig. 5 shows the sine triangular PWM for the proposed multi level inverter topology.
VI.
ISBN : 978 - 1502851550
SIMULINK/MATLAB CIRCUITS
The proposed five level inverter is simulated using MATLAB/SIMULINK. Sine triangular pulse width modulation is used to generate gating pulses for the power electronic switching devices which are used in the inverter. Four triangular carrier waves of frequency 10 kilo hertz are compared with sine wave of frequency 50hertz. Four inverters are supplied with single DC link of magnitude . The simulation circuit with open ended stator winding is shown in fig 6.
Fig. 5. Sine triangular PWM
The table-III shows the pattern which is followed for generating five voltage levels at the output. TABLE III COMPARISON BETWEEN MODULATING AND CARRIER SIGNALS Fig. 6.Simulation circuit of proposed five level inverter with open ended winding
The proposed five level inverter output voltage for different modulation index values is shown in fig 7 and fig 8.
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torque or maximum torque. Then torque decrease with further increase in speed.
Fig. 7. Output voltage for modulation index 0.2,0.4 Fig. 10. Speed-torque characteristics of induction motor
VII.
Fig. 8. Output voltage for modulation index 0.6, 0.8
The simulation circuit of proposed inverter is with induction motor is shown in fig 9.
CONCLUSION
In this paper three phase induction motor which is fed from the five level inverter is presented. The stator winding of induction motor is disconnected and each phase is separated into two halves. The identical voltage profile windings are fed with four two-level inverters to generate five level voltages in the phase windings. Sine triangular pulse width modulation is applied to the proposed inverter to generate gating pulses for switching devices. These four inverters are fed with common DC link with magnitude . Speed torque characteristics are observed. The important feature of this topology is that, it will be operated as three level inverter if the middle inverter switches are failed. REFERENCES
Fig.9.Proposed inverter with induction motor.
The speed torque characteristics of the induction motor are shown in fig 10. As speed increases torque also increase upto break down
[1] N.kiran Kumar, K.Sivakumar,” A Five level Inverter topology for a four Pole Induction Motor Drive with single DC Link” IEEE conference 2012 [2] J. Rodriguez, S. Bernet, B. Wu, J. O. Pontt, and S. Kouro, “Multilevel voltage-source-converter Topologies for Industrial Medium-voltage Drives,” IEEE Transactions on Industrial Electronics., vol. 54, no. 6, pp. 2930–2945, Dec. 2007 [3] K. Sivakumar, Anandarup Das, Rijil Ramchand, Chintan Patel, and K.Gopakumar, “A Five-Level Inverter Scheme for a Four-Pole Induction Motor Drive by Feeding the Identical Voltage-Profile Windings From Both Sides”, IEEE Transactions on industrial electronics, vol. 57, No. 8, August 2010, 2776-2784. [4] P. P. Rajeevan, K. Sivakumar, Chintan Patel, Rijil Ramchand, and K. Gopakumar “A Seven-Level Inverter Topology for Induction Motor Drive Using Two-Level Inverters and Floating Capacitor Fed H-Bridges IEEE Transactions on power electronics, VOL. 26, NO. 6, JUNE 2011. [5] Mohan M. Renge and Hiralal M. Suryawanshi, “Five-Level Diode clamped Inverter to eliminate Common Mode Voltage and Reduced dv/dt in Medium voltage rating Induction Motor Drives, IEEE Transactions on Power Electronics, vol. 23, no.4, pp. 1598–1607 July 2008. [6] Mostafa Khazraei, Hossein Sepahvand, Keith A. Corzine, and Mehdi Ferdowsi, “Active Capacitor Voltage Balancing in Single-Phase FlyingCapacitor Multilevel Power Converters” IEEE Transactions on Industrial Electronics, VOL. 59, NO. 2, FEBRUARY 2012.
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[7] Fernanda Carnielutti, Humberto Pinheiro, and Cassiano Rech, “Generalized Carrier-Based Modulation Strategy for Cascaded Multilevel Converters Operating Under Fault Conditions” IEEE Transactions on Industrial Electronics, VOL. 59, NO. 2, FEBRUARY 2012. [8] K. Sivakumar Anandarup Das Rijil Ramchand Chintan Patel K Gopakumar, “A Hybrid Multilevel Inverter Topology for an Open-End Winding Induction-Motor Drive Using Two-Level Inverters in Series With a Capacitor-Fed H-Bridge Cell” IEEE Transactions on Industrial Electronics, Vol. 57, NO. 11, November 2010. [9] V. T. Somasekhar, K. Gopakumar, M. R. Baiju, Krishna K. Mohapatra and L. Umanand “A Multilevel Inverter System for an Induction Motor With Open-End Windings” IEEE Transactions on Industrial Electronics, VOL. 52, NO. 3, JUNE 2005.
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Vlsi Implementation Of Efficient Convolutional Encoder And Modified Viterbi Decoder Anaparthi Sunanda1 PG Student [VLSID], Department of ECE1 Shri Vishnu Engineering College for Women1 Bhimavaram, India. Email-id:sunandaanaparthi18@gmail.com1
Abstract_-In digital communication Convolution encoder and Viterbi decoder are widely used due to the excellent error control performance. The most popular communications decoding algorithm, the Viterbi Algorithm (VA), requires an exponential increase in hardware complexity to achieve greater decode accuracy. The path associated with the input bits are large, hence it needs to implement the path memory with lesser hardware for lesser computations to decode the original data. When the decoding process uses the Modified Viterbi Algorithm (MVA) computations are reduced to 50% thereby reduction in the hardware utilization, which follows the maximum-likelihood path. This work focuses on the realization of convolutional encoder and modified Viterbi decoder (MVD) with a constraint length, K of 3 and a code rate (k/n) of 1/2 using Field Programmable Gate Array (FPGA) technology. Keywords--Convolutional Encoder, Modified Viterbi Algorithm (MVA), Verilog HDL, FPGA
I
INTRODUCTION
Convolutional coding with Viterbi decoding [1] is a powerful method for forward error correction. In today’s digital communications, the reliability and efficiency of data transmission is the most concerning issue for communication channels. Error correction technique plays a very important role in communication systems. The error correction technique improves the capacity by adding redundant information for the source data transmission. All communication channels are subject to the additive noise. Forward error correction (FEC) techniques are used in the transmitter to encode the data stream and receiver to detect and correct bits in errors, hence minimize the bit error rate (BER) to improve the performance. RS decoding algorithm complexity is relatively low and can be implemented in hardware at very high data rates. It seems to be an ideal code
Susmitha Remmanapudi2 Assistant Professor, Department of ECE2 Shri Vishnu Engineering College for Women2 Bhimavaram, India. Email-id:susmitha.in@gmail.com2 attributes for any application. However, RS codes perform very poorly in additive noise. Due to weaknesses of using the block codes for error correction in useful channels, another approach of coding called convolutional coding had been introduced in 1955 [1]. Convolutional encoding with Viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by additive white Gaussian noise (AWGN) [2]noise. It operates on data stream to encode. It is simple and has good performance with high implementation cost. But the implementation requires the exponential increase in the area and power consumption to achieve increased decoding accuracy. So we introduce modified viterbi decoder with memory. Modified Viterbi [3], decoders are used to decode Convolutional codes. In most of real time applications like audio/video and recently in digital wireless communications, the Convolutional codes are used for error correction. It is very efficient and robust. The main advantage of Modified Viterbi Decoder is it has fixed decoding time and also it suites for hardware decoding implementation.
Figure: 1 Basic Block Diagram
II CONVOLUTIONAL ENCODER Convolutional codes are frequently used to correct errors in noisy channels. They have rather good
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correcting capability and perform well even on very bad channels (with error probabilities of about (10-3) [4]. Convolutional codes are extensively used in satellite communications. Although convolutional encoding is a simple procedure, decoding of a convolutional code is much more complex task.
ISBN : 978 - 1502851550
State diagram: This offers a complete description of the system. However, it shows only the instantaneous transitions. It is illustrate in the State table as fallows
Where A, B are outputs. Figure: 2 Convolutional encoder. Convolutional Encoder shown in Figure2 takes input data bit and gives out two bits. Convolutional encoding is a process of adding redundancy to a signal stream. To convolve the encode data; start with 2 memory registers, each holding 1 input bit. Registers start with a value of 0. The encoder has 2 modulo-2 adders which are implemented with a XOR gate. It generates 2 bit polynomials, one for each adder.
Figure: 4 State table for next state of convolutional encoder
A=m0 XOR m1 XOR m2 B=m0 XOR m2 The convolutional encoder is basically a finite state machine [5].The k bit input is fed to the constraint length K shift register and the n outputs are calculated from the generator polynomials by the modulo-2 addition. Encoder functions depending on the applied input, and then the corresponding state transition takes place. The function of encoder understood with the help of the following state diagram. These state diagrams generally implemented with the sequential circuits based on the constraint length [6] used at the transmitter side.
Figure: 5 State table for output symbols of convolutional encoder.
III. VITERBI ALGORITHM The Viterbi decoding algorithm is a decoding process for convolutional codes in memory-less noise channel [7]. The algorithm can be applied to a host of problems encountered in the design of communication systems. The Viterbi Algorithm (VA) finds the most-likelihood path transition sequence in a state diagram, given a sequence of symbols,
Figure:6 Block diagram of viterbi decoder. Figure: 3 State diagram of convolutional encoder.
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A Viterbi algorithm consists of the following three major parts: A. Branch metric calculation The first unit is called branch metric unit. Here the received data symbols are compared to the ideal outputs of the encoder from the transmitter and branch metric is calculated by performing the XOR operation, thereby counting the number of ones.
Figure: 7 Branch metric calculation
B. Path metric calculation For every encoder state, calculate a metric for the Survivor path ending in this state (a survivor path is a path with the minimum metric).it is per formed by Add Compare Select Unit. Add Compare Select The function of ACS is completing survivor paths and generating decision vector, and the whole computation process includes add operation, compare operation, and select operation. By analysis on accumulation process, can find that each branch metric value is non-negative. So the branch accumulation metric value is continually incremental, in case the accumulator overflows, so there is a normalization function. This function means that every time the accumulation metric value of each state must subtract the minimum of all accumulation metric values. The structure of ACS is shown in the Figure below.
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C. Trace back unit This step is necessary for hardware implementations that don't store full information about the survivor paths, but store only one bit decision every time when one survivor path is selected from the two. IV MODIFIED VITERBI ALGORITHM The average computation and path storage required by the MVA are reduced [3]. Instead of computing and retaining all 2K-1 possible paths, only those paths which satisfy certain cost conditions are retained for each received symbol at each state node here we have path memory to store the total path of the input and output. Survivor Path unit The survivor path unit stores the decisions of the ACS unit and uses them to compute the decoded output. The trace-back technique and the registerexchange approaches are two major techniques used for the path history management .The Trace back unit takes up less area but require much more time than the Register Exchange method.
Figure: 9 Survior path unit with path memory
In figure 9 the operation performed is the shortest path obtained from the local memory is stored in the trace back unit. Then it is compared with the shortest path from the global winner memory and the shortest is replaced in the global winner memory. V. SIMULATION OF VITERBI ALGORITHM The various modules of Convolutional encoder and Viterbi decoder in verilog HDL is implemented here. The whole process of convolutional encoder and Modified Viterbi decoder can be summarized as shown in the flowchart shown in figure10.
Figure: 8 Add Compare Select Unit.
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state, then based on the output and in accordance to the state diagram the next state is assigned.
B.
BRANCH METRIC UNIT
The branch metric and path metrics calculation is shown in the simulation figure 12 and figure 13 respectively.
Figure: 10 Flowchart of the convolutional encoder and viterbi decoder
VI. EXPERIMENTAL RESULTS The function of convolutional encoder and Viterbi decoder can be observed by manually in Isim simulator. The “clk“is the clock signal of whole system, and the reset is the reset signal of whole system. When the reset is set high, the convolution encoder and Viterbi decoder begin to work. The”inp” and “out” respectively stand for input signals to convolution encoder and output signals. The results are obtained as follows.
Figure.12. Simulation result of Branch Metric Unit.
In figure 12 the output obtained from the convolutional encoder is taken and XOR operation is performed and if the output is “1” counter status will be incremented by “1”. C.
PATH METRIC UNIT
In figure 13 the operation performed is, the output obtained from the branch metric unit are compared at each and every node and the node with highest metrics is obtained from the multiplexer.
A. CONVOLUTIONAL ENCODER
Figure.13. Simulation result of Path Metric Unit Figure: 11 Simulation results of convolutional encoder.
In figure 11 the initial input given is “1” previous states are “0” and”0” respectively. And initial at “00”
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D. VITERBI DECODER
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VII COMPARISION OF TWO DECODERS (Estimated values) Logic Utilization
Viterbi Decoder
Number of slices Number of slice flip flops
499
Modified Viterbi Decoder 59
404
29
Number of 4 input LUTs
898
108
Figure: 16 Comparison of viterbi decoder and modified viterbi decoder in design summary.
Figure: 14 Simulation results of viterbi decoder.
The figure 14 shown is the output of viterbi decoder which consists of large number of Add Compare Select Units the initial input given is “0” and the output obtained is also “0”.
E.MODIFIED VITERBI DECODER
Figure: 15 Simulation result of modified viterbi decoder.
From the experimental results, it is clear that the input signal to the convolution encoder is identical to the output signal from the Viterbi decode. The input data is given to the encoder and from which the encoded data is given to the viterbi decoder and it performs all the operations in it. And after the decoding time, the decoded data is obtained and is similar to the original input data. The simulation result of the modified viterbi decoder operation is shown in above figure. The input sequence “10100”is given to the convolutional encoder and the final output obtained from the modified viterbi decoder is also “10100” after a delay of 6 clock cycles.
This shows that viterbi decoder occupies the area almost 50 times more than that of modified viterbi decoder. So the power required for viterbi decoder will also be more than that of modified viterbi decoder since the number of Add Compare Select Units are reduced in the modified viterbi decoder. So, modified viterbi decoder is more efficient than viterbi decoder. VIII. CONCLUSION Here the convolutional encoder, viterbi decoder and modified viterbi decoder are implemented. This design has been simulated in Isim and synthesized using XILINX-ISE 12.2a for the given input sequence and shown that modified viterbi decoder is more suited to a channel in which transmitted signal is corrupted mainly by additive white Gaussian noise (AWGN). At the same time, the look-up table requirements are kept to a minimum. Thus the area utilized is reduced and thereby low power consumption can be achieved. The future work is focused on design a variable convolution encoder and Viterbi decoder. Because a variable convolution encoder and Viterbi decoder has a better flexibility in application.
IX REFERENCES [1] A. J. Viterbi and J. K. Omura, Principles of Digital Communication and Coding. New York: McGraw-Hill, 1979 [2] Ms.G.S. Suganya, Ms. G.kavya ,”RTL Design and VLSI Implementation of an efficient Convolutional
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Encoder and Modified Viterbi Decoder”, 978-1-4673-48669/13 ©2013 IEEE. [3]Mahender Veshala, Tualsagari Padmaja and Karthik Ghanta,FPGA Based Design and Implementation of Modified Viterbi Decoder for a Wi-Fi Receiver, 978-14673-5758-6/13 © 2013 IEEE
[4] Lei -ou Wang 1, Zhe-ying Li 1, Institute of Microelectronic Application Tech,Beijng Union University Beijing,C, Design and Implementation of a Parallel Processing Viterbi Decoder Using FPGA”, 978-1-42446936-9/10 ©2010 IEEE. [5] Zhao Bing·, Hei Yong. Qiu Yulin Institute of Microelectronics, Chinese Academy of Sciences, Beijing, 100029, China “An Asynchronous Data-path Design for Viterbi Decoder”, 0-7803-8511-X/04 ©2004 IEEE. [6] Yin Sweet Wong, Wen Jian Ong, Jin Hui Chong, Chee Kyun Ng, Nor Kamariah Noordin Universitiy Putra Malaysia, 43400, “Implementation of Convolutional Encoder and Viterbi Decoder using VHDL”, 978-1-42445187-6/09 ©2009 IEEE. [7] R. W. Hamming, “Error detecting and correcting codes,” Bell Sys. Tech.J., vol. 29, pp. 147–160, 1950 18, Pp. 794-807, May 2010. [8] B. Sklar, Digital Communications Fundamentals and Applications, Prentice Hall, New Jersey, 2001.
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A Transformerless Single-Stage AC-DC Converter with Closed Loop System Mastan. Moka PG Student[PEED],EEE Department Gudlavalleru Engg College, Gudlavalleru, AP, India
D. Vijay Arun Assistant Professor,EEE Department Gudlavalleru Engg College, Gudlavalleru, AP, India
mastan.ans@gmail.com Abstract—This paper presents a transformerless three phase single-stage single-switch ac/dc converter with closed loop suitable for universal line applications. The topology integrates a buck-type power-factor correction (PFC) cell with a buck–boost dc/dc cell, PI controller and part of the input power is coupled to the output directly after the first power processing. With this direct power transfer feature, the converter is able to achieve efficient power conversion, high power factor, low voltage stress on intermediate bus and required output voltage. The absence of transformer reduces the component counts and cost of the converter. Unlike most of the boost-type PFC cell, the main switch of the proposed converter only handles the peak inductor current of dc/dc cell rather than the superposition of both inductor currents. In this paper operation of the proposed circuit is given and verified by experimental results.
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efficiency of the overall system. Besides, leakage inductance of the transformer causes high spike on the active switch and lower conversion efficiency. To protect the switch, snubber circuit is usually added resulting in more component counts. In addition, the other drawbacks of the boost-type PFC cell are that it cannot limit the input inrush current and provide output short-circuit protection. In this paper, an integrated buck–buck–boost (IBuBuBo) converter with low output voltage is proposed. The converter utilizes a buck converter as a PFC cell. It is able to reduce the bus voltage below the line input voltage effectively. In addition, by sharing voltages between the intermediate bus and output capacitors, further reduction of the bus voltage can be achieved.
Index Terms—Direct power transfer (DPT), integrated buck– buck–boost converter (IBuBuBo), closed loop, power-factor correction (PFC), single-stage (SS), transformer less.
I. INTRODUCTION
S
INGLE-STAGE (SS) ac/dc converters
have received much attention in the past decades because of its cost effectiveness, compact size, and simple control mechanism. Among existing SS converters, most of them are comprised of a boost power-factor correction (PFC) cell followed by a dc/dc cell for output voltage regulation. Their intermediate bus voltage is usually greater than the line input voltage and easily goes beyond 450 V at high-line application. Although there are a lot of efforts to limit this bus voltage, it is still near or above the peak of the line voltage due to the nature of boost-type PFC cell. For application with low output voltage (e.g.≤48V), this high intermediate bus voltage increases components stresses on the dc/dc cell. With a simple step-down dc/dc cell (i.e. buck or buck–boost converter), extremely narrow duty cycle is needed for the conversion. This leads to poor circuit efficiency and limits the input voltage range for getting better performance. Therefore, a high step-down transformer is usually employed even when galvanic isolation is not mandatory. For example, LED drivers without isolation may satisfy safety requirement. Also, in some multistage power electronics system (e.g., in data center, electrochemical and petrochemical industries, and subway applications), the isolation has been done in the PFC stage; the second transformer in the dc/dc cell for the sake of isolation is considered as redundant. Hence, non-isolated ac/dc converter can be employed to reduce unnecessary or redundant isolation and enhance
Fig. 1: (a) Proposed IBuBuBo SS ac/dc converter. (b) Input voltage and Current waveforms
Therefore, a transformer is not needed to obtain the low output voltage. To sum up, the converter is able to achieve: 1) Low intermediate bus and output voltages in the absence of transformer; 2) Simple control structure with a single-switch; 3) Positive output voltage; 4) High conversion efficiency due to part of input power is processed once and 5) Input surge current protection because of series connection of input source and switch. II. PROPOSED CIRCUIT AND ITS OPERATING PRINCIPLE The proposed IBuBuBo converter, which consists of the merging of a buck PFC cell (L1 , S1 , D1 , Co , and CB
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Proceedings of International Conference On Current Innovations In Engineering And Technology ) and a buck–boost dc/dc cell (L2 , S1 , D2 , D3 , Co , and CB) is illustrated in Fig. 1(a). Although L2 is on the return path of the buck PFC cell, it does not contribute to the cell electrically. Thus, L2 is not considered as in the PFC cell. Moreover, both cells are operated in discontinuous conduction mode (DCM) so there are no currents in both inductors L1 and L2 at the beginning of each switching cycle t0. Due to the characteristic of buck PFC cell, there are two operating modes in the circuit. Mode A(vin (θ)≤VB + Vo ): When the input voltage vin (θ) is smaller than the sum of intermediate bus voltage VB , and output voltage Vo , the buck PFC cell becomes inactive and does not shape the line current around zero-crossing line voltage , owing to the reverse biased of the bridge rectifier. Only the buck–boost dc/dc cell sustains all the output power to the load. Therefore, two dead-angle zones are present in a half-line period and no input current is drawn as shown in Fig. 1(b). The circuit operation within a switching period can be divided into three stages and the corresponding sequence is Fig. 2(a),(b), and (f). Fig. 3(a) shows its key current waveforms. 1) Stage 1 (period d1Ts in Fig. 3) [see Fig. 2(a)]: When switch S1 is turned ON, inductor L2 is charged linearly by the bus voltage VB while diode D2 is conducting. Output capacitor Co delivers power to the load. 2) Stage 2 (period d2Ts in Fig. 3) [see Fig. 2(b)]: When switch S1 is switched OFF, diode D3 becomes forward biased and energy stored in L2 is released to Co and the load. 3) Stage 3 (period d3Ts - d4Ts in Fig. 3) [see Fig. 2(f)]: The inductor current iL2 is totally discharged and only Co sustains the load current. Mode B (vin (θ) > VB + Vo): This mode occurs when the input voltage is greater than the sum of the bus voltage and output voltage. The circuit operation over a switching period can be divided into four stages and the corresponding sequence is Fig. 2(c), (d), (e), and (f). The key waveforms are shown in Fig. 3(b). 1) Stage 1 (period d1Ts in Fig. 3) [see Fig. 2(c)]: When switch S1 is turned ON, both inductors L1 and L2 are charged linearly by the input voltage minus the sum of the bus voltage and output voltage (vin (θ) − VB − Vo), while diode D2 is conducting. 2) Stage 2 (period d2Ts in Fig. 3) [see Fig. 2(d)]: When switch S1 is switched OFF, inductor current iL1 decreases Linearly to charge CB and Co through diode D1 as well as transferring part of the input power to the load directly. Meanwhile, the energy stored in L2 is released to Co and the current is supplied to the load through diode D3. This stage ends once inductor L2 is fully discharged. 3) Stage 3 (period d3Ts in Fig. 3) [see Fig. 2(e)]: Inductor L1 continues to deliver current to Co and the load until its current reaches zero. 4) Stage 4 (period d4Ts in Fig. 3) [see Fig. 2(f)]: Only Co delivers all the output power.
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III. DESIGN CONSIDERATIONS To simplify the circuit analysis, some assumptions are made as follows: 1) All components are ideal; 2) Line input source is pure sinusoidal, i.e. vin (θ) = Vpksin (θ) where Vpk and θ are denoted as its peak voltage and phase angle, respectively; 3) Both capacitors CB and Co are sufficiently large such that they can be treated as constant DC voltage sources without any ripples; 4) The switching frequency fs is much higher than the line frequency such that the rectified line input voltage |vin (θ)| is constant within a switching period.
Fig.2: Circuit operation stages of the proposed ac/dc converter
A. Circuit Characteristics According to Fig. 1(b), there is no input current drawn from the source in Mode A, and the phase angles of the dead-time α and β can be expressed as
------(1) Where VT is the sum of VB and Vo . Thus, the conduction angle of the converter is -------(2) From the key waveforms (see Fig. 3), the peak currents of the two inductors are -------(3) And
--------(4) Where Ts (1/fs) is a switching period of the converter. In (3) and (4), the dependency of iL1 pk on θ has been omitted for clarity. It is noted that L2 does not contribute
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Proceedings of International Conference On Current Innovations In Engineering And Technology in (3) even though it is on the current return path of the PFC cell. In addition, by considering volt–second balance of the L1 and L2, respectively, the important duty ratio relationships can be expressed as follows:
--------(5)
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Putting (7) to zero due to the steady-state operation, this leads to
-(9) Where M is the inductance ratio L2/L1. As observed from (9), the bus voltage VB can be obtained easily by numerical method. It is noted that VB is independent on the load, but dependent on the inductance ratio M. Fig. 4 depicts the relationship among VB, rms value of the line voltage, and inductance ratio M. It is noted that the bus voltage is kept below 150 V at high-line input condition.
Fig.3: Key waveforms of the proposed circuit. Fig. 5: Estimated Power Factor under variation of inductance ratios.
By applying charge balance of CB over a half-line period, the bus voltage VB can be determined. From Fig. 3, the average current of CB over a switching and halfline periods are expressed as follows:
------(6) And
IV.SIMULATION RESULTS TRANSFORMERLESS SINGLE STAGE SINGLE-SWITCH SINGLE-PHASE AC/DC CONVERTER The performance of the proposed circuit is verified by the Matlab simulation. To ensure the converter working properly with constant output voltage, a simple voltage mode control is employed. To achieve high performance of the converter for universal line operation in terms of low bus voltage (< 150V) and high power (> 96%), the inductance ratio has to be optimized according to Figs. 4 and 5. The lower the bus voltage of the converter, the lower voltage rating capacitor (150 V) can be used.
---------(7) Where the constants A and B are
---------(8)
Fig.6: single-phase single stage single-switch AC/DC converter
Fig. 4: Calculated intermediate bus voltage under different inductance ratios.
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Fig.7: Measured input characteristics of the converter at (a) 90Vrms under 100-W condition
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Fig.10: Input voltage and input current
Fig.11: Output voltage at 415v rms input condition Fig.8: output voltage waveform at 90Vrms
V. SIMULATION RESULTS OF TRANSFORMERLESS SINGLE STAGE SINGLESWITCH THREE PHASE AC/DC CONVERTER WITH PI CONTROLLER The performance of the proposed circuit is verified by the prototype. To ensure the converter working properly with constant output voltage, a simple voltage mode control is employed. To achieve high performance of the converter for universal line operation in terms of low bus voltage and high power factor, the inductance ratio has to be optimized.
Fig.9: Three-phase single stage single-switch AC/DC converter with PI controller
Fig.12: Power factor under 415V rms and 100W condition
In addition, the inductance ratio will affect the efficiency of the converter. Taking the performance of the converter on bus voltage, power factor, and efficiency into account, the inductance ratio around M = 0.4 is selected. The circuit components are calculated based on the analysis performed in previous sections, and they are given as L1 = 106 μH, L2 = L2, crit = 46 μH, C = 5 mF, and Co = 5 mF. Duty cycle D1 is set to 0.22. A highfrequency input filter (LF =2 mH, and CF = 2 μF) is inserted after the bridge recti- fier to filter the ripples in the rectified line current. The simulated waveforms are shown in Fig. 10,11,12 which correctly demonstrates the DCM operating mode. The simulation result gives a total harmonic distortion in the input line current of about 1%. Moreover, it is clear that output voltage Vo has a significant lowfrequency ripple, which is unacceptable for some specific applications. However, the low-frequency ripple in Vo can be greatly reduced by simply regulating the output voltage. Therefore, a simple feedback controller has been implemented to regulate Vo.
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VI. CONCLUSION The proposed IBuBuBo three phase single-stage ac/dc converter with closed loop has been experimentally verified, and the results have shown good agreements with the predicted values. Thus the required DC output voltage was obtained for the applications with different input ratings. Here, the lower voltage rating of capacitor can be used. Moreover, the topology is able to obtain low output voltage without high step-down transformer. Owing to the absence of transformer, the demagnetizing circuit, the associated circuit dealing with leakage inductance and the cost of the proposed circuit are reduced compared with the isolated counterparts. In addition. Thanks to the direct power transfer path in the proposed converter, it is able to achieve high efficiency around 89%. REFERENCES [1]
[2]
[3]
[4]
[5]
[6]
Q. Zhao, F. C. Lee, and F.-s. Tsai, “Voltage and current stress reduction in single-stage power-factor correction AC/DC converters with bulk capacitor voltage feedback,” IEEE Trans. Power Electron., vol. 17, no. 4, pp. 477–484, Jul. 2002. O. Garcia, J. A. Cobos, R. Prieto, P. Alou, and J. Uceda, “Single phase power factor correction: A survey,” IEEE Trans. Power Electron., vol. 18, no. 3, pp. 749–755, May 2003. S. Luo,W. Qiu,W.Wu, and I. Batarseh, “Flyboost power factor correction cell and a new family of single-stage AC/DC converters,” IEEE Trans. Power Electron., vol. 20, no. 1, pp. 25–34, Jan. 2005. D. D. C. Lu, H. H. C. Iu, and V. Pjevalica, “A SingleStage AC/DC converterWith high power factor, regulated bus voltage, and output voltage,” IEEE Trans. Power Electron., vol. 23, no. 1, pp. 218–228, Jan. 2008. M. K. H. Cheung, M. H. L. Chow, and C. K. Tse, “Practical design and evaluation of a 1 kW PFC power supply based on reduced redundant power processing principle,” IEEE Trans. Ind. Electron., vol. 55, no. 2, pp. 665–673, Feb. 2008. D. D. C. Lu, H. H. C. Iu, and V. Pjevalica, “Single-Stage AC/DC Boost: Forward converter with high power factor and regulated bus and output voltages,” IEEE Trans. Ind. Electron., vol. 56, no. 6, pp. 2128–2132, Jun. 2009.
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An Interleaved Boost Converter Integrating with Switched Capacitor and Coupled Inductors for Renewable Energy Sources P V RAMANJANEYULU PG student [PEED], EEE Department, Gudlavalleru Engg College, Gudlavalleru, AP, India
K SANTHOSH KUMAR Assistant professor, EEE Department, Gudlavalleru Engg College, Gudlavalleru, AP, India
venkataramanjaneyulu@gmail.com Abstract: A new type of high step-up converter, which is suitable for conventional energy sources, is introduced in this paper. A voltage multiplier module composed of switched capacitors and coupled inductors; a conventional parallel boost converter gets high step-up gain without operating at large duty ratio. The arrangement of the proposed converter reduces the current stress and also limits the input current ripple, which decreases the conduction losses and it improves the lifetime of the input source. In addition, due to the lossless passive clamp performance, leakage energy is returned to the output terminal. Hence, large voltage spikes across the main switches are less severe, and improve the efficiency. The low-voltage-rated MOSFETs are chosen for reductions of conduction losses and cost in the proposed converter system. The obtained DC voltage is utilized by using an inverter for AC loads and directly to DC loads with appropriate step down converters. Index Terms: Boostâ&#x20AC;&#x201C;fly back converter, high step-up, renewable energy sources, voltage multiplier module, and inverter.
I.INTRODUCTION The development of â&#x20AC;&#x153;green powerâ&#x20AC;? generation has recently become very important to address environmental pollution and the problem of exhaustion of fossil energy reserves. Solar cells represent one of the most efficient and effective alternative renewable energy sources for many applications, such as hybrid electric vehicles, uninterruptible power supplies, telecom back-up facilities, and portable electronics. Today, interleaved boost converters are widely applied in fuel cell, photovoltaic arrays, and battery sources for boosting a very low voltage to an appropriate voltage for the alternating current (ac) inverters or front-end applications. Their main advantages are the current distribution, current ripple cancellation, fast transient response, and the size of the passive components reduction ; so the reliability is increased and high power output is realized. Fig. 1 shows a typical renewable energy system that consists of renewable energy sources, a stepup converter, and an inverter for ac application. The high step-up conversion may require two-stage converters with cascade structure for enough step-up gain, which decreases the efficiency and increases the cost. Thus, a high step-up converter is seen as an important stage in the system because such a system requires a sufficiently high step-up conversion with high efficiency. Theoretically, conventional step-up converters, such as the boost converter and fly back converter, cannot achieve a high step-up conversion with high efficiency because of the resistances of elements or leakage inductance; also, the voltage stresses are large. Thus, in recent years, many
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novel high step-up converters have been developed. Despite these advances, high step-up single-switch converters are unsuitable to operate at heavy load given a large input current ripple, which increases conduction losses. The conventional interleaved boost converter is an excellent candidate for high-power applications and power factor correction. However, the conventional interleaved boost converter has some disadvantages in high step-up direct current (dc/dc) applications. First, the duty ratio is extremely large in order to get a high gain, which increases the current ripple, the conduction losses and the turnoff losses. The transient response is limited by the narrow turnoff period of the switches. Second, the voltage stress of the switches is the high output voltage, which makes low-voltage high-performance devices unsuitable. Last, the output diode reverse-recovery problem is very severe, which induces additional voltage and current stresses and losses. The electromagnetic interference (EMI) noise is very serious. A lot of improvements have been made for the interleaved boost converters. To integrate switched capacitors into an interleaved boost converter may make voltage gain reduplicate, but no employment of coupled inductors causes the step-up voltage gain to be limited. Oppositely, to integrate only coupled inductors into an interleaved boost converter may make voltage gain higher and adjustable, but no employment of switched capacitors causes the step-up voltage gain to be ordinary. Thus, the synchronous employment of coupled inductors and switched capacitors is a better concept; moreover, high step-up gain, high efficiency, and low voltage stress are achieved even for high-power applications.
Fig 1. Block diagram of renewable energy and load
The proposed converter is a conventional interleaved boost converter integrated with a voltage multiplier module, and the voltage multiplier module is composed of switched capacitors and coupled inductors. The coupled inductors can be designed to extend step-up gain, and the switched capacitors offer extra voltage conversion ratio. In
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represent the output diodes for boost operation with switched capacitors, Df1 and Df2 represent the output diodes for fly back–forward operation, and nis defined as turn ratio Ns/Np. In the circuit analysis, the proposed converter operates in continuous conduction mode (CCM), and the duty cycles of the power switches during steady operation are greater than 0.5. The key steady waveform in one switching period of the proposed converter contains eight modes, which are shown in Fig. 3, and Fig. 4 shows the topological stages of the circuit.
Fig 2.Equivalent of circuit proposed converter
The advantages of the proposed converter are as follows. 1) The proposed converter is designed by low input current ripple and low conduction losses, which increases the lifetime of renewable energy sources and makes it suitable for high-power applications. 2) The converter achieves the high step-up gain that renewable energy systems require. 3) Due to the lossless passive clamp performance, leakage energy is recycled to the output terminal. Hence, large Voltage spikes across the main switches are alleviated, and the efficiency is improved. 4) Low cost and high efficiency are achieved by employment of the low-voltage-rated power switch with low RDS(ON); also, the voltage stresses on main switches and diodes are substantially lower than output voltage. 5) The inherent configuration of the proposed converter makes some diodes decrease conduction losses and alleviate diode reverse recovery losses. II.OPERATING PRINCIPLES The proposed high step-up interleaved converter integrating with two coupled inductors and two switched capacitors and is inserted between a conventional interleaved boost converter to form a modified boost–fly back–forward interleaved structure. When the switches turn off by turn, the phase whose switch is in OFF state performs as a fly back converter, and the other phase whose switch is in ON state performs as a forward converter. Primary windings of the coupled inductors with Np turns are employed to decrease input current ripple, and secondary windings of the coupled inductors with Ns turns are connected in series to extend voltage gain. The turn ratios of the coupled inductors are the same. The coupling references of the inductors are denoted by “·” and “∗”. The equivalent circuit of the proposed converter is shown in Fig. 2, where Lm1 and Lm2 are the magnetizing inductors; Lk1andLk2represent the leakage inductors; Ls represents the series leakage inductors in the secondary side;S1 and S2denote the power switches; Cc1 and Cc2are the switched capacitors; andC1, C2, and C3 are the output capacitors.Dc1 and Dc2 are the clamp diodes, Db1 and Db2
Fig. 3. Steady waveform of the proposed converter in CCM for R load
Mode 1 [t0, t1]: At t = t0, the power switch S2 remains in ON state, and the other power switch S1 begins to turn on. The diodes Dc1, Dc2, Db1, Db2, and Df1 are reversed biased, a shown in Fig. 4. The series leakage inductors Ls quickly release the stored energy to the output terminal via fly back–forward diode Df2, and the current through series leakage inductors Ls decreases to zero. Thus, the magnetizing inductor Lm1 still transfers energy to the secondary side of coupled inductors. The current through leakage inductor Lk1 increases linearly, and the other current through leakage inductor Lk2 decreases linearly.
Fig 4. Mode 1
Mode 2 [t1, t2]: At t = t1, both of the power switches S1and S2 remain in ON state, and all diodes are reversed biased, as shown in Fig. 5. Both currents through leakage
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Fig 7. Mode 4
Mode 5 [t4, t5]: At t = t4, the power switch S1 remains in ON state, and the other power switch S2 begins to turn on. The diodes Dc1, Dc2, Db1, Db2, and Df2 are reversed biased, as shown in Fig. 8. The series leakage inductors Ls quickly release the stored energy to the output terminal via fly back–forward diode Df1, and the current through series leakage inductors decreases to zero. Thus, the magnetization inductor Lm2 still transfers energy to the secondary side of coupled inductors. The current through leakage inductor Lk2 increases linearly and the other current through leakage inductor Lk1 decreases linearly.
Fig 5. Mode 2
Mode 3 [t2, t3]: At t = t2, the power switch S1 remains in ON state, and the other power switch S2 begins to turn off. The diodes Dc1, Db1, and Df2 are reversed biased, as shown in Fig. 6. The energy stored in magnetizing inductor Lm2 transfers to the secondary side of coupled inductors, and the current through series leakage inductors Ls flows to output capacitor C3 via fly back–forward diodeDf1. The voltage stress on power switch S2 is clamped by clamp capacitor Cc1 which equals the output voltage of the boost converter. The input voltage source, magnetizing inductor Lm2, leakage inductor Lk2,and clamp capacitor Cc2 release energy to the output terminal; thus, VC1 obtains a double output voltage of the boost converter.
Fig 8. Mode 5
Mode 6 [t5, t6]: At t = t5, both of the power switches S1 and S2 remain in ON state, and all diodes are reversed biased as shown in Fig. 9. Both currents through leakage inductorsLk1 and Lk2 are increased linearly due to charging by input voltage source Vin.
Fig 6. Mode 3
Mode 4 [t3, t4]: At t = t3, the current iDc2 has naturally decreased to zero due to the magnetizing current distribution, and hence, diode reverse recovery losses are alleviated and conduction losses are decreased. Both power switches and all diodes remain in previous states except the clamp diode Dc2, as shown in Fig. 7.
Fig 9. Mode 6
Mode 7 [t6, t7]: At t = t6, the power switch S2 remains in ON state, and the other power switch S1 begins to turn off. The diodes Dc2, Db2, and Df1 are reversed biased, as shown in Fig. 10. The energy stored in magnetizing inductor Lm1 transfers to the secondary side of coupled inductors, and the current through series leakage inductors flows to output capacitor C2 via fly back–forward diode Df2. The voltage stress on power switch S1 is clamped by clamp capacitor Cc2 which equals the output voltage of the boost converter. The input voltage source magnetizing inductor Lm1, leakage inductor Lk1, and clamp capacitor Cc1 release energy to the output terminal; thus, VC1 obtains double output voltage of the boost converter
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Proceedings of International Conference On Current Innovations In Engineering And Technology V = V = n. V
1+
ISBN : 978 - 1502851550 =
V
(3)
The output voltage can be derived from V =V
+V
+V
=
V
(4)
In addition, the voltage gain of the proposed converter is =
(5)
Equation (5) confirms that the proposed converter has a high step-up voltage gain without an extreme duty cycle. The curve of the voltage gain related to turn ratio n and duty cycle is shown in Fig. 12. When the duty cycle is merely 0.6, the voltage gain reaches ten at a turn ratio n of one; the voltage gain reaches 30 at a turn ratio n of five.
Fig10. Mode 7
Mode 8 [t7, t8]: At t = t7, the current idc1 has naturally decreased to zero due to the magnetizing current distribution and hence, diode reverse recovery losses are alleviated an conduction losses are decreased. Both power switches and all diodes remain in previous states except the clamp diode Dc1 as shown in Fig.11.
Fig12. Voltage gain versus turn ratio n and duty cycle
Fig 11. Mode 8
III.STEADY-STATEANALYSIS A. Step-Up Gain The voltage on clamp capacitor Cc can be regarded as an output voltage of the boost converter; thus, voltage VCc can be derived from V
=
V
(1)
When one of the switches turns off, voltage VC1 can obtain a double output voltage of the boost converter derived from V =
V +V
=
V
(2)
The output filter capacitors C2 and C3 are charged by energy transformation from the primary side. When S2 is in ON state and S1 is in OFF state, VC2 is equal to the induced voltage o Ns1 plus the induced voltage of Ns2, and when S1 is in ON state and S2 is in OFF state, VC3 is also equal to the induced voltage of Ns1 plus the induced voltage of Ns2. Thus, voltages VC2 andVC3 can be derived from
B. Voltage Stress on Semiconductor Component The voltage ripples on the capacitors are ignored to simplify the voltage stress analysis of the components of the propose converter. The voltage stress on power switch S is clamped and derived from V =V = V = V (6) Equation (6) confirms that low-voltage-rated MOSFET with low RDS(ON) can be adopted for the proposed converter to reduce conduction losses and costs. The voltage stress on the power switch S accounts for a fourth of output voltage Vo, even if turn ratio n is one. This feature makes the proposed converter suitable for high step-up and high-power applications. The voltage stress on diode Dc is equal to VC1, and the voltage stress on diode Db is voltage VC1 minus voltage VCc. These voltage stresses can be derived from V
=V V
=
=V
V = =V
â&#x2C6;&#x2019;V
V =
(7) V =
V
(8)
The voltage stress on diode Db is close to the voltage stress on power switch S. Although the voltage stress on diode Dc is larger, it accounts for only half of output voltage Vo at a turn ratio n of one. The voltage stresses on the diodes are lower as the voltage gain is extended by increasing turn ratio n. The voltage stress on diode Df equals the VC2 plus VC3, which can be derived from V
=V
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=
V =
V
(9)
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Proceedings of International Conference On Current Innovations In Engineering And Technology Although the voltage stress on the diode Df increases as the turn ratio n increases, the voltage stress on the diodes Df is always lower than the output voltage. C. Performance of current distribution The inherent design of the proposed converter makes the energy stored in magnetizing inductors transfer via three respective paths as one of the switches turns off. Thus, the current distribution decreases the conduction losses by lower effective value of current and increases the capacity by lower peak value of current. In addition, if the load is not heavy enough, currents through some diodes decrease to zero before they turn off, which reduce diode reverse recovery losses. Under light-/medium-load condition, the currents through diodes Db and Dc decrease to zero before they turn off. When the load is continuously added, only the current iDc decreases to zero before diode Dc turns off. Under heavy load, although every current through the diode cannot decrease to zero before the related diode turns off, the reduction of conduction losses and the increase of capacity still perform well.
ISBN : 978 - 1502851550
favourable for dc-micro grid applications, and the other high step-up interleaved converter introduced in [6] is suitable as a candidate for high step-up high-power conversion of the PV system. Both of the converters use coupled inductors and switched capacitors to achieve high step-up conversion. The step-up gain of the proposed converter is the highest, and the voltage stresses on semiconductor devices are the lowest. In addition, the extra winding or core may result in the circuit being costly and bulky. The proposed converter only uses two normal coupled inductors; thus, the cost and degree of difficulty of design are lower. Oppositely, the performances of current sharing and distribution make the reliability, capacity, and efficiency higher. Thus, the proposed converter is suitable for high step-up high-power applications. TABLE I: PERFORMANCE COMPARISION
D. Consideration for Applications of Renewable Energy Source and Low-Voltage Source Many low-voltage sources, such as battery, and renewable energy sources, such as solar cell or fuel cell stack, need a high step-up conversion to supply power to high-voltage applications and loads. However, an excellent high step-up converter not only supplies efficient step-up conversion but also should lengthen the lifetime of sources such as battery set and fuel cell stack. Thus, suppression of input current ripple for lengthening the lifetime of sources is also a main design consideration. The proposed converter can satisfy the aforementioned applications even for high-power load due to the interleaved structure, which makes the power source or battery set discharge smoothly. The proposed converter operated in CCM is even more suitable than that operated in discontinuous conduction mode (DCM) for suppression of input current ripple, because the peak current in DCM is larger. However, the duty cycles of the proposed converter are greater than 0.5 due to the interleaved structure. Thus, if the proposed converter operates in some PV system, which must be satisfied with enough output voltage, duty cycle limitation, and MPPT, the turn ratio n should be set to make the maximum power point easily located in duty cycles greater than 0.5. The turn ratio n can be decreased slightly as a suitable value based on (5), which makes the duty cycle increase. This section provides important information on characteristic analysis, feature, and consideration, which indicates the relationship among duty cycle, turn ratio, and components. The proposed converter for each application can be designed on the basis of selected turn ratios, components, and other considerations. E. Performance Comparison For demonstrating the performance of the proposed converter, the proposed converter and the other high stepup interleaved converters introduced in [5] and proposed converter are compared, as shown in Table I. The high step-up interleaved converter introduced in [5] is
IV. SIMULATION CIRCUITS AND RESULTS The design parameters of the circuit components are, input voltage is 40V, Switching frequency is 40 KHz, Turns ratio is one, Load Ro is 4000 Ω, Magnetizing inductors are Lm1 = Lm2 = 133μH, Capacitors Cc1, Cc2, C2, and C3 = 220 μF, and C1 = 470 μF. The design consideration of the proposed converter includes component selection and coupled inductor design. In the proposed converter, the values of the primary leakage inductors of the coupled inductors are set as close as possible for current sharing performance, and the leakage inductors Lk1 and Lk2 are 1.6 μH. Due to the performances of high step-up gain, the turn ratio n can be set as one for the prototype circuit with 40-V input voltage and 380-V output for R load, and 3- Φ induction motor load. The simulink circuit of R load and 4 KW, 50 Hz, 1430 rpm three phase induction motor load is shown in fig 13 and fig 14 respectively. The output voltage of R load is shown fig 15. The Speed of the three phase induction motor is shown in fig 16.
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Fig 15. Output voltage for R load
Fig 13. Simulink circuit for R load
Fig 16. Speed of 3- Φ induction motor
(a)
V. CONCLUSION A new modular interleaved boost converter by integrating a forward energy-delivering circuit and voltage multiplier is proposed for achieving high step-up and highefficiency objective. Steady-state analyses are then made to show the merits of the proposed converter topology.. The proposed converter has been successfully implemented in an efficiently high step-up conversion without an extreme duty ratio and a number of turns ratios. The interleaved PWM scheme reduces the currents that pass through each power switch and reduce the input current ripple. We reached the 380V o/p voltage for R load and rated speed for motor load. Thus, the proposed converter is suitable for PV systems or other renewable energy applications that need high step-up high-power energy conversion. REFERENCES [1]
[2]
[3]
[4]
(b) [5] Fig 14. (a) Simulink circuit for 3-phase motor load, (b)sub system for load [6]
Kuo-Ching Tseng and Chi-Chih Huang, “ High Step-Up High- Efficiency Interleaved Converter With Voltage Multiplier Module for Renewable Energy System,’’IEEE transactions on industrial electronics, vol. 61, no. 3, pp.13111318,march 2014 N. Denniston, A. M. Massoud, S. Ahmed, and P. N. Enjeti, “Multiplemodule high-gain high-voltage DC–DC transformers for offshore wind energy systems,” IEEE Trans. Ind. Electron., vol. 58, no. 5, pp. 1877– 1886, May 2011. R. J. Wai, W. H. Wang, and C. Y. Lin, “High-performance stand-alone photovoltaic generation system,” IEEE Trans. Ind. Electron., vol. 55, no. 1, pp. 240–250, Jan. 2008. W. Li and X. He, “Review of non isolated high-step-up DC/DC converters in photovoltaic grid-connected applications,” IEEE Trans. Ind. Electron., vol. 58, no. 4, pp. 1239–1250, Apr. 2011. C. M. Lai, C. T. Pan, and M. C. Cheng, “High-efficiency modular high step-up interleaved boost converter for DCmicro grid applications,” IEEE Trans. Ind. Appl., vol. 48, no. 1, pp. 161–171, Jan./Feb. 2012 K. C. Tseng, C. C. Huang, and W. Y. Shih, “A high step-up converter with a voltage multiplier module for a photovoltaic system,” IEEE Trans. Power Electron., vol. 28, no. 6, pp. 3047–3057, Jun. 2013.
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Single-Phase Single-Stage Multi-Level AC–DC Converter for power factor correction M.SUPRIYA
K. BHAVYA
PG scholar Department of Electrical & Electronics Engineering, Gudlavalleru Engineering College, JNTU K Gudlavalleru, A.P, India. e-mail: supriya.maddali@gmail.com
Assistant Professor Department of Electrical & Electronics Engineering, Gudlavalleru Engineering College, JNTU K Gudlavalleru, A.P, India. e-mail: bhavya.eee.08@gmail.com
Abstract: Single-stage power-factor-correction (PFC) circuits usually suffer from high rising intermediate bus voltage stress at light load condition due to power imbalance between the input and output. By repeating power processing the efficiency of converter is also low. A singlestage AC-DC power-factor-corrected voltage regulator (PFCVR) is presented for which a portion of the input power is transferred to the output directly after the first power process, voltage stress decreases bus storage capacitor while achieving a high quality of power factor. In this paper five-level ac-dc single-stage converter is presented. The operation of the converter is explained, the PWM method was used to operate the converter. Finally, the proposed topology developed by using MATLAB/SIMULINK software.
Conversions process resulting in higher cost and lower efficiency which is as shown in figure1. This has led to the emergence of single-stage Powerfactor-corrected (SSPFC) converters shown in figure2.
Index Terms—AC–DC power factor correction, single-stage converters, five-level converters.
I.
INTRODUCTION
POWER FACTOR CORRECTION (PFC) is necessary nowadays for an ac-dc power supply [9]. Three techniques are used to obtain unity power factor. One of them is adding passive filter elements to the traditional passive diode rectifier/LC filter to input side; this resulting the converter size is high and bulky of low frequency inductor and capacitors [8]. Another method is using an active PFC, by adding the AC-DC boost converter at front end leads to two-stage converter which can shape the input line current almost sinusoidal shape and also for DC-DC conversion. By adding the boost converter in spite of its good performance, the two stage approaches [7] requires more circuit components and two powers
SSPFC converters, particularly for lowpower ac–dc flyback and forward converter are cheaper and simpler converters are widely used [5][9]. Research on the topic of higher power AC-DC single challenging some of them are Single-stage ac–dc full-bridge current-fed converters; these converters have a boost inductor connected to the input of the full-bridge circuit. By using this we can get near-unity input power factor, but absence of energy-storage capacitor across the primary-side dc bus, high voltage stresses appears across the dc bus. Some resonant converters that must be controlled using varying switching-frequency control, which makes it difficult to design. Single-stage ac–dc full-bridge converter is based on voltage-fed single-stage pulse width modulation (PWM) converter is most commonly used converter [4]-[7].Large energy-storage capacitor connected across their primary-side dc bus in this converter. By connect the bus capacitor we can eliminates voltage overshoots and ringing across the dc bus. This converter can be controlled by a single controller and the dc bus voltage is left unregulated and this can also used for implementing the two level topologies which can increases the high voltage stresses. so we are going to multi level topologies. Multilevel converters have been proposed to try to reduce the peak voltage stresses of the converter devices. This converter can be made to operate with an output current that has less ripple and
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an input current that is less distorted than that of a two-level converter. The drawbacks of previously proposed converters can be overcome by a three-level (TL) voltage-fed single-stage PWM[2]converter as shown in fig 3and its characteristics are shown in fig.4,by using this converter turn on and turn off time period of switches increases. This leads to increases the stress on switches. By using this PWM method is not standard phase shift and is therefore not found in commercially available integrated circuits.
So we are going to a new TL ac窶電c singlestage converter with some standard phase shift is given to the switches so by using this converter we can reduces the stress on switches. In this paper we are using five level ac窶電c single-stage converter with some standard phase shift is used. This converter can be used to increase the voltage levels and reduces the stress on the individual switch. In this paper the operation of single stage five levels AC-DC converter can be explained.
Fig 3: Single-stage TL ac窶電c converter with PWM
Fig 4: Typical waveforms of TL ac窶電c converter with PWM
II.OPERATION OF PROPOSED CONVERTER Fig 1: Two stage converter
Fig 2: Single stage converter
The proposed converter is shown in fig:5, consists of AC-DC boost PFC into three level DC/DC converter[13]. It consists of an ac input section, a five-level dc-dc converter, and dc link circuitry that contains an inductor Lin.The PFC is performed by using an auxiliary winding taken from the main transformer that acts like a switch that turns on and off in an appropriate manner. The diode rectifier bridge output is replaced by a rectified sinusoidal source, and the thick lines represent the paths of current conduction. The design of this converter are identical to that presented in [2] for the converter shown in Fig.3.The analysis of the TL single-stage converter[1] is shown in Fig.4.
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During this mode, S2 remains ON and S1 is OFF. Capacitor Cs1 charged by C1 and capacitor Cs4 discharges through Cf. DC-link capacitors are charged by the energy stored in input inductor in mode1. At the end of this mode ends when S4 turns on. Mode3:
Fig 5: Single-stage TL ac窶電c converter with Phase shift.
Modes of operation of proposed converter are given below: Mode1:
In this mode, S1 and S2 switches are ON, and energy from dc bus capacitor C1 is transferred to the output load, total dc-link capacitor voltage is equal to voltage generated across the auxiliary winding voltage. so that the current in input inductor current starts rising.
In this Mode, S1 is OFF and S2 remains ON. The stored energy in the input inductor during Mode 1 is completely transferred into the dc-link capacitors. The input inductor current reaches to zero at the end of this mode and the load inductor current freewheels in the secondary of the transformer. Mode4:
Mode2:
In mode4, S1 is OFF and S2 is ON, the primary current of the main transformer circulates through diode D1 and S2, and the load inductor current freewheels in the secondary of the transformer.
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Mode 5:
Fig 8.Response at input side
During this mode, S1 and S2 are OFF, and the current in the primary of transformer charges capacitor C2 through the switch S4 and body diode of S3.In this mode the current in load inductor continues to transfer energy from the input to the output. This mode ends then symmetrical period begin, when switches S3 and S4 are switched on. Typical converter waveforms are shown in fig 6.
Fig 9. Top switches voltages
Fig 6: Typical waveforms for the proposed converter. Fig 10. Primary voltage of the transformer
III. SIMULATION RESULTS
Fig11.Response at output side Fig 7Single-stage TL ac窶電c converter with PWM
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Fig 16. Response at Output side Fig12.Single-stage TL ac窶電c converter with Phase shift.
IV.OPERATION OF SINGLE-STAGE FIVE LEVEL AC/DC CONVERTERS
Fig13.Response at input side
Fig 14.Top switches voltages
The five level converter is shown in fig:17, consists of AC-DC boost PFC into five level DC/DC converter. It consists of an ac input section, a fivelevel dc-dc converter, and dc link circuitry that contains an inductor Lin.The PFC is performed by using an auxiliary winding taken from the main transformer that acts like a switch that turns on and off in an appropriate manner. The five levels of voltages are obtained as follows: 1) Maximum positive output voltage, 2V: when the switches A11, A12, A13, A14 are on remaining all switches are off. 2) Half positive output voltage, V: when the switches A12, A13, A14, A21 are on remaining all switches are off. 3) Zero output voltage,0: when the switches A13, A14, A21,A22 are on remaining all switches are off. 4) Half negative output voltage,-V: when the switches A14, A21, A22, A23 are on remaining all switches are off. 5) Maximum negative output voltage,-2V: when the switches A21, A22, A23, A24 are on remaining all switches are off. V. SIMULATION RESULTS
Fig15.Voltage at primary of the transformer
Fig17: Single-stage five level AC/DC converter
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Fig18. Response at input side
Fig19. Voltage at primary of the transformer
ISBN : 978 - 1502851550
correction ac–dc converter,” IEEE Trans. Power Electron., vol. 27, no. 6, pp. 2888–2899, Jun. 2012. [3] H. Ribeiro and B. Borges, “New optimized fullbridge, single stage ac/dc converters,” IEEE Trans. Ind. Electron., vol. 58, no. 6, pp. 2397–2409, Jun. 2011 [4] H. L. Cheng, Y. C. Hsieh, and C. S. Lin, “A novel single-stage high-power factor ac/dc converter featuring high circuit efficiency,” IEEE Trans. Ind.Electron., vol. 58, no. 2, pp. 524–532, Feb. 2011. [5] H. S. Ribeiro and B. V. Borges, “Analysis and design of a high-efficiency full-bridge single-stage converter with reduced auxiliary components,” IEEE Trans. Power Electron., vol. 25, no. 7, pp. 1850– 1862, Jul. 2010. [6]J. Zhang, D. D.-C. Lu, and T. Sun, “Fly backbased single-stage power factor-correction scheme with time-multiplexing control,” IEEE Trans. Ind. Electron., vol. 57, no. 3, pp. 1041–1049, Mar. 2010. [7]Octavian Dranga,Chi K.Tse,Siu Chung Wong, Stability analysis of complete two-stage power factor correction power supplies”,2 September 2005. [8] J. Zhang, M. M. Jovanovic, and F. C. Lee, “Comparison between CCM single-stage and twostage boost PFC converters,” in Proc. Appl. Power Electron. Conf., 1999, vol. 1, pp. 335–341 [9]D. D. C. Lu, D. K. W. Cheng, and Y. S. Lee, “Single-stage AC–DC power-factor-corrected voltage regulator with reduced intermediate bus voltage stress,” Proc. Inst. Elect. Eng.—Elect. Power Appl., vol. 150, no. 5, pp. 506–514, Sep. 2003.
Fig20. Response at Output side
VI.CONCLUSION A five level single-stage converter has been proposed in this paper. The operation of the converter was explained, and its feasibility was confirmed with experimental results obtained from a prototype converter. Multilevel converters have been proposed to try to reduce the peak voltage stresses of the converter devices. This converter can be made to operate with an output current that has less ripple and an input current that is less distorted than that of a two-stage converter. REFERENCES [1] Mehdi Narimani, Student Member, IEEE,and Gerry Moschopoulos, “A New Single-Phase SingleStage Three-Level Power-Factor-Correction AC–DC Converter With Phase-Shift Modulation”IEEE transactions on industrial electronics, vol.60,no.9,September 2013. [2] M. Narimani and G. Moschopoulos, “A new single-phase single-stage three-level power factor
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Fuel cell based Single-Input Multiple-Output DC– DC Converter for BLDC Motor G.HARITHA PG Scholar Department of Electrical &Electronics Engineering, Gudlavalleru Engineering College, JNTU K Gudlavalleru, A.P, India. e-mail: gangaharitha23@gmail.com Abstract: Brushless dc motors have only a lot of history. They are used in various industrial and household appliance manufacturers because of its high efficiency, low maintenance cost, silent operation, compact form, and reliability. The aim of this project is to develop fuel cell based single input multiple output DC-DC converter for BLDC drive. The proposed converter can boost the voltage of a low voltage input power source to a controllable high voltage dc bus and middle voltage output terminals. In this paper fuel cell connected as input and total converter connected to BLDC drive. The high-voltage dc bus can take as the main power for a high-voltage dc load or the front terminal of a dc-ac inverter. Moreover, middle-voltage output terminals can supply powers for individual middle-voltage dc loads or for charging auxiliary power sources (e.g., battery modules). In this paper, a coupled-inductor-based dcdc converter scheme utilizes only one power switch with the properties of voltage clamping and soft switching techniques. The proposed topology will be developed by using MATLAB/ SIMULINK and simulation results will be presented. Index Terms—Coupled inductor, single-input multiple-output (SIMO) converter, soft switching, voltage clamping, fuel cell, BLDC motor.
I.
K.BHAVYA Assistant Professor Department of Electrical & Electronics Engineering, Gudlavalleru Engineering college, JNTU K Gudlavalleru, A.P, India. e-mail: bhavya.eee.08@gmail.com DC converter with shared ZCS lagging leg.[10] It is used to full bridge converters so cost is high. Finally to propose single input multiple output converter with coupled inductor [1]. It uses only single switch and to obtain the different output voltage levels. Soft switching and voltage clamping techniques are used to reduce switching and conduction losses. In this paper fuel cell is used as the input so to eliminate the environment pollution [2]-[7]. Fuel cell is a device; it converts chemical energy into electricity through a chemical reaction with oxidizing agent or oxygen. Fuel cell has many applications. They are used in automobiles, airplanes, boats, submarines and hybrid vehicles. II.
The proposed system can generate two different voltage levels shown in fig 1. It has five parts, they are low voltage side circuit (LVSC), clamped circuit, auxiliary circuit, middle voltage circuit and high voltage side circuit (HVSC). Equivalent circuit is shown in fig 2. It is used to define the polarities of voltages and direction of currents. The turns ratio N and coupling coefficient k of this ideal transformer is = ⁄
INTRODUCTION
=
DC-DC converters are used in many applications. Boost converter is used to increase the voltage level of the input voltage. Normal boost converter has single input single output but obtain the various voltage levels to combine the various single input single output DC-DC converters with different voltage gains but control is complicated. The existing system of the converter generating buck, boost and inverted outputs [8] at a time but over three switches are used for one output is required. It is only suitable for low voltage and low power applications. Nami [9] is proposed DC-DC multi output boost converter but two switches are required for one output and control is complex. After to propose a multiple output DC-
PROPOSED CONVERTER
(
+
)
Fig 1: single input multiple outputs DC-DC converter (SIMO)
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The coupling coefficient effect is less on the voltage gain and capacitor c1 is selected to a completely absorb the leakage energy [11]. The characteristic waveforms are shown in fig 3.
ISBN : 978 - 1502851550
At time t=t1, the switch S1 is turned on during this mode because the primary inductor is charged by the input power source. In this way secondary voltage charges the middle voltage capacitor C2 through the diode D3. At mode 1 and 2 is equal to the input voltage. = = = = Mode 3: (
< <
)
Fig 2: Equivalent circuit
Mode 1: (
III.
MODES OF OPERATION
< <
)
At time t=t2, the switch S1 is turned off. The voltage across the switch is higher than the voltage across the clamped capacitor then diode D1 conducts. At that time the primary side leakage inductor Lkp partial energy is transmitted to the Laux, the diode D2 conducts. When the leakage energy of the secondary side of the coupled inductor releases completely then the diode D3 turns off.
In this mode, the switch S1 is turned on. At the time diode D4 was turned off because coupled inductor winding polarity is positive, the diodeD3 turns on. Middle voltage capacitor C2 charges and secondary current reverses. At the end of this mode auxiliary inductor releases its stored energy and the diode D2 turns off. Mode 2: ( < < )
Apply KVL
Mode 4: (
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< <
+ (1 − ) = 0 = [− /(1 − )] =− = [ /(1 − )] )
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In this mode at t=t3, switch S1 is turned off. Primary side of the coupled inductor leakage energy is released then flows through the diode D4 to the HVSC. In this time the current passes through the diode D2 to output load in the auxiliary circuit. = Mode 5: (
< <
+
+
−
ISBN : 978 - 1502851550
Voltage gain formulas: =
=
=
=
+1 1− 1
1−
+
)
At t=t4, the switch S1 is turned off and diode D1 is off because primary leakage current equals to the current of auxiliary inductor. In this time, input source, primary winding of the coupled inductor and auxiliary inductor connect in series to supply the power for auxiliary circuit through diode D2. At that time, secondary winding of the coupled inductor, clamped capacitor C1 and C2 connect in series to release the energy in to the HVSC through the diode D4. + Mode 6:(
< <
(1 −
)
=0
)
At t=t5, the switch S1 is on. To select the diode as a low voltage schottky diode, it will be cut off prompty without a reverse recovery current. Soft switching is used to alleviating the switching loss. Remaining is same as the mode 5.After operation of mode 1 is repeated. Fig 3: characteristic wave forms of proposed converter
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IV.
ISBN : 978 - 1502851550
SIMULATION RESULTS
The simulation circuit of single input multiple outputs DCDC converter is shown in below and to observe the low power DC to DC converter and high power DC to DC converter waveforms of voltage and current across the high voltage side, auxiliary circuit and main switch are shown in below. Case-1 Low power DC to DC Converter Fig.8 Simulated output wave form of the VD4,iD4 in Low power DC to DC converter
Fig.4 Matlab/simulink model of Low power DC to DC converter
Fig.9 Simulated output wave form of Inductor leakage current in Low power DC to DC converter
Fig.5 Simulated output wave form of the VS1,iS1 in Low power DC to DC converter
Fig.10 Simulated output wave form of Secondary side current in Low power DC to DC converter
Fig.6 Simulated output wave form of the VD2,iD2 in Low power DC to DC converter
Fig.7 Simulated output wave form of the VD3,iD3 in Low power DC to DC converter
Fig.11 Simulated output wave form of Inductor auxiliary current in Low power DC to DC converter
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Fig.12 Simulated output voltage wave form of the Low power DC to DC Converter
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Fig.16 Simulated DC output voltage wave form in High power DC to DC Converter
Case-2 High power DC to DC Converter
V.
BLDC MOTOR
BLDC motor is one of the popular motor. These motors are used in industries such as automotive, medical, aerospace, industrial automation equipment and instrumenttation. In this motor brushes are not use for the commutation instead, they are electronically commutated. In this motor back emf shape is trapezoidal [12]-[13].
Fig.13 Simulated output wave of the Primary side current in High power DC to DC Converter
Hall sensors are used to sense the rotor position and to know which winding is energized in energizing sequence. In this paper, high voltage dc load is connected to BLDC motor and to observe the performance of BLDC motor. Speed torque characteristics: In continuous operation, motor is loaded up to the rated torque. In BLDC motor, the torque is remains constant for a speed range up to rated speed.
Fig.14 Simulated output wave forms of the Secondary side current in High power DC to DC Converter
Fig 17: speed torque characteristics of BLDC motor
Fig.15 Simulated output wave forms of the auxiliary inductor current in High power DC to DC Converter
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VI.
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SIMULATION RESULTS
The simulation circuit of single input multiple outputs DCDC converter with BLDC motor is shown in fig 10 and to observe the response of speed and torque are shown in below.
Fig 20: stator current and back emf waveforms
Fig 18: proposed converter with BLDC motor
Fig 21: speed response of BLDC motor
Fig 19:input voltage of BLDC motor
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Fig 22: Torque response of BLDC motor
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VII.
ISBN : 978 - 1502851550
CONCLUSION
This paper is to develop a single input multiple output DC-DC converter. Two output terminals are auxiliary battery module and high voltage dc bus. In this proposed converter uses only single switch with soft switching, so to reduce the switching losses. The high voltage dc bus is connected to the BLDC motor and the performance of the BLDC motor is observed. The auxiliary battery module is used to other DC loads. REFERENCES [1] Rong-Jong Wai, Kun- Huai Jheng, “High Efficiency Single InputMultiple Output DC-DC converter”IEEE Trans. power Electronics, vol. 28, no.2, Feb 2013. [2] A. Kirubakaran, S. Jain, and R. K. Nema, “DSP-controlled power electronic interface for fuel-cell-based distributed generation,” IEEE Trans. Power Electron., vol. 26, no. 12, pp. 3853–3864, Dec. 2011. [3] B. Liu, S. Duan, and T. Cai, “Photovoltaic dc-building-module-based BIPV system-concept and design considerations,” IEEE Trans. Power Electron., vol. 26, no. 5, pp. 1418–1429, May 2011. [4] M. Singh and A. Chandra, “Application of adaptive network-based fuzzy interference system for sensor less control of PMSG-based wind turbine with nonlinear-load-compensation capabilities,” IEEE Trans. Power Electron., vol. 26, no. 1, pp. 165–175, Jan. 2011. [5] C. T. Pan, M. C. Cheng, and C. M. Lai, “A novel integrated dc/ac converter with high voltage gain capability for distributed energy resource systems,” IEEE Trans. Power Electron., vol. 27, no. 5, pp. 2385–2395, May 2012. [6] S. D.Gamini Jayasinghe, D. Mahinda Vilathgamuwa and U. K. Madawala, “Diode-clamped three-level inverter-based battery/super capacitor direct integration scheme for renewable energy systems,” IEEE Trans. Power Electron., vol. 26, no. 6, pp. 3720–3729, Dec. 2011. [7] T. Kim, O. Vodyakho, and J. Yang, “Fuel cell hybrid electronic scooter,” IEEE Ind. Appl. Mag., vol. 17, no. 2, pp. 25–31, Mar./Apr. 2011. [8] P. Patra, A. Patra, and N. Misra, “A single-inductor multiple-output switcher with simultaneous buck, boost and inverted outputs,” IEEE Trans. Power Electron., vol. 27, no. 4, pp. 1936–1951, Apr. 2012. [9] A. Nami, F. Zare, A. Ghosh, and F. Blaabjerg, “Multiple-output DC– DC converters based on diode-clamped converters configuration: Topology and control strategy,” IET Power Electron., vol. 3, no. 2, pp. 197–208, 2010. [10] Y. Chen, Y. Kang, S. Nie, and X. Pei, “The multiple-output DC–DC converter with shared ZCS lagging leg,” IEEE Trans. Power Electron., vol. 26, no. 8, pp. 2278–2294, Aug. 2011. [11] R. J. Wai and R. Y. Duan, “High step-up converter with coupled inductor, ”IEEE Trans. Power Electron., vol. 20, no. 5, pp. 1025–1035, Sep. 2005. [14] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications, and Design. New York: Wiley, 1995. [12] BLDC motor Vol. 3, Issue 3, May-Jun 2013, pp.612-620 [13] BLDC motor fundamentals author by Padmaraja Yedamale
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Pipelined Parallel FFT Architecture through Folding Transformation M.S.Krishna priya, M.TECH Student, DEPARTMENT of ECE, Shri Vishnu Engg college for women D.Murali Krishna, Sr.ASST.PROFESSOR, DEPARTMENT of ECE, Shri Vishnu Engg college for women
is the basis for several television and radio broadcast
ABSTRACT:
applications, including the European digital broadcast This project presents a FUSING FFT system using
television standard, as well as digital radio in North
OFDM application. It is demonstrated by a software
America. FUSING platform provides software
reconfigurable
a
control of variety of modulation schemes, wideband
programmable floating point DSP. A new VLSI
or narrow band operation, communications security
architecture for real-time pipeline FFT processor is
functions such as frequency hopping and waveform
proposed in this project. In this project, high radix
requirements of current and evolving standards over a
floating point butterflies are implemented more
broad frequency range. It is viewed as a single radio
efficiently
floating-point
platform, providing services to multiple cellular
operations. The fused operations are a two-term dot
standards. F AST FOURIER TRANSFORM (FFT) is
product and add-subtract unit. Both discrete and
widely used in the field of digital signal processing
fused radix processors are implemented; compared
(DSP) such as filtering, spectral analysis, etc., to
in regarded with area wise. OFDM systems and the
compute the discrete Fourier transform (DFT). FFT
associated clock cycles required to demodulate data
plays
using loop and straight-line FFT programming
communications such as digital video broadcasting
methods are provided. Higher execution speed is
and orthogonal frequency division multiplexing
achieved by using straight-line code instead of
(OFDM) systems. Much research has been carried
looped code. The tradeoff of this optimization is a
out
larger program memory requirement of the straight-
computation of FFT of complex valued signals
line assembly code.
(CFFT). Various algorithms have been developed to
OFDM
with the
system
two
fused
using
a
on
critical
designing
role
in
pipelined
modern
digital
architectures
for
reduce the computational complexity, of which KEYWORDS: Fusing, OFDM, FFT, Radix, Dot product,
Folding
transformation,
Cooley-Tukey radix-2 FFT [1] is very popular.
Optimization,
complex valued Fourier transform, Add-substract
Note that this is not the only way to represent floating
unit.
point numbers, it is just the IEEE standard way of
1.INTRODUTION:
OFDM
is
a
multimode
modulation and multiple access technique used in a number
of
commercial
wired
and
doing it. Here is what we do: the representation has three fields:
wireless
applications. In the wired side, it is used for a variant of digital subscriber line (D). SLFor wireless, OFDM
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|S| E
|
F
|
ISBN : 978 - 1502851550
difference calculation, significand swapping, and the significand shifting for both the add and the subtract
----------------------------
operations are performed with a single set of hardware and the results are shared by both the
S is one bit representing the sign of the number
operations. This significantly reduces the required
E is an 8-bit biased integer representing the exponent
circuit area. The significand swapping and shifting is
F is an unsigned integer
done based solely on the values of the exponents (i.e., without comparing the significands).
the decimal value represented is: S
e
(-1) x f x 2 where e = E â&#x20AC;&#x201C; bias f = ( F/(2^n) ) + 1 for single precision representation (the emphasis in this
class)
n
=
23
bias = 127 for
double
precision
representation
(a
64-bit
representation) n = 52 (there are 52 bits for the mantissa field) bias = 1023 (there are 11 bits for the exponent field) 2.FUSED FLOATING-POINT ADD-SUBTRACT UNIT:The floating-point fused add-subtract unit (Fused AS) performs anaddition and a subtraction in
To demonstrate the utility of the Fused DP and Fused
parallel on the same pair of data. The fused add-
AS units for FFT implementation, FFT butterfly unit
subtract unit is based on a conventional floatingpoint
designs using both the discrete and the fused units
adder [8]. Although higher speed adder designs are
have been made. First, a radix-2 decimation in
available(see [9] for example), the basic design
frequency FFT butterfly was designed. All lines carry
shown here serves todemonstrate the concept. A
complex pairs of 32-bit IEEE-754 numbers and all
block diagram of the fused addsubtractunit is shown
operations are complex. The complex add, subtract,
in Fig. 5 (after the initial design from [10]). Some
and multiply operations can be realized with a
details, such as the LZA and normalization logic are
discrete implementation that uses two real adders to
omitted here to simplify the figure. The exponent
perform the complex add or subtract and four real
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multipliers and two real adders to perform the complex multiply.
The nodes from
A0…A7.represent the eight
butterflies in the first stage of the FFT and B0..B7. represent the butterflies in the second stage. Assume the butterflies have only one multiplier at the bottom output instead of both outputs. 3.HIGH
THROUGHPUT
ARCHITECTURE:
The
proposed
FFT architecture
consists of the following main parts, together with their specific novelties and advantages. (i) A memory unit composed of 16 dual-port memory banks, which facilitates 16-way parallel data access. (ii) A memory bank index and address generation unit (BAGU), Although there is a multiplicative factor “j ” after the
which generates conflict-free and in-place memory
first stage, the first two stages consists of only real-
bank indexes and address for the radix-16 FFT
valued datapath.We need to just combine the real and
operation. (iii) Four commutator blocks located in
imaginary parts and send it as an input to the
front of the input side and after the output side of the
multiplier in the next stage. For this, we do not need a
memory, provide efficient data routing mechanism
full complex butterfly stage. The factor is handled in
which is governed by the BAGU signals. (iv) A
the second butterfly stage using a bypass logic which
scaling
forwards the two samples as real and imaginary parts
operations for block floating point (BFP) operations,
to the input of the multiplier. The adder and
which generates higher signal-to-quantization noise
subtractor in the butterfly remains inactive during
ratio (SQNR) than the existing designs. (v) The
that time. Scheduling Method 2: Another way of
kernel
scheduling
performance computing
is
proposed
which
modifies
the
unit (SU) coordinates controlled scaling
processing
engine,
which
is
a
high
engine for radix-16
architecture slightly and also reduces the required
butterfly operations. Four radix-16 PEs (i.e., PE_R16
number of delay elements. In this scheduling, the
0 through PE_R16 3), two sets of radix 2 PEs (each
input samples are processed sequentially, instead of
set contains four radix-2 PEs), and four sets of
processing the even and odd samples separately. This
complex multipliers(each contains four complex
can be derived using the following folding sets:
multipliers) for twiddle factor multiplications. Those multipliers are optimized with the help of commonsubexpression sharing technique and a new twiddle-
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factor multiplication scheme. All the function units
order of the output samples in the proposed
inside the kernel processing engine are detailed. To
architectures is not in the bit-reversed order. The
avoid possible conflicts in simultaneously reading (or
output order changes for different architectures
writing) 16 data from (or to) the memory banks
because of different folding sets/scheduling schemes.
during FFT operations, a proper memory addressing scheme is necessary. The well-known non-conflict memory addressing schemes [5], [7] are only
5.BOOTH
ENCODER
FOR
MULTIPLICATION:
applicable to radix-2 FFT algorithm. Although the
We use the sign extension circuitry developed in [2]
addressing scheme in [6] is for general radix- FFT
and [3]. The conventional MBE partial product array
operations, its FFT size should be a power-of-
has two drawbacks: 1) an additional partial product
number. Besides, those schemes are only limited to
term at the (n-2)th bit position; 2) poor performance
single-PE architecture. On the other hand, the radix-2
at the LSB-part compared with the non-Booth design
addressing scheme for multiple PEs [16] is relatively
when using the TDM algorithm. To remedy the two
inefficient compared with higher-radix schemes. The
drawbacks, the LSB part of the partial product array
proposed scheme has three special features. First, it
is modified. Referring to theory, the Row_LSB (gray
ensures conflict-free FFT butterfly executions during
circle) and the Neg_cin terms are combined and
the entire FFT operation. Second, it supports parallel
further simplified using Boolean minimization. All
data outputs with normal ordering. This feature is
these are efficiently implemented using this advanced
always desirable for providing immediate and
modified booth algorithm. Below figure shows the
normal-order
succeeding
architecture of the commonly used modified Booth
functional blocks, such as channel estimator for
multiplier. The inputs of the multiplier are multiplicand
timely operations. Thirdly, like many other designs,
X and multiplier Y. The Booth encoder encodes input Y
the in-place FFT computation strategy is also adopted
and derives the encoded signals as shown in below
for low memory overhead consideration.
figure The Booth decoder generates the partial products
FFT
outputs
to
the
according to the logic diagram using the encoded signals
4. REORDERING OF THE OUTPUT SAMPLES:
and the other input X. The carry save tree computes the
Reordering of the output samples is an inherent
last two rows by adding the generated partial products.
problem in FFT computation. The outputs are
The last two rows are added to generate the final
obtained in the bit-reversal order [5] in the serial
multiplication results using the carry save addition.
architectures. In general the problem is solved using a memory of size . Samples are stored in the memory in natural order using a counter for the addresses and then they are read in bit-reversal order by reversing the bits of the counter. In embedded DSP systems, special memory addressing schemes are developed to solve this problem. But in case of real-time systems, this will lead to an increase in latency and area. The
Fig: Modified Booth Encoder
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6.RESULT:
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designed and experimental results are obtained with XILINX. REFERENCES: [1] J. W. Cooley and J. Tukey, “An algorithm for machine calculation of complex fourier series,” Math. Comput., vol. 19, pp. 297–301, Apr. 1965. [2] A. V. Oppenheim, R.W. Schafer, and J.R.Buck, Discrete-Time Singal Processing, 2nd ed. Englewood Cliffs, NJ: Prentice-Hall, 1998. [3] P. Duhamel, “Implementation of split-radix FFT algorithms for complex, real, and real-symmetric data,” IEEE Trans. Acoust., Speech, Signal Process., vol. 34, no. 2, pp. 285–295, Apr. 1986. [4] S. He and M. Torkelson, “A new approach to pipeline FFT processor,” in Proc. of IPPS, 1996, pp. 766–770. [5] L. R. Rabiner and B. Gold, Theory and Application of Digital Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1975. [6] E. H. Wold and A. M. Despain, “Pipeline and parallel-pipeline
FFT
processors
for
VLSI
7. CONCLUSION: Finally, This paper describes the
implementation,” IEEE Trans. Comput.,vol. C-33,
design of two new fused floating-point arithmetic
no. 5, pp. 414–426, May 1984.
units and their application to the implementation of
[7] A. M. Despain, “Fourier transfom using CORDIC
FFT butterfly operations. Although the fused add-
iterations,” IEEE Trans. Comput., vol. C-233, no. 10,
subtract unit is specific to FFT applications, the fused
pp. 993–1001, Oct. 1974.
dot product is applicable to a wide variety of signal
[8] E. E. Swartzlander, W. K. W. Young, and S. J.
processing applications. Both the fused dot product
Joseph, “A radix-4 delay commutator for fast Fourier
unit and the fused add-subtract unit are smaller than
transform processor implementation,” IEEE J. Solid-
parallel implementations constructed with discrete
State Circuits, vol. SC-19, no. 5, pp. 702–709, Oct.
floating-point adders and multipliers. The fused dot
1984.
product
conventional
[9] E. E. Swartzlander, V. K. Jain, and H. Hikawa,
implementation, since rounding and normalization is
“A radix-8 wafer scale FFT processor,” J. VLSI
not required as a part of each multiplication. Due to
Signal Process., vol. 4, no. 2/3, pp. 165–176, May
longer interconnections, the fused add-subtract unit is
1992.
slightly slower than the discrete implementation. An
[10] G. Bi and E. V. Jones, “A pipelined FFT
efficient and more flexible architecture of FFT is
processor for word-sequential data,” IEEE Trans.
is
faster
than
the
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Acoust., Speech, Signal Process., vol. 37, no. 12, pp. 1982–1985, Dec. 1989. [11] Y. W. Lin, H. Y. Liu, and C. Y. Lee, “A 1-GS/s FFT/IFFT processor for UWB applications,” IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1726–1735, Aug. 2005. [12] J. Lee, H. Lee, S. I. Cho, and S. S. Choi, “A High-Speed two parallel radix- FFT/IFFT processor for MB-OFDM UWB systems,” in Proc. IEEE Int. Symp. Circuits Syst., 2006, pp. 4719–4722. [13] J. Palmer and B. Nelson, “A parallel FFT architecture for FPGAs,” Lecture Notes Comput. Sci., vol. 3203, pp. 948–953, 2004. [14] M. Shin and H. Lee, “A high-speed four parallel radix- FFT/IFFT processor for UWB applications,” in Proc. IEEE ISCAS, 2008, pp. 960–963. [15] M. Garrido, “Efficient hardware architectures for the computation of the FFT and other related signal processing algorithms in real time,”Ph.D. dissertation, Dept. Signal, Syst., Radio commun., Univ. Politecnica Madrid, Madrid, Spain, 2009.
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A DESIGN OF FPGA WITH LEDR ENCODING AND DUAL RAIL ARCHITECTURE K.Swapna(1), M.TECH Student, DEPARTMENT of ECE, Shri Vishnu Engg college for women V.Valli(2), ASST.PROFESSOR, DEPARTMENT of ECE, Shri Vishnu Engg college for women
Abstract: This project proposed design of asynchronous FPGAs presented with power optimization techniques. The important challenge in IC industry is low power consumption, low cost, better timing. Asynchronous FPGAs having advantage is low power consumption. Proposing two techniques here to reduce power consumption. One is fine grain power gating and reducing the dynamic power by using the level encoding dual rail (LEDR) architecture. Generally power consumptions are two types, static and dynamic. If consider fine grain power gating it consists of sleep resistor and a controller. When a lookup table is inactive, it automatically goes to sleep mode. LEDR encoding is used to data flow at the input and output of FPGAs. Keywords: LEDR, FPGA, lookup table. I
INTRODUCTION A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing â&#x20AC;&#x201C; hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an applicationspecific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare). Contemporary
FPGAs have large resources of logic gates and RAM blocks to implement complex digital computations. As FPGA designs employ very fast I/Os and bidirectional data buses it becomes a challenge to verify correct timing of valid data within setup time and hold time. Floor planning enables resources allocation within FPGA to meet these time constraints. FPGAs can be used to implement any logical function that an ASIC could perform. The ability to update the functionality after shipping, partial re-configuration of a [1] portion of the design and the low nonrecurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications.[2] On the other hand, FPGAs are cost-effective and flexible since FPGAs consist of programmable logic blocks and pro-gram able switch blocks to make design modifications after production. The major disadvantage of FPGAs is its low performance because of the following reasons. 1. The area and delay of a switch block become large for a switch block consists of many programmable switches. 2. The time for data transfer between logic blocks becomes large since data from one logic block usually traverse through FPGAs are programmable, so they allow product differentiation. Selecting an appropriate FPGA architecture is critical in achieving the best static and dynamic power consumption. Flash-
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based FPGAs by Micro semi are the lowpower leaders in the industry. In addition to utilizing the low-power attributes of flashbased FPGAs, you can deploy several design techniques to further reduce overall power. The important FPGA power components to consider in The following sections: Power-up (inrush power): Inrush power is the amount of power drawn by the device during power-up. And Configuration power: Configuration power is the amount of power required during the loading of the FPGA upon power-up (specifically to SRAM-based programmable logic devices).
II
FINE GRAIN POWER GATING Overcome the problems of coarse grain power gating, we introduce the Fine grain power gating technique. In fine grain power gating technique each lookup table having own sleep controller and related to sleep transistor, so any of the lookup table active states all other lookup tables are going to sleep state [l]. In this paper reduce the both standby power and dynamic power. Asynchronous Architecture Design The asynchronous architecture, it detects the activity of a power gated domain. The activities are: 1) To determine Logic block is standby state, when sleep state & when Active state. 2) It compares the phase of the input data and Output data 3) It determines the function of lookup table. Dynamic power, reducing purpose introduce dual rail encoding (existing) [2] and level encoding dual rail (proposed) architecture. Standby power, reducing purpose introduced autonomous fine grain power gating technique. III
DUAL RAIL ENCODING They use four-phase dual-rail encoding because of relatively small hardware cost. In four-phase dual-rail encoding, a spacer must be inserted between two consecutive valid data Values. This
ISBN : 978 - 1502851550
results in low throughput and high dynamic power consumption because of the large number of signal transitions.
Fig 1.0 Dual and single rail encoding
IV
FPGA Field Programmable Gate Arrays are two dimensional array of logic blocks and flipflops With a electrically programmable interconnections between logic blocks. The interconnections consist of electrically programmable switches which is why FPGA differs from Custom ICs, as Custom IC is programmed using integrated circuit fabrication technology to form metal interconnections between logic blocks. In an FPGA logic blocks are implemented using multiple level low fan-in gates, which gives it a more compact design compared to an implementation with two-level AND-OR logic. FPGA provides its user a way to configure: 1. The intersection between the logic blocks and 2. The function of each logic block. Logic block of an FPGA can be configured in such a way that it can provide functionality as simple as that of transistor or as complex as that of a microprocessor. It can used to implement different combinations of combinational and sequential logic functions. Logic blocks of an FPGA can be implemented by any of the following: 1. Transistor pairs 2. Combinational gates like basic NAND gates or XOR gates 3. n-input Lookup tables 4. Multiplexers 5. Wide fan-in And-OR structure.
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Routing in FPGAs consists of wire segments of varying lengths which can be interconnected via electrically programmable switches. Density of logic block used in an FPGA depends on length and number of wire segments used for routing. Number of segments used for interconnection typically is a tradeoff between density of logic blocks used and amount of area used up for routing. The ability to reconfigure functionality to be implemented on a chip gives a unique advantage to designer who designs his system on an FPGA It reduces the time to market and significantly reduces the cost of production.
Fig 2.0 FPGA architecture
V
ISBN : 978 - 1502851550
LEDR ENCODING DESIGN
Fig 3.0 Architecture of LEDR
This architecture operation based on data's and phase signal. The D latch signal given to selectors and selectors produce the output of level encoding signal. In LEDR encoding, no spacer is required. Table 1 shows the code table of LEDR encoding. In LEDR encoding, each data value has two types of code words with different phases. Above example shows the data values "0,""0," and " 1" are transferred. The main feature is that the sender sends data values alternately in phase 0 and phase 1. Because no spacer is required, the number of signal transitions is half of four phase dual-rail encoding. As a result, the throughput is high and the power consumption is small. Based on this observation, in the proposed FPGA, LEDR encoding is employed for implementing the asynchronous architecture to reduce the dynamic power.
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FULL ADDER SIMULATION RESULT The full adder logic block in the full adder circuit there are two Xor gate and two AND gate and one OR gate are used to perform the full adder. The corresponding logic blocks are active state all other logic blocks are sleep state. The first logic block worked on Xor gate that time the same logic
ISBN : 978 - 1502851550
VI
VI
block generate the sleep signal is zero. The output of the first logic block and third input given to the next logic block that time the second logic block worked on Xor operation and sleep signal is one its given to the third logic block, so the third logic block goes to sleep state
POWER REPORT
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VI I
CONCLUSION
This paper consists of an autonomous finegrain power gating with small overheads of an asynchronous FPGA architecture has been developed and analyzed. The implementation of the FPGA has been done efficiently using the standby power to wake up the Logic block before the data arrives and power OFF the Logic block only when the data does not come for quite a while. As
ISBN : 978 - 1502851550
[7] E. Sutherland, “Micropipelines,” Commun. ACM, vol. 32, no. 6, pp. 720–738, Jun. 1989. [8] R. Hosain, L. D. Wronshi, and A. albicki, “Low power design using double edge triggered flipflop,” IEEE Trans. Very Large Scale Integr. (VLSI ) Syst., vol. 2, no. 2, pp. 261–265, Jun. 1994. architecture," in
Proc. IEEE Asian Solid-State Circuits Conf. (ASSCC), Jeju, Korea, Nov. 2007, pp. 380-383.
a result, the wake-up time has been reduced. Since their data paths change dynamically and frequently, it is more difficult than FPGAs to determine the transistors for each Logic block using offline analysis. The power analysis also has been carried out and it has been found that using the proposed fine-grain power gating method, the FPGA consumes 7 m W powers
REFERENCES [I] Masanori Hariyama, "A Low Power FPGA Based on FineGrain Power Gating Shota Ishihara, Student Member," IEEE Trans. (VLSI) Systems, Vol. 1 9, No. 8, August 20 1 1 . [2] J. Teifel and R . Manohar, "An asynchronous dataflow FPGA architecture," IEEE Trans. Computers, vol. 53, no. 1 1 , pp . 1 376-1 392, Nov. 2004. [3] M. Hariyama, S. Ishihara, C.c. Wei and M. Kameyama, "A field programmable VLSI based on an asynchronous bitserial. [4] W. Li and L.Wanhammar, “A pipeline FFT processor,” in Proc. Workshop Signal Process. Syst. Design Implement., 1999, pp. 654–662. [5] E. K. Tsern and T. H. Meng, “A low-power videorate pyramid VQ decoder,” IEEE J. Solid- State Circuits, vol. 31, no. 11, pp. 1789–1794, Nov. 1996. [6] N. Shibata, M.Watanabe, and Y. Tanabe, “A currentsensed high-speed and low-power first-infirst- out memory using a wordline/bitline- swapped dual-port SRAM cell,” IEEE J. Solid-State circuits, vol. 37, no. 6, pp. 735–750, Jun. 2002.
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ISBN : 978 - 1502851550
WAVELET TRANSFORM BASED LATENCY OPTIMIZED IMAGE COMPRESSION FOR LOW DENSE APPLICATIONS 1 1 2
.K.Sindhu,2.M.pradeep
M.tech, sindhukodali777@gmail.com, VLSI, Shri Vishnu Engineering College for Women
. M.tech (phD), Assoc.Prof,pradeepm999@gmail.com,E.C.E, Shri Vishnu Engineering College for Women
ABSTRACT: The main objective of this project is to
the results are not optimal. In lossless compression,
compress an image using advanced wavelet filters.
the data (such as executables, documents, etc.) are
This project involves application of discrete wavelet
compressed such that when decompressed, it gives an
transform (DWT) which has significant advantages
exact replica of the original data. They need to be
over real wavelet transform for certain image
exactly
processing problems. The proposed architecture,
example, the popular PC utilities like Winzip or and
based on new and fast convolution approach, reduces
Adobe Acrobat perform lossless
the hardware complexity in addition to reduce the
compression. Compression can be done in many
critical path to the multiplier delay. Furthermore, an
ways as below mentioned.
advanced two dimensional (2-D) discrete wavelet
Spatial Redundancy is the correlation between
transform (DWT) implementation, with an efficient
neighboring pixel values.
memory area, is designed to produce one output in
Spectral Redundancy is the correlation between
less number of clock cycles.
different color planes or spectral bands.
KEYWORDS: Discrete wavelet transforms (DWT),
Temporal Redundancy is the correlation between
Convolution, Filter, FIFO, Embedded Zero Tree,
adjacent frames in a sequence of images (in video
Entropy, Quantizer.
applications).
INTRODUCTION: of the most used techniques for
reducing the number of bits needed to represent an
image compression and is applied in a large category
image by removing the spatial and spectral
of applications [1]. DWT can provide significant
redundancies. The compression phase is mainly
compression ratios without great loss of visual
divided into three sequential steps: (1) Discrete
quality than the previous techniques such as the
Wavelet Transform, (2)Quantization, and (3) Entropy
Discrete Cosine Transform (DCT) and the Discrete
Encoding. After preprocessing, each component is
Fourier Transform (DFT). The DWT present the
independently analyzed by an appropriatediscrete
main part of the JPEG2000 standard, which permits
wavelet transform. For an efficient compression all
both lossy and lossless compression of digital
above techniques are utilized.
images. It allows an
The
encoded image to be
reproduced
Image
computational
when
decompressed.
compression
block
focuses
diagram
of
For
on
the
reconstructed progressively. Image compression is
functionalities of the compression system is shown in
different from binary data compression. When binary
Fig. 1
data compression techniques are applied to images,
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Wavelet-based Compression
Filter
Quantizer
Entropy Encoder
Digital image is represented as a two-dimensional array of coefficients, each coefficient representing the brightness level in that point. Most natural images
Fig1
have smooth color variations, with the fine details
Lifting and convolution present the two computing
being represented as sharp edges in between
approaches to achieve the discrete wavelet transform
the smooth variations. Technically, the smooth
[3].While conventional lifting-based architectures
variations in color can be termed as low frequency
require fewer arithmetic operations compared to the
variations, and the sharp variations as high frequency
convolution-based
variations.
approach
for
DWT,
they
sometimes have long critical paths. IfTa and Tm are
The low frequency components (smooth variations)
the delays of the adder and multiplier, respectively,
constitute the base of an image, and the high
then the critical path of the lifting-based architecture
frequency components (the edges which give the
for the (9,7) filter.
details) add upon them to refine the image, thereby
Principles of Image Compression
giving a detailed image. Hence, the smooth variations
A typical lossy image compression scheme is shown
are more important than the details. Separating the
in Figure 1. The system consists of three main
smooth variations and details of the image can be
components, namely, the source encoder, the
performed in many ways.
quantizer, and the entropy encoder.
decomposition of the image using the discrete
source encoder An encoder is the first major
wavelet transform.
component of image compression system. A variety
The basic difference between wavelet-based and
of linear transforms are available such as Discrete
Fourier-based techniques is that short-time Fourier-
Fourier Transform (DFT), Discrete Cosine Transform
based techniques use a fixed analysis window, while
(DCT), and Discrete Wavelet Transform (DWT). The
wavelet-based techniques can be considered using a
Discrete Wavelet Transform is main focus of our
short window at high spatial frequency data and a
work.
long window at low spatial frequency data. This
Quantizer A quantizer reduces the precision of the
makes DWT more accurate in analyzing image
values generated from the encoder and therefore
signals at different spatial frequency, and thus can
reduces the number of bits required to save the
represent more precisely both smooth and dynamic
transform co coefficients.
regions in image. Wavelet-based image compression
Entropy Encoder An entropy encoder does further
has good compression results in both rate and
compression on the quantized values. This is done to
distortion sense.
achieve even better overall compression. The
DISCRETE WAVELET TRANSFORM:
commonly used entropy encoders are the Huffman
One-Dimensional Discrete Wavelet Transform The
encoder, arithmetic encoder, and simple run-length
basic DWT can be realized by convolution-based
encoder.
implementation using the FIR-filters to do the
One way is the
transform. Theinput discrete signal X(n) is filtered by
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3
Two-level
ISBN : 978 - 1502851550
a low-pass filter (h) and a high-pass filter (g) at each
Fig.
multi-resolution
transform level. The two output streams are then sub-
decomposition
sampled by simply dropping the alternate output
FAST
samples in each stream to produce the lowpass
WAVELET TRANSFORM ARCHITECTURE:
subband YL and high-pass subband YH. The
There are many implementations of the convolution-
associated equations can be written (1).
based DWT [15]-[18]. A semi-systolic form of a
CONVOLUTION-BASED
wavelet
DISCRETE
VLSI architecture has been proposed by Acharya and Chen [15]. The proposed architecture, based on new and
fast
convolution
approach,
presents
an
Fig. 2 shows the signal analysis and reconstruction in
implementation of a very high-speed discrete wavelet
onedimensional (1-D) Discrete Wavelet Transform.
transform with reduced hardware complexity and memory. The main principle of the architecture can be applied to implement any symmetric filter. The (9, 7) wavelet filter presents the developed example. These (9, 7) filter has 9 lowpass filter coefficients h =
Fig. 2 Signal analysis and reconstruction in DWT Two-Dimensional Discrete Wavelet Transform For two-dimensional (Image) analysis and reconstruction the multi-resolution approach for Discrete Wavelet decomposition of signals using a pyramidal filter structure proposed by Mallat can be adopted. Fig. 3 shows
the
twolevel
multi-resolution
wavelet
decomposition of signals using pyramidal filter structure.
{ h-4 , h-3 , h-2 , h-1, ho, h1 , h2 ,h3, h4} and 7 high-pass filter coefficients g = { g-2 , g-1, go, g1, g2 , g3 , g4}. The architecture to compute the YLi and YHi is shown in Fig. 4. Additional registers are added, between multipliers and adders, to speed up the computing. The critical path is reduced to the multiplier delay (Tcm). Furthermore, the outputs YLi and YHi are obtained alternately at the trailing edges of the even and odd clock cycles. (e.g., YL0, YL1, YL2, â&#x20AC;Ś.. are obtained at clock cycles 9, 11, 13, . . . and YH0, YH1, YH2, â&#x20AC;Ś are obtained at clock cycles 8, 10, 12, .. . respectively).
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Embedded Zero Tree Encoding Technique
ISBN : 978 - 1502851550
RESULT:
The image compression scheme using wavelet transform consists of the following procedure: •Decomposition of signal using filters
banks.
•Down sampling of Output of filter bank. •Quantization of the above. •Finally encoding. The Embedded Zero tree (EZT) wavelet algorithm was invented by Shapiro in 1993. Basically a wavelet transform on an image leads to the formation of sub bands. The EZT algorithm exploits the self similarity of coefficients in different wavelet bands. The algorithm is in such a way that it takes care of the intermediate quantization process. In this scheme, the lower rate codes or the averages (LL) are embedded at the beginning of the bit stream
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[6] J. NEUMANN and G. STEIDL. Dual–tree PARAMETER
EXISTING
PROPOSED
complex wavelet transform in the frequency domain
AREA
4258
3988
and
TIME
3.56(ns)
2.14(ns)
International Journal of Wavelets, Multiresolution
an
application
to
signal
classification.
and Information Processing IJWMIP, 2004. CONCLUSION: Finally, this project presents a parallel architecture for very high-speed computing Discrete Wavelet Transform using SRAM and FIFO memory. This concept introduced the basic wavelet theory used for wavelet transform based image compression. To produce one output in every clock cycle in addition to reduce the critical path as well as more efficient memory area, new fast convolutionbased architecture approach is performed. In this approach, the system stars the column-processing as soon as sufficient numbers of rows have been filtered. Two fast convolution based blocks, for the two-dimensional (2-D) discrete wavelet transform (DWT), are used to accelerate the computing
[8] J. K. ROMBERG, H. CHOI, R. G. BARANIUK, and N. G. KINGSBURY. Hidden Markov tree models for complex wavelet transforms. Tech. Rep., Rice University, 2002. [9] Q. P. Huang, R. Z. Zhou, and Z. L. Hong, “Low memory and low complexity VLSI implementation of JPEG2000 codec,” IEEE Trans.Consum. Electron., vol. 50, no. 2, pp. 638–646, May 2004. [10] Descampe, A, et al: A Flexible, Hardware JPEG 2000 Decoder for Digital Cinema. IEEE Transactions on Circuits and Systems for Video Technology, Vol. 16, No 11. (2006) 1397-1410.
Q. Zeng “VLSI Design of a High-Speed and Area-
REFERENCES: [1] A. K. JAIN. Fundamentals of Digital Image
[2] N. G. KINGSBURY. The dual-tree complex wavelet transform: a new technique for shift invariance and directional filters . In Proceedings of the IEEE Digital Signal Processing Workshop, 1998. [3] N. G. KINGSBURY. Image processing with wavelets.
Phil.
Efficient JPEG2000 Encoder,” IEEE Trans. Circuits Syst. Video Technol., vol. 17, no. 8, pp. 1065–1078,
Processing. Prentice Hall, 1989.
Trans.
Royal
SocietyLondon, 1999. [4] N. G. KINGSBURY. A dual-tree complex wavelet transform with improved orthogonality and symmetry properties . In Proceedings of the IEEE Int. Conf. on Image Proc. (ICIP), 2000. [5] J. S. LIM. Two-Dimensional Signal and Image Processing. Prentice-Hall, Englewood Cliffs, NJ, 1990.
Wiley, Inc., 2001.
[11] K. Z. Mei, N. N. Zheng, C. Huang, Y. Liu, and
operations.
complex
[7] W. K. PRATT. Digital Image Processing. John
Agu. 2007. [12]
JPEG2000
Decoder:
BA109JPEG2000D
Factsheet.Barco-Silex. (2008). [13] JPEG 2000 Video CODEC (ADV212). Analog Devices. (2008). [14] CS6510 JPEG2000 Encoder Amphion Inc. [Online]. Available: http://www.amphion.com [15] Acharya, T., Chen, P.: VLSI Implementation of a DWT Architecture. Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS). Monterey, CA. (1998).[16] Acharya, T.: Architecture for Computing a Two-Dimensional Discrete Wavelet Transform. US Patent 6178269. (2001).
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POSITION CONTROL OF SERVO SYSTEMS USING PID CONTROLLER TUNING WITH SOFT COMPUTING OPTIMIZATION TECHNIQUE P.RAVI KUMAR M.Tech (control systems) Gudlavalleru engineering college Gudlavalleru,Andhra Pradesh,india Pravikumara9@gmail.com
V.NAGA BABU ASSISTANT PROFESSOR Gudlavalleru engineering college Gudlavalleru,Andhra Pradesh,india Nagababu243@gmail.com
Abstract: in this paper, position control of servo motor using PID controllers with soft computing optimization techniques is discussed .PID controllers widely used in the industry. Different methods are available for tuning the PID controllers. In this paper ZN method, GA and PSO are used for the position control of the servo motor. KEY WORDS: servo motor, position control, tuning methods, ZN, GA and PSO methods. INTROUDUCTION
Position control systems are normally unstable when they are implemented in closed loop configuration. Now a day’s PID controllers are widely used in the industry. About 85-90% of the controllers are used in the industry are of PID type.PID controllers tuning for positional control systems is a time consuming task , therefore much effort has been given to analyse the servo systems. The main aim of this paper is to analyse the soft computing methods and enumerate their advantages over conventional PID tuning methodologies. Position control of a 3 rd ordered plant (Servomotor) using Conventional and soft computing methods with their comparisons is analysed. Conventional PID tuning method Ziegler-Nichols, soft computing methods like genetic algorithm and PSO is used for the position control of servo systems. Except for miner difference in constructional features a dc servo motor is essentially an ordinary dc motor. Physical requirements of servo motor are Low inertia and High starting torque. Low inertia is attained with reduced armature diameter with consequent in armature length such that the desired power output is reached.
SYSTEM MODELLING In this paper considering an armature controlled dc motor. In this dc servo motor can be consider as a linear SISO system having 3 rd order transfer function. Relation between shaft position and armature voltage is derived from the physical laws. The air gap flux is given by k f if Torque is proportional to product of Flux and Armature current
T k1I a (t ) Or T k1k f I f (t ) I a (t ) T K m I a (t ) Back EMF of the motor is given by Vb kb
FIG1: separately exited dc motor By apply Laplace transform to the armature loop ( )= ( )+ ( )+ ( )
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Where Vb(s) is back EMF voltage proportional to the motor speed. Therefore, we have ( )= ( ) The armature current is expressed as ( )− ( ) ( )= + The motor torque is expressed as ( ) = ( )+ ( ) Where Tl is the load torque ( )= ( )+ ( ) The relation between speed and position is given by ( )= ∗ ( ) The above equations can be represent in a block diagram as
ISBN : 978 - 1502851550
the formulas Kp=0.6*Ku ,Ki=Kp/Ti ,Kd=Kp*Td . Kp, Ti, Td are calculated using the formulas given in below table Control type P PI
kp
Ti
Td
0.5 Ku 0.45 1.6(Kp/Ku) Ku PID 0.6 Ku 2*(Kp/Ku) (Kp/Ku) The advantage of this method is applying easy rules to simple mathematical models. But the disadvantage of this method is Do not provide as good results as expected.
GENETIC ALGORITHM: A genetic algorithm is a powerful searching capabilities and heuristic characteristics. GA has also been used in control tuning applications, being shown to obtain better results than classical techniques
Fig2 :equivalent block diagram From the above block diagram the relation between shaft position and armature obtained as by assuming the Td=0, ( ) = ⌈( ( )
+
)(
+ )+(
)⌉
J=0.01kg/ ,b=0.1n.m.s, kb=0.01 v/rad/sec, km=0.01n.m/amp, Ra=1 ohm,L=0.5H Substitute above values in the above equation, ( ) = ( ) 0.005
0.01 + 0.06 + 0.1001
ZN Method: Set Kd=0 and Ki=infinity. ku and Pu are determined by using R-H criteria. Ku is
determined by equating the row containing ‘s’ in R-H row to zero. Pu is determined b equating the row containing ‘s^2’ in R-H row to zero. Evaluate parameters described by Z-N method. Find kp, ki ,and kd using
The components of GA are A problem definition as input, and encoding principles (gene, chromosome), initialization procedure followed by cross over, mutation and selection operators for reproduction with the help of an objective function. Simple Genetic Algorithm: { Initialize population; Evaluate population; While Termination Criteria Not Satisfied { Select parents for reproduction; Perform recombination and mutation; Evaluate population; } }
GA parameters: In this paper the following genetic algorithm parameters are used
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parameters
Values [0 0 0] [100 100 100] Stopping criteria 100 Population size 40 Cross over fraction 0.4 Mutation fraction 0.08 These are the parameters of the genetic algorithms.
ISBN : 978 - 1502851550
FLOW CHART OF PSO
Lower bounds [kp ki kd] Upper bounds [kp ki kd]
PSO PSO is a robust stochastic optimization technique based on the movement and intelligence of swarms. The components of PSO are Swarm Size, Velocity, position components and maximum no of iteration. Here I have consider the
following objective function F=(1-exp(-0.5))*(Mp+Ess)+exp(-0.5)*(ts-tr) Algorithm of PSO
1. Create an initial population of particles with random positions and velocities within the solution space. 2. For each particle, calculate the value of the fitness function. 3. Compare the fitness of each particle with local- best. If current solution is better than its local- best, then replace its local best by the current solution. 4. Compare the fitness of all the particles with global best. If the fitness of any particle is better than global-best, then replace global-best. 5. Update the velocity and positions of all particles using velocity update equations. 6. Repeat steps (2)-(5) until a stopping criterion is met.
Block diagram of servo motor with PID controllr :
Fig3: Block diagram of servo motor
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STEP RESPONSE OF Z-N METHOD:
Fig4: Step response of Z-N method STEP RESPONSE OF GA
Fig 5:step response of GA STEP RESPONSE OF PSO
Fig 6:step response of PSO
Fig7: Comparisons of all Wave forms Comparisons of all methods GA parameters ZN PSO Settling 5.0139 1.6 0.56 time(sec) Rise 0.2901 0.25 0.35 time(Sec) Peak over 61.74 30 3 shoot (%) ISE 0.43 0.0847 0.1539 IAE 0.153 0.1905 0.4312
CONCLUSION: By comparing the all methods PSO gives better response in terms of performance indices. Also for the position control of servo systems the genetic algorithm method gives better response. This may be extending by using advanced genetic algorithm, particle swarm optimization and also using evolutionary algorithms. References: 1. DC motor angular position control using PID controller for the purpose of controlling the hydraulic pump. International conference on control, Engineering &information technology (ICIT13). 2. modelling and control of motorized robotic arm using hybrid PSO algorithm.2012 nimra university
Comparisons of all Wave forms
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international conference on engineering (NUICONE-2012) 3. Emphasis on genetic algorithm (GA) over different PID tuning methods for controlling the servo systems using MATLAB. International journal of scientific research in computer science engineering. 4. Dc motor control by using genetic algorithm. International journal of digital applications & contemporary research 2012. 5. Design and implementation of discrete augmented Ziegler-Nichols PID controller.(ACEEE international journal of control systems and instrumentation- 2013)
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VLSI Implementation of Spatial Modulation Receiver Irshad begum Mohammad M.Tech.,(VLSID) Student Shri Vishnu Engineering College for Women Bhimavaram, AndhraPradesh, India e-mail ID: md.irshadbegum@gmail.com Abstractâ&#x20AC;&#x201D;In this paper, a new transmission approach, called Spatial Modulation(SM) is presented. The use of multiple antennas at the transmitter and receiver sides (MIMO) can significantly enhance the capacity and reliability of wireless links. Spatial modulation (SM) is a relatively new modulation technique for multiple antenna systems which addresses these issues.In SM, the stream of bits to be transmitted in one channel is divided into two groups. One group i.e., m-bit sequence chooses one antenna from a total of Nt =2m antennas. A known signal is transmitted on this chosen antenna. The remaining Nt-1 antennas remain silent. The second group determines the symbol to be transmitted from the chosen antenna. By doing so, the problem of detection at the receiver becomes one of merely finding out which antenna is transmitting. This leads to a significantly reduced complexity at the Receiver. We have implemented the design of SMMIMO receiver in VLSI with low complexity and achieved high performance. Keywords- Spatial Modulation, MIMO systems, IEEE-754 single precision floating point numbers, Complex number multiplication, Floating point adder/subtractor.
.
I.INTRODUCTION
MIMO is an acronym that stands for Multiple Input Multiple Output. MIMO technology utilizes multiple antennas at both transmitter and receiver terminals.The need to improve the spectral efficiency and reliability of radio communication is driven by the ever increasing requirement for higher data rates and improved Quality of service (QOS) across wireless links. MIMO technology is one solution to attain this by transmitting multiple data streams from multiple antennas [1]. MIMO transmission strongly depends on transmit and receive antenna spacing, transmit antenna synchronization and the reduction of interchannel interference (ICI) at the receiver input. An alternative transmission approach that entirely avoids ICI at the receiver input is used for BPSK and QPSK transmission respectively. The basic idea is to compress a block of Nt symbols into a single symbol prior to transmission, where Nt indicates the number of transmit antennas. Information is retained by this symbol
Pushpa Kotipalli Professor: ECE Department, Head of ATL Shri Vishnu Engineering College for Women Bhimavaram, AndhraPradesh, India e-mail ID: pushpak@svecw.edu.in and is mapped to one and only one of the Nt antennas. The task of the receiver is twofold: First, to estimate the single symbol and second to detect the respective antenna number from which the symbol is transmitted. However this scheme suffers from a loss of Spectral efficiency. Traditional modulation techniques such as BPSK (binary phase shift keying), QPSK (Quadrature phase shift keying) etc. map a fixed number of information bits into one symbol. Each symbol represents a constellation point in the complex two dimensional signal planes. This is referred to as signal modulation. In this paper an alternative transmission approach is proposed in which this two dimensional plane is extended to a third dimension i.e., spatial dimension. This is referred as Spatial modulation. This new transmission technique will result in a very flexible mechanism which is able to achieve high spectral efficiency and very low receiver complexity. Spatial modulation (SM) is introduced by Mesleh in an effort to remove ICI, and the need for precise time synchronization amongst antennas. SM is a pragmatic approach for transmitting information, where the modulator uses well known modulation techniques (e.g., QPSK, BPSK), but also employs the antenna Index to convey information. Ideally, only one antenna remains active during transmission so that ICI is avoided. Spatial Modulation (SM) is a recently proposed spatial multiplexing scheme for Multiple-InputMultiple-Output (MIMO) systems without requiring extra bandwidth or extra transmission power. SM does not place any restriction on the minimum number of receive-antennas. This is particularly beneficial for mobile handsets because of the limited available space and the cost constraints for these mass market devices. All these properties and requirements make SM a very attractive MIMO scheme for many potential applications. The idea of using the transmit antenna number as an additional source of information is utilized in spatial modulation. The number of information bits that can be transmitted using spatial modulation depends on the used constellation diagram and the given number of transmit antennas. In view of the fact that information is not only included in the transmitted symbol but also in the actual physical location of the antenna. Estimation of transmit antenna number is of key importance. The antenna number may change at the subsequent
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transmission instants, but at any given time only a single transmit antenna is transmitting. The channel vectors between each transmit antenna and the number of receive antennas are considered separately at the receiver. Assuming full knowledge of the channel at the receiver, the receiver chooses the transmit antenna number which gives highest correlation. In addition to eliminating ICI at the receiver [5], spatial modulation produces no correlation between the transmit antennas and it requires no synchronization between them. On the other hand, lack of synchronization is shown to have a major effect on system performance. Furthermore, in spatial modulation, the symbol duration is unchanged while the transmitted symbol carries a higher number of information bits due to the novel extension of modulation to the spatial domain. As a result, an improvement in spectrum efficiency is obtained.
II.SYSTEM MODEL This paper is organized as follows: In section II System model is discussed, in section III hardware implementation is discussed, section IV is simulation results and section V is conclusion. We consider a generic Nt × Nr Multiple-InputMultiple-output (MIMO) system with Nt and Nr being the number of transmit and receive antennas respectively[2]. Moreover, we assume that the transmitter can send digital information via M distinct signal waveforms (i.e., the so-called signalconstellation diagram).
Fig1: MIMO System with Nt Transmit Antennas and Nr receive antennas
The basic idea of SM is to map block of information bits into two information carrying units. 1.
A symbol is chosen from a complex signal constellation diagram. 2. A unique transmit antenna index is chosen from the set of transmit antennas in the antenna-array. The principal working mechanism of SM is depicted in fig 2:
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Fig 2: Three dimensional constellation diagram of SM
Each Spatial constellation point defines an independent complex plane of signal constellation points. For illustrative purpose only two of such planes are shown in Fig2. For i) Nt =4 and ii) M =4 Legend: i) Re = real axis of the signal constellation diagram and ii) Im = imaginary axis of the signal constellation diagram. The spatial modulation system model is shown in Fig 3. q (k) is a vector of n bits to be transmitted. The binary vector is mapped into another vector x(k). Symbol number l in the resulting vector x(k) is xl , where l is the mapped transmit antenna number l € [1:Nt]. The symbol xl is transmitted from the antenna number l over the MIMO channel, H(k). H(k) can be written as a set of vectors where each vector corresponds to the channel path gains between transmit antenna v and the receive antennas as follows: H = [h1 h2 h3 ….. h Nt] (1) Where: hv = [h1,v h2,v … hNr,v]T (2) The received vector is then given by y(k)=hxl + w(k); Where w(k) is the additive white Gaussian noise vector. The number of transmitted information bits n, can be adjusted in two different ways, either by changing the signal modulation and/or changing the spatial modulation. Different modulation techniques can be used for SM-MIMO such as BPSK, QPSK or 4QAM, 8QAM, 16QAM etc. These modulation techniques will be used to map the information bits to the symbols by using constellation diagrams. These symbols have to be transmitted from the chosen transmitting antennas. For example we consider only BPSK and QPSK modulation techniques for mapping of information bits to the symbols of BPSK and QPSK constellation diagrams.BPSK (Binary Phase Shift Keying) has two symbols +1 and -1 represented by 0 or 1 and QPSK (Quadrature Phase Shift Keying) has four quadtatures with 90 degrees phase shift each. It requires two bits to represent four symbols such as [-1-1i, -1+1i, +1-1i, +1+1i]
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Fig 3: Spatial modulation system model
III. HARDWARE IMPLEMENTATION OF SM-MIMO SYSTEM A. .Transmitter Design of the SM-MIMO System using BPSK/QPSK modulation
The transmitter of the SM-MIMO system has to transmit the symbol and also have to select the antenna for the transmission of the symbol from among the group of antennas. A block of information bits is mapped into the constellation point in the signal and the spatial domain (antenna
Fig 5: Block diagram of MIMO Transmitter
Fig 4: Spatial Modulation Transmitter From the binary source the serially generated binary data will be converted into parallel data. This binary data will be segmented into two groups containing log2 (Nt) +log2(M) bits each, with log2(Nt ) and log2 (M) being the number of bits needed to identify a transmit-antenna in the antenna-array and a symbol in the signalconstellation diagram, respectively. The bits in the first sub-block are used to select the antenna that is switched on for data transmission, while all other transmit-antennas are kept silent in the current signaling time interval. The bits in the second subblock are used to choose a symbol in the signalconstellation diagram using SM Mapper [3] as shown in Fig.4. Then symbol will be transmitted from antenna which is chosen among Nt transmitting antennas as shown in Fig.4. In general, the number of bits that can be transmitted using Spatial modulation is given as follows: n = log2 (Nt) + m (3) m = log2 (M) where â&#x20AC;&#x2DC; Mâ&#x20AC;&#x2122; is the used constellation size.
The SM-MIMO transmitter is implemented in the hardware using multiplexers. The multiplexers are designed in such away to select the antenna and choose the symbol from the input bit sequence based on the modulation technique used. Flip flops and ROM are used to store the binary input bits. If BPSK modulation is considered for symbol mapping, it requires two bits to represent antenna index and four transmit antennas are required. If the modulation is changed to QPSK, it requires only one bit to represent antenna index and hence only two transmit antennas will be sufficient. The Random Binary data which is to be transmitted is stored in an N-bit register. The random binary sequence can be of any length and it is given to the serial to parallel converter. From there we send 3bits parallely to the antenna. This 3-bit vector has the transmitted symbol and also the antenna index. The symbol is modulated using modulation techniques such as BPSK or QPSK. Here we are considering the noise free transmission over the Rayleigh Fading Channel. The number of bits that can be transmitted using spatial modulation is given in equ 3 and it depends on the used modulation technique. Here we consider only BPSK and QPSK modulation techniques. 3bits transmission using 4x4 antenna configuration and 2x4 antenna configuration is shown in Fig.6 & 7.
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Fig 6:
3bits
transmission
using BPSK
Fig 7:
B. SM Wireless Channel The transmission of binary data using spatial modulation is carried out over a Wireless Flat Fading Channel. The channel is a complex matrix of channel path gains. It varies according to the number of antennas and used signal constellation.
3bits
transmission
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using
QPSK
ii) To detect the respective antenna number from which the symbol is transmitted.
Fig 9. Block diagram of Receiver Task
The receiver iteratively computes the maximum ratio combining results between the channel paths from each transmit antenna to the corresponding receive antenna. Assuming to have full knowledge of the channel at the receiver, the receiver chooses the transmit antenna number which gives highest correlation.
Fig 8. SM Wireless Channel C. Receiver design of SM-MIMO systems for BPSK and QPSK modulated transmission Fig 10: Spatial modulation Receiver
The receiver of the SM-MIMO system is having the full knowledge of the channel. The task of the receiver is twofold: i)
To estimate the transmitted symbol and
Assume the following sequence of bits to be transmitted, q(k) = [0 1 1]. Mapping this to BPSK symbol and four transmit antennas results in x(k) = [0,-1,0,0]T. The vector x(k) is transmitted over the MIMO channel H(k). We have to note that only antenna number 2 will be transmitting the symbol xl and the remaining three antennas will be
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transmitting zero energy. The channel matrix for the noise free transmission using BPSK modulation is given as follows.
According to the given sequence the symbol ‘-1’ is detected at antenna 2 and maximum correlation is obtained at that antenna position. The received vector at the receiver input is obtained as follows: y(k) = H(k)xl Where
y(k) =
y(k) =
The resultant is obtained by applying maximum ratio combining to the received vector y(k) and results in g.The obtained resultant g for the received vector y(k) is given as follows:
g =
0.5377+0.1229i 0.5450+0.0964i -0.4624+0.2680i -0.2854+0.1493i
1.0000-1.0000i 0.2978-0.3271i
Hence we can observe from the above resultant vector that maximum correlation is obtained at antenna 1 and it is transmitting the QPSK symbol. The Receiver in the SM-MIMO System has to perform the matrix multiplications and additions of complex numbers between the channel matrix H(k) and the received vector y(k) at the receiver inputs. The number of complex multiplications performed by the receiver is given as Nt Nr and Nt (Nr -1) complex additions. So, the total number of complex operations required is given as:
The obtained resultant g for the received vector y(k) is given as follows:
=
-0.6606+0.4149i -0.6415+0.4486i 0.1944-0.7304i 0.1361-0.4348i
(4)
The resultant is obtained by applying maximum ratio combining to the received vector y(k) and results in g and is given as follows: gj =hjH y, For j = 1 : Nt (5) where g = [ g1 g2 …gNt]T (6)
g
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-0.3124-0.0146 -1.0000 -0.1951+0.0719 -0.1811
Hence we can observe from the above resultant vector that maximum correlation is obtained at antenna 2 and it is transmitting the BPSK symbol. Similarly, for QPSK modulated transmission of 3bits in the Spatial modulation the receiver of the SM-MIMO system functions as follows: Consider another 3bit sequence for transmission, q(k) = [0 1 0].Mapping this to QPSK symbol and two transmit antennas, results in x(k) = [1-i , 0]T. The vector x(k) is transmitted over the MIMO channel H(k). We have to note that only antenna number 1 will be transmitting the symbol xl and the antenna 2 will be transmitting zero energy.The channel matrix H(k) and the noise free transmission for QPSK modulation is given as follows:
The received vector at the receiver input is obtained as follows:
[2Nt Nr – Nt]
(7)
Each complex number of the channel matrix H(k) and the received signal matrix y(k) is first separated to its real part and imaginary part. It is then converted to 32-bit floating point number using the IEEE-754 format. The term floating-point refers to the fact that the decimal point can float, that it is placed anywhere relative to the many digits of the amount. The single precision format is shown in Fig 7.
1
8
SIGN
EXPONENT (E)
23 MANTISSA (F)
Fig 11: Representation of single precision Floating point number.
This format consists of 3fields- a sign bit(s), a biased exponent (E) and a mantissa (F). 1-bit sign, S: A value of ‘1’ indicates that the number is negative, and a ‘0’ indicates a positive number. Bias- 127 exponent, e = E + bias: This gives us an exponent range from Emin = 126 to Emax = 127 Fraction/mantissa: The fractional part of the number significand, which is 1 plus
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the fractional part. The leading 1 in the significand is implicit. Single precision floating point numbers have 1 bit sign bit, 8bit exponent and 23 bit mantissa as shown in Fig 7. Single precision can represent 32 bits. The floating point numbers are represented by the equation which is given as follows: X = (-1)^ s*1.F*2^ (E-127) (7)
Fig.12:Flow chart for floating point multiplication Floating point multiplication process can be given in the algorithmic form as follows: Multiply the significands i.e.(M1*M2) Placing the decimal point in the result. Adding the exponent i.e, (E1+E2-bias). Obtaining the sign, s1 xor s2 Normalizing the result Rounding of the result to fit in an available bit. D. Floating point Adder/Subtractor Floating –point addition has mainly 3 parts: 1. 2. 3.
Adding hidden ‘1’ and Alignment of the mantissas to make exponents equal. Addition of aligned mantissas. Normalization and rounding the result.
The initial mantissa is of 23-bit wide. After adding the hidden ‘1’, it is 24 bit wide. First the exponents are compared by subtracting one from the other and looking at the sign (MSB which is carry) of the result. To equalize the exponents, the mantissa part of the number with lesser exponent is shifted right‘d’ times. Where‘d’ is the absolute value difference between the exponents. The sign of the larger number is anchored. In Normalization, the leading zeroes are detected and shifted so that a leading one comes. Exponent also changes accordingly forming the exponent for the final packed floating point result. The whole process is explained clearly in Fig13.
Fig 13: Architecture for Detection of Symbol by SMMIMO Receiver
The Receiver of the SM-MIMO system has to iteratively perform multiplication operations of the complex numbers between channel matrix H(k) and received signal matrix y(k) for different antennas. The received signal y(k) is different for different symbols of BPSK and QPSK modulation techniques for different transmit antenna numbers. The complex number matrix multiplication is highly optimized in terms of area, speed and power. It is functionally verified in VHDL language and synthesized.
IV. a)
RESULTS
MATLAB Simulation Results
For the purpose of simulation, a flat Rayleigh fading channel is assumed with additive white Gaussian noise (AWGN). The receiver is assumed to have full channel knowledge. Random binary data of length 10,00,000 bits was generated. Let us consider first thirty information bits of transmission data.
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BPSK Modulation
-1
10
-2
10
-3
BER
10
-4
10
-5
10
Fig14: Sampling index vs magnitude plot of first 30 bits of transmitting data For 3bits transmission using QPSK modulation, the 2nd and 3rd bits used for selection of symbol. Those bits will be mapped to QPSK symbol and 1st bit used for choosing the transmitting antenna. So twenty bits are mapped as ten QPSK symbols having magnitude and phase. These symbols have transmitted from the chosen transmitting antenna. The indices of chosen antennas will be transmitted implicitly.
-6
10
0
1
2
3
4
5 6 SNR in dB
7
8
9
10
Fig17: SNR V S BER Plot BPSK System
Additive white Gaussian Noise is added to QPSK symbols. Now by changing the SNR insteps of 1dB from 0dB to 10dB. Corresponding BER values are calculated. It is having maximum BER equal to 0.15 and falling as SNR increases. QPSK Modulation
0
10
-1
10
-2
BER
10
-3
10
-4
10
-5
10
0
1
2
3
4 5 SNR in dB
6
7
8
9
Fig18: SNR Vs BER Plot of QPSK system Fig15: Magnitude and phase plots of QPSK symbols
These QPSK symbols are multiplied by respective path gains while transmitting through wireless channel.
BER for SM-MIMO was calculated at different SNRs. SNR is changed in steps of 2dB from 0dB to 20dB. MATLAB simulations are repeated for QPSK and BPSK modulation techniques with SMMIMO and its BER values are plotted. Spatial Modulation
0
10
BPSK QPSK -1
10
-2
BER
10
-3
10
Fig16: Magnitude and Phase plots of channel effected QPSK symbols
AWGN noise was added to BPSK symbols and received bits are detected and number of errors is detected. This procedure is repeated by changing SNR in steps of 1dB from 0dB to 10dB. It is having maximum BER equal to 0.08 and falling as SNR increases.
-4
10
-5
10
0
2
4
6
8
10 12 SNR in dB
14
16
18
20
Fig19: SNR Vs BER Plots for SM-BPSK and SM-QPSK
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In SM detection errors occur more because information bits are to be recovered from both transmitted symbol and antenna number. The BER for BPSK is less than that of QPSK modulation. b) VLSI SIMULATION RESULTS
Fig23: Detection of BPSK symbol -1 at Antenna-2 by Receiver
Fig20: Detection of BPSK symbol +1 at Antenna-1 by Receiver
Fig24: Detection of BPSK symbol +1 at Antenna-3 by Receiver Fig21: Detection of BPSK symbol -1 at Antenna-1 by Receiver
Fig22: Detection of BPSK symbol +1 at Antenna-2 by Receiver
Fig25: Detection of BPSK symbol -1 at Antenna-3 by Receiver
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Fig26: Detection of BPSK symbol +1 at Antenna-4 by Receiver
Fig27: Detection of BPSK symbol -1 at Antenna-4 by ReceiveR
Fig28: Detection of QPSK symbol +1+i at Antenna-1 by Receiver
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Fig29: Detection of QPSK symbol -1+i at Antenna-1 by Receiver
Fig30: Detection of QPSK symbol +1-i at Antenna-1 by Receiver
Fig31: Detection of QPSK symbol -1-i at Antenna-1 by Receiver
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Fig32: Detection of QPSK symbol 1+i at Antenna-2 by Receiver
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Fig35: Detection of QPSK symbol -1-i at Antenna-2 by Receiver
C) RTL Schematics of BPSK/QPSK Transmitter
Fig33: Detection of QPSK symbol -1+i at Antenna-2 by Receiver
Fig34: Detection of QPSK symbol 1-i at Antenna-2 by Receiver
Fig36: Top module of BPSK Transmitter
Fig37: Internal module of BPSK Transmitter
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Fig41: Technology Schematic of QPSK Transmitter Fig38: Technology Schematic of BPSK Transmitter
D) RTL Schematics of BPSK/QPSK Receiver
Fig39: Top module of QPSK Transmitter
Fig40: Internal module of QPSK Transmitter
Fig42: Top module of QPSK Receiver
Fig43: Total Architecture of QPSK Receiver
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E) Synthesis Report of QPSK/BPSK Receiver Logic Utilization
QPSK Receiver
Number of Slices Number of 4 input LUTs Number of bonded IOBs Number of MULT 18X18SIOs Number of GCLKs Combinational Path delay
BPSK Receiver
[2] R.Mesleh and H.Haas, “ Spatial Modulation-A
4353
8826
8630
17492
897
897
4
4
1
1
93.547ns 143.524ns Fig 44: Comparison Table for BPSK/QPSK Receiver
V.CONCLUSION In this paper, we have implemented the hardware design of the Spatial Modulation MIMO Receiver with low complexity using VLSI technology. It employs the Complex number multiplication and Addition operations between channel matrix and received signal matrix. A novel high rate, low complexity MIMO transmission scheme called Spatial Modulation (SM) that utilizes the spatial information in an innovative fashion has been presented. It maps multiple information bits into a single information symbol and into the physical location of the single transmitting antenna. The task of the receiver is to detect the transmitted symbol and to estimate the respective transmitting antenna. Spatial modulation avoids ICI at the receiver input. In addition, only one RF (radio frequency) chain is required at the transmitter because at any given time only one antenna transmits. Hence the energy efficiency is achieved and the cost of the transmitter is significantly reduced. The Receiver of the SM-MIMO system has been deigned, which computes complex number multiplications with less amount of resources and with low complexity and thereby achieved high performance. REFERENCES
[1] Caijun Zhong “Capacity and Performance Analysis of Advance Multiple Antenna Communication Systems”, London, March 2010.
New Low Complexity Spectral Efficiency Enhancing Technique”, Communication and Networking in China 2006. ChinaCom 06. First International Conference on 25-27, Oct 2006. [3] M. Di Renzo, Member, IEEE, H.Haas, Member, IEEE, Ali Ghrayeb, senior Member, IEEE, and Shinya Sugiura, senior member, IEEE, “Spatial Modulation for generalized MIMO: Challenges, opportunities and implementation. [4] Y.Chau and S-H. Yu, “ Space modulation on Wireless fading Channels,” Proc.IEEE VTC’2001, vol.3, pp. 1668-1671, October 2001. [5] H. Haas, E. Costa, and E. Schulz, “Increasing Spectral Efficiency by Data Multiplexing Using Antenna Arrays”, Proceedings of the International Symposium on personal, Indoor and Mobile Radio Communications (PIMRC 2002), vol. 2, pp.610613, September 15 – September 18 2002. [6] R.Mesleh, H.Haas, Y.Lee, and S.Yun, “Interchannel Interference Avoidance in MIMO Transmission by Exploitng Spatial Information,” Proceedings of the International Symposium on Personal, Indoor and Mobile Radio Communications PIMRC 2005,September 11September 14, 2005 [7] J. Jeganathan, A.Ghrayeb and L.Szczecinski, “Spatial modulation:Optimal detection and performance analysis,” IEEE Commun.Lett.Vol.12, no.8,pp.545-547, July 2009 [8] M.D.Renzo and H.Haas, “Performance analysis of Spatial Modulation,” In Proc. Int. ICST Conf.CHINACOM,Aug.2010,pp.1-7. [9] Pritam Som and A.Chokalingam “A Spatial Modulation and Space shift Keying in Single Carrier Communication”, 2012 IEEE 23rd International Symposium on Personal, Indoor and Mobile Radio Communications – (PIMRC). [10] Y.Chau and S-H.Yu, “Space modulation on Wireless fading Channels”, Proc.IEEE VTC’2001,vol.3,pp. 1668-1671, October 2001. [11] Apple Inc., http://www.apple.com/ (current July 09, 2008. [12]dspLog-Signal Processing for communication, www.dspLog.com [12] G.Even and P.M. Seidel, “A comparison of three rounding algorithms for IEEE floating-point multiplication”, Technical Report EES 1998-8,EES Dep., Tel-Aviv Univ.,1998. http://www.eng.tau.ac.il/Utils/reportlist/reports /repfram.html [13] IEEE standard for binary floating arithmetic. ANSI/IEEE 754-1985, New York, 1985.
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A Decisive Fuzzy Controlled Single switch based Converter for SRM Drive for Wide Speed Range Operation PUVVADA SAI KRISHNA krish0856@gmail.com
D.SRINIVASA RAO dsrinivasarao1993@gmail.com
M-tech Student Scholar Department of Electrical & Electronics Engineering, Gudlavalleru Engineering College, Gudlavalleru; Krishna (Dt); A.P, India.
Associate Professor Department of Electrical & Electronics Engineering, Gudlavalleru Engineering College, Gudlavalleru; Krishna (Dt); A.P, India
Abstract- The design of the fuzzy logic controller is the voltage control action as feedback for significantly improving the dynamic performance of converter. The switches pertaining in reluctance motor (SRM) drive is receiving increasing attentions from various researchers as well as viable candidate for adjustable speed and servo applications. Using the 3-Level converter, switched reluctance drive has a fast magnetization and fast demagnetization to improve dynamic performance and efficiency. High speed drive systems are much interested in the industrial application such as blower, compressor, pump and spindle due to the compact size and high efficiency. In recent, the demands of high speed drives are much increased due to the mechanical advantages of high speed system. SRMs (Switched Reluctance Motors) have simple structure and inherent mechanical strength without rotor winding and permanent magnet. This paper presents a new fuzzy controller design for a switched reluctance motor drive system. One switch for each phase is the least number of switches among the converters used in the switch reluctance motor drive. The simulation results based on Matlab/Simulink are discussed in detail.
permanent magnet (PM) brushless dc motor and induction motor drives.
Keywords- Fuzzy Logic Controller, PI Controller, Switched Reluctance Motor Drive.
I.INTRODUCTION Switched reluctance machines (SRMâ&#x20AC;&#x2122;s) are considered to be mechanically robust. This is by virtue of their simple structure. The stator and rotor typically comprise of a lamination stack displaying appropriate magnetic saliency. The rotor has no windings and stator coils are mounted on individual poles with no overhang thus reducing as far as possible end-winding inductance. For high-speed operation, motors with low pole numbers are preferred. This reduces hysteresis and eddy current losses by minimizing the magnetic core pulsations per rotor revolution. In recent years, the switched reluctance motor (SRM) has received considerable attention for variablespeed drive applications. Itâ&#x20AC;&#x2122;s simple construction, due to the absence of magnets, rotor conductors, and brushes, and high system efficiency over a wide speed range make the SRM drive an interesting alternative to compete with
In construction, the SRM is the simplest of all electrical machines. Only the stator has windings. The rotor contains no conductors or permanent magnets. It consists simply of steel laminations stacked onto a shaft. It is because of this simple mechanical construction that SRMs carry the promise of low cost, which in turn has motivated a large amount of research on SRMs in the last decade. The mechanical simplicity of the device, however, comes with some limitations. Like the brushless DC motor, SRMs cannot run directly from a DC bus or an AC line, but must always be electronically commutated. Also, the saliency of the stator and rotor, necessary for the machine to produce reluctance torque, causes strong non-linear magnetic characteristics, complicating the analysis and control of the SRM. Not surprisingly, industry acceptance of SRMs has been slow. This is due to a combination of perceived difficulties with the SRM, the lack of commercially available electronics with which to operate them, and the entrenchment of traditional AC and DC machines in the marketplace. SRMs do, however, offer some advantages along with potential low cost. For example, they can be very reliable machines since each phase of the SRM is largely independent physically, magnetically, and electrically from the other motor phases. Also, because of the lack of conductors or magnets on the rotor, very high speeds can be achieved, relative to comparable motors. Switched reluctance machines are used in electric vehicles, washers, dryers and aerospace applications as the machine is brushless, fault tolerant, maintenance free and rugged and simple in construction. However, some of its limitations are noise, torque ripple and low torque to volume. Noise and low torque to volume have been addressed in the segmented switched reluctance machine (SSRM). SSRM has full-pitched winding while concentrated winding is used in variable reluctance switched reluctance machine (VSRM). The geometry of
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VSRM and SSRM is shown in Fig. 1. This change in winding arrangement in SSRM reduces length of flux paths as compared to those in VSRM. It is shown there that SSRM can give double torque than SRM for the same frame size. This increase in torque is because of the increase in aligned flux, while the torque of SSRM increases with the use of full pitch winding, the end winding volume of the motor also increases by a factor which depends on the ratio of motor air gap diameter (D) to stack length (L). For higher values of D/L ratio, as required in in-wheel electric vehicle (EV) or in fans, the copper loss and end winding volume become significantly higher than those corresponding to concentric winding. This arrangement is particularly more effective for machines with D/L ratio equal to and greater than 2.
Fig. 1,VSRM
II. PROPOSED SRM DRIVE CONVERTER A. Converter Topology
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Fig. (3) shows the operating modes of this converter for 2 phase SRM. As shown in Fig. (3-a), in the magnetization mode, the switch T1 turns on in order to magnetize phase ‘a’. As T1 turns on, the energy is transferred from the source to phase winding and the current in phase inductance increases. Also, in this mode if the magnetizing inductance of coupled inductors is not reset yet, diode D1 would conduct the magnetizing inductance current of the coupled inductors and the input voltage would reset this inductor. When the magnetizing inductance of coupled inductors is reset, Diode D1 turns off. The reset of coupled inductors magnetizing inductance is similar for other phases. When the phase current reaches the reference, T1 is turned off and demagnetization starts. This mode is shown in Fig. (3-b). Since the voltage across phase winding is reversed, diode D1 turns on in this mode. When D1 turns on, Db1 turns on and a negative voltage is placed across the phase winding in proportion to the coupling ratio which accelerates phase current commutation. Fig. (3-c) and Fig. (3-d) show two overlapping modes of stator phase currents. In the first mode, the phase inductance ‘a’ is being demagnetized and phase ‘b’ is being magnetized. In the second mode, both ‘a’ and ‘b’ phases are being demagnetized. As it can be observed, this converter has the ability to separately control phase currents. Also, It is important to notice that the snubber circuit of each switch will absorb the voltage spikes across the switches that otherwise would occur due to leakage inductance of coupled inductors.
Fig. (2) Shows the per phase structure of the proposed SRM drive topology. The converter operation is simple with a minimum number of switches while performing phase current commutation quickly. Regarding the number of switches used, the converter is similar to the Rdump converter, and it functions like the C-dump converter since the phase inductance energy is recovered. In fact, in addition to its simple structure, this converter has higher efficiency than the R-dump converter and a simpler structure and higher phase current commutation speed than the C-dump converter.
Fig. 2. Proposed SRM per phase converter
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Fig. 3. Operating modes of the proposed converter
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B. DESGN CONSIDERATIONS For designing this converter, the coupled inductors ratio has to be determined considering the performing speed of the drive. If the phase current does not reach zero fast enough during the commutation, the phase current continues to exist in the negative torque production area and the phase torque becomes negative. This negative torque will cause large ripples in the torque generated by the motor. This is especially important at higher speeds, because higher speed requires faster commutation. So, each SRM drive can function to an extent of speed with regard to its converters structure. The maximum SRM drive speed depends on the type of converter used and is illustrated by the following equation. (1) where Tf is the time needed for the current to reach from reference value to zero, τa is the electrical time constant of machine phases, Rs is the resistance of each phase winding, Vc is the reverse voltage applied to the phase inductance during commutation. The electrical time constant equation of the machine is as follows.
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widely used in the control area with some application to dc-to-dc converter system. A simple fuzzy logic control is built up by a group of rules based on the human knowledge of system behavior. Matlab/Simulink simulation model is built to study the dynamic behavior of dc-to-dc converter and performance of proposed controllers. Furthermore, design of fuzzy logic controller can provide desirable both small signal and large signal dynamic performance at same time, which is not possible with linear control technique. Thus, fuzzy logic controller has been potential ability to improve the robustness of dcto-dc converters. The basic scheme of a fuzzy logic controller is shown in Fig.5 and consists of four principal components such as: a fuzzification interface, which converts input data into suitable linguistic values; a knowledge base, which consists of a data base with the necessary linguistic definitions and the control rule set; a decision-making logic which, simulating a human decision process, infer the fuzzy control action from the knowledge of the control rules and linguistic variable definitions; a de-fuzzification interface which yields non fuzzy control action from an inferred fuzzy control action [10].
(2) The phase inductance at the current commutation area equals to aligned inductance, thus L and τ would take an “a” subscript. Current drop angle at speed ω is calculated as follows. (3) As it can be observed from (3), when speed increases, θf becomes larger resulting in a larger negative torque and, consequently, more torque ripples. Therefore, it is needed to look for a way to reduce θf at higher speeds. As it can be observed from (3), commutation can be carried out faster by increasing Vc. In the proposed converter, the reverse voltage across the phase winding can be increased for faster commutation purposes by increasing the coupled inductors L1 and L2 turns ratio. Also it is important to notice that Vc is constant in most of the converters introduced so far. But in this converter, Vc can be designed by changing the coupled inductors turns ratio considering the maximum SRM drive functioning speed.
Fig. 4. General Structure of the fuzzy logic controller on closed-loop system
The fuzzy control systems are based on expert knowledge that converts the human linguistic concepts into an automatic control strategy without any complicated mathematical model [10]. Simulation is performed in buck converter to verify the proposed fuzzy logic controllers.
IV. PROPOSED FUZZY CONTROLLER L. A. Zadeh presented the first paper on fuzzy set theory in 1965. Since then, a new language was developed to describe the fuzzy properties of reality, which are very difficult and sometime even impossible to be described using conventional methods. Fuzzy set theory has been
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Fig.8. the Membership Function plots of duty ratio
Fig.5. Block diagram of the Fuzzy Logic Controller (FLC) for dc-dc converters
A. Fuzzy Logic Membership Functions: The Fuzzy controllers do not require an exact mathematical model. Instead, they are designed based on general knowledge of the plant. Fuzzy controllers are designed to adapt to varying operating points. Fuzzy Logic Controller is designed to control the output of converter using Mamdani style fuzzy inference system. Two input variables, error (e) and change of error (de) are used in this fuzzy logic system. The single output variable (u) is PWM generation of the converter to control the output.
B. Fuzzy Logic Rules: The objective of this dissertation is to control the output voltage of the boost converter. The error and change of error of the output voltage will be the inputs of fuzzy logic controller. These 2 inputs are divided into five groups; NB: Negative Big, NS: Negative Small, ZO: Zero Area, PS: Positive small and PB: Positive Big and its parameter. These fuzzy control rules for error and change of error can be referred in the table that is shown in Table I as per below: Table I Table rules for error and change of error (e) (de)
NB
NS
ZO
PS
PB
NB
NB
NB
NB
NS
ZO
NS
NB
NB
NS
ZO
PS
ZO
NB
NS
ZO
PS
PB
PS
NS
ZO
PS
PB
PB
PB
ZO
PS
PB
PB
PB
IV.MATLAB MODELING AND SIMULATION RESULTS Fig. 6 The Membership Function plots of error
Here simulation is carried out in different cases, the simulation results of SRM drive using the proposed converter is compared to the results of a SRM drive operated under fuzzy logic control technique. Case 1: Performance of Proposed Converter Fed SRM Drive under Open-Loop Condition.
Fig. 7 The Membership Function plots of change error
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Case 2: Performance of Proposed Converter Fed SRM Drive under Closed-Loop Condition
Fig.9 Matlab/Simulink Model of Proposed Converter Fed SRM Drive under Open-Loop Condition
Fig.9 shows the Matlab/Simulink Model of Proposed Converter Fed SRM Drive under Open-Loop Condition using Matlab/Simulink Tool. Fig.11 Matlab/Simulink Model of Proposed Converter Fed SRM Drive under Closed-Loop Condition
Fig.11 shows the Matlab/Simulink Model of Proposed Converter Fed SRM Drive under Closed-Loop Condition using Matlab/Simulink Tool.
(a)
Phase Currents
(a)Phase Currents
(b)Electro-Magnetic Torque
(b)
Electromagnetic Torque
(c)Speed Fig.10 Phase Currents, Electromagnetic Torque, Speed of the SR drive, when operating under open loop condition, the SR drive need 1.2 sec to settle down the steady state condition. (c)
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Speed
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Fig.12 Phase Currents, Electromagnetic Torque, Speed of the SR drive, when operating under closed loop condition, the SR drive need 0.4 sec to settle down the steady state condition.
Fig.14 Phase Currents, Electromagnetic Torque, Speed of the SR drive, when operating under closed loop fuzzy control condition, the SR drive need 0.3 sec to settle down the steady state condition.
Case 3: Performance of Proposed Converter Fed SRM Drive under Closed-Loop Fuzzy Controller.
V.CONCLUSION This proposed model is implemented using Matlab Simulink software and the obtained resultant waveforms were evaluated and the effectiveness of the system stability and performance of converter have been established. In this paper a new SRM drive is introduced. The proposed converter is analyzed and its operating modes are discussed. The proposed converter only uses one switch for each motor phase. Also, in the proposed converter the phase inductance energy is recovered to achieve high efficiency. Simulation results are presented to justify the validity of the theoretical analysis. Without using any dedicated converter, one converter can be used to attain low steady state error values, maintain high stability factor.
Fig.13 Matlab/Simulink Model of Proposed Converter Fed SRM Drive under Closed-Loop with Fuzzy Logic Controller
Fig.13 shows the Matlab/Simulink Model of Proposed Converter Fed SRM Drive under Closed-Loop Fuzzy Controller by using Matlab/Simulink Tool.
(a) Phase Currents
(b) Electromagnetic Torque
REFERENCES [1] F. J. Lin, “Real-time IP position controller design with torque feed forward control for PM synchronous motor,” IEEE Trans. Ind. Electron., vol. 44, pp. 398–407, June 1997. [2] F. J. Lin, R. F. Fung, and Y. C. Wang, “Sliding mode and fuzzy control of toggle mechanism using PM synchronous servomotor drive,” Proc. IEE—Control Theory Applicat., vol. 144, no. 5, pp. 393–402, 1997. [3] F. J. Lin and Y. S. Lin, “A robust PM synchronous motor drive with adaptive uncertainty observer,” IEEE Trans. Energy Conversion, vol. 14, pp. 989–995, Dec. 1999. [4] F. J. Lin and S. L. Chiu, “Robust PM synchronous motor servo drive with variable-structure model-output-following control,” Proc. IEE— Elect. Power Applicat., vol. 144, no. 5, pp. 317–324, 1997. [5] T. L. Chern and Y. C. Wu, “An optimal variable structure control with integral compensation for electro hydraulic position servo control systems,” IEEE Trans. Ind. Electron., vol. 39, pp. 460–463, Oct. 1992. [6] M. Ghribi and H. Le-Huy, “Optimal control and variable structure combination using a permanent-magnet synchronous motor,” in Conf. Rec. IEEE-IAS Annu. Meeting, vol. 1, Denver, CO, Oct. 1994, pp. 408– 415. [7] K. K. Shyu and H. J. Shieh, “A new switching surface sliding-mode speed control for induction motor drive systems,” IEEE Trans. Power Electron., vol. 11, pp. 660–667, July 1996. [8] , “Variable structure current control for induction motor drives byspace voltage vector PWM,” IEEE Trans. Ind. Electron., vol. 42, pp. 572–578, Dec. 1995. [9] Li Jun-hong, Wang Fei, Li Lanjun. Adaptive Fuzzy Sliding Mode Variable Structure Control for AC Servo Systems[J]. Power Electronic,
(c) Speed
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ROBO CONTROL SYTSEM DESIGN USING ARM D SUDHEER BABU1, PURSUING M-TECH IN LIMAT, VIJAYAWADA P RAGA LAVIMA2, PURSUING M-TECH IN LIMAT, VIJAYAWADA R TULASI3, PURSUING M-TECH IN LIMAT, VIJAYAWADA Abstract: In this paper we present the multimodal - repairs, cleaning, etc.). interaction of matlab systems for control of a - Other autonomous tasks (surveillance, transportation, inspection, etc.). robot. These systems consist of (1) The monitoring The autonomy capacity required for such systems is of the place by using wireless camera in matlab (2) obtained by means of a control system able to interact a visual sensor that perceives and identifies with the environment of application. To accomplish commands based on the Mexican Sign Language this, the system must have sensors to perceive the (MSL). According to the stimuli, either movement, events that occur in the environment, and the multimodal interface of the robotic system is actuators/mechanisms to react and realize able to weight each signs contribution to perform a modifications to it. particular task. The multimodal interface was tested in a simulated environment to validate the This work is focused in developing tasks of service pattern recognition algorithms (both, robotics for the human being, looking for the robotic independently and integrated). The independent system to be controlled by means of natural language performance of the signs was in average of 93.62% represented in acoustic form (speech) and visual form (visual signs and spoken commands), and of (signs). Hence, the service robot must interpret visual 95.60% for the multimodal system for service and acoustic commands to perform a task. The tasks tasks. to be performed are considered to be simple in order to be arranged in sequences to accomplish more complex tasks such as to “serve a glass with water” 1. Introduction and “take it to” a particular work space or person. Our advances towards this system are presented in From its beginnings, robotics has been an this paper, which is structured as follows: in Section II important assistive technology for the human being, a review of related studies to this problem is making possible the existence of constant production presented, while in Section III the details of the design lines with minimum error rates for the realization of of the visual and acoustic sensor systems are repetitive tasks. This is an example of industrial presented; in Section IV are presented the design robots, which although they provide a service to the details of the integrated multimodal system, whose human being, cannot be classified as service robots. results are presented and discussed in Section V; According to the International Federation of Robotics finally in Section VI we present our conclusions and (IFR) a service robot is defined as: a robot that works future work. autonomously either partially or totally, and that performs useful services for the well being of humans 2. Research review and equipments. These robots can have mobility and the Communication between humans is performed by capacity to manipulate objects. means of voice and gestures. Unfortunately, robots cannot understand these human natural languages. Thus, the application field of service robots can be Thus, a mechanism is necessary for the robot to classified in: understand these languages as a human does. To accomplish this, many research projects have been - Applications of service for human beings (personal developed to perform communication between protection and assistance of handicapped people, etc.). humans and robots. Among those projects we can - Applications of service for equipments (maintenance, mention to Posada-Gómez et al.that controlled a International Association Of Engineering & Technology For Skill Development 111
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wheelchair with hand signals. Such equipment has also been controlled by Hashimoto by tracking other signals such as ocular movements, while used spoken commands. A project more related to the focus of our work is presented that developed the multimodal control of a service robot for a shop. This robot was used as an informative kiosk which was able to locate a user by processing audio signals in addition to perceived visual information. On the other hand there are developments for companion robots (i.e., Aibo, Robosapien, etc.). In this field we can mention to Weitzenfeld et al. [6] that controlled a group of Aibo robots to play football by means of spoken commands and visual feedback. BLOCK DIAGRAM: Person Section
Robot Section
LPC2148 MICROCONTROLLER LPC2148 Microcontroller vogue. The ARM7TDMI-S could also be a general purpose 32-bit chip, that gives high performance and extremely low power consumption. The ARM vogue depends on Reduced Instruction Set laptop computer (RISC) principles, and collectively the instruction set and
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connected decipher mechanism are swarming easier than those of very little programmed advanced Instruction Set Computers (CISC). This simplicity finishes up in AN extremely high instruction turnout and spectacular amount of your time interrupt response from a little and economical processor core. Pipeline techniques are used therefore as that each one elements of the strategy and memory systems will operate endlessly. Typically, whereas one instruction is being dead, its successor is being decoded, and a 3rd instruction is being fetched from memory. TheARM7TDMI-S processor jointly employs a singular bailiwick strategy discovered as Thumb, that makes it ideally suited to high-volume applications with memory restrictions, or applications wherever code density can be a issue. The key discovered behind Thumb is that of a superreduced instruction set. Basically, the ARM7TDMI-S processor incorporates a combine of instruction sets: •The customary 32-bitARMset. •A16-bitThumbset. The Thumb set’s 16-bit instruction length permits it to approach double the density of ancient ARM code whereas retaining most of the ARM’s performance advantage over a daily 16-bit processor victimization 16-bit registers. Typically this will be} typically doable as a results of Thumb code operates on an identical 32-bit register set as ARM code. Thumb code is in AN extremely position to produce up to sixty five exploit the code size of ARM, and one hundred and sixty exploit the performance of identical ARM processor connected to a 16-bitmemory The ARM7EJ-S processor could also be a synthesizable core that has all the advantages of the ARM7TDMI – low power consumption, small size, and therefore the the} thumb instruction set – whereas collectively incorporating ARM’s latest DSP extensions and Jazelle technology, facultative acceleration of java-based applications. Compatible with the ARM9™, ARM9E™, and ARM10™ families, and Strong-Arm® vogue package written for the ARM7TDMI processor is 100 percent binarycompatible with whole completely different members of the ARM7 family and forwards-compatible with the ARM9, ARM9E, and ARM10 families, still as product in Intel’s sturdy ARM and xscale architectures. this provides designers a range of software-compatible processors with sturdy priceperformance points. Support for the ARM vogue presently includes: •Operating systems like Windows chemical element, Linux, palm OS and SYMBIAN OS ALGORITHM(PCA):
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A) Principal half associate degree analysis (PCA) can be a mathematical procedure that uses AN orthogonal transformation to convert a group of observations of presumptively correlative variables into a group of values of linearly unrelated variables cited as principal elements. Quantity the quantity the number of principal elements may be a smaller amount than or up to the number of original variables. This transformation is printed in such the manner that the first principal half has the largest potential variance (that is, accounts for the utmost quantity of the variability inside the data as possible), and each succeeding half in turn has the easiest variance potential to a lower place the constraint that it's orthogonal to (i.e., unrelated with) the preceding elements. Principal elements are guaranteed to be freelance if the knowledge set is place along ordinarily distributed. PCA is sensitive to the relative scaling of the primary variables. Depending on the sphere of application, it's collectively named the distinct Karhunen–Loève process (KLT) in signal method, the Hotelling process in variable control, correct orthogonal decomposition (POD) in bailiwick, singular value decomposition (SVD) of X (Golub and Van Loan, 1983), eigenvalue decomposition (EVD) of XTX in pure mathematics, multivariate analysis, Eckart–Young theorem (Harman, 1960), or Schmidt–Mirsky theorem in psychological science, empirical orthogonal functions (EOF) in natural science, empirical Eigen function decomposition (Sirovich, 1987), empirical half analysis (Lorenz, 1956), quasiharmonic modes (Brooks et al., 1988), spectral decomposition in noise and vibration, and empirical modal analysis in structural dynamics. PCA was fictional in 1901 by Karl Pearson, as academic degree analogue of the principal axes theorem in mechanics; it had been later severally developed (and named) by Harold Hotel ling inside the 19 Thirties. the strategy is typically used as a tool in preliminary data analysis and for making prognostic models. PCA could also be done by eigenvalue decomposition of a data variance (or correlation) matrix or singular value decomposition of a data matrix, usually once mean centering (and normalizing or pattern Z-scores) the knowledge matrix for each attribute. The results of a PCA ar usually mentioned in terms of half scores, usually cited as issue scores (the reworked variable values hold dear a particular data point), and loadings (the weight by that each standardized original variable need to be augmented to induce the half score).
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PCA is that the best of truth eigenvector-based variable analyses. Often, its operation could also be thought of as revealing the inner structure of the information in AN extremely approach that best explains the variance inside the information. If a variable knowledge set is envisioned as a group of coordinates in AN extremely high-dimensional knowledge space (1 axis per variable), PCA can offer the user with a lower-dimensional image, a "shadow" of this object once viewed from its (in some sense; see below) most informative viewpoint. this will be done by pattern exclusively the first few principal elements so as that the spatiality of the reworked data is reduced. 3. Sensor systems 3.1 Signs recognition system In order to develop in a satisfactory manner the sign recognition system, this was developed in different stages: imaging, segmentation, obtaining the descriptor form, learning patterns by the neural network and recognition. Relation among these stages is shown in the flowchart. In the paragraphs below we will briefly explain each of the stages mentioned above. Obtaining images In Fig. 2 the 23 symbols that were used, from the 27 that comprise the alphabet of the MSL, are presented. We choose those whose shape was different from each other and image sequences were not considered.
Figure 2. The 23 symbols of the MS L alphabet.
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The images of the signs were taken using a uniform background. Additionally, the user wore a garment that let uncover only the hand in order to avoid interference by objects in the wrist (watch, bracelets, etc.). This ensured that the region of interest to be processed belonged only to the hand. We used four different sets similar to that shown in Fig. 2, each with a different background. These four image sets served to create a database of images by varying their parameters using a photometric filter. The used filter was a power function of the form shown in Eq. 1. f(x)= cex 0.9 ≤ x ≤ 1.1
(1)
Where c is a constant and x is the parameter to be varied to obtain different intensities in the image that is being processed. The parameter x was varied in a random way in order to obtain different light variation for the input image. In evaluating Eq. (1) we have that, if x < 1, the image is darker, and if x > 1, is bright (see Fig. 3). Segmentation The first step in the realization of the sign recognition system was the image segmentation by active contours [9]. These contours shape the boundaries between the object, background and other objects in the image. Also allow extraction of the contours of the objects of interest based on models that use a priori information on the shape of objects. These techniques are much more robust to the presence of noise, and allow more complex image segmentation. In this paper, snakes were used to perform segmentation (segmentation by region [10]).
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and(d) final contour, (e) contour of sign. Descriptor Since the snake as result gives us the edge of the object, the shape signature was used as descriptor. In our case, the object is the shape of the hand with one sign of the MSL alphabet (Fig. The signature of the object is done by calculating the distances from the object’s center of gravity to each one of ASR system trained with speech samples from a single speaker. For multi-user purposes, Maximum Likelihood Linear Regression (MLLR) was performed to adapt this system for its use by other users. The training corpora of the SD ASR system consisted of a selection of a short It is now common practice to build HMMs at the phonetic level instead of at the word level. A phoneme is a sub-word unit that forms a word, for example, the word HELLO is formed by the sequence of phonemes Lexicon, or Phonetic Dictionary, is used in this case to establish the sequence of phonemes that define each word in a vocabulary. In our case, we defined a sequence of phonemes for each word of the control sentences associated to 12 symbols of the MSL (see Table 3). The Transcribe Mex tool was used to define the phoneme sequences for the vocabulary words of the application. Because of limited availability of Mexican speech corpora, we developed a Speaker Dependent (SD) ASR system trained with speech samples from a single speaker. For multi-user purposes, Maximum Likelihood Linear Regression (MLLR) was performed to adapt this system for its use by other users. The training corpora of the SD ASR system consisted of a selection of a short
In Fig. 4 an example is presented of the different transitions of the snake for the image of MSL symbol representing the letter "y".
Figure 4. Different snake transitions (a) initial snake International Association Of Engineering & Technology For Skill Development 114
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the points that form the boundary. This yields a histogram of distances as shown in Fig. 5 which is the histogram contour for the symbol.This histogram consisted of 360 different values which was the input vector for training the neural network. 6. Conclusions and future work In this paper a multimodal system to control a service robot was presented. This system was built with two main blocks to control the moment and video monitoring by using matlab technology. The proposed system was validated by means of implementation in a simulation environment. The robot was constituted by a mobile platform & voice based control.Among the future research and expectations for this work we present the following: A Robust Period Embedded Vision System on an Unmanned Rotorcraft for Ground Target Following - To use a ZigBee network devices to synchronize the received signals. - To control the robot we are using hand geusture bu using matlab for finger signs detection by using a different scheme to RGB such as the CieLAB system. - Implementation of monitoring the place of MSL signs that have movement.
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References: 1.International Federation of Robotics (IFR): http://www.ifr.org/service-robots/ 2.Posada-Gomez, R., Sanchez-Medel, L.H., Hernandez, G.A., Martinez-Sibaja, A., AguilarLaserre, A., Leija-Salas, L., "A Hands Gesture System Of Control For An Intelligent Wheelchair", 4th International Conference on Electrical and Electronics Engineering (ICEEE 2007), pp.68-71, 2007. 3.Hashimoto, M., Takahashi, K., Shimada, M., "Wheelchair control using an EOG- and EMG-based gesture interface", IEEE/ASME International Conference on Advanced Intelligent Mechatronics, 2009. AIM 2009, pp.1212-1217, 2009. 4.Alcubierre, J.M., Minguez, J., M ontesano, L., Montano, L., Saz, O., Lleida, E., “Silla de Ruedas Inteligente Controlada por Voz”, In Primer Congreso Internacional de Domótica, Robótica y Teleasistencia para Todos, 2005. 5.Böhme, H.-J., Wilhelm, T., Key , J., Schauer, C., Schröter, C., Groß, H.-M., Hempel, T., “A n approach to multi-modal human–machine interaction for intelligent service robots”, Robotics and Autonomous Systems, Vol. 44, pp. 83-96, ISSN 0921-8890, 2003.
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DESIGN AND IMPLEMENTATION OF INTELLIGENT CONTROLLERS FOR A CONTINUOUS STIRRED TANK REACTOR SYSTEM D.SIVA NAGARAJU M-tech â&#x20AC;&#x201C; control system Sivadevarala.d3@gamil.com. Departmemt of Electical and Electronic Engg Gudlavalleru engg college,gudlavalleru, Krishna dist,A.P.
ABSTRACT All the industrial process applications require solutions of a specific chemical strength of the chemicals or fluids considered for analysis. Continuous Stirred Tank Reactor (CSTR) is one of the common reactors in chemical process and all industrial process requires a solution of specific chemical strength of chemicals considered for analysis. Such specific concentrations are achieved by mixing a full strength solution with water in the desired proportions. In this paper design a controller for controlling the concentration of one chemical with the help of other has been analyzed. This paper features the influence of different controllers like PI, PID, Fuzzy logic controller and Genetic algorithm (GA) upon the process model. Model design and simulation are done in MATLAB SIMULINK. The concentration control is found better controlled with the addition of Genetic algorithm (GA) instead of fuzzy logic and conventional PID controllers. The improvement of the process has been observed. KEY WORDS: Genetic algorithm(GA) Fuzzy Logic (FL), conventional PID Control, Chemical Concentration, CSTR. 1. INTRODUCTION The Continuous Stirred Tank Reactor system (CSTR) is a complex nonlinear system. Due to its strong nonlinear behaviour, the problem of identification and control of CSTR is always a challenging task for control
G.RAMESH Asst.professor Departmemt of Electical and Electronic Engg Gudllavaleru engg college,gudlavalleru. Krishna dist,A.P.
systems engineer[1]. Chemical reactors often have significant heat effects, so it is important to be able to add or remove heat from them. In a CSTR (continuously stirred tank reactor) the heat is add or removed by virtue of the temperature difference between a jacked fluid and the reactor fluid. Often, the heat transfer fluid is pumped through agitation nozzle that circulates the fluid through the jacket at a high velocity. The reactant conversion in a chemical reactor is a function of a residence time or its inverse, the space velocity. For a CSTR, the product concentration can be controlled by manipulating the feed flow rate, which change the residence time for a constant chemical reactor. In the conventional PID controller, the proportional, integral and derivative actions on error are placed in the forward path. The proportional or derivative action on the error cause an abrupt change in the controller output when the set point change is introduced. This one is the addressed drawbacks of conventional PID controller [4]. This proportional and derivative kick can be avoided by I-PD controller where the proportional and derivative terms are given in the feedback path to avoid the set point kick. In this paper parameters of I-PD controller an abstract algebra and linear algebra and the structure of a Fuzzy system, which comprised of an implication between actions and conclusion as antecedents and consequents. Abstract algebra incorporates systems or models dealing with groups, fields and rings. Linear algebra incorporates system models dealing with vector spaces, state vector and transition matrices.
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The primary benefit of fuzzy system theory is to approximate system behaviour where numerical functions or analytical functions do not exist. Hence, Fuzzy systems have high potential to understand the very systems that are devoid of analytical formulations in a complex System. Complex systems can be new systems that have not been tested, they can involve with the human conditions such as biological or medical systems. The ultimate goal of the fuzzy logic is to form the theoretical foundation for reasoning about the imprecise reasoning, such reasoning is known as approximate reasoning. Genetic Algorithm (GA) was first introduced by Holland [7] and popularized by Goldberg [8]. It is one of the modern heuristic algorithms based on a principle of Charles Darwinian theory of evolution to natural biology. The GA technique can generate a high quality solution within shorter calculation time and stable convergence characteristics. GA method is an excellent method for solving the optimal PID controller parameters. Therefore, this study develops the GA-PID controller to search optimal PID parameters. In this paper, CSTR has been used to mix ethylene oxide with water to make ethylene glycol. Here the purpose is to control the concentration of ethylene glycol with the help of concentration of ethylene oxide. But undershoot, overshoot and inverse response come in the considered system while performing in a conventional way. But after implementation of PID controller to the process, removing of those shoots can be seen but still the design requirement is not achieved. So finally auto tuning method of PID controller is implemented in order to achieve the design requirement [3]. 2.Continuous Stirred Tank Reactor (CSTR) Modeling :
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chemical ‘X‘ and ‘Y‘ and the byproduct is ‘Z‘. Ethylene oxide (X) is reacted with water (Y) in a continuously stirred tank reactor (CSTR) to form ethylene glycol (Z) .Assume that the CSTR is manipulated at a constant temperature and that the water is in large excess.
Fig. 1. A CSTR Control System. The stoichiometric equation is X+Y= Z…………………(1) The reactant conversion in a chemical reactor is a function of residence time or its inverse, the space velocity. For anisothermal CSTR, the product concentration can be controlled by manipulated the feed flow rate, which change the residence time (for a constant volume reactor). It is convenient to work in molar units when writing components balances, particularly if chemical reaction is involved. Let CX and CZ represent the molar concentration of X and Z (mol/volume). dVC = F CX − FC + V … … (2) dt
In this paper, CSTR has been considered in which concentration of two chemicals is controlled for better results, the
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dVC = −FC + V … … … (3) dt
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Where rX and rZ represent rate of generation of species X and Z per unit volume, and CXi represents the inlet concentration of species X. If the concentration of the water change than the reaction rate is second order with respect to the concentration of Ethylene oxide.
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The first input (dilution rate) is manipulated and the second(feed concentration of A) is a disturbance input. Linearization of the two modeling equations (from equation (6) & (7)) at steady state solution to find the following state space matrices is done:
r = −K C − K C … … … (4) Where k1, k2 & k3 are the reaction rate constants and the minus sign indicate that X is consumed in the reaction. Each mole X reacts with a mole of Y and produces one mole of Z, so the rate of generation of Z is r = K C − K C … … … … … … (5)
Expanding the left hand side of equation (1) =V
+C
……………(6)
Combining eq (1) & (5)
dC F = C −C dt V
− K C − K C . . (7)
Similarly, dC F = − C + K C − K C … (8) dt V 3. PROBLEM FORMULATION The linear space model or case study of CSTR is given by . x = Ax + Bu …………… (9) y = Cx + Du …………….. (10)
For the particular reaction under consideration, the rate constants are k1=5/6 /min k2 =5/3 /min k3=1/6 mol/litre.min Based on the steady state operating point of CXs = 3 gmol/liter, CZs = 1.117 gmol/liter and Fs/V = 0.5714 min-1. The state model is
Where the states, inputs and output are in deviation variable form.
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controllers structures requires modifications. The structures are given below ( )=
1+
1
+
… … (11)
the controller parameters are calculated. The desired parameters for the PID controller are the proportional gain (KP), integral gain (KI) and the differential gain (KD). Firstly, find and solve for the characteristic equation of the process which is given by + (4.6429 – 1.117kc) s + (5.3821 + 3.1472 kc ) = 0………. (12) The manipulated input output process transfer function G(s)= C(sI –A)-1 B is calculated with the help of Matlab. G (S) =
Where kc is the critical (ultimate) gain. The value of kc can be calculated by the Routh Hurwitz criterion and the other parameters can be calculated by the Ziegler Nichols tuning method.
−1.117S + 3.1472 … (10) S + 4.6429S + 5.3821
It is desired to produce 100 million pounds per day of ethylene glycol. The feed stream concentration is 1.0 lbmol/ft3 and an 80% conversion of ethylene oxide has been to be determined reasonable. Since 80% of ethylene oxide is converted to ethylene glycol, the ethylene glycol concentration is 0.8 lbmol /ft3. In this process it is seen that the process has inverse response with delay time as well as overshoot while tunning in conventional PI,PID and fuzzy logic controllers are used. To overcome this problem and to obtain the desired response For that, soft computing based optimization method is used. 4. Controller design Industrial PID controllers usually available as a form and to perform well with the industrial process problems,the PID
Fig 2:Block diagram of conventional PID controller A basic PID controller directly operates on the error signal and this may produce a large overshoot in the process response due to the proportional and derivative kick. The process is unstable and to overcome the effect of proportional and derivative kick, a modified PID structure known as I-PD is considered. In I- PD structure, the integral term responds based on the error and the P+D terms works based on the measured process output. In conventional PID controller (Fig. 3), the changes in set point cause an impulse signal or sudden change in the controller output as well as in output response [2]. This spike in the controller output is called
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proportional or derivative kick. The controller output is given to the final control elements like control valve, motor or electronic circuit in which the spikes create serious problem. But in I-PD controller (Fig. 4) , the proportional and derivative terms are acting only to the change in process variable not on the error as these terms are given in the feedback path. This structure may eliminate the proportional and derivative kick during any set point change [5]. Minimizing the ISE criterion generates the controller parameters. The values of the controller parameters are continuously adjusted, until the ISE of the closed loop system is minimum [7].
Figure 3. Tuning of I-PD controllers 4.1 Ziegler-Nichols Tuning Method ZN tuning rule was the first such effort to provide a practical approach to tune a PID controller. According to the rule, a PID controller is tuned by firstly setting it to the Ponly mode but adjusting the gain to make the control system in continuous oscillation. The corresponding gain is referred to as the ultimate gain uK and the oscillation period is termed as the ultimate period uP . The key step of the ZN tuning approach is to determine the ultimate gain and period. Then, the PID controller parameters are determined from uK and uP using the ZN tuning Table I. controller P pi pid
0.5 0.45 0.6
0.83 0.5
0.125
Table 1. Commonly used Ziegler-Nichols rule. By putting the proportional gain (KP), integral gain (KI) and the differential gain (KD) values in the simulink PID controller,
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the response for the step input is obtained. We see that the output have overshoot little inverted response and also its settling time and rise time is little bit more. That is not the desired response. Now for the better control, the Fuzzy logic controller is used. 4.2 Fuzzy logic controller When we connect a Fuzzy logic controller, then we require a multiplexer to give input to the controller.The inputs to the controller are error (difference of the set point and output) and feedback output (output as the feedback). Now construct the membership function for the inputs and the output taking triangular memberships. In this paper, the input is unit step input. In this process, the 80% of the ethylene oxide converted in to the ethylene glycol (output is 80% of the input). Thus the range for the output is [0 â&#x20AC;&#x201C; 0.8]. The second input is error and its range is [0 â&#x20AC;&#x201C; 0.2]. Using these values, make fuzzy rules in the fuzzy rule base editor and observe the response that there is no inverted response, no overshoot, no undershoot, rise time and settling time are reduced. 4.3. GENETIC ALGORITHM The GA is a global optimization and search technique based on the principles of genetics and natural selection. GA differs significantly from most classical optimization techniques in many aspects. First of all, unlike classical methods, GA are not gradient based, i.e. they do not require the objective functions to be continuous, neither do they need information about the derivatives of the objective functions, therefore they can handle problems with discrete solution spaces. Second, the search mechanism is stochastic in nature, which makes them capable of searching the entire solution space with more
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likelihood of finding the global optima. Third, GA are able to solve problems with nonconvex solution space, where classical procedures usually fails. All these differences make GA superior over classic methods in some real world applications, particularly for some very complex engineering problems, for example: complex truss-beam design, componentâ&#x20AC;&#x2122;s design, and structure design. GAs features can be explained for solving complex control system engineering problems Controller design System Identification Fault Diagnosis System Analysis Robotics Further control related combination problem In GA, the individuals (solutions) in a population are represented by chromosomes; each of them is associated to a fitness value. According to the principle of survival of the fittest, the population reproduces, crossovers, mutates and produces a new generation that is fitter than the old generation. Those processes are done again and again until the fittest chromosome is found and the best result of the problem is got. Figure.3 shows GA process flowchart having key blocks as initial population, fitness evaluation, and optimization
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Selection Crossover Mutation A GA starts iteration with an initial population. Each member in this population is evaluated and assigned a fitness value. Strings with higher fitness values have more opportunities to be selected for reproduction in next step. Reproduction makes the clones of good chromosomes but does not create new one because of this crossover operator is applied. Crossover operator produces new individuals which have some part of both the parents genetic material. The crossover probability indicates how often crossover is performed. Using reproduction and crossover on their own will generate a large amount of different strings. However there are two main problems with this: Depending on the initial population chosen, there may not be enough diversity in the initial strings to ensure the GA searches the entire problem space. The GA may converge on sub-optimum strings due to a bad choice of initial population These problems overcome by the introduction of a mutation operator into the GA. Mutation are the occasional random alteration of a value of a string position. The probability of mutation is normally low because a high mutation rate would destroy fit strings and degenerate the GA into a random search. 4. SIMULATION, TESTING AND RESULTS The process is represented by the transfer function given in fig. 5, and fig. 6 depicts the output of the process.
. Fig.4 Genetic algorithm process flowchart Simple GA has three basic operators:
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Fig. 5: Process model Fig. 8: Time response with P controller By using P controller there is not much effect to the output response as compared to uncontrolled process.
Fig. 6: Time response of uncontrolled process When there is no control to the process, there is some time delay and inverted response and also the response is settled below the desired magnitude.
As can be seen from fig. 8, there is almost the same response as that of uncontrolled and P controller model. The process with PID controller is shown in the fig. 9 and fig. 10 depicts the output of the process. The tuning of controller parameters is done by Zeigler & Nichols method. Here KP= 1.2, KI =5.73, KD= 0.78
The process with P controller is shown in the fig.7 and fig.8 depicts the output of the process.
Fig. 9: Process model with PID controller Fig. 7: Process model with P controller
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The output response is shown below.
Fig. 10: Time response with PID controller As can be observed from the fig. 8, Rise time ( tr) = 1.5sec Overshoot= 78% Settling time ( ts) = 23sec
Fig. 13: Time response with fuzzy controller As can be seen from fig. 10, Rise time ( tr) = 3 sec Settling time ( ts) = 4 sec Overshoot= 0% Undershoot= 0% There is no any time delay and also no any inverted response. All the limitations are reduced as compared to the PID controller. In fig.14, membership values of input 1 called ―errorǁ having three ranges low, medium and high is shown.
Fig.11: Time response with i-pd controller There is almost negligible time delay and inverted response.So Fuzzy controller is used to reduce the rise time, settling Time, overshoot and also try to remove the time delay and inverted response Fig. 14: Fuzzy membership sets of input ‘1’ (error) In fig. 15, the membership values of input 2 called ―change in error having the three ranges low, medium and high.
Fig. 12: Process model with fuzzy logic controller.
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Fig. 15: Fuzzy membership sets of input ‘2’ (change in error) In fig. 16, membership values of ―outputǁ having the same ranges low, medium and high.
Fig. 18: mesh analysis of both the inputs and outputs Fig. 19 depicts the surface view of the two inputs (error and change in error) and output.
Fig. 16: Fuzzy membership sets of output (output) In fig. 17, fuzzy if-then rules using mamdani fuzzy model are shown.
Fig.19: surface analysis of both inputs and outputs To overcome the problems occurs in fuzzy logic controller we are using the soft computing technique. By using the Gentic algorithm we can reduce the rise time, settling time is shown in the fig 20.
Fig. 17: Fuzzy If – then rules Fig. 18 depicts the mesh analysis of the two inputs (error and change in error) and output.
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6. REFERENCES
Fig. 20 : time response for Genetic algorithm Parameters/ Peak Rise Delay Sett type overshoot time time time (%) (Sec) (Sec) (Sec) PID 78% 1.95 1.2 28 I-PD Fuzzy logic controller Genetic algorithm
75% 0
2.1 3
1.6 1.3
17 4
0
2
1.3
2.5
Table.2:comparision results of pid,i-pd Fuzzy logic and genetic algorithm 5. CONCLUSION When there is no control to the process, it generates an inverse response together with an overshoot and considerable delay time. But when the PID controller and fuzzy logic controllers is implemented to the process, the problems of inverse response and delay time are controlled in the ongoing process and are removed considerably but then it was showing instability in terms of rise time, overshoot and settling time. To overcome this instability in rise time, overshoot & in settling time a soft computing technique Genetic algorithm used and the results are shown in the above figs.so the Rise time and settling time and overshoots are also reduced. By comparison with ZN, fuzzy and genetic algorithm, it shows that this method can improve the dynamic performance of the system in a better way by the selection of an appropriate objective function.
[1] Schmidt, Lanny D. (1998). The Engineering of Chemical Reactions. New York: Oxford University Press. ISBN 0-19510588-5 [2] Yung C. Shin, Chengying Xu ―Intelligent Systems: Modeling, Optimization, and Controlǁ CRC Press 2009. [3] Fried land B., ―Advanced Control System Designǁ, Prentice Hall, New Jersey, 1996. [4] Jaya, N. , Sivakumar, D. and Anandanatarajan, R. (2007)— Implementation of fuzzy gain scheduling of PID controllers for a two capacity interacting nonlinear process, paper presented at TIMA, January [5] K.J. Astrom, & T. Hagglund, ―The future of PID control Control Engineering Practice”, pp.1163 -1175. 2001. [6] Rajani K. Mudi, Chanchal Dey, & Tsu – Tian Lee, “An improved auto – tuning scheme for PI controllersǁ, Journal of science Direct ISA Transactions, 47: 45 – 52, 2008. [7] Luis E. Zarate, Peterson Resende, & M. Benjamin,” A Fuzzy Logic and Variable Structure Base Controller forCSTR Controlǁ. Annual conference of IEEE, 2001. [8] Xiao-Feng Li, Jian Sun, Hui-Yan Wu, Wei-Dong Zong, “Application of the fuzzy PID to the Power Plantǁ, IEEE 2007. [9] Yun Li,Kiam Heong Ang and Gregory C.Y.Chong,―PID Control System Analysis and Design – Problems, Remedies, and Future Directionsǁ. IEEE control system magazine, February 2006 pp. 32-41,2006 [10] Dimiter Driankov, Hans Hellendoorn, Michael Reinfrank, Fuzzy control
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Classification of lung tumour Using Geometrical and Texture Features of Chest X-ray Images Dr. P.V. RAMARAJU Department of Electronics and communication. SRKR ENGINEERING COLLEGE ANDHRA PRADESH, INDIA. Email: pvrraju50@gmail.com Abstract: Early detection is the most promising way to enhance a patientâ&#x20AC;&#x2122;s chance for survival of lung cancer. One of the most important tasks in medical image analysis is to detect the absence or presence of disease in an image, without having precise delineations of pathology available for training. A computer algorithm for nodule detection in chest radiographs is presented. The algorithm consists of four main steps: 1. Image acquisition 2. Image pre-processing; 3. Nodule candidate detection; 4. Feature extraction. Algorithm is applied on two main types of lung cancer images, like Small-Cell, Non-Small-Cell type and as well as on TB database. Total 75 images are used (25 from each category) during experiment to estimate geometrical and texture features. Active Shape Model (ASM) technique is used for lung field segmentation. Gary Level Co-occurrence Matrix (GLCM) technique is used to estimate texture features. Keywords:Computer Aided Diagnosis MATLAB,NCLC,SCLC DATABAES, malignant.
(CAD), benign,
I.INTRODUCTION Lung cancer is one of the most common and deadly diseases in the world. The prognosis and the cure of lung cancer depend highly on the early detection and treatment of small and localized tumors. The 5-year patient survival rate is approximately 40% when lung cancer is detected in the early stage. About 87% of lung cancers are thought to result from smoking or passive exposure to tobacco smoking. Physical characteristics of the nodules, such as rate of growth, pattern of calcification, type of margins are very important in the investigation of the solitary lung nodules. Every lung nodule grows in volume over time. However malignant nodules grow at an exponential rate, which is usually expressed as a tumorâ&#x20AC;&#x2122;s doubling time. Malignant nodules have a doubling time of between 25 to 450 days, whereas the benign nodules are stable and have a doubling time more
SATTI PRAVEEN Department of Electronics and communication. SRKR ENGINEERING COLLEGE ANDHRA PRADESH, INDIA. Email: praveenreddy148@gmail.com than 500 days. In addition to the rate of growth of the nodules, the pattern of the calcification is an important indicator of whether the nodule is benign or malignant. Nodules which are centrally or diffuse calcified are usually benign. Chest X-ray image has been used for detecting lung cancer for a long time. The early detection and diagnosis of pulmonary nodules in chest X-ray image are among the most challenging clinical tasks performed by radiologists. Some of these lesions may not be detected due to the fact that they may be camouflaged by the underlying anatomical structures, or the low quality of the images, or the subjective and variable decision criteria used by the radiologist. Computer-aided diagnosis (CAD) has been proven to be a very effective approach as assistant to radiologists for improving diagnostic accuracy. Numerous systems were reported for detecting lung nodules on chest X-ray images. However, the strong concern of almost all of them is that the false positives per image are too large. How to reduce the number of false positives while maintaining a high true positive detection rate is the most important work in realizing a chest CAD system. Most of the proposed computer-aided diagnosis systems (CAD systems) adopt a two-step pattern recognition approach, which is a combination of a feature extraction process and a classification process using neural network classifier or statistical classifier. The performance of the classifier depends directly on the ability of characterization of candidate regions by the adopted features. Many kinds of features have been proposed for discriminating between normal tissues and abnormal ones. However, there have been a few researches on comparing the effectiveness of those features. The purpose of our research is to find the optimal feature set from the available database for the classification. II. METHODOLOGY The lung cancers are classified as SmallCell type of lung cancer (SCLC), and Non-Small-
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Cell type of lung cancer (NSCLC) (Fig.1). Usually Small-Cell type of lung cancer arises at alveolar level or at terminal bronchial level, and seen to be more scattered in nature on X-ray. Non- Small-Cell type of lung cancer arises in the larger, more central bronchi; tends to spread locally; and metastasizes somewhat larger than the other patterns, but its rate of growth in its site of origin is usually more rapidly than that of other types.
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avg. gray level, standard deviation, contrast, skew ness, kurtosis, and entropy. 2.Second-Order Statistics features Co-occurrence matrix method has been adopted to extract features of second-order statistics. They are obtained by using Haralick transformation. Co-occurrence matrices are obtained from the inner and the outer regions of each SR. Correlation, energy, homogeneity and contrast are the features computed by using cooccurrence matrix. III. IMPLIMENTATION
Fig. 1 SCLC and NSCLC images
Feature selection is a very important step in organizing a classifier. Theoretical approach cannot be applied to determine the optimal combination of features, and the only way to select the optimal feature subset is to evaluate all possible combinations of the features. Moreover, sufficient numbers of test materials are necessary to evaluate the performance of each feature combination. It means that the number of combinations and the total amount of computation time become impractically huge. Therefore Jun Wei, Yoshihiro Hagihara, Akinobu Shimizu, and Hidefumi Kobatake accepted heuristic algorithms such as a genetic algorithm, a forward stepwise and a backward stepwise selection technique to decide the optimal feature set. A. Geometric Features Spread-ness, circularity, area, equivalent radius,distance from the candidate point to the pulmonary hilum, and flatness are some of the geometric features. Such geometric features are calculated from the binary suspicious region (SR) using thresholding technique. B.Texture or Contrast Features Generally, tumor region is brighter than its background on X-ray image. So, the contrast information can be used as features. Contrast features are again classified under two categories, first order statistic and second order statistic. In this work, such ten kinds of features are calculated from SR regions. 1.First-Order Statistics features First-order statistic features are calculated fromhistograms of the grey-scale values. The histograms are obtained from filtered images. Features calculated from each histogram include
The steps followed for analysis and feature extraction from lung cancer and TB X-ray images are described in this section. As an initial step, the images are obtained using image acquisition method and then the application of preprocessing algorithms, including size normalization and filtering of the image. The features, those are identified to be useful for diagnosis and analysis, require separation of the lung fields from the background. Lung field masks are prepared manually by segmenting the lung fields. As well as readily available masks developed by using Active Shape Model (ASM) technique are used to separate the lung fields. Thresholding along with region based segmentation techniques are used to segment the lung nodules (in case of NSCLC images) and cancerous portion (in case of SCLC images) from the separated lung field area. Next step deals with detail description and methodology adapted to estimate geometrical and texture features from the Postero-Anterior (PA) X-ray images. The chest unit used for screening X-ray films is mobile KlinoskopH unit (Siemens, India make). Keeping the tube voltage equal to 150 kV, 500 mA at 2.2 mm Pb the images were printed on 14 X 17 centimeter film. Then these films were digitized with a high-resolution scanner (Scanjet 2400, HP India make).These films were collected from the private medical institutes. Lung cancer and TB images from the public database are also used in this study. Every image data is acquired with 256 gray levels (8 bits) and stored as JPEG (.jpg, .jpeg) data. Before extraction of the features from an image, it is necessary to pre-process the image to reduce irrelevant information or noise, and to enhance the image properties, which makes the feature measurement easier and more reliable. Scanned images are resized to a size of 512 X 512 pixels. Median filter is used to remove the noise or
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irrelevant information from the images. The purpose of the segmentation is to find suspicious regions within the lung fields. Segmentation of lung fields on PA chest radiographs has received considerable attention in the literature Active Shape Model, a general technique for image segmentation has been developed by Cootes and Taylor and has been applied to various segmentation tasks in medical imaging Around 180 such lung field masks (separate for each right and left lung field) are prepared using ASM technique. These masks (Fig. 2) are the part of JSRT (Japanese Society for Radiological Technology) public database and useful for lung field segmentation.
(a)
(b)
(c)
Fig. 4 (a) segmented lung fields after multiplication, (b) Image after thresholding, (c) Separated nodule
Fig. 4 depicts the resultant images of the nodule segmentation (NSCLC type) technique. Resultant images for the SCLC type of image segmentation are included in Fig. 6
.
(a)
(b)
(c)
Fig. 5 (a) SCLC original image, (b) Separated lung fields, (c) Separated cancerous portion Fig. 2 Original X-ray image along with lung field masks prepared using ASM technique
Lung field masks (see Fig. 3) are also prepared manually by segmenting the lung fields. Manual segmentation is carried out by determining the peripheral lung field pixel co-ordinates with region based segmentation technique.
Bit Quads technique devised by Gray is used to extract geometrical features like area and perimeter. Distance is a real valued function d {(j1, k1), (j2, k2)} of two image points (j1, k1) and (j2, k2). The most common measures encountered in image analysis are the Euclidean distance, defined as: dE= [( j1 - j2)2 + ( k1 - k2)2]1/2 In discrete images, the coordinate differences ( j1- j2) and ( k1 - k2) are integers, but the Euclidean distance is usually not an integer. Here diameter is estimated using Euclidean distance. As per the literature survey it is seen that the growth of the malignant part (nodule here) is usually circular in nature, therefore roundness of the nodule is calculated using a simple equation:
Fig. 3 Original X-ray image & manually segmented lung fields mask
Further the lung fields are separated from the background by multiplying the mask image with the filtered X-ray image. Above discussed technique is applied on SCLC, NSCLC and TB database images. Thresholding is applied on the separated lung fieldsâ&#x20AC;&#x2122; image to separate the nodule or infected portion. Valley point value between the two peaks of the histogram is selected as a threshold value. Region based segmentation techniques like region-growing (in case of NSCLC) and region-labeling (in case of SCLC) have been applied further to separate the nodules and infected portion.
I = 4 * pi * area / perimeter ^ 2 This metric value or roundness or circularity index or irregularity index (I ) is equal to 1 only for circle and it is less than 1 for any other shapes. Here it has been assumed that, more the circularity of the object, the probability of that object being nodule is high.
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Table –I GEOMETRICAL FEATURES
Sr. No. 1 2 3 4
Features Area Perimeter Diameter Irregularity Index (I)
value 2815 226.85 59.286 0.69
The geometrical features estimated for theseparated nodule, shown in Fig. 4 (c) are included in Table I. An important approach for describing a region isto quantify its texture content. A frequently used approachused for texture analysis is based on statistical propertiesof the intensity histogram. One class of such measures isbased on statistical moments. An expression for the nthmoment about the mean is given by: L-1 μn = Σ (zi - m)n p(zi) i=0 wherezi is a random variable indicating intensity levels in an image, p(z) is the histogram of the intensity levels in a region, L is the possible intensity levels. A histogram component p(zj), is an estimate of the probability of occurrence of intensity value zj , and the histogram may be viewed as an approximation of the probability density function (PDF). GLCM is the technique used to calculate PDF. L-1 m = Σ zi p(zi) i=0 Here m is the mean (average) intensity. These moments can be computed using MATLAB function statmoments, which is acting as a sub function in another MATLAB function known as statxture. This function is used to calculate firstorder statistic texture features like mean, standard deviation, smoothness, third moment, uniformity and entropy. A measure of average contrast or the standard deviation can be calculated by using following equation, where μ2 (z) is the second moment. σ = √ μ2 (z) = √ σ2 Smoothness measures the relative smoothness ofintensity in a region. R is 0 for a region of constant intensity and approaches 1 for region with large excursions in the values of its intensity levels. Smoothness is calculated by using the following equation. R = 1 – 1/ (1 + σ2) Skew-ness of the histogram is also known as third moment. This measure is 0 for symmetric histograms, positive by histograms skewed to the right (about the mean) and negative for histograms
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skewed to the left. For smooth images this value comes to be negative. Following equation is used to calculate third moment. L-1 μ 3 = Σ (z i – m)3 p(z i) i=0 When all gray levels are equal, uniformity measures maximum and goes on decreasing from there for the inequality. L-1 U = Σ p2 (z i) i=0 Entropy is nothing but the measure of randomness,given by the following equation. L-1 e = - Σ p(z i) log2 p(z i) i=0 The GLCM functions characterize the texture of animage by calculating how often pairs of pixel with specific values and in a specified spatial relationship occur in an image. However, a single GLCM might not be enough to describe the textural features of the input image. For example, a single horizontal offset might not be sensitive to texture with a vertical orientation. Therefore it is essential to generate multiple GLCMs with different offset values or at different angles. MATLAB function graycomatrix is used to generate such multiple GLCMs. Using multiple GLCMs, second-order statistic features like, Contrast Correlation, Energy, and Homogeneity are estimated. IV. RESULTS Results shown below are taken for 7 patientsShown below.There will be three types of classifications based on area of the tumour present in the resulted image. They are 1. Normal (i.e; no tumour present in the organ) 2. Benign (less dangerous) 3. Malignant (very dangerous)
Fig. 6showing x-ray of patient and detected benign tumour
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V. CONCLUSION
Fig 7 showing x-ray and on tumour in it.
Results of SCLC images show that, the area values are quite larger than the other types, like NSCLC. This is because of the scattered nature of the infected area. Irregularity index is always closer to ‘1’ for the circular objects, The segmented portion in case of NSCLC images are having irregularity index closer to ‘1’, which concludes that the segmented portion is a malignant portion or a lung nodule. Referring 1st and 2nd order statistic features, it is concluded that the uniformity and energy values arealmost identical in all cases. VI. REFERENCES
Fig 8 showing x-ray of patient and detected malignant tumour
Fig 9 showing x-ray of patient and detected malignant tumour
Fig 10 showing x-ray of patient and detected malignant tumour
Fig 11 showing x-ray of patient and detected benigntumour
Fig 12 showing x-ray of patient and detected benign tumour
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Dr. P.V. Rama Raju is a Professor at the Department of Electronics and Communication Engineering. SRKR engineering college AP, India. His research interests include Biomedicalsignal Processing, VLSI Design And Microwave Anechoic Chambers Design. He is author ofseveral research studies published in national and international journals and conference proceedings Satti Praveen is an M.tech student at the department of electronics and communication engineering. SRKR engineering college. AP. India. He received his B.tech degree from swarnandhra institute of engineering & technology in 2012
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