ICsense ASIC for MEMS

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ASIC design and supply for MEMS February 2016

WWW.ICSENSE.COM

Š ICsense NV | Confidential

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Chip miracle

This MEMS lab-on-chip ASIC identifies cancer tumor cells. It contains 10.000 through-silicon holes to trap the cells. Every hole has its own dedicated analog-front-end that measures the cell’s impedance. This chip was manufactured in a 0.35um BCD process.

It is the largest ASIC so far designed at ICsense (12mm x 14mm)

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Trends in MEMS. Challenges for the ASIC.

www.icsense.com

Trends in MEMS. Challenges for the ASIC.

Trends in MEMS Consumer market is important driver for MEMS

MEMS ASIC: Lower power Lower noise Lower area

• MEMS become cheaper • MEMS become smaller • Higher noise • Less sensitivity

© Chipworks

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Trends in MEMS. Challenges for the ASIC.

Trends in MEMS Continued integration • • • •

MEMS ASIC: Lower power Lower area Higher complexity

6 DoF: 3-axis accelero + 3-axis gyro 9 DoF: + 3-axis magneto +10 DoF: + pressure/altimeter/humidity All in one package / ASIC

“Innovation is likely to occur in the signal processing ASIC and packaging, rather than in the MEMS part of the product” (quote St. J. Dixon-Warren, Chipworks on MEMS microphones) © Yole development

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6 Trends in MEMS. Challenges for the ASIC.

Challenges for MEMS-ASIC co-design Performance up, cost down • • • • •

Lower power Lower size Higher integration More features Standard technologies

IC design to cross the chasm • • • • •

MEMS co-design Improved architectures Deploy digital force Technology Circuit innovations

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7 Trends in MEMS. Challenges for the ASIC.

Challenge 1: importance of good MEMS modelling Physical model

≠ electrical model

Physical parameter in, digital out

Simplified electrical model of accelerometer

• • •

System level specs (datasheet) MEMS measurements FEM

Details for electrical model:

FEM model of pre stressed micro mirror (COMSOL)

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• • • • • • • •

Cpar Vlatch/hold Temp effects Process variations Non-linearities Offset and gain errors Noise levels excellence | innovation Quadrature signals (IMU) | trust

8 Trends in MEMS. Challenges for the ASIC.

Challenge 2: noise Noise of MEMS system Proportional to • 1/(V_drive)2 (technology) • ΔC/C fixed (MEMS) • Sqrt(current consumption) (circuit) • Mechanical sensor noise (MEMS) • Driver noise (circuit)

Therefore lower noise by ++++

Increase of drive voltage

++

Increase of sensitivity (ΔC ) (<> linearity)

++

Decrease of fixed cap and/or parasitic capacitances

+

Increase in current

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9 Trends in MEMS. Challenges for the ASIC.

Challenge 3: circuit level focus Circuit optimization and innovation Ultra-low-power techniques for read-out • Current domain operation, Class AB • ULP and low area ADC • Time versus accuracy and hardware • Read-out instrumentation in a few uA’s

Highly-accurate oscillators to lock on to MEMS • High temperature/noise/supply stability • ΔΣ Fractional-N techniques

Power management

High voltage drive • High accuracy DAC • Added cost and complexity CONFIDENTIAL © ICsense

Optimal performance through system optimization • Co-design of MEMS and ASIC • Architecture choice • Technology choice • Circuit choice excellence | innovation | trust

10 Trends in MEMS. Challenges for the ASIC.

Challenge 4: selecting the right technology Separate MEMS process enables optimal ASIC technology choice Maximum voltage determines maximal SNR Digital force of low cost technologies (CMOS) • Move as much processing to the digital domain (~SDR) • Digital becomes area and power dominant • Move to lower technology nodes 0.18um → 0.13um → 90nm

Area/size • Exploit digital scaling • Analog hardly scales

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Why moving so much to the digital domain ?

• More flexibility • Filtering in digital domain is easier • Calibration of analog circuits • Time-accuracy trade-off excellence | innovation | trust

11 Trends in MEMS. Challenges for the ASIC.

Mixed-signal ASIC design flow DfT/DfM (Design for Test/Manufacturing) Development and verification 100% PVT corner coverage FME(D)A, (A)SIL

ASIC DEFINITION

DEVELOPMENT & VALIDATION

MANUFACTURING, ASSEMBLY & TEST

ESD/LU, HTOL, HAST, …

AEC-Q100 Skew lots

QUALIFICATION & INDUSTRIALIZATION

SUPPLY

Foundry and technology selection Wafer fabrication (MPW, MLM, SLM) ATE test HW/SW development Platform selection: Teradyne, Credence, …

Assembly (QFN, BGA, WLCSP,…)

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Worldwide ASIC supply Wafer ordering, test/assembly Screening/burn-in Quality control Yield management Customer returns and FA

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12 Trends in MEMS. Challenges for the ASIC.

Mixed-signal ASIC design flow MEMS data processing is increasing. Digital design important !

• Automation to minimize fault occurrence • Extensive use of coverage and assertions • Power aware verification

Typical requirements • • • • • •

I2C - SPI master/slave 1-wire communication Flash, EEPROM and OTP controllers DSP data-paths MCU core integration with on-chip peripherals Dedicated FSM (Finite-State-Machine) and closed-loop systems

=> Solid mixed-signal ASIC design flow is key to success CONFIDENTIAL © ICsense

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13 Trends in MEMS. Challenges for the ASIC.

Mixed-signal ASIC design flow Modeling Simulink VerilogA(MS)

Schematic entry Virtuoso

Simulators Spectre, APS, XPS, UltraSim, AFS

Layout Virtuoso (GXL)

Analog: Matlab controlled

System level Modeling

Mixed-mode simulations Model-based

Mixed-Mode

Matlab + Simulink

Physical Verif.

Calibre DRC, LVS Calibre xRC PVS

Digital: Script controlled

HDLanguages VHDL Verilog SystemVerilog SystemC

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Full mixed-mode simulations AMS (multiple solvers) Models/schematics/xRC Regression suits

Simulators Incisive VCS

Verification LEC/Formal verification Power analysis(UPF, CPF) Assertion coverage Constraint randomized

Synthesis Test Insertion Clock gating Isolation gates

Place & route ATPG Test patterns

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14 Trends in MEMS. Challenges for the ASIC.

Mixed-signal ASIC design flow Enhance first-time-succes through: • • • •

Structured design environment Traceability, systematic design approach Full Mixed-Signal coverage (analog + digital under 1 roof) Version control systems for co-design in larger design teams

Modelling

Block level

Top level

Mixed-mode

Digital

Verilog-A

Spectre

Ultrasim

AMS (+Spectre)

Verilog

Verilog-AMS

Spectre RF

APS

AMS (+APS)

VHDL

Simulink

AFS (BDA)

AFS (BDA)

AMS (+Ultrasim)

SystemVerilog

Matlab

APS

System-C PSL/CPF/UPF

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Design tools supported at ICsense

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15 Trends in MEMS. Challenges for the ASIC.

Business aspects Top 5 reasons for ASIC 1.

2.

3.

4.

5.

small form factor reduce productâ&#x20AC;&#x2122;s bill-of-material protect your IP lower power consumption increase performance/reliability

Breakdown ASIC cost 1.

2.

3.

Silicon area Package Test time during production

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16 Trends in MEMS. Challenges for the ASIC.

Business aspects Unit price can be minimized through: 1.

Silicon area minimization (!!)

2.

Test time optimization

3.

Packaging and connection methods

4.

Finding the best technology fit (technical + commercial)

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Trends in MEMS. Challenges for the ASIC.

Important considerations before starting ASIC design

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About ICsense

www.icsense.com

19 Corporate overview

Facts Mixed-signal IC design and ASIC supply Experts in analog, mixed-signal and high-voltage Largest independent European design group Unique, risk mitigating design methodology • First silicon success • Fastest time-to-market • 100% project execution success

Skilled in innovative, first-of-a-kind ASIC developments ISO9001 / ISO13485 certified

Design HQ in Leuven, Belgium. Founded in 2004.

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20 Corporate overview

Facts Key Figures

93%

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Repeat Business

50+

2A+

On-site D&B designers Financial rating

Turnover

Finalist "Most promising company of the year 2014" (Ernst & Young )

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"Fastest growing company", Trends Gazelle 2013 & 2014

Deloitte Fast-50 “Fastest growers” 2014 & 2015

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21 Corporate overview

Worldwide customer base International presence Corporate HQ in Leuven, Belgium Sales in Switzerland, Germany, Japan

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22 Corporate overview

Recent first-of-a-kind ASIC developments

MEMS speaker HV driver ASIC

Portable X-ray readout ASIC

40-channel brain stimulation ASIC

Medical patch pulse generation ASIC

Impedance spectroscopy for cancer cell detection

EPC Gen-2 RFID for use in Airbus 380

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Automotive communication ASIC

Cochlear implant ICs

Satellite power mgmt and motor control

Wireless Li-Ion battery charger ASIC for IPG/INS

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23 Corporate overview

Cooperation models Design Service

ASIC Supply

Architectural design / spec freeze

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System modeling

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Technology selection

o

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Analog and digital design/layout

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Functional safety

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Qualification and production test plan

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Prototyping

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Functional tests (bench testing)

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ATE HW/SW

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Assembly / production

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Qualification (AEC-Q100)

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QA, SCM

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Yield guarantees by ICsense (fixed unit price)

•

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• = included, o = optional

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24 “The bitter taste of poor quality lingers long after the sweet taste of low price is forgotten”

Quality, reliability and functional safety ISO 13485 – ISO 9001 certified IEC 61508 – ISO26262 functional safety Development

• • • • • • •

Unique design environment 100% PVT corner coverage (6-sigma) Version Control SOS Cliosoft, SVN Issue management (JIRA) FME(D)A, (A)SIL ESD, EMC (IEC61067, IEC62132) ISO pulses (ISO16750-2, ISO7637-2)

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ASIC production

• • • • •

Zero-defect strategy Robustness validation AEC-Q100 qualification (grade 4-0) 8D reporting – failure analysis QA / reliability monitoring

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25 Corporate overview

Markets served

Automotive • • • • • • • • • • •

Communication (CAN,SENT,PSI5,...)

Fuel injection driver Gyroscope interface ASIC Hall sensor read-out GMR sensor interface Gyroscope interface H-bridge drivers Xenon HID lamp driver Battery management chip Motor control ...

Medical • • • • • • • • • •

X-ray imaging chipset Power management chip Deep brain stimulator Li-ion Battery charger Nerve stimulation IC Hearing aid power mgmt Lab-on-chip interface ECG readout Wireless power/data transfer ...

Industrial • • • • • • • • • • •

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Pressure & flow sensors Communication (RS485, ...)

Inductive proximity sensor High-power DC-DC controllers Wheatstone bridge Passive RFID tags Digital processing Motor control interfaces Strain gauge interfacing Inertial Measurement Units (IMU) ...

Aerospace

Consumer • • • • • • • • • • • •

HV MEMS digital speaker 3-axis magnetic compass MEMS gyroscope Accelerometer interface Hall sensor interface 40W PoE PD SMPS controller DC-DC converters Class D audio drivers Frac-N synthesizers Low ppm X-less oscillators ...

• • • • • • • •

Custom rad hard design Rad hard IP portfolio available Rad hard ADCs Rad hard DACs X-tal less oscillators Digital power controllers High reliability applications ...

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26 Corporate overview

Silicon proven ULTRA-LOW-POWER Ultra-low-power AFE, low quiescent current PMU, active PVT monitoring and compensation, RFID, nano-amp clocks RADIATION HARD CUSTOM IP ADC, DAC, Vref, PLL, DC-DC AUXILIARY CIRCUITS On-chip temp measurement, POR, watchdog, reverse voltage & short circuit protection, OV/UV/OC/SC protection, temperature stable oscillators, precision Vref SENSOR/MEMS INTERFACING Accelerometer, gyroscope, wheatstone bridge, capacitive, inductive proximity, Hall, fluxgate, GMR, CMOS/CCD/X-ray imagers ANALOG FRONT END (AFE) Instrumentation amp, PGA, offset-compensation ,lownoise amp, chopping/CDS, high-performance ADC & DAC

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HIGH-VOLTAGE High-side, low-side drivers, HV level shifters, gate drivers, power control, piezo drivers, neural interfacing, ClassD/AB/G/H amplifiers, HV switch arrays, floating switches, HV in standard CMOS (patented) POWER MANAGEMENT AND DC-DC Inductive DC-DC, multi-level/single-coil, charge pumps, PWM controllers, LDO, linear regulators, RF energy harvesting BATTERY MANAGEMENT Wireless charging, Li-Ion, State-of-Charge/Health, bandgap, brownout detection, soft-start/inrush limitation COMMUNICATION PROTOCOLS SPI, I2C, UART, RS485, CAN, J1850, xDSL, EPC Gen-2, OWI, PWM, SENT, LIN, OBD, PSI5, 4-20mA, LVDS CLOCK AND FREQUENCY +/- 500 ppm on-chip clock (no external components), lowjitter PLL, DS fractional-N synthesis MICROCONTROLLERS MSP430, ARM core, 8051, custom FSM MEMORY OTP, MTP, Flash, EEPROM, RAM, ROM, NV-RAM excellence | innovation | trust

27 Corporate overview

93% returning customers ”ICsense developed the analog front-end for our new industrial transceiver in TSMC 40nm. ICsense is a valuable partner for Renesas and we highly appreciated the flexibility, expertise and innovativeness of ICsense.”

“ICsense’s turnkey approach which includes test and manufacturing services, delivers an efficient and cost effective mass-production solution to seamlessly integrate the HighVoltage ASIC driver with our MEMS structure”

Niels Trapp, Senior Manager

Yuval Cohen, CTO

“Based on the excellent project track record of ICsense, ON has selected ICsense as one of its preferred IC design partners for analog, mixed-signal and high-voltage. In the numerous projects with different BUs, ICsense has proven to deliver highquality and reliable IC designs compliant with our stringent demands.”

“With ICsense, we found a skilled, innovative partner for the development of our RF front-end. Their high quality of service, innovation, IC knowledge and dedication has been instrumental to our success to date.”

Geert Evens, Director ASIC Design

Bob Hamlin, VP Engineering

”ICsense’s expertise in making high-voltage circuits with lowvoltage transistors led to first silicon success for this complex and innovative design. We particularly appreciate our close cooperation with ICsense's engineers and their proactive and flexible attitude."

“The flexible attitude of the ICsense design team combined with their advanced analog IC design expertise, specifically for high voltages, significantly impacted the feasibility and the successful integration of our Cochlear implant IC. “

Shannon Morton, Senior Manager

Tony Nygard, Mgr. Enabling Technologies

”ICsense is one of our major outsource partners to develop large IP blocks to our requirements. We especially value them for their strong technical engagement, robust management, track record of on-time delivery, high-integrity people and their relax company culture.”

Clem Robertson, Project Manager

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watch on-line video testimonial :

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28 Corporate overview

Contact us ICsense NV Gaston Geenslaan 14 3001 Leuven Belgium Tel Fax

: +32 16 58 97 00 : +32 16 58 97 20

sales@icsense.com www.icsense.com linkedin.com/company/icsense

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Satellite motor control ASIC (Sealevel + 160 km)

RFID ASIC for airplanes (Sealevel + 10 km)

ASIC 9-DOF IMU MEMS (Sealevel)

Cancer cell detection ASIC (Sealevel)

Gas sensor ASIC (Sealevel)

Electronic compass ASIC (Sealevel)

ASIC for mining industry (Sealevel -4 km)