154

Proc. of Int. Conf. on Control, Communication and Power Engineering 2010

Fully Digital Controlled Front - End Converter Based on Boost Topology 1

Atul Gupta1, and Amita Chandra2

School of instrumentation/DAVV, Indore, India Email: atul_gupta_ait@yahoo.com 2 Allahabad central university/Science, Allahabad, india Email: amita10jan2006@gmail.com power factor preregulators (PFP's) or power factor correction (PFC) converters. In most cases, PFP's consist of a network of capacitors, inductors and switches. These switches are switched at a high frequency (>20kHz), while the control circuit determines the duty ratio. The main tasks of the controller are: obtaining an AC input current similar in shape to the AC input voltage and guaranteeing a constant value for the DC output voltage.

Digital regulators over conventional analog controllers offer several advantages such as programmability i.e. the possibility of implementing nonlinear and sophisticated control algorithms, reduction of the number of control/passive components, high reliability, low sensitivity to components aging, negligible offsets, thermal drifts, and improved dynamic response.

The digital control for Power Factor Preregulators (PFPs) are gaining growing interest, since when it has been shown the feasibility and advantages of digital controller ICs specifically developed for high-frequency switching converters [4]–[5]. Relatively new and the main contributions on this subject are given in [6]–[15]. The control structure described in previous papers [6]–[8] is defined according to what is normally done in analog controllers; thus, the control algorithm is essentially based on a multi-loop control where the outer voltage loop determines the current reference amplitude by multiplying a signal proportional to the rectified input voltage waveform. Moreover, in [6]–[12] some potentialities of the digital implementation have been exploited and, more specifically, digital techniques to remove the output voltage ripple at twice the line frequency have been used, so as to improve system dynamics. Moreover, techniques which do not require input voltage sensing have been proposed in [14]–[15] and, more specifically, in [14] the input voltage has been estimated using a disturbance observer and in [15] using the integral part of the Proportional-Integral (PI) current regulator.

This paper proposes a fully digital control of PFP boost that uses synchronized (with line frequency) sine look up table as current reference, generated by DSP software and the wave can be perfect even if the input voltage has great distortion, so the system input current can be a very clean sine wave, which consequently results in a perfect PFC effect. In addition, in analog arithmetic, the denominator of current reference must be the square of input voltage for constant power operation. The digital equation doesn’t require the square of the input voltage, so it is also simpler.

PFC rectifier, a switching converter is controlled by two loops: an inner, current loop that forces the input current 'Iin' to follow the rectified input voltage waveform

Abstract—In higher power applications, to fully utilize the line, power factor correction (PFC) is a necessity. Passive solutions were developed first, which required bulky inductors and capacitors. To reduce the volume of these bulky solutions active Power factor correction (PFC) using a boost topology was developed. PFC converters for the higher power range are commonly designed for continuous conduction mode (CCM). This paper presents the practical implementation of a fully digital control for boost converter with the following features. A power factor of unity, total harmonic distortion (THD) in line current to be < 3%, the phase displacement of input line current w.r.t voltage to be zero degrees, output voltage to be tightly regulated, the power drawn by converter to be independent of input voltage variations. These are accomplished by interposing a high frequency switching pre regulators between the input bridge rectifier and filter capacitor. The switching controls algorithms, which are simple and fast, provides a significant improvement in the system’s dynamic performance compared to usual analog control techniques. The paper discusses the design criteria and the actions taken for the implementation of the digital control, which is performed by means of standard DSP controllers. The effectiveness of the approach is assessed by experimental tests.

Index Terms—Digital control, power factor preregulator.

I.

INTRODUCTION

As technology advances, electric power usage is moving from simple, non-electronic loads (tungsten lamps, motors, relays, resistive heaters, etc.) to electronic ones (fluorescent lamps with energy-efficient ballasts, motors with solid-state drivers, personal computers and home appliances) with more electronics in them. The electric current drawn by these new devices (current in short pulses) is typically different from that of the predecessors (smooth sine waves), and causes problems in overall capacity of the electric utilities. In order to deliver the same amount of power in short pulses; the current peaks (rms values) are much higher. This puts more stress on the wiring in the home or office, the circuit breakers, and even on the generation and distribution equipment provided by the electric utilities.

To minimize these stresses and maximize the power handling capabilities of a switched-mode power supply typically an AC to DC converters, circuitry can be added to improve the shape of the input current. Ideally, the input current should have a sine wave shape, and be in phase with the input voltage. In this case, the maximum amount of power can be drawn from the ac line within the limits of power available from the source. AC-DC converters actively reducing the amount and amplitude of the harmonics contained in the input current are called 171 © 2009 ACEEE

Proc. of Int. Conf. on Control, Communication and Power Engineering 2010

'Vin' according to and an outer voltage loop that changes the value 'k' (i.e. the emulated resistance 'Re') to regulate the output voltage.

I in (t ) =

Vin (t ) Re

= k ⋅ Vin (t )

below the switching period is derived by considering the average voltage across the inductor. It is assumed that the input voltage to the boost converter remains unchanged for the time duration under consideration. So this model is valid for frequencies which are very much higher than the frequency of the input voltage and which are very much below the switching frequency. The average voltage across the inductor, is given by

(1)

Due to the low frequency power unbalance, the output capacitor always presents a voltage ripple at twice the line frequency 'ωf'. The voltage ripples, assuming unity power factor and neglecting the input inductor energy is given by,

ΔVo (t ) =

Po ∗ Sin(2πω t ) f 2 ⋅ ω ⋅ C ⋅ Vo f

)

(3)

For Steady State Solution, VL=0 i.e average voltage across the inductor over the one switching period is zero.

Therefore from (3) we can get,

(2)

VO =

This cannot be compensated by the voltage control loop without causing the input-current distortion, the change of the emulated resistance 'Re' must not be influenced by the output capacitor ripple, therefore, usually limits the achievable bandwidth of voltage loop to a fraction of the line frequency (10–20 Hz). As a result, the dynamic response of the low-bandwidth voltage controller is poor and over-design of the power stage and a downstream DC-DC converter may be required to account for increased voltage overshoots and dips during transients.

II.

) (

(

VL = d ∗ Vin + 1 − d ∗ Vin − Vo

Vin

(4)

1− D

Therefore, the rate at which this voltage changes for small changes in the duty ratio is derived by differentiating (3) and is given by VˆL ( s ) = Vo ⋅ dˆ

(5)

Where 's' is the complex frequency at which the duty ratio changes. The small signal relationship between the inductor voltage, and current, is given by

DYNAMIC MODEL OF THE CONVERTER IN THE AVERAGE CURRENT CONTROLLED MODE

VˆL ( s ) = s ⋅ L ⋅ IˆL ( s )

(6)

By equating (5) and (6), the small signal relationship between the duty ratio and inductor current is readily derived as Iˆ ( s ) Vo Gid = L = ˆ d (s) s⋅L

(7)

The duty ratio 'd' is derived practically by comparing a control voltage 'Uca' with a ramp function whose frequency is 'fs'. The gain of the Pulse Width Modulator (PWM) is expressed as the ratio of the duty ratio to the control voltage. Once again, this model is valid for frequencies very much below the switching frequency.

The expression for the PWM gain is given by Fm = Figure 1. Block diagram of dynamic model of the boost converter

(8)

Uˆ ca

The software is implemented such that, when the modulator 'Fm' input 'Uca' is 1, the modulator output, i.e., the PWM duty ratio 'd' is 100%, so Fm = 1. The gain of the boost converter 'G1', from the duty ratio to the inductor current follows from (7) and (8) is given by

The use of the front-end converter with unity power factor operation is widespread and the dynamic model and the design methods for the controller are readily available in [1]–[3] This section briefly describes the modelling of the converter in the average current controlled operation in analog domain. The small signal model of the converter and the controller is shown in Fig. 1.This model is valid for frequencies much below the switching frequency 'fsw'.

Unity power factor operation and DC bus voltage regulation are the features achieved in this control scheme.

The gain of the converter 'G1' from the control voltage 'Uca' to the inductor current 'iL' for frequencies much

G1( s ) = Gid ⋅ Fm =

172 © 2009 ACEEE

dˆ

K1 s

where

K1 =

Vo L

(9)

Proc. of Int. Conf. on Control, Communication and Power Engineering 2010

⎛ K1 ⎞ 1 G1( s ) ⋅ H 1( s ) = ⎜ ⎟ ⋅ , where ⎝ s ⎠ s

1 s ⎛ K1 ⎞ ⇒ K = Lt [s ∗ G1( s ) ⋅ H 1( s )] = Lt ⎜ ⎟=∞ V s→0⎝ s ⎠ s→0 1 ⇒ e(∞ ) = =0 KV

Figure 2. Small signal model of outer loop. Current source feeding load. For constant power loads, Re= -RL

When the current loop is closed: a second order system with two reactive elements (L and C) becomes a single pole system. Feedback theory provides the rational for this. The fact that a feedback loop is controlling the inductor current is effectively like having a current source feeding the output capacitor and load. Therefore, at frequencies below the current loop bandwidth, the current mode power stage has only one pole dominated by the C||RL impedance as shown in Fig. 2.

Therefore, the gain 'G2' corresponds to the filter capacitor and the load resistor. This model of the boost converter is used to design the current loop controller, 'H1' and the voltage loop controller 'H2'. The model of the power stage with current loop closed is shown in Fig. 1.

The relationship between 'Pin' and 'Uca' is linear, so the AC and DC ratio is the same.

Case where the load is a dc-to-dc converter, the load is considered a constant power load. Therefore, it has a negative small signal resistance associated with it. The negative resistance is equal an opposite in sign to the dc resistance and the two cancel each other. The gain of the power stage included the multiplier gain is by G 2( s ) =

vO ( s ) U CA ( s )

III.

=

PIN

reducing the steady state velocity error to zero) reduces the bandwidth of the system drastically and the phase margin to zero. The effect of reduction in bandwidth is higher distortion in the current waveform (because higher harmonics in the reference waveform are not forced in the inductor current faithfully). Obviously, a phase margin 'PM' close to zero is not desirable. It is therefore necessary to improve the phase angle of the loop gain 'G1.H1'. To increase 'PM' and to make the crossover slope as 20dB/decade, a single zero can be introduced anywhere before the gain crossover frequency of G1. Therefore, G1.H1' is given as

G1( s) ⋅ H 1( s) =

(10)

A. Current Loop Controller Design The open loop transfer function of the current loop is given by 'G1'. The desired response in the inductor current is that it tracks the reference current waveform. The reference current itself is time varying. This demands a large, preferably infinite, velocity error constant to obtain zero steady state velocity error. The velocity error constant, 'KV'' is given by

⋅ K2⋅

s

ωz

s

1+ ⋅, where H 1( s) = K 2 ⋅

s

ωz

(11)

s

ωz

TABLE I. REFERENCE WAVEFORM HARMONICS ANALYSIS

Lt [s ∗ G1( s )] = K1 s→0

In the present case, the velocity error constant is seen to be 'K1' for the current loop. The steady state velocity error is given by

Harmonics

0

2

Harmonics %

63.7

42.4

4

6

8

10 & above

8.5

3.6

2.0

1. 3

Since the switching frequency is very high compared to the fundamental, the bandwidth can be chosen to be around one tenth the switching frequency which can faithfully reproduce sufficient order of harmonics in the current waveform. From the PFC control block diagram in Fig. 1, the loop gain equation for the current loop is,

1 1 = KV K1

The steady state velocity error is dependent on the circuit parameters and the output voltage. Zero steady state velocity error can be achieved by adding an integrating compensation in the 'H1' block. Along with the controller, the open loop transfer function is given by The steady state error is now independent of the output voltage and the circuit parameter variations. The integral compensation (though improves the performance by

Ti = Gid ⋅ K s ⋅ GCA ⋅ Fm

173 © 2009 ACEEE

s

1+

The position of zero 'ωz' can be found out from the phase margin and the bandwidth requirements. To adjust the bandwidth of the current loop, a gain 'K2' is introduced in the transfer function of the current controller. However, in a digital implementation some of this phase margin can be lost because of the control loop sampling and computation delay. To compensate for this loss, it might be necessary to place the compensator zero 'ωz' somewhere below the crossover frequency 'fci'. The bandwidth of the current loop is chosen such that the reference waveform is tracked with good accuracy. This calls for an analysis of the harmonic content in the reference waveform. The reference waveform is a rectified sinusoid with considerable harmonic content up to the 10th harmonic, whose break up is given in Table I.

DESIGN OF CONTROLLERS

e(∞ ) =

K1

ωz

δU CA ⋅ sCVO

K = V

H 1( s ) =

dˆ where, Fm = Uˆ ca

(12)

Proc. of Int. Conf. on Control, Communication and Power Engineering 2010

I ref ( s ) = U nv ( s ) ⋅ G ⋅ K f ⋅ Vin

For a current loop crossover frequency of 'fci', the required current error amplifier compensator follows from (7), (8) and (12) is given by

GCA =

2π ⋅ fci ⋅ L K s ⋅ Vo

where, K s =

1

Where, 'G' is the gain of the current reference generator, must be constant every line half cycle to avoid distortion of the multiplier current. The closed loop transfer function from the reference 'Iref' to the actual current 'iL' is given by the expression

(13)

I in max

iL ( s)

B. Voltage Loop Controller Design

I ref ( s )

Output voltage regulation by feedback of output voltage:

H 2( s ) = K 3 ⋅

The power taken in from the mains is given by Pin ( s ) = Vin ⋅ i L ( s ) = F ( s ) ⋅ U nv ( s ) ⋅ G ⋅ K f ⋅ Vin

From (17) and (18), by power invariance,

ωz

(14)

Vo ( s )

ωz

U nv ( s )

(15)

1 Vo max

(16)

Output voltage regulation by feed forward of input voltage:

The reference current to the current loop, Iref Fig. 1, is generated from the output of the bridge rectifier. This is multiplied by the 'Unv' to get the actual reference. The mains voltage can vary over a wide range as per the input voltage tolerance specification. Due to this, the reference current, 'Iref' also changes. This in turn alters 'IL' and hence the 'Vo'. Thus it is seen that there is a variation in the 'Vo' or the 'Unv' (which is proportional to the output voltage under steady state) due to variations in the input mains voltage. (In the practical case, the input voltage may vary as widely as 90 Volts to 270 Volt). The value of the current reference is given by

2

(19)

s ⋅ C ⋅ Vripple

(

)

I ref = K m ⋅ A ⋅ B ⋅ C = K m ⋅ Vin ⋅ K f ⋅ U nv ⋅ Vinv I ref = I in ⋅ K s ⇒ I ref max = I max ⋅ K s = 1

174 © 2009 ACEEE

= F (s) ⋅

G ⋅ K f ⋅ Vin

From (19), it is seen that the output voltage is dependent on the square of the magnitude of the input voltage for a given 'Unv'. Dividing the reference current by the rms value of the input voltage can eliminate this dependency of the output voltage. The feed forward block 'Hff ' and the multiplier unit shown in Fig. 1. The block 'Hff ' converts the 'Vg' into a DC voltage equivalent to its rms value. However, the actual design is a trade off between the dynamics response of the filter to the line voltage changes and the acceptable limit on the amount of '2ωf' ripple present at the input of squarer. For each 1% of ripple present, there will be a contribution of 1% to the 3rd harmonics of the line current. This effect is additive with the contribution of due to the voltage loop where 1% ripple will contribute 0.5% to the 3rd harmonic.

In a digital control system, the sine reference can be given accurately and conveniently by DSP software, which will not only be a perfect sine wave, so there is no effect from input voltage, but also simplifies the arithmetic structure The multiplier gain 'Km' is adjusted such that at the minimum input voltage, the reference current 'Iref' is at its maximum when the PFC converter delivers the maximum load. From the block diagram in Fig. 1, with the current loop closed,

Once the current loop is closed, and under constant power load, Pin=Po the voltage loop power stage transfer function can be given from (10). Using this loop gain equation, for a voltage loop crossover frequency 'fcv, the required 'Gvea' compensator is, K d ⋅ Po

(17)

(18)

Po ( s ) = Vo ( s ) ⋅ I chg = Vo ( s ) ⋅ s ⋅ C ⋅ Vripple

s

where, K d =

2

The power given to the DC bus is given by

s

Tv = K d ⋅ GVEA ⋅ GVC

2π ⋅ f cv ⋅ C ⋅ Vo

1 + G 1( s ) ⋅ H 1( s )

⇒ i L ( s ) = F ( s ) ⋅ U nv ( s ) ⋅ G ⋅ K f ⋅ Vin

Above compensator is useful in increasing the gain at the low frequency end without influencing the high frequency slope and phase. From the block diagram in Fig. 1, the loop gain equation for the voltage loop is,

GVEA =

G 1( s ) ⋅ H 1( s )

⇒ i L ( s ) = F ( s ) ⋅ I ref ( s )

Output voltage regulation is achieved by multiplying the current reference given to the current loop by a voltage error, 'Unv' which is generated by the voltage loop compensator, 'H2' Fig. 1. 'H2' is designed based on the amount of distortion introduced in the reference current waveform due to the '2ωf' component that comes out in 'Unv'. This means that the voltage loop crossover frequency 'fcv' will be very small and hence loop dynamics will be very slow. The pre-regulator will respond slowly to line and load changes. This is not a serious drawback as pre-regulator will follow by a SMPS. The transfer function of the voltage loop compensator 'H2' is given by 1+

= F (s) =

2

Proc. of Int. Conf. on Control, Communication and Power Engineering 2010

TABLE II. PFC PI PARAMETERS

At the minimum operating voltage 'Vinv' =1. Again, for full load power the voltage controller output will be at its

⎛ 1 K m = I ref max ⎜ 2 ⎜V ⎝ in min ⋅ K f ⋅ U nv ⋅ Vinv

⎞ V ⎟ = in max ⎟ Vin min ⎠

Specification

Parameters

maximum i.e., 'Unv' =1. Therefore, at minimum operating voltage, to generate maximum reference current the required value of 'Km' is, IV.

Current

SOFTWARE IMPLEMENTATION OF THE VOLTAGE AND CURRENT LOOP COMPENSATORS

fcx fcx_z (Hz) (Hz)

3184 318

H(s)

GCA(s) =

UCA(s) E ( s)

1+ = 1.6116⋅

s 20000 s

20000

The voltage and current loop controllers, given in previous section, are transformed to an equivalent digital form as below, before they are implemented in software.

For example, the current controller can be written as

H 2( s) = K p +

Po=1000W, Vo=390V, C=470uf, L=2mH, f=50Hz, fsw=20K, fsamp=10K, Vinmax=1/Kf=382V, Vinmin=127V, Vomax=1/Kd=410V, Iinmax=1/Ks=15.7, Km=3

Voltage

10

10

GVEA(s) =

U NV (s) E(s)

1+ = 4.722⋅

s

63 s

63

Ki s

For ( s ≥ jω ci ), K p = H 2 ( jω ci ) and K i = K p ⋅ ω z

In discrete form, the current controller mentioned before, can be expressed as, n U CA ( n ) = K p ⋅ E ( n ) + K i ⋅ Ts ∑ E ( j ) j =0 Figure 3. Simulation results are shown above

Where, 'Ts' is loop-sampling time. This is implemented with output saturation and integral component correction using the following three equations U CA ( n ) = K p ⋅ E ( n ) + I ( n − 1) I ( n ) = I ( n − 1) + K i ⋅ Ts ⋅ E ( n ) +

K i ⋅ Ts Kp

(

⋅ U S − U CA ( n )

)

where, U S = U CA max

when U CA ( n ) ≥ U CA max

U S = U CA min

when U CA ( n ) ≤ U CA min

otherwise, U S = U CA ( n )

Here, 'Us' represent the final output of the current controller with saturation and integral component correction. The design rules presented at Table II. were used to design the front-end converter built as a part of the 1000 VA prototype on line UPS. Simulation results are shown at Fig. 3. While inner current 'H1' and outer voltage 'H2' compensator bode plots designs are given at Fig. 4.

Figure 4. Bode Plot of Power Stage, Compensator, Loop Gain Ti and Tv

175 © 2009 ACEEE

Proc. of Int. Conf. on Control, Communication and Power Engineering 2010

[9]

CONCLUSIONS The front-end converter is implemented using a bridge rectifier and a boost circuit. The model of the converter in the average current controlled operation was derived. The current through the inductor in the boost circuit is programmed to be a synchronized (with line voltage frequency) rectified sinusoid, using sine look up table.

This made the current drawn from the mains sinusoidal and in phase, irrespective of harmonic distortion present in line voltage waveform. A suitable controller is designed to meet the system specification. The design rules presented were used to design the front-end converter built as a part of the 1000 VA prototype on line UPS.

[10]

[11]

[12]

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BIOGRAPHIES Atul Gupta received his B.Tech degree in Electronic and Telecom at Army Institute of technology from Pune University, Pune, MH, India in 2002. And M.Tech degree in Instrumentation at SOI, from DAVV University, Indore, MP, India in 2005. His research interest includes power conditioning, Solar Energy, Hybrid Energy; Grid Interconnection of Renewable Energy sources.

Amita Chandra received her M.Sc degree from Banaras Hindu University, Banaras, UP, India in 2008. She has won several gold medals in her academic carrier. And presently, pursuing her PHD from Allahabad Central University, UP, India.

176 © 2009 ACEEE

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