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Proc. of Int. Conf. on Control, Communication and Power Engineering 2010

Designing, Modeling and Implementation of Memory Built In Self Test (BIST) Controller Jayashri Patil1, Shashank Pujari2,, Dr. A.D. Shaligram3 1 ,2

International Institute of Information Technology, Pune, India Email: jayashripatil3@yahoo.com shashankp@isquareit.ac.in 3 Name Pune University, Pune, India Email: adshaligram@gmail.com

Abstract—Memory is increasingly important because of the high density of current memory chips. We have entered an era of integration of various layouts or cores from different companies onto a single chip. For example, one custom VLSI chip may now contain an embedded RAM, a microprocessor, a DSP processor, and various analog circuit layouts. Embedded RAM memories are perhaps the hardest type of digital circuit to test, because memory testing requires delivery of a huge number of pattern stimuli to the memory and the readout of an enormous amount of cell information. The difficulty and time required propagating all of that information through the various glue logic and buses in an embedded core chip almost forces the use of memory Built In Self Test (BIST).

BIST is a design technique in which parts of circuits are used to test the circuit itself. With properly designed BIST the cost of added test hardware will be more than balanced by the benefits in terms of reliability and the reduced maintenance cost. The saving from BIST include reduced test generation effort at all levels, reduced test effort at chip through system levels, improved system level maintenance and repair and improved component repair. With memory BIST, the entire memory-testing algorithm is implemented on-chip, and operates at the speed of the circuit, which is 2 to 3 orders of magnitude faster than a conventional memory test. A 2% chip area overhead for memory BIST can be expected. The regularity of March tests makes them most suitable for memory BIST. March test achieve higher fault coverages with shorter pattern sequences than random or pseudo- random memory tests. This paper discusses the design of BIST hardware for the memory system to implement the MARCH C algorithm.

Index Terms—BIST, Fault models, March C algorithm.

I. INTRODUCTION Over the years, there has been a tremendous growth in digital systems. Many fault models for SRAMs and tests for faults of these models are available. This paper discusses VHDL implementation of a set of march tests together with methods to make composite tests for collections of fault types. Digital systems are composed of data paths, control paths and memories.

Defects in memory arrays are generally due to shorts and opens in memory cells, address decoder and read/write logic. These defects can be modeled as single and multi-cell m e m o ry f au l t s . The dominant use of embedded memory cores along with emerging new architectures and technologies make providing a low cost test solution for these on chip memories a 359 © 2009 ACEEE

very challenging task. The addition of extra circuitry to facilitate testing of memory chips, called design for testability (DFT), or to allow the test mechanism to be completely contained within the chip, called built-in self- test, has only recently become of interest.

Memory BIST has been proven to be one of the most cost- effective and widely used solutions for memory testing for the following reasons: no external test equipment, Reduced development efforts, tests can run at circuit speed to yield a more realistic test time, on-chip test pattern generation to provide higher controllability and observability, On-chip response analysis, test can be on-line or offline, adaptability to engineering changes The paper is organized as follows: Section 2 describes memory faults, which discusses all faults occurs in memory. Section 3 discusses the BIST controller, which is uses march algorithms in order to detect memory faults. Lastly Section 4 describes how Memory BIST Controller is implemented using VHDL hardware description language.

Fig.u re1 shows Functional model of memory, which consists of address decoder, memory cell array and read/write logic. For all these parts there are different functional faults like Address decoder faults (AF), Stuck at Faults (SAF), Transition faults, Coupling Faults and many more. These are either faults in the Address decoder or faults in the memory cell array.

To detect these faults MARCH C algorithm is used. It is one of memory test has proven to be superior for test time and simplicity of the algorithm. A March test consists of a sequence of March elements A March element consists of a sequence of operations applied to each cell in the memory.

Proc. of Int. Conf. on Control, Communication and Power Engineering 2010

III. VHDL IMPLEMENTATION OFMBIST CONTROLLER

Address

In order to implement the March C- test, we follow the state diagram to write the VHDL program.

Generally, the number of states required for a hardware implementation of a march test in a finite state machine is equal to 2 x the number of march elements + 3. The extra three states are a START state, where the controller sits until the TEST command is asserted to start a test; an ERROR state, where the controller sits when a memory error is detected and a CORRECT state, where the controller ends up if the memory passes the march test.

Address decoder

Memory cell array

Read/Write logic

IV. RESULTS The MBIST Controller was simulated and synthesized using Altera’s Maxplus-II tool, targeting on stratix – EP1S10B672C6 by writing structural VHDL description. The simulation waveforms for MBIST controller are shown in Figure 3.

Data Figure1. Functional SRAM chip model

II. BIST CONTROLLER

Figure 2. MBIST architecture

Figure 2 shows the block diagram of the memory BIST architecture. The memory must be equipped with the following test hardware: 1) A memory BIST controller 2) An Address stepper 3) A MUX circuit feeding the memory during self test from the controller.

4) A comparator for response checking 5) A background pattern inserter or data generator for inserting test patterns into memory columns.

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Figure 3. Simulation waveforms for MBIST controller

Proc. of Int. Conf. on Control, Communication and Power Engineering 2010 march algorithm,” Asian Test Symposium, 2001.

Proceedings. 10th, 2001, pp. 391-395.

[7] Zarrineh, K. and Upadhyaya, S.J., “On programmable memory built-in self test architectures,” Design, Automation and Test in Europe Conference and Exhibition Proceedings, 1999, pp. 708 -713.

[8] Jee, A., “Defect-oriented analysis of memory BIST tests,” Memory Technology, Design and Testing, 2002. (MTDT 2002) [9] Hunter, C., “Integrated diagnostics for embedded memory built-in self test on PowerPC™ devices,” IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1997. (ICCD 1997).

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[13] E- References: www.ieeeexplore.ieee.org

CONCLUSIONS In memory testing is very important but challenging. Memory BIST is considered the best solution due to various engineering and economic reasons. March tests are the most popular algorithms currently implemented in BIST hardware. Various implementation schemes for memory BISTs are presented and their trade-offs are discussed. The future Memory BIST designs should be fast, small, efficient, robust and flexible. Using memory BIST has various advantages much as no external test equipment, reduced development efforts, at-speed tests.

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[3] Charles H. Roth, “Digital Systems Design Using VHDL”.

[4] R Dean Adams, High Performance Memory Testing: Design Principles, Fault Modeling and Self Test (Frontiers in Electronic Testing).

[5] J Bhaskar “VHDL Primer” PHI, New Delhi.

[6] Dongkyu Youn, Taehyung Kim, Sungju Park, “A microcode-based memory BISTimplementing modified

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