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Proc. of Int. Conf. on Control, Communication and Power Engineering 2010

Digital Implementation Of Fpga Based Pwm Generator For Cascade H-Bridge Multilevel Inverter R. Rajendra 1 A. Chitra2 T. Meenakshi3 1

PG student, School of Electrical Engineering, VIT University, Vellore-632014, India 2 Assistant Professor (senior), SELECT, VIT University, Vellore-632014, India 3 Assistant Professor, IFET College of Engineering, Villupuram-605602, India 1 rachururraj@gmail.com , 2chitra.a@vit.ac.in, 3mechand22@gmail.com

Abstract— Multilevel inverter technology has emerged recently as a very important alternative in the area of highpower medium-voltage energy control due to their low switch voltage stress and modularity. Cascaded H-bridge multi level inverters (CHMLI) are a promising breed of multi level inverters which generally require several independent dc sources.

Recently, progress of PLD (Programmable Logic Device) like FPGA or CPLD makes it realize the digital control system of power electronics without microprocessor (CPU or DSP). Complex control algorithm can be implemented into FPGA and the calculation time can be dramatically reduced based on parallel processing hardware circuit. But commercial based controller board for power electronics is mainly designed based on DSP or CPU. In this paper, design concept of original FPGA based controller for Cascaded H-Bridge MLI is proposed. 5-level Cascaded H-bridge multi level inverter is modeled and simulated in MATLAB / SIMULINK environment. The PWM generation scheme is coded in XILINX and the results are presented.

employed in real time applications, the digital controller employed for PWM generation plays a major role on the dynamic performance of the system. Hence an attempt has been made in this work to generate PWM pulses using FPGA controller and the results are discussed.

The paper has been organized as follows. The details of CHMLI are dealt in Chapter II. The simulation results are exhaustively presented in Chapter III. The PWM generation using FPGA is illustrated in chapter IV. Chapter V concludes this paper.

Index Terms– Multilevel inverter (MLI), Cascaded H-bridge multilevel inverter(CHMLI), Carrier based pwm, FPGA

three discrete outputs

I. INTRODUCTION The Multilevel inverter has gained much attention in recent years due to its advantages in high power possibility with low switching frequency and low harmonics. The essential advantage of multilevel inverters is the improvement in the output voltage signal quality using devices of low voltage rating with lesser switching frequency, thereby increasing the overall efficiency of the system. The general function of the multilevel inverter is to synthesize a desired high voltage from several levels of dc voltages [1],[2]. The dc sources can be batteries, fuel cells, etc., where all the dc levels are considered to be identical.

In fact, several major manufacturers commercialize Neutral point clamped(NPC) or Diode clamped converter, Flying capacitor clamped converter (FC) and cascaded Hbridge(CHB) multi level inverter topologies with a wide variety of control methods, each one strongly depending on the application. The cascaded H-bridge has been successfully commercialized for very high-power and power-quality demanding applications up to a range of 31 MVA, due to its series expansion capability. When

II. CASCADED H-BRIDGE MLI A cascaded H-bridge converter is several H-bridges in series configuration; a single H-bridge is shown in Figure 1. A single H-bridge is a three-level converter. The four switches S1, S2, S3 and S4 are controlled to generate dc

.When S1and S4 are on, the output is V

dc

; when S2

and S3 are on, the output is –V dc ; when either pair S1 and S2 or S3 and S4 are on, the output is 0. Figure.2 shows the three phase 5-level cascaded H-bridge multilevel inverter.

Figure.1: Single H-bridge topology

It can be observed from Table 1 that some voltage levels can be obtained by more than one switching state.

The voltage level E, for instance, can be produced by four sets of different (redundant) switching states. The switching state redundancy is a common phenomenon in multilevel converters. It provides a great flexibility for switching pattern design, especially for Space vector modulation schemes. The number of voltage levels in a CHB inverter can be found from

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V out with levels V dc, 0 and –V

Proc. of Int. Conf. on Control, Communication and Power Engineering 2010

m = (2H + 1)

III. SIMULATION RESULTS FOR CHMLI

Where, H is the number of H-bridge cells per phase leg. The voltage level m is always an odd number for the CHB inverter while in other multilevel topologies such as diode-clamped inverters; it can be either an even or odd number. The total number of active switches (IGBTs) used in the CHB inverters can be calculated by

In order to validate the proposed converter, computer simulation using MATLAB/Simulink has been created.

The MATLAB simulation results for 5-level CHMLI with input voltage of each bridge is 100 volt and R-load of 100 ohm is shown below. Figure.4 shows the sine-PWM method with a reference frequency of 50 hz and carrier frequency of 2khz. The switching pulses generated for the inverter switches are presented in the figures.5 & 6. The output voltage waveforms for 5-level MLI are shown in figures.7.

As the number of levels increases, the THD decreases.

Also the filter components size is also reduced.

Depending on the application for which the MLI is employed, it can be designed with required number of levels.

N sw = 6(m – 1) The principle of multi-carrier sinusoidal pulse width modulation (MSPWM) is to use several triangular carrier signals with only one modulation signal per phase. For an m-level multi level inverter, (m-1) triangular carriers of the same frequency fc and amplitude Ac.

Figure.2: A general 3-phase (wye) connected 5-level CHMLI Figure 4: PD scheme for 5-level Multi level inverter TABLE- 1

The amplitude modulation index,

OUTPUT VOLTAGE AND SWITCHING STATUS (FIVE-LEVEL)

ma =

Am N ' Ac

Where,

N’ =

(m − 1) 2

Where, Am is the amplitude of modulating signal Ac is the peak to peak value of the carrier(triangular) signal.

The frequency modulation index,

mf =

fc fm

Where, fc is the frequency of the carrier signal fm is the frequency of the modulating signal

In this paper, the CHMLI presented is controlled using carrier based SPWM techniques, which reduces both switching losses/number and THD.

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Proc. of Int. Conf. on Control, Communication and Power Engineering 2010

circuits (ASIC) are gaining higher and higher performance while their cost is constantly decreasing. Therefore, digital control techniques are becoming the most widespread solution in modem power converters.

Many authors report the use of FPGA in the field of switching converters recently [3], [4]. Shorter development cycles, lower costs and higher density are reported. There was when we want to migrate from sequential executed software of sampled control algorithm to parallel executed hardware of FPGA. Most of today control software is developed in Matlab, which uses floating point type for calculation purposes. Contrary to Matlab, an HDL modeling system used in design entry and simulation process by FPGA programming is based on using the variables that represent logic values. A power mapping between FPGA hardware with HDL software and mathematical model of experimental switching converter and nonlinear switching control of it is extremely important [5]. The main difference from DSPbased solution is that FPGA allows simultaneous execution of all control procedures, enabling high performance and novel control methods. The FPGA switching controller has been designed as simple as possible while maintaining good accuracy and dynamic response.

The hardware description language and several development tools are almost device independent. One field which can obtain significant advantages by the use of FPGA is multilevel converters [6]. This is because the high number of switching components requires a high number of output signals, needed to apply the modulation pattern to power devices and most microcontrollers are not able to satisfy this demand. In fact, they can only generate few of them (generally six). because they are designed to control standard inverters. Multilevel converters, moreover, often require complex control algorithms which cannot be implemented in real-time using standard low cost microcontrollers or DSP, but can be successful implemented using hardware description languages and FPGA.

Figure.5: PWM pulses for +ve cycle of 5-level Multi level inverter

Figure.6: PWM pulses for -ve cycle of 5-level Multi level inverter

Figure.7: Output Voltage for 5-level CHB inverter

Figure.8: FFT analysis for 5-level CHB inverter with THD as 17.26%

IV. DIGITAL IMPLEMENTATION OF FPGA BASED PWM GENERATOR FOR CHMLI The field programmable gate array (FPGA) is a new PLD developed by Xilinx. The basic block diagram of FPGA is shown in figure (9). Digital controllers, such as microprocessors, DSP and application specific integrated 179 © 2009 ACEEE

Figure.9: Generic FPGA Architecture

Proc. of Int. Conf. on Control, Communication and Power Engineering 2010

V.CONCLUSION

FPGA kit details:

A simulation model for the cascaded H-bridge multilevel inverter (CHMLI) is developed in the userfriendly MATLAB/SIMULINK simulation platform. The PWM pulses are generated by using HDL(verilog) code simulated in Xilinx/Modelsim software. Xlinix FPGA offers easy, fast and flexible design and implementation.

The simulation results obtained are satisfactory in terms of THD and output voltage and output current wave shapes.

Device family : Spartan 3E Device

: XC3s250e

Package

: tq144

Speed

: -5

Synthesis Tool : XST (VHDL/Verilog)

REFERENCES

Preferred Language : verilog The application of Field Programmable Gate Array (FPGA) in the development of power electronics circuits control scheme has drawn much attention lately due to its shorter design cycle, lower cost and higher density.This paper presents an FPGA-based gate signal generator for a multilevel inverter. FPGA is chosen for the hardware implementation of the switching strategy mainly due to its high computation speed that can ensure the accuracy of the instants that gating signals are generated.

[1]. J. S. Lai and F. Z. Peng, “Multilevel converters – A new breed of power converters,” IEEE Transactions on Industry Applications, vol. 32, no.3, May. /June 1996, pp. 509-517.

[2]. J. Rodríguez, J. Lai, and F. Peng, “Multilevel inverters: a survey of topologies, controls and applications,” IEEE Transactions on Industry Applications, vol. 49, no. 4, Aug. 2002, pp. 724-738.

[3]. A.Poli and K. Jezernik, "Event-driven Current Control Structure for a Three Phase Inverter", International Review of Electrical Engineering, vol. 2, no. 1, pp. 28-35, jan.-Feb. 2007.

[4]. S. Berto, A. Paccagnella, M. Ceschia, S. Bolognani, and M. Zigliotto, "Potential and Pitfalls of FPGA Application in Inverter Drives - A Case Study". IEEE Int. Conf. on Industrial Technology, ICIT'03, vol.1, pp. 500-505, Dec. 2003 [5]. K.H. Cheng, C.F. Hsu, C.M. Lin, T.T. Lee and C. Li, "Fuzzy- Neural Sliding-Mode Control for DC-DC Converters using Asymetric Gaussian Membership Functions", IEEE Transactions on Industrial Electronics, vol. 54, no. 3, pp. 15281536, March 2007.

[6]. N. A. Azli. and A. H. M. Yatim, “Optimal pulse width modulation (PWM) online control of a modular structured multilevel inverter (MSMI)”, presented at the 4’” IEEE lntcrnational Conference on Power Electronics and Drive Systems, Bali. Indonesia, 2001,

Figure.10: PWM signal for CHMLI

The carrier wave of 715 Hz is compared with the reference wave. In same time a pulse signal has frequency of (50 Hz) is generated shown in figure.10 and inverted to get its inverse pulse signal.

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